repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21o/sky130_fd_sc_ls__a21o.behavioral.pp.v | 1,994 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR1 ,
VAR2 ,
VAR15,
VAR13,
VAR8 ,
VAR7
);
output VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR15;
input VAR13;
input VAR8 ;
input VAR7 ;
wire VAR3 ;
wire VAR4 ;
wire VAR10;
and VAR16 (VAR3 , VAR6, VAR1 );
or VAR12 (VAR4 , VAR3, VAR2 );
VAR11 VAR14 (VAR10, VAR4, VAR15, VAR13);
b... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai.pp.blackbox.v | 1,401 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3 ,
VAR5 ,
VAR9 ,
VAR4,
VAR8,
VAR6 ,
VAR7
);
output VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR7 ;
endmodule | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | vga_pll.v | 17,250 | module MODULE1 (
input wire VAR5, input wire rst, output wire VAR1, output wire VAR3 );
VAR4 VAR2 (
.VAR5 (VAR5), .rst (rst), .VAR1 (VAR1), .VAR3 (VAR3) );
endmodule | epl-1.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_engine_classic.v | 40,316 | module MODULE2
parameter VAR110 = 1,
parameter VAR168 = 1,
parameter VAR109 = 256,
parameter VAR7 = "VAR12")
( input VAR170,
input VAR14, input VAR181, output VAR18,
output VAR57,
input [VAR31-1:0] VAR1,
input VAR64,
output [VAR78-1:0] VAR112,
output VAR4,
output VAR141,
output [VAR157(VAR78/32)-1:0] VAR122,
output VAR... | gpl-3.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_gt_rx_valid_filter_7x.v | 9,138 | module MODULE1 #(
parameter VAR44 = 28,
parameter VAR41 = 1
)
(
output [1:0] VAR31,
output [15:0] VAR21,
output VAR9,
output VAR33,
output [ 2:0] VAR13,
output VAR38,
input [1:0] VAR7,
input [15:0] VAR3,
input VAR40,
input VAR11,
input [ 2:0] VAR10,
input VAR45,
input VAR36,
input VAR5,
input VAR37,
input VAR16
);
loca... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPCG_Toggle_BNC_P_read_AW30h.v | 9,087 | module MODULE1
(
parameter VAR26 = 4
)
(
VAR32 ,
VAR29 ,
VAR24 ,
VAR3 ,
VAR12 ,
VAR23 ,
VAR19 ,
VAR10 ,
VAR39 ,
VAR37 ,
VAR18 ,
VAR1 ,
VAR27 ,
VAR21 ,
VAR25 ,
VAR20 ,
VAR35 ,
VAR8 ,
VAR31 ,
VAR22
);
input VAR32 ;
input VAR29 ;
input [5:0] VAR24 ;
input [4:0] VAR3 ;
input [4:0] VAR12 ;
input VAR23 ;
output VAR19 ;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi.pp.symbol.v | 1,448 | module MODULE1 (
input VAR8 ,
input VAR9 ,
input VAR4 ,
input VAR5 ,
input VAR6 ,
output VAR2 ,
input VAR3 ,
input VAR7,
input VAR10,
input VAR1
);
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v | 201,262 | module MODULE1
VAR123 = 2,
VAR256 = 1,
VAR149 = 8,
VAR230 = 1,
VAR121 = 1,
VAR78 = 6,
VAR244 = 1,
VAR29 = 10,
VAR71 = 0,
VAR207 = 0,
VAR16 = 2,
VAR88 = 1,
VAR12 = 1,
VAR122 = "VAR233",
VAR174 = 0
)
(
VAR249,
VAR145,
VAR235,
VAR183,
VAR241,
VAR213,
VAR58,
VAR21,
VAR54,
VAR49, VAR38,
VAR50,
VAR52,
VAR202,
VAR204,
VAR254,... | gpl-3.0 |
efabless/openlane | designs/jpeg_encoder/src/jpeg_qnr.v | 5,213 | module MODULE1(clk, VAR5, rst, VAR18, din, VAR22, VAR19, dout, VAR20);
parameter VAR16 = 12;
parameter VAR6 = 2 * VAR16;
input clk; input VAR5; input rst;
input VAR18; input [VAR16-1:0] din; input [ 7:0] VAR22;
output [ 5:0] VAR19; output [10:0] dout; output VAR20;
wire [VAR6-1:0] VAR17; wire [VAR16-1:0] VAR15; wire [V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi_1.v | 2,483 | module MODULE2 (
VAR9 ,
VAR10 ,
VAR1 ,
VAR7 ,
VAR2 ,
VAR12 ,
VAR8,
VAR3,
VAR6 ,
VAR4
);
output VAR9 ;
input VAR10 ;
input VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR12 ;
input VAR8;
input VAR3;
input VAR6 ;
input VAR4 ;
VAR5 VAR11 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR8(... | apache-2.0 |
anderson1008/PAB-NOC | RTL/Top.v | 5,257 | module MODULE1 (VAR69, VAR27, VAR70, VAR6, VAR83, VAR18, clk, reset, VAR2, VAR16, VAR3, VAR75, VAR24, VAR71, VAR17, VAR51, VAR40, VAR64);
input [VAR86-1:0] VAR69, VAR27, VAR70, VAR6,VAR83;
input clk, reset,VAR18;
input [3:0] VAR2, VAR16;
output reg [VAR86-1:0] VAR3, VAR75, VAR24, VAR71,VAR17;
output VAR51;
output [3:0]... | gpl-2.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/BypassWire.v | 1,373 | module MODULE1(VAR3, VAR2);
parameter VAR1 = 1;
input [VAR1 - 1 : 0] VAR2;
output [VAR1 - 1 : 0] VAR3;
assign VAR3 = VAR2;
endmodule | gpl-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_buffer.v | 1,749 | module MODULE1 #(
parameter VAR12 = 8,
parameter VAR8 = 1
) (
input VAR14,
input VAR13,
output VAR1,
input VAR7,
output VAR17,
input [VAR12-1:0] VAR10,
output VAR9,
input VAR6,
output [VAR12-1:0] VAR5
);
reg [VAR12-1:0] VAR16[0:(1 << VAR8)-1];
reg [VAR8-1:0] VAR3;
reg [VAR8-1:0] VAR15;
reg [VAR8:0] VAR2;
wire VAR11 = V... | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_two_buncher.v | 2,995 | module MODULE1 #(parameter VAR4(VAR5))
(input VAR15
, input VAR22
, input [VAR5-1:0] VAR16
, input VAR17
, output VAR12
, output [VAR5*2-1:0] VAR10
, output [1:0] VAR1
, input [1:0] VAR6
);
logic [VAR5-1:0] VAR9, VAR7;
logic VAR20, VAR19, VAR2;
always @(posedge VAR15)
assert ( (VAR6[1] !== 1'b1) | VAR6[0])
else ("VAR8 ... | bsd-3-clause |
jas0n1ee/THU-DSD | FB/ip/ISP1362/ISP1362_IF.v | 2,457 | module MODULE1( VAR15,
VAR3,
VAR1,
VAR18,
VAR9,
VAR11,
VAR26,
VAR25,
VAR19,
VAR12,
VAR7,
VAR4,
VAR5,
VAR21,
VAR20,
VAR16,
VAR10,
VAR22,
VAR27,
VAR2,
VAR6,
VAR8,
VAR24,
VAR14,
VAR17,
VAR13
);
input [15:0] VAR15;
input VAR1;
input VAR18;
input VAR9;
input VAR11;
input VAR26;
input VAR25;
output [15:0] VAR3;
output VAR19;... | mit |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/clock_n210.v | 3,389 | module MODULE1
(
input VAR41, input VAR25, output VAR54,
output VAR69,
output VAR71,
output VAR35,
output VAR32
);
wire [7:0] VAR79;
wire VAR73, VAR66, VAR64, VAR58, VAR77, VAR7, VAR31;
assign VAR31 = ~VAR7;
VAR28 # (
.VAR50 ("1X"),
.VAR27 (2.0),
.VAR11 (4),
.VAR45 (5),
.VAR83 ("VAR49"),
.VAR80 (10.000),
.VAR29 ("VAR74... | lgpl-3.0 |
mamijaz/RISC-V | src/riscv_pipeline/instruction_fetch/INSTRUCTION_FETCH_STAGE.v | 2,013 | module MODULE1 #(
parameter VAR6 = 32 ,
parameter VAR11 = 1'b1 ,
parameter VAR12 = 1'b0
) (
input VAR3 ,
input VAR1 ,
input VAR8 ,
input [VAR6 - 1 : 0] VAR9 ,
input VAR10 ,
output [VAR6 - 1 : 0] VAR5 ,
output VAR7
);
reg [VAR6 - 1 : 0] VAR4 ;
reg VAR2 ;
always@(posedge VAR3)
begin
if(VAR8 == VAR12)
begin
if(VAR1 == VAR... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4/sky130_fd_sc_hdll__nand4.pp.blackbox.v | 1,328 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1 ,
VAR9 ,
VAR7 ,
VAR5,
VAR3,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR9 ;
input VAR7 ;
input VAR5;
input VAR3;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
secworks/sha1 | src/rtl/sha1_w_mem.v | 8,231 | module MODULE1(
input wire clk,
input wire VAR11,
input wire [511 : 0] VAR13,
input wire VAR36,
input wire VAR26,
output wire [31 : 0] VAR7
);
reg [31 : 0] VAR32 [0 : 15];
reg [31 : 0] VAR27;
reg [31 : 0] VAR23;
reg [31 : 0] VAR16;
reg [31 : 0] VAR3;
reg [31 : 0] VAR6;
reg [31 : 0] VAR37;
reg [31 : 0] VAR34;
reg [31 : ... | bsd-2-clause |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_RVT_TT_210930.v | 73,174 | module MODULE1 (VAR1, VAR16, VAR9, VAR3);
output VAR1;
input VAR16, VAR9, VAR3;
reg VAR10;
wire VAR4, VAR6;
wire VAR8, VAR13, VAR14;
wire VAR11;
not (VAR8, VAR4);
not (VAR14, VAR9);
VAR2 (VAR11, VAR6, VAR8, VAR14);
VAR15 (VAR13, VAR10, VAR6, VAR8, VAR14, VAR11);
buf (VAR1, VAR13);
wire VAR7, VAR5, VAR12;
and (VAR7, VAR... | bsd-3-clause |
efabless/openlane | designs/151/src/TagSRAMs.v | 1,385 | module MODULE1 #(
parameter VAR10 = 2,
parameter VAR9 = 24
)(
input clk,
input VAR14,
input [VAR10-1:0] addr,
input [VAR9-1:0] VAR5,
output [VAR9-1:0] VAR3
);
wire VAR15 = 1'b0; wire VAR4 = 1'b0;
wire [6:0] VAR20 = {{7-VAR10{1'b0}}, addr};
wire [5:0] VAR17 = VAR20[5:0];
localparam VAR2 = 32;
localparam VAR1 = VAR2 - VA... | apache-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_fetch.v | 3,750 | module MODULE1(
clk,
VAR14,
VAR20,
VAR22,
VAR5,
VAR11,
VAR12,
VAR25,
VAR19,
VAR10,
VAR6,
VAR28,
VAR18,
VAR21,
VAR8,
VAR15,
VAR17,
VAR9,
VAR7,
VAR26,
VAR1,
VAR3
);
localparam [VAR24-1:0] VAR13 = 32'h00000000;
input wire clk;
input wire VAR14;
input wire [VAR4-1:0] VAR20;
input wire [VAR4-1:0] VAR22;
input wire VAR5;
inp... | bsd-2-clause |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Clock_Generators.v | 12,019 | module MODULE1
(
VAR4,
VAR10,
VAR3,
VAR6) ;
input VAR4;
input VAR10;
input [0:0] VAR3;
output [0:0] VAR6;
tri0 VAR4;
tri1 VAR10;
reg [0:0] VAR9;
reg [0:0] VAR1;
reg [0:0] VAR7;
wire VAR5;
wire VAR2;
wire VAR8; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxtp/sky130_fd_sc_hvl__dfxtp.blackbox.v | 1,266 | module MODULE1 (
VAR6 ,
VAR7,
VAR1
);
output VAR6 ;
input VAR7;
input VAR1 ;
supply1 VAR4;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/lab3.v | 56,605 | module MODULE1 (
input wire VAR51, input wire VAR262, output wire [14:0] VAR160, output wire [2:0] VAR339, output wire VAR412, output wire VAR8, output wire VAR384, output wire VAR82, output wire VAR413, output wire VAR360, output wire VAR419, output wire VAR63, inout wire [31:0] VAR331, inout wire [3:0] VAR176, inout ... | gpl-2.0 |
mda-ut/AquaTux | fpga/fpga_hw/top_level/imu/imu_controller.v | 1,212 | module MODULE1(
input VAR9,
input [3:0]addr,
input read,
output reg [31:0] VAR4,
input VAR3,
input VAR7,
input VAR10,
output VAR1,
output VAR6,
output VAR12
);
wire [8*32-1:0] VAR13;
VAR8 VAR8(
.VAR11(1'b1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(),
.VAR2(),
.VAR13(VAR13),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR12(VAR12... | gpl-2.0 |
seyedmaysamlavasani/GorillaPP | chisel/Gorilla++/verilog/spMem32.v | 1,356 | module MODULE1(input clk, input reset,
output VAR13,
input VAR14,
input [9:0] VAR26,
input VAR7,
input [1023:0] VAR31,
input [9:0] VAR2,
input VAR29,
output VAR10,
output[1023:0] VAR27,
output[9:0] VAR20,
input VAR11,
input VAR22,
input [15:0] VAR4,
input [7:0] VAR15,
input [19:0] VAR9,
input [3:0] VAR16,
output VAR18,... | bsd-3-clause |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.runs/scfifo_24in_24out_12kb_synth_1/scfifo_24in_24out_12kb_stub.v | 1,497 | module MODULE1(clk, rst, din, VAR1, VAR3, dout, VAR4, VAR2, VAR5)
;
input clk;
input rst;
input [23:0]din;
input VAR1;
input VAR3;
output [23:0]dout;
output VAR4;
output VAR2;
output [0:0]VAR5;
endmodule | gpl-3.0 |
rurume/openrisc_vision_hardware | ISE/or1200_dc_top.v | 10,364 | module MODULE1(
clk, rst,
VAR51, VAR59, VAR16, VAR44, VAR33, VAR77, VAR63,
VAR30, VAR69, VAR42,
VAR18,
VAR21, VAR28, VAR17,
VAR31, VAR67, VAR68, VAR22,
VAR12, VAR54, VAR57, VAR9, VAR23,
VAR14, VAR34, VAR43,
VAR10, VAR66, VAR24
);
parameter VAR1 = VAR40;
input clk;
input rst;
output [VAR1-1:0] VAR51;
output [31:0] VAR59... | gpl-2.0 |
c4puter/bridge-hdl | modules/wb_conmax/wb_conmax_rf.v | 9,761 | module MODULE1(
VAR6, VAR30,
VAR38, VAR24, VAR34, VAR18, VAR26, VAR4,
VAR42, VAR41, VAR19, VAR5,
VAR29, VAR22, VAR15, VAR28, VAR1, VAR11,
VAR45, VAR8, VAR31, VAR27,
VAR23, VAR39, VAR16, VAR20, VAR13, VAR21, VAR14, VAR3,
VAR10, VAR46, VAR36, VAR12, VAR25, VAR17, VAR2, VAR7
);
parameter [3:0] VAR37 = 4'hf;
parameter VAR3... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_3.behavioral.pp.v | 1,236 | module MODULE1( VAR6, VAR4, VAR8, VAR3, VAR7 );
input VAR6, VAR4;
inout VAR3, VAR7;
output VAR8;
VAR1 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8),.VAR3(VAR3),.VAR7(VAR7));
VAR1 VAR5(.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp.behavioral.pp.v | 1,841 | module MODULE1 (
VAR15 ,
VAR9 ,
VAR5,
VAR10,
VAR3,
VAR11 ,
VAR7
);
output VAR15 ;
input VAR9 ;
input VAR5;
input VAR10;
input VAR3;
input VAR11 ;
input VAR7 ;
wire VAR8 ;
wire VAR13;
wire VAR4 ;
reg VAR12 ;
wire VAR1 ;
VAR2 VAR6 (VAR8 , VAR4, VAR13, VAR12, VAR10, VAR3);
buf VAR14 (VAR15 , VAR8 );
assign VAR1 = ( VAR10 ... | apache-2.0 |
hpcn-uam/hardware_packet_train | NetFPGA10G/Verilog/timestamp_insertion_pkt_train.v | 5,852 | module MODULE1
parameter VAR38 = 64,
parameter VAR26 = 256,
parameter VAR4 = 128
)
(
output reg [VAR26-1:0] VAR9,
output reg [VAR4-1:0] VAR50,
output reg [VAR26/8-1:0]VAR20,
output reg VAR45,
output reg VAR31,
input VAR17,
input [VAR38-1:0] VAR39,
input VAR40,
input [VAR26-1:0] VAR41,
input [VAR4-1:0] VAR43,
input [VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3b/sky130_fd_sc_hs__nand3b_1.v | 2,102 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR6 ,
VAR8,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR8;
input VAR2;
VAR4 VAR7 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5 ,
VAR1,
VAR3 ,
VAR6
);
output VAR5 ;
input VAR1;
input VAR3 ... | apache-2.0 |
elegabriel/myzju | junior1/CA/pipeline3/code/EX_ME.v | 1,290 | module MODULE1(
clk,rst,
VAR14, VAR12, VAR2, VAR5, VAR13, VAR3,VAR4,
VAR1, VAR8, VAR10, VAR11, VAR9, VAR7,VAR6
);
input clk,rst;
input wire [31:0] VAR14,VAR2,VAR4;
input wire [4:0] VAR12;
input wire VAR5,VAR13,VAR3;
output reg [31:0] VAR1,VAR10,VAR6;
output reg [4:0] VAR8;
output reg VAR11,VAR9,VAR7;
always @(posedge c... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b.blackbox.v | 1,284 | module MODULE1 (
VAR3 ,
VAR4,
VAR6
);
output VAR3 ;
input VAR4;
input VAR6 ;
supply1 VAR1;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a.blackbox.v | 1,326 | module MODULE1 (
VAR7 ,
VAR2,
VAR4,
VAR8
);
output VAR7 ;
input VAR2;
input VAR4;
input VAR8;
supply1 VAR6;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
nyaxt/dmix | resampler.v | 10,479 | module MODULE1
parameter VAR63 = 8,
parameter VAR37 = 3,
parameter VAR80 = 16,
parameter VAR36 = 4,
parameter VAR27 = 160,
parameter VAR23 = 8,
parameter VAR84 = 147,
parameter VAR20 = VAR23+VAR36,
parameter VAR86 = 64,
parameter VAR53 = 6
)(
input wire clk,
input wire rst,
output wire [(VAR20-1):0] VAR8,
input wire [2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2.blackbox.v | 1,269 | module MODULE1 (
VAR3 ,
VAR4,
VAR2,
VAR1
);
output VAR3 ;
input VAR4;
input VAR2;
input VAR1 ;
supply1 VAR7;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
mindstation/Famicom_mappers | UNROMproj/UNROM_quartus/hc161_like.v | 1,518 | module MODULE1 ( input wire [3:0] VAR7
, input wire VAR2
, input wire VAR6
, output wire VAR1
, output wire VAR8
, output wire VAR3
, output wire VAR4
);
reg [3:0] VAR5;
assign VAR1 = VAR5 [0:0];
assign VAR8 = VAR5 [1:1];
assign VAR3 = VAR5 [2:2];
assign VAR4 = VAR5 [3:3];
always @(posedge VAR6) begin
if (!VAR2) begin
... | mit |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v | 4,487 | module MODULE1 #
(
parameter integer VAR17 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR17-1:0] VAR8 ,
input wire [7:0] VAR5 ,
input wire [2:0] VAR16 ,
input wire VAR15 ,
output wire [VAR17-1:0] VAR6 ,
input wire VAR7 ,
output reg VAR13
);
reg VAR10;
reg [11:0] VAR12;
reg [8:0] VAR4;
reg VAR14;
wire [3:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3_2.v | 2,071 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR1,
VAR7
);
output VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR1;
input VAR7;
VAR8 VAR3 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR4,
VAR6,
VAR5,
VAR2
);
output VAR4;
input VAR6;
input VAR5;
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o.functional.pp.v | 2,290 | module MODULE1 (
VAR5 ,
VAR20 ,
VAR16 ,
VAR10 ,
VAR12 ,
VAR7 ,
VAR8 ,
VAR3,
VAR13
);
output VAR5 ;
input VAR20 ;
input VAR16 ;
input VAR10 ;
input VAR12 ;
input VAR7 ;
input VAR8 ;
input VAR3;
input VAR13;
wire VAR12 VAR15 ;
wire VAR12 VAR9 ;
wire VAR12 VAR6 ;
wire VAR1 ;
wire VAR18;
and VAR14 (VAR15 , VAR10, VAR12 );
... | apache-2.0 |
sirchuckalot/zet | cores/serial/rtl/serial.v | 18,208 | module MODULE1 (
input VAR11, input VAR23, input [15:0] VAR81, output [15:0] VAR14, input VAR48, input VAR69, input [ 1:0] VAR20, input [ 1:0] VAR64, input VAR39, output reg VAR80, output VAR37,
output VAR88, input VAR28 );
reg [7:0] VAR89;
wire [7:0] VAR54;
wire [2:0] VAR17;
wire VAR43;
wire VAR60;
wire VAR76;
wire VA... | gpl-3.0 |
alexforencich/verilog-ethernet | example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 5,277 | module MODULE1 (
input wire VAR1,
input wire VAR24,
input wire VAR53,
input wire VAR42,
input wire VAR6,
input wire VAR57,
output wire VAR28,
output wire VAR3,
output wire VAR16,
output wire VAR29,
output wire VAR9,
output wire VAR22,
input wire VAR18,
input wire VAR71,
output wire VAR50,
input wire VAR94,
output wire ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu_mamul.v | 24,845 | module MODULE1 (
VAR17,
VAR145,
VAR103,
VAR93,
VAR125,
VAR124,
VAR139,
VAR132,
VAR69,
VAR44,
VAR96,
VAR154,
VAR66,
VAR28,
VAR127,
VAR88,
VAR149,
VAR113,
VAR37,
VAR24,
VAR142,
VAR23,
VAR45,
VAR131,
VAR117,
VAR1,
VAR176,
VAR38,
VAR152,
VAR122,
VAR91,
VAR102,
VAR178,
VAR30,
VAR7,
VAR158,
VAR14,
VAR12,
VAR72,
VAR43,
VAR40,... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_compare.v | 3,249 | module MODULE1
(input wire clk,
input wire [VAR9:0] VAR32, VAR2,
output reg VAR23,
output reg [VAR9:0] VAR31, VAR24);
genvar VAR3;
wire [35:0] VAR29;
wire [35:0] VAR10;
wire [35:0] VAR28;
wire [35:0] VAR7 = {1'b0,VAR32[34:0]};
wire [35:0] VAR14 = {1'b0,VAR2[34:0]};
generate
for(VAR3=0; VAR3 <= 35; VAR3 = VAR3 + 2) begi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o.blackbox.v | 1,352 | module MODULE1 (
VAR5 ,
VAR3,
VAR6,
VAR8,
VAR1,
VAR4
);
output VAR5 ;
input VAR3;
input VAR6;
input VAR8;
input VAR1;
input VAR4;
supply1 VAR7;
supply0 VAR2;
endmodule | apache-2.0 |
tomhartley/EIEProj | quartus_proj_DE0/rtl_mgc_ioport_v2001.v | 18,747 | module MODULE1 (clk, en, VAR14, VAR66, VAR29, VAR11, VAR10, VAR44);
parameter integer VAR67 = 1;
parameter integer VAR5 = 8;
parameter VAR13 = 1'b1;
parameter VAR24 = 1'b1;
parameter VAR30 = 1'b1;
input clk;
input en;
input VAR14;
input VAR66;
input VAR29;
input [VAR5-1:0] VAR11;
output VAR10;
output [VAR5-1:0] VAR44;
... | mit |
pradeep9676/pradeep_9676 | boxmuller.v | 1,630 | module MODULE1( clk,reset, VAR18,VAR26,VAR7,VAR17,VAR24,VAR14, VAR10,VAR28,VAR15);
input clk;
input reset;
input[31:0] VAR18,VAR26,VAR7,VAR17,VAR24,VAR14;
wire [31:0] VAR6,VAR12;
wire VAR23,VAR25;
output reg VAR15;
output reg signed [15:0] VAR10,VAR28;
reg [47:0]VAR5;
wire signed [30:0]VAR19;
wire signed [16:0] VAR11;
... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_dmmu_top.v | 12,169 | module MODULE1(
clk, rst,
VAR12, VAR32, VAR3, VAR18, VAR17, VAR34,
VAR44, VAR2,
VAR31, VAR42, VAR40, VAR38, VAR48,
VAR1, VAR15, VAR4,
VAR29, VAR52, VAR47, VAR13, VAR22
);
parameter VAR45 = VAR25;
parameter VAR36 = VAR25;
input clk;
input rst;
input VAR12;
input VAR32;
input VAR3;
input [VAR36-1:0] VAR18;
input VAR17;
i... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_cclk_inv_96x.v | 1,293 | module MODULE1 (
VAR1,
VAR2 );
output VAR1;
input VAR2;
assign VAR1 = ~( VAR2 );
endmodule | gpl-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/m26_rx/m26_rx_core.v | 10,178 | module MODULE1 #(
parameter VAR77 = 16,
parameter VAR35 = 0,
parameter VAR3 = 0
) (
input wire VAR72,
input wire VAR45,
input wire [1:0] VAR48,
input wire VAR19,
output wire VAR67,
output wire [31:0] VAR1,
input wire VAR41,
input wire [VAR77-1:0] VAR12,
input wire [7:0] VAR13,
output reg [7:0] VAR99,
input wire VAR73,
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv_4.v | 2,003 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR8,
VAR2,
VAR5 ,
VAR7
);
output VAR6 ;
input VAR3 ;
input VAR8;
input VAR2;
input VAR5 ;
input VAR7 ;
VAR4 VAR1 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR8;
supply0 VAR2;... | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/SOC_NIOS_II_jtag_debug_module_wrapper.v | 9,876 | module MODULE1 (
VAR35,
VAR49,
clk,
VAR32,
VAR47,
VAR60,
VAR53,
VAR59,
VAR5,
VAR29,
VAR10,
VAR58,
VAR15,
VAR43,
VAR44,
VAR13,
VAR48,
VAR51,
VAR1,
VAR17,
VAR8,
VAR31,
VAR34,
VAR19,
VAR21,
VAR23,
VAR3,
VAR42,
VAR56,
VAR57,
VAR33,
VAR24,
VAR6,
VAR39,
VAR27,
VAR2
)
;
output [ 37: 0] VAR8;
output VAR31;
output VAR34;
output... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxbp/sky130_fd_sc_hd__edfxbp.pp.blackbox.v | 1,398 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR8 ,
VAR9 ,
VAR3 ,
VAR1,
VAR7,
VAR6 ,
VAR4
);
output VAR5 ;
output VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR3 ;
input VAR1;
input VAR7;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_sstl_dq_pad.v | 5,669 | module MODULE1(
VAR3, VAR30, VAR5,
VAR24,
VAR17, VAR9, VAR4, VAR7, VAR10, VAR26, VAR27, VAR13, VAR21,
VAR1, VAR11, VAR23, VAR14, VAR22, VAR31,
VAR34, VAR25, VAR18, VAR15, clk, VAR29
);
inout VAR24;
output VAR3; output VAR30; output VAR5;
input VAR17; input VAR9; input [7:0] VAR4; input VAR7; input [8:1] VAR10; input [8... | gpl-2.0 |
ZiCog/P8X32A_Emulation | P8X32A_DE0_Nano/cog_ctr.v | 3,794 | module MODULE1
(
input VAR9,
input VAR19,
input VAR2,
input VAR21,
input VAR5,
input VAR14,
input [31:0] VAR13,
input [31:0] VAR16,
output reg [32:0] VAR12,
output [31:0] VAR15,
output VAR10
);
reg [31:0] VAR17;
reg [31:0] VAR3;
always @(posedge VAR9 or negedge VAR2)
if (!VAR2)
VAR17 <= 32'b0;
else if (VAR21)
VAR17 <= ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3b/sky130_fd_sc_lp__and3b.pp.symbol.v | 1,307 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR6 ,
output VAR3 ,
input VAR1 ,
input VAR8,
input VAR5,
input VAR7
);
endmodule | apache-2.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/command_decoder.v | 5,301 | module MODULE1(
clk,
VAR10,
VAR18,
VAR12,
VAR8,
VAR17,
VAR14,
VAR15,
VAR2
);
input clk;
input VAR10;
input [VAR13-1:0] VAR18;
output reg VAR12;
output reg VAR8;
output reg VAR17;
output reg VAR14;
output reg VAR15;
output reg VAR2;
reg [VAR13-1:0] VAR7;
always @(posedge clk or negedge VAR10)
begin
if (~VAR10)
begin
VAR... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.functional.v | 2,099 | module MODULE1( VAR4, VAR12, VAR2, VAR23, VAR13, VAR15 );
input VAR13, VAR15, VAR23, VAR2, VAR12;
output VAR4;
wire VAR3;
not VAR5( VAR3, VAR13 );
wire VAR16;
not VAR7( VAR16, VAR23 );
wire VAR18;
not VAR19( VAR18, VAR12 );
wire VAR6;
and VAR10( VAR6, VAR3, VAR16, VAR18 );
wire VAR14;
not VAR25( VAR14, VAR2 );
wire VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4_0.v | 2,242 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR2 ,
VAR9,
VAR10,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR2 ;
input VAR9;
input VAR10;
input VAR4 ;
input VAR3 ;
VAR11 VAR7 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai_4.v | 2,435 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR8 ,
VAR7 ,
VAR11 ,
VAR12 ,
VAR4,
VAR10,
VAR2 ,
VAR3
);
output VAR9 ;
input VAR6 ;
input VAR8 ;
input VAR7 ;
input VAR11 ;
input VAR12 ;
input VAR4;
input VAR10;
input VAR2 ;
input VAR3 ;
VAR1 VAR5 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR4... | apache-2.0 |
sabertazimi/hust-lab | digitalLogic/design/washmach_design/src/controler.v | 14,764 | module MODULE1
(
input VAR45, input VAR72, input VAR69, input VAR22, input VAR28,
output VAR71,output [2:0]VAR78, output VAR64,
output VAR86, output reg VAR40, output reg VAR5,
output reg VAR33, output VAR79,
output [7:0]VAR68, output [7:0]VAR1, output reg [2:0]state,
output VAR18
);
reg [2:0]VAR39;
reg [2:0]VAR21; reg... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/attic/audio_clock.v | 17,311 | module MODULE1 (
input wire VAR5, input wire rst, output wire VAR6, output wire VAR1 );
VAR2 VAR3 (
.VAR5 (VAR5), .rst (rst), .VAR6 (VAR6), .VAR1 (VAR1), .VAR4 () );
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_aluaddsub.v | 3,775 | module MODULE1
(
VAR21, VAR3, VAR1, VAR4,
VAR12, VAR26,
clk, VAR22, VAR25, VAR18, VAR16,
VAR20
);
input clk;
input VAR22;
input [63:0] VAR25; input [63:0] VAR18; input VAR16; input VAR20;
output [63:0] VAR21; output [63:0] VAR3; output VAR1;
output VAR4;
output VAR12;
output VAR26;
wire [63:0] VAR14; wire [63:0] VAR11;... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_2.behavioral.v | 8,908 | module MODULE1( VAR75, VAR17, VAR14, VAR80, VAR10 );
input VAR80, VAR14, VAR75, VAR17;
output VAR10;
reg VAR37;
VAR35 VAR5(.VAR75(VAR75),.VAR17(VAR17),.VAR14(VAR14),.VAR80(VAR80),.VAR10(VAR10),.VAR37(VAR37));
VAR35 VAR19(.VAR75(VAR75),.VAR17(VAR17),.VAR14(VAR14),.VAR80(VAR80),.VAR10(VAR10),.VAR37(VAR37));
not VAR41(VAR... | apache-2.0 |
LordRafa/Sobel-FPGA | SISSources/V/Sobel.v | 7,505 | module MODULE1 (
input clk,
input rst,
output [31:0] VAR4,
output VAR17,
input wire [8:0] VAR11,
output wire[31:0] VAR16,
input VAR20,
input VAR37,
output wire[3:0] VAR24,
output wire VAR33,
input wire[31:0] VAR35,
output wire[5:0] VAR8,
input VAR47,
output VAR38,
input [31:0] VAR7
);
parameter VAR2=32;
parameter VAR49... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/J1_soc-master/hdl/MicrofonoFIFO/interface_microfono.v | 2,296 | module MODULE1(clk, reset, din, VAR16, addr, rd, wr, dout, VAR20, VAR17, VAR15);
input wire clk;
input wire reset;
input wire [15:0] din;
input wire VAR16;
input wire [3:0] addr;
input wire rd;
input wire wr;
output wire dout;
output wire VAR20;
output wire VAR17;
input wire VAR15;
VAR1 VAR1(
.reset(reset),
.clk(clk),
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311ai/sky130_fd_sc_hs__o311ai.functional.v | 1,957 | module MODULE1 (
VAR4,
VAR14,
VAR10 ,
VAR12 ,
VAR1 ,
VAR11 ,
VAR2 ,
VAR5
);
input VAR4;
input VAR14;
output VAR10 ;
input VAR12 ;
input VAR1 ;
input VAR11 ;
input VAR2 ;
input VAR5 ;
wire VAR2 VAR15 ;
wire VAR7 ;
wire VAR8;
or VAR16 (VAR15 , VAR1, VAR12, VAR11 );
nand VAR6 (VAR7 , VAR5, VAR15, VAR2 );
VAR3 VAR13 (VAR8,... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.functional.v | 2,099 | module MODULE1( VAR13, VAR9, VAR5, VAR7, VAR3, VAR17 );
input VAR17, VAR3, VAR9, VAR13, VAR5;
output VAR7;
wire VAR23;
not VAR1( VAR23, VAR17 );
wire VAR25;
not VAR21( VAR25, VAR9 );
wire VAR10;
not VAR2( VAR10, VAR5 );
wire VAR18;
and VAR6( VAR18, VAR23, VAR25, VAR10 );
wire VAR16;
not VAR12( VAR16, VAR13 );
wire VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.behavioral.v | 3,781 | module MODULE1( VAR2, VAR27, VAR23, VAR17 );
input VAR2, VAR27, VAR23;
output VAR17;
reg VAR1;
VAR32 VAR16(.VAR2(VAR2),.VAR27(VAR27),.VAR23(VAR23),.VAR17(VAR17),.VAR1(VAR1));
VAR32 VAR20(.VAR2(VAR2),.VAR27(VAR27),.VAR23(VAR23),.VAR17(VAR17),.VAR1(VAR1));
not VAR5(VAR25,VAR27);
and VAR8(VAR28,VAR23,VAR25);
and VAR19(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf.pp.blackbox.v | 1,223 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR5,
VAR4,
VAR3 ,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR5;
input VAR4;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9144/axi_ad9144_if.v | 5,623 | module MODULE1 (
VAR9,
VAR5,
VAR6,
VAR8,
VAR16,
VAR12,
VAR15,
VAR3,
VAR18,
VAR11,
VAR4,
VAR14,
VAR2,
VAR20,
VAR13,
VAR7,
VAR10,
VAR19,
VAR1,
VAR17);
input VAR9;
output [255:0] VAR5;
output VAR6;
input VAR8;
input [15:0] VAR16;
input [15:0] VAR12;
input [15:0] VAR15;
input [15:0] VAR3;
input [15:0] VAR18;
input [15:0] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi_1.v | 2,261 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR7,
VAR4,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR7;
input VAR4;
input VAR6 ;
input VAR5 ;
VAR8 VAR10 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/b73b442e1fb83bed/ip_design_nco_0_0_stub.v | 2,652 | module MODULE1(VAR5,
VAR7, VAR2, VAR12,
VAR15, VAR4, VAR9,
VAR18, VAR19, VAR3,
VAR16, VAR11, VAR13,
VAR10, VAR6, VAR17,
VAR8, VAR14, VAR1)
;
input [5:0]VAR5;
input VAR7;
output VAR2;
input [31:0]VAR12;
input [3:0]VAR15;
input VAR4;
output VAR9;
output [1:0]VAR18;
output VAR19;
input VAR3;
input [5:0]VAR16;
input VAR11;... | mit |
Mahdi89/eTeak | tech/st65-mapping.v | 3,443 | module MODULE1 (output VAR9, input VAR5, VAR15);
VAR14 VAR1 (VAR9, VAR5, VAR15);
endmodule
module MODULE7 (output VAR9, input VAR5, VAR15, VAR31);
VAR4 VAR1 (VAR9, VAR5, VAR15, VAR31);
endmodule
module MODULE4 (output VAR9, input VAR5, VAR15);
VAR10 VAR1 (VAR9, VAR5, VAR15);
endmodule
module MODULE12 (output VAR9, inpu... | bsd-3-clause |
eda-globetrotter/MarcheProcessor | src/control.v | 5,647 | module MODULE1(VAR26,
VAR29, VAR19,
VAR7, VAR27, VAR11, VAR24,
VAR13, VAR30, VAR4, VAR10,
VAR31,
VAR33,
VAR2);
input [0:31] VAR26;
output [0:4] VAR29, VAR30, VAR4, VAR10;
output [0:2] VAR13;
output [0:1] VAR19;
output [0:20] VAR11;
output VAR7, VAR27;
output VAR31, VAR33;
output [0:15] VAR24;
output [0:127] VAR2;
reg [... | mit |
theapi/nand2tetris_fpga | hack/rtl/verilog/cpu.v | 6,110 | module MODULE1 (
input clk,
input reset,
input [15:0] VAR19,
input [15:0] VAR6,
output [15:0] VAR2,
output [14:0] VAR37,
output VAR18,
output [14:0] VAR20,
output [15:0] VAR31,
output [15:0] VAR14
);
parameter VAR28 = 32'd5;
reg [15:0] VAR25 = 16'b0;
reg [14:0] VAR10 = 15'b0;
reg VAR26 = 0;
reg VAR36 = 0;
reg VAR15 = 0... | mit |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii/synthesis/submodules/niosii_altpll_0.v | 11,591 | module MODULE1
(
VAR2,
VAR7,
VAR9,
VAR6) ;
input VAR2;
input VAR7;
input [0:0] VAR9;
output [0:0] VAR6;
tri0 VAR2;
tri1 VAR7;
reg [0:0] VAR1;
reg [0:0] VAR3;
reg [0:0] VAR10;
wire VAR5;
wire VAR4;
wire VAR8; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4_1.v | 2,275 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR5 ,
VAR9 ,
VAR8 ,
VAR10,
VAR6,
VAR4 ,
VAR11
);
output VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR9 ;
input VAR8 ;
input VAR10;
input VAR6;
input VAR4 ;
input VAR11 ;
VAR1 VAR3 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR4(VAR4),
.VA... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_decoder_32_syn.v | 31,740 | module MODULE3
(
VAR127,
VAR75) ;
input [5:0] VAR127;
output [63:0] VAR75;
tri0 [5:0] VAR127;
wire [5:0] VAR115;
wire [63:0] VAR86;
wire [63:0] VAR64;
wire [3:0] VAR30;
wire [3:0] VAR51;
wire [3:0] VAR114;
wire [3:0] VAR12;
wire [3:0] VAR61;
wire [3:0] VAR40;
wire [3:0] VAR8;
wire [3:0] VAR84;
wire [3:0] VAR77;
wire [3... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b.symbol.v | 1,349 | module MODULE1 (
input VAR5 ,
input VAR7 ,
input VAR2,
output VAR4
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/Raster_Laser_Projector_Video_In_video_clipper_0.v | 8,056 | module MODULE1 (
clk,
reset,
VAR24,
VAR17,
VAR30,
VAR42,
VAR44,
VAR16,
VAR45,
VAR40,
VAR11,
VAR36,
VAR23,
VAR12
);
parameter VAR15 = 7; parameter VAR32 = 0;
parameter VAR3 = 720; parameter VAR9 = 244; parameter VAR1 = 9; parameter VAR39 = 7;
parameter VAR34 = 40;
parameter VAR28 = 40;
parameter VAR38 = 2;
parameter VAR... | gpl-3.0 |
strigeus/fpganes | src/dsp.v | 11,679 | module MODULE2(input clk, input VAR31, input [17:0] VAR33, input [17:0] VAR10, input [17:0] VAR5, output [47:0] VAR40);
wire [7:0] VAR24 = VAR31 ? 8'b00011001 : 8'b00010001;
VAR1 #(
.VAR23(0), .VAR16(0), .VAR21(0), .VAR47(0), .VAR34(0), .VAR32("VAR38"), .VAR22(0), .VAR49(0), .VAR15(0), .VAR41(0), .VAR19(0), .VAR2(1), .... | gpl-3.0 |
GSejas/Karatsuba_FPU | my_sourcefiles/cordic_jorge/CORDIC_FSM_v3.v | 4,344 | module MODULE1
(
input wire clk, input wire reset, input wire VAR14, input wire VAR20, input wire VAR16,
input wire VAR12, input wire VAR5, input wire VAR15,
output reg VAR11,
output reg VAR3, output reg VAR25, output reg VAR19, output reg VAR2, output reg VAR22, VAR9, VAR17,
output reg VAR1
);
localparam [3:0] VAR18 =... | gpl-3.0 |
Diego-HR/SystemC-Fails | dflipflop/model/dflipflop_post_build.v | 1,322 | module MODULE1(din, clk, reset, dout);
input din;
input clk;
input reset;
output reg dout;
always begin : VAR4
reg VAR2;
reg VAR3;
reg VAR1;
VAR3 = 1'b0;
if (reset) begin
dout <= 1'b0;
VAR3 = 1'b1;
end
else begin
VAR1 = din;
dout <= VAR1;
VAR3 = 1'b1;
end
if (VAR3 == 1'b1) begin
VAR3 = 1'b0;
VAR2 <= 1'b0;
end
@(posedge... | gpl-2.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/verilog/axi_vdma_v6_2_axis_register_slice_v1_0_axisc_register_slice.v | 19,751 | module MODULE1 #
(
parameter VAR7 = "VAR2",
parameter VAR8 = 32,
parameter VAR22 = 32'h00000000
)
(
input wire VAR19,
input wire VAR1,
input wire VAR17,
input wire [VAR8-1:0] VAR6,
input wire VAR18,
output wire VAR13,
output wire [VAR8-1:0] VAR16,
output wire VAR26,
input wire VAR11
);
generate
if (VAR22 == 32'h0000000... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/add_rm_hdr/rm_hdr.v | 2,676 | module MODULE1
parameter VAR22 = 64,
parameter VAR3 = VAR22/8
)
(
VAR10,
VAR21,
VAR23,
VAR24,
VAR1,
VAR6,
VAR14,
VAR18,
reset,
clk
);
input [VAR22-1:0] VAR10;
input [VAR3-1:0] VAR21;
input VAR23;
output VAR24;
output [VAR22-1:0] VAR1;
output [VAR3-1:0] VAR6;
output reg VAR14;
input VAR18;
input reset;
input clk;
functi... | mit |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_0_ui_top.v | 15,318 | module MODULE1 #
(
parameter VAR86 = 100,
parameter VAR34 = 256,
parameter VAR75 = 32,
parameter VAR17 = 3,
parameter VAR26 = 12,
parameter VAR82 = 5,
parameter VAR88 = 5,
parameter VAR12 = "VAR4",
parameter VAR89 = "VAR4",
parameter VAR1 = "VAR83",
parameter VAR40 = 2,
parameter VAR50 = 4,
parameter VAR39 = "VAR44", p... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb.functional.pp.v | 1,998 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR12 ,
VAR11 ,
VAR5 ,
VAR8,
VAR14,
VAR10 ,
VAR6
);
output VAR2 ;
input VAR3 ;
input VAR12 ;
input VAR11 ;
input VAR5 ;
input VAR8;
input VAR14;
input VAR10 ;
input VAR6 ;
wire VAR17 ;
wire VAR4 ;
wire VAR15;
nor VAR9 (VAR17 , VAR3, VAR12 );
and VAR7 (VAR4 , VAR17, VAR11, VAR5 );
VAR16 VA... | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/bench/capture/fake_signal.v | 3,435 | module MODULE1
parameter VAR9 = VAR13-1,
parameter VAR20 = 12,
parameter VAR7 = VAR20-1,
parameter VAR25 = 0,
parameter VAR12 = 1,
parameter VAR24 = 1,
parameter VAR19 = 3)
(
input VAR21,
input reset,
input enable,
output VAR16,
output VAR22,
output [VAR9:0] VAR28
);
reg [VAR9:0] VAR10 = 'VAR27; wire [VAR9:0] VAR26, VA... | lgpl-3.0 |
dmlloyd/PBIBox | etherpbi/cpld/EtherPBI.v | 9,514 | module MODULE1(
inout tri [15:0] VAR8,
input wire VAR47,
input wire VAR23,
input wire VAR10,
output wire VAR22,
output wire VAR17,
output tri VAR43,
inout tri VAR11,
output wire VAR26,
output wire VAR3,
output wire VAR25,
output wire [9:0] VAR41,
inout tri [7:0] VAR19,
input wire [2:0] VAR45,
output tri VAR33,
output t... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.behavioral.pp.v | 1,164 | module MODULE1( VAR3, VAR6, VAR4, VAR5 );
input VAR3;
inout VAR4, VAR5;
output VAR6;
VAR2 VAR1(.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5));
VAR2 VAR7(.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.symbol.v | 1,478 | module MODULE1 (
input VAR7 ,
output VAR3 ,
input VAR6 ,
input VAR2 ,
input VAR5,
input VAR1 ,
input VAR4
);
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/snescmd_buf.v | 10,669 | module MODULE1 (
VAR38,
VAR28,
VAR34,
VAR48,
VAR20,
VAR10,
VAR56,
VAR24,
VAR33);
input [8:0] VAR38;
input [8:0] VAR28;
input VAR34;
input [7:0] VAR48;
input [7:0] VAR20;
input VAR10;
input VAR56;
output [7:0] VAR24;
output [7:0] VAR33;
tri1 VAR34;
tri0 VAR10;
tri0 VAR56;
wire [7:0] VAR30;
wire [7:0] VAR2;
wire [7:0] VA... | gpl-2.0 |
sh-chris110/chris | FPGA/chris.system_ok/db/ip/soc_design/submodules/soc_design_niosII_core.v | 6,655 | module MODULE1 (
input wire clk, input wire VAR30, input wire VAR2, output wire [16:0] VAR5, output wire [3:0] VAR10, output wire VAR26, input wire [31:0] VAR15, input wire VAR4, output wire VAR28, output wire [31:0] VAR13, output wire [3:0] VAR19, input wire VAR25, output wire VAR17, output wire [16:0] VAR9, output wi... | gpl-2.0 |
TheMadSocrates/vercpu-project | rtl/fpga/sseg_driver.v | 1,922 | module MODULE1(
input wire [ 3 : 0] VAR1,
input wire [ 1 : 0] sel,
output reg [ 3 : 0] VAR3,
output reg [ 6 : 0] VAR2
);
always @(sel) begin
case(sel)
2'b00: VAR3 = 4'b1110;
2'b01: VAR3 = 4'b1101;
2'b10: VAR3 = 4'b1011;
2'b11: VAR3 = 4'b0111;
endcase
end
always @(VAR1) begin
case(VAR1)
4'h0: VAR2 = 7'b0000001;
4'h1: VA... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/image_filter_Block_Mat_exit1220_proc1.v | 30,482 | module MODULE1 (
VAR69,
VAR66,
VAR121,
VAR77,
VAR23,
VAR114,
VAR27,
VAR56,
VAR6,
VAR20,
VAR151,
VAR73,
VAR1,
VAR13,
VAR153,
VAR60,
VAR124,
VAR91,
VAR107,
VAR81,
VAR49,
VAR148,
VAR104,
VAR7,
VAR149,
VAR127,
VAR143,
VAR63,
VAR95,
VAR54,
VAR84,
VAR32,
VAR129,
VAR10,
VAR101,
VAR83,
VAR152,
VAR146,
VAR50,
VAR26,
VAR156,
VAR... | gpl-3.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-kc705/mig_interface_model.v | 4,476 | module MODULE1
(
input [27:0] VAR2,
input [2:0] VAR28,
input VAR8,
input [511:0] VAR11,
input VAR30,
input [63:0] VAR17,
input VAR35,
output wire [511:0] VAR6,
output wire VAR27,
output wire VAR26,
output wire VAR10,
output wire VAR19,
output reg VAR22,
output reg VAR15,
output reg VAR20,
input VAR32
);
parameter VAR25... | gpl-2.0 |
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