repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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Jafet95/proy_3_grupo_2_sem_1_2016 | generador_imagenes_v2.v | 7,750 | module MODULE1
(
input clk,
input reset,
input wire VAR3,input wire [9:0] VAR40, VAR6,
output wire VAR24,
output wire [7:0] VAR36
);
localparam VAR28 = 256; localparam VAR48 = 384; localparam VAR43 = 64; localparam VAR5 = 8192;
localparam VAR50 = 416; localparam VAR12 = 496; localparam VAR47 = 416; localparam VAR7 = 47... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a_1.v | 2,422 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR6 ,
VAR9 ,
VAR8 ,
VAR2 ,
VAR11,
VAR7,
VAR3 ,
VAR12
);
output VAR5 ;
input VAR1 ;
input VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR11;
input VAR7;
input VAR3 ;
input VAR12 ;
VAR4 VAR10 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR11(VAR... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_reset_sync.v | 1,925 | module MODULE1(
VAR4,
clk,
VAR1
);
parameter VAR2 = 4;
parameter VAR6 = 1;
input VAR4;
input clk;
output [VAR6-1:0] VAR1;
reg [VAR2+VAR6-2:0] VAR5 ;
generate
genvar VAR3;
for (VAR3=0; VAR3<VAR2+VAR6-1; VAR3=VAR3+1)
begin: VAR7
always @(posedge clk or negedge VAR4)
begin
if (~VAR4)
VAR5[VAR3] <= 1'b0;
end
else
begin
if ... | lgpl-3.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/VGA_Audio_PLL.v | 17,272 | module MODULE1 (
VAR33,
VAR42,
VAR71,
VAR13,
VAR80);
input VAR33;
input VAR42;
output VAR71;
output VAR13;
output VAR80;
wire [5:0] VAR98;
wire [0:0] VAR53 = 1'h0;
wire [2:2] VAR103 = VAR98[2:2];
wire [1:1] VAR91 = VAR98[1:1];
wire [0:0] VAR22 = VAR98[0:0];
wire VAR71 = VAR22;
wire VAR13 = VAR91;
wire VAR80 = VAR103;
w... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/util_axis_upscale.v | 4,164 | module MODULE1 # (
parameter VAR11 = 4,
parameter VAR8 = 24,
parameter VAR10 = 32)(
input clk,
input VAR5,
input VAR1,
output reg VAR19,
input [(VAR11*VAR8)-1:0] VAR6,
output reg VAR3,
input VAR12,
output reg [(VAR11*VAR10)-1:0] VAR18,
input VAR13,
input VAR4,
input VAR14);
wire VAR7;
wire VAR9;
wire VAR2;
wire [(VAR11... | mit |
fallen/milkymist-mmu | boards/milkymist-one/standby/standby.v | 5,686 | module MODULE1(
input VAR23,
input VAR1,
input VAR36,
input VAR62,
output VAR22,
output VAR53,
output VAR60,
output VAR30,
output VAR25,
output VAR47,
output VAR19,
output VAR5,
output VAR3,
output VAR13,
output VAR26,
output VAR18,
output VAR54,
output VAR55,
output VAR57,
output VAR37,
output VAR11,
output VAR21,
out... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_reg_instances.v | 39,888 | module MODULE1
parameter VAR87 = 13,
parameter VAR131 = 8,
parameter VAR17 = 2,
parameter VAR108 = 8,
parameter VAR69 = VAR12(VAR108),
parameter VAR152 = 11,
parameter VAR125 = VAR152-VAR12(VAR131),
parameter VAR3 = 2048/VAR131, parameter VAR116 = 60/VAR131 + 1,
parameter VAR33 = VAR12((2**VAR87)/VAR116)
)
(
output [VA... | mit |
devinacker/sd2snes | verilog/sd2snes_cx4/mcu_cmd.v | 12,849 | module MODULE1(
input clk,
input VAR55,
input VAR25,
input [7:0] VAR9,
input [7:0] VAR37,
output [2:0] VAR6,
output VAR22,
output VAR12,
output VAR30,
input VAR21,
output [7:0] VAR15,
input [7:0] VAR26,
output [7:0] VAR49,
input [31:0] VAR48,
input [2:0] VAR43,
output [23:0] VAR16,
output [23:0] VAR35,
output [23:0] VA... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v | 5,453 | module MODULE1 (
VAR16, VAR12, VAR10, VAR30, VAR35, VAR14, VAR6, VAR25, VAR22, VAR2,
VAR8, VAR29, VAR32, VAR13, VAR15, VAR28, VAR33,
VAR21, VAR19, VAR26
);
output [15:0] VAR16;
output [4:0] VAR12, VAR10, VAR30;
output [10:0] VAR35;
output [5:0] VAR14;
output [31:0] VAR6;
output [31:0] VAR25;
output VAR22;
input VAR8;
i... | gpl-2.0 |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab7/one_pulse.v | 1,307 | module MODULE1(
output reg out,
input in,
input clk,
input VAR5
);
parameter VAR4 = 0;
parameter VAR2 = 1;
reg state, VAR1, VAR3;
always @(posedge clk or negedge VAR5) begin
if (!VAR5) begin
state <= VAR4;
out <= 0;
end else begin
state <= VAR1;
out <= VAR3;
end end
always @(*) begin
case (state)
VAR4: begin if (in == ... | mit |
chaohu/Daily-Learning | Verilog/lab2/lab2_1/lab1_4_2/lab1_4_2.srcs/sources_1/new/bcdto7segment_dataflow.v | 1,109 | module MODULE1(
input [3:0] VAR3,
output [3:0] VAR1,
output [6:0] VAR2
);
assign VAR1 = VAR3;
assign VAR2[6] = (VAR3[2]&(~VAR3[1])&(~VAR3[0]))|((~VAR3[3])&(~VAR3[2])&(~VAR3[1])&VAR3[0]);
assign VAR2[5] = (VAR3[2]&(~VAR3[1])&VAR3[0])|(VAR3[2]&VAR3[1]&(~VAR3[0]));
assign VAR2[4] = (~VAR3[3])&(~VAR3[2])&VAR3[1]&(~VAR3[0])... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/rp2a03.v | 5,402 | module MODULE1
(
input VAR47, input VAR50,
input VAR14, input [ 7:0] din, input VAR22, input VAR30, output [ 7:0] dout, output [15:0] VAR16, output VAR49, output VAR37,
input [7:0] VAR28, input [7:0] VAR9, input [ 3:0] VAR46, output VAR36,
input [ 3:0] VAR21, input [ 7:0] VAR18, input VAR19, output [ 7:0] VAR29 );
wire... | mit |
lnls-dig/dsp-cores | hdl/modules/cic/cic_decim.v | 6,864 | module MODULE1
parameter VAR23 = 16,
parameter VAR32 = VAR23,
parameter VAR11 = 2,
parameter VAR20 = 5,
parameter VAR8 = 64,
parameter VAR7 = 35, parameter VAR15 = 0
)
(
input VAR13,
input VAR1,
input VAR14,
input [VAR23-1:0] VAR25,
output [VAR32-1:0] VAR27,
input VAR3,
input VAR26,
output VAR18
);
localparam VAR10 = V... | lgpl-3.0 |
felixmo/Pong | keyboard.v | 1,918 | module MODULE1(VAR2, VAR4, VAR6, reset, read, VAR11, VAR12);
input VAR2;
input VAR4;
input VAR6; input reset;
input read;
output VAR11;
output [7:0] VAR12;
reg VAR3;
reg [7:0] VAR12;
reg VAR11;
reg VAR9;
reg VAR7;
reg [3:0] VAR8;
reg [8:0] VAR5;
reg [7:0] VAR1;
reg VAR10;
always @ (posedge VAR3 or posedge read)
if (rea... | mit |
aap/pdp6 | verilog/iobus_4_connect.v | 4,215 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR38,
input wire VAR52,
input wire VAR48,
input wire VAR63,
input wire VAR61,
input wire VAR69,
input wire VAR2,
input wire VAR6,
input wire VAR30,
input wire [3:9] VAR39,
input wire [0:35] VAR50,
output wire [1:7] VAR45,
output wire [0:35] VAR75,
output wir... | mit |
e33b1711/rfnoc_pp_channelizer | custom_sources/noc_block_channelizer_256.v | 4,615 | module MODULE1 #(
parameter VAR68 = 64'h11FB000000000000,
parameter VAR2 = 11)
(
input VAR38, input VAR71,
input VAR50, input VAR43,
input [63:0] VAR19, input VAR52, input VAR12, output VAR69,
output [63:0] VAR60, output VAR14, output VAR23, input VAR32,
output [63:0] VAR67,
output [31:0] VAR4
);
wire [31:0] VAR8;
wire... | gpl-3.0 |
UA3MQJ/fpga-synth | benches/fifo/fifo.v | 1,873 | module MODULE1(VAR7, VAR14, clk, VAR2, VAR1, VAR9);
parameter VAR13=8;
parameter VAR3=16;
parameter VAR10=VAR3 - 1;
parameter VAR4 = (VAR10[7:7]==1'b1) ? 8 :
(VAR10[6:6]==1'b1) ? 7 :
(VAR10[5:5]==1'b1) ? 6 :
(VAR10[4:4]==1'b1) ? 5 :
(VAR10[3:3]==1'b1) ? 4 :
(VAR10[2:2]==1'b1) ? 3 :
(VAR10[1:1]==1'b1) ? 2 :
(VAR10[0:0]=... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a_2.v | 2,322 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR10 ,
VAR7 ,
VAR1 ,
VAR3,
VAR4,
VAR8 ,
VAR5
);
output VAR9 ;
input VAR11 ;
input VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR3;
input VAR4;
input VAR8 ;
input VAR5 ;
VAR6 VAR2 (
.VAR9(VAR9),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.... | apache-2.0 |
jameshegarty/rigel | platform/camera1x/vsrc/axi_master_stub.v | 2,925 | module MODULE1(
output VAR18,
output VAR8,
input VAR14,
output [31:0] VAR2,
output [1:0] VAR5,
output [3:0] VAR19,
output [1:0] VAR13,
input VAR3,
output VAR7,
input VAR9,
input [63:0] VAR24,
input [1:0] VAR22,
output VAR23,
input VAR15,
output [31:0] VAR11,
output [1:0] VAR4,
output [3:0] VAR20,
output [1:0] VAR26,
ou... | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/riffa_wrapper_vc709.v | 35,499 | module MODULE1
parameter VAR91 = 128,
parameter VAR263 = 256,
parameter VAR212 = 5,
parameter VAR334 = "VAR295"
)
(
input VAR257,
input VAR148,
input [VAR91-1:0] VAR269,
input [(VAR91/32)-1:0] VAR265,
input [VAR169-1:0] VAR301,
output VAR19,
input VAR174,
input VAR241,
input [VAR91-1:0] VAR164,
input [(VAR91/32)-1:0] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a.behavioral.v | 1,666 | module MODULE1 (
VAR14 ,
VAR15,
VAR4,
VAR7 ,
VAR2
);
output VAR14 ;
input VAR15;
input VAR4;
input VAR7 ;
input VAR2 ;
supply1 VAR9;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR16 ;
wire VAR6 ;
wire VAR13 ;
wire VAR3;
nand VAR10 (VAR6 , VAR4, VAR15 );
or VAR1 (VAR13 , VAR2, VAR7 );
and VAR12 (VAR3, VAR6, VAR13);
buf VAR11 ... | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/c_fp_arbiter.v | 2,556 | module MODULE1
(req, VAR4);
parameter VAR3 = 32;
input [0:VAR3-1] req;
output [0:VAR3-1] VAR4;
wire [0:VAR3-1] VAR4;
generate
if(VAR3 > 1)
begin
wire [0:VAR3-1] VAR7;
VAR8
VAR5
(.VAR9(req),
.VAR6(VAR7));
wire [0:VAR3-1] VAR1;
assign VAR1 = VAR7 & -VAR7;
VAR8
VAR2
(.VAR9(VAR1),
.VAR6(VAR4));
end
else
assign VAR4 = req;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probe_p/sky130_fd_sc_hd__probe_p.behavioral.pp.v | 1,788 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR5,
VAR2 ,
VAR7 ,
VAR11
);
output VAR8 ;
input VAR4 ;
input VAR5;
input VAR2 ;
input VAR7 ;
input VAR11;
wire VAR1 ;
wire VAR10;
buf VAR6 (VAR1 , VAR4 );
VAR9 VAR3 (VAR10, VAR1, VAR11, VAR5);
buf VAR12 (VAR8 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfstp/sky130_fd_sc_ms__dfstp.pp.blackbox.v | 1,335 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR7 ,
VAR1,
VAR6 ,
VAR4 ,
VAR8 ,
VAR5
);
output VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR1;
input VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR5 ;
endmodule | apache-2.0 |
tanbotao5/RS485 | RS485.v | 1,585 | module MODULE1(VAR28,VAR14,VAR26,VAR29,VAR9,VAR17,VAR15,VAR25,VAR13,VAR4,VAR30,VAR5,
VAR22,VAR16,VAR18,VAR7,VAR21,VAR1,VAR11, VAR33,VAR32,VAR24,VAR3,VAR2,VAR23,VAR20,VAR12,VAR8,VAR6,VAR10,VAR31, VAR19,VAR27);
output VAR28,VAR29,VAR9,VAR17,VAR15,VAR25,VAR13,VAR4,VAR30,VAR2,VAR23,VAR20,VAR12,VAR8,VAR6,VAR10,VAR31;
input ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1.blackbox.v | 1,288 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR3;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ammelto/FPGAdventure | Adventure/HallwayTop.v | 1,036 | module MODULE1(VAR4, VAR3, VAR5, VAR1, VAR2);
input VAR4;
input [9:0]VAR3;
input [8:0]VAR5;
input [7:0]VAR2;
output [7:0]VAR1;
reg [7:0]VAR6;
always @(posedge VAR4) begin
if(~(VAR5 < 440)) begin
VAR6[7:0] <= VAR2;
end
else if(VAR3 > 600)begin
VAR6[7:0] <= VAR2;
end
else if(((VAR5 < 40) && (VAR3 < 260)) || ((VAR5 < 40) ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211o/sky130_fd_sc_hd__a211o.functional.pp.v | 2,032 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR14 ,
VAR13 ,
VAR3 ,
VAR8,
VAR4,
VAR1 ,
VAR2
);
output VAR7 ;
input VAR9 ;
input VAR14 ;
input VAR13 ;
input VAR3 ;
input VAR8;
input VAR4;
input VAR1 ;
input VAR2 ;
wire VAR11 ;
wire VAR16 ;
wire VAR5;
and VAR6 (VAR11 , VAR9, VAR14 );
or VAR12 (VAR16 , VAR11, VAR3, VAR13 );
VAR17 VAR15... | apache-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T18-notas/notas.v | 1,782 | module MODULE1(input wire clk, output wire VAR26, VAR10, VAR16, VAR27, VAR32, VAR6, VAR23, VAR25);
parameter VAR21 = VAR19;
parameter VAR31 = VAR12;
parameter VAR2 = VAR11;
parameter VAR7 = VAR34;
parameter VAR29 = VAR9;
parameter VAR15 = VAR22;
parameter VAR30 = VAR8;
parameter VAR24 = VAR17;
VAR5 #(VAR21)
VAR28 (
.VA... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/10KEYBOARD/Version_01/02 verilog/Touch/ps2.v | 1,476 | module MODULE1 (
input VAR10,
input VAR7,
output reg VAR3,
output [7:0] VAR9,
output reg VAR8
);
reg [8:0] VAR1;
reg [7:0] VAR2;
reg [3:0] VAR11;
reg [3:0] VAR6;
reg [1:0] VAR12;
reg VAR4;
reg VAR5;
begin
begin
begin
begin
begin
begin
begin
begin
end
begin | gpl-3.0 |
Alexoner/RiscCPU | clk_gen.v | 2,822 | module MODULE1 (clk,reset,VAR1,VAR14,VAR3,VAR8,VAR2);
input clk,reset;
output VAR1,VAR14,VAR3,VAR8,VAR2;
wire clk,reset;
reg VAR14,VAR3,VAR8,VAR2;
reg[7:0] state;
parameter VAR9 = 8'b00000001,
VAR10 = 8'b00000010,
VAR12 = 8'b00000100,
VAR4 = 8'b00001000,
VAR11 = 8'b00010000,
VAR7 = 8'b00100000,
VAR5 = 8'b01000000,
VAR6... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.behavioral.pp.v | 1,407 | module MODULE1( VAR9, VAR1, VAR5, VAR4, VAR3, VAR7, VAR2 );
input VAR3, VAR4, VAR5, VAR1;
inout VAR7, VAR2;
output VAR9;
VAR8 VAR6(.VAR9(VAR9),.VAR1(VAR1),.VAR5(VAR5),.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2));
VAR8 VAR10(.VAR9(VAR9),.VAR1(VAR1),.VAR5(VAR5),.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2)); | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/841f5df448bf42bc/zqynq_lab_1_design_auto_pc_2_stub.v | 4,672 | module MODULE1(VAR48, VAR40, VAR10, VAR49,
VAR58, VAR52, VAR43, VAR57, VAR27, VAR25,
VAR60, VAR19, VAR47, VAR50, VAR24, VAR36,
VAR16, VAR45, VAR29, VAR35, VAR55, VAR54, VAR1,
VAR23, VAR41, VAR14, VAR13, VAR51, VAR28,
VAR31, VAR46, VAR22, VAR17, VAR8, VAR37,
VAR44, VAR42, VAR26, VAR56, VAR21, VAR2, VAR3,
VAR30, VAR4, VA... | mit |
SymbiFlow/yosys | techlibs/intel_alm/common/quartus_rename.v | 5,941 | module MODULE4(output VAR61);
MODULE12 #(.VAR51(4'b1111)) VAR30 (.VAR52(1'b1), .VAR83(1'b1), .VAR61(VAR61));
endmodule
module MODULE11(output VAR61);
MODULE12 #(.VAR51(4'b0000)) VAR30 (.VAR52(1'b1), .VAR83(1'b1), .VAR61(VAR61));
endmodule
module MODULE2(input VAR15, VAR79, VAR97, VAR11, VAR93, VAR24, VAR32, output reg ... | isc |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_mac_1.v | 6,286 | module MODULE1 (
clk,
VAR14,
VAR28,
VAR41,
VAR33,
VAR4,
VAR40,
VAR23,
VAR34);
localparam VAR9 = 16'h024d; localparam VAR26 = 16'hf155; localparam VAR25 = 16'h4c77; localparam VAR29 = 16'h4c77; localparam VAR22 = 16'hf155; localparam VAR8 = 16'h024d;
input clk;
input [15:0] VAR14;
input [15:0] VAR28;
input [15:0] VAR41;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.v | 2,825 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR9 ,
VAR11 ,
VAR2 ,
VAR12 ,
VAR14 ,
VAR1,
VAR10 ,
VAR6 ,
VAR4 ,
VAR8
);
output VAR7 ;
output VAR5 ;
input VAR9 ;
input VAR11 ;
input VAR2 ;
input VAR12 ;
input VAR14 ;
input VAR1;
input VAR10 ;
input VAR6 ;
input VAR4 ;
input VAR8 ;
VAR3 VAR13 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.V... | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_9to1_sel4_6_1.v | 2,134 | module MODULE1 #(
parameter
VAR31 = 0,
VAR22 = 1,
VAR28 = 32,
VAR4 = 32,
VAR29 = 32,
VAR21 = 32,
VAR26 = 32,
VAR11 = 32,
VAR7 = 32,
VAR5 = 32,
VAR12 = 32,
VAR6 = 32,
VAR25 = 32
)(
input [5 : 0] VAR17,
input [5 : 0] VAR8,
input [5 : 0] VAR2,
input [5 : 0] VAR18,
input [5 : 0] VAR13,
input [5 : 0] VAR33,
input [5 : 0] VA... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/PIO.v | 7,825 | module MODULE1 (
VAR5,
VAR30,
VAR33,
VAR3,
VAR6,
VAR8,
VAR20,
VAR37,
VAR17,
VAR34,
VAR32,
VAR15,
VAR25,
VAR36,
VAR26,
VAR2,
VAR23,
VAR16,
VAR29,
VAR27,
VAR1
);
input VAR5;
input VAR30;
input VAR33;
output [63:0] VAR3;
output [7:0] VAR6;
output [127:0] VAR3;
output [1:0] VAR6;
output [31:0] VAR3;
output VAR8;
output VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3.functional.pp.v | 1,810 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1 ,
VAR5 ,
VAR2,
VAR8,
VAR9 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR2;
input VAR8;
input VAR9 ;
input VAR6 ;
wire VAR12 ;
wire VAR11;
and VAR13 (VAR12 , VAR5, VAR3, VAR1 );
VAR14 VAR7 (VAR11, VAR12, VAR2, VAR8);
buf VAR10 (VAR4 , VAR11 );
endmodule | apache-2.0 |
combinatorylogic/soc | backends/c2/hw/blackice/ice.v | 6,557 | module MODULE3(input clk,
input rst,
input VAR31,
output VAR40,
output [31:0] VAR25,
output reg VAR7,
input [31:0] VAR34,
input [31:0] VAR1,
input [31:0] VAR43);
wire VAR24;
VAR54 VAR15(.clk(clk), .VAR29(VAR31), .rd(VAR24));
reg VAR9, VAR48, VAR21, VAR5;
wire VAR37, VAR17;
wire [7:0] VAR16;
reg [7:0] VAR2;
wire [7:0] V... | mit |
Mw1993/5CPipelinedCPU | Icache.v | 1,979 | module MODULE1(clk,VAR7,addr,VAR15,VAR6,VAR11,VAR14,VAR9,VAR10,VAR1,VAR4);
input clk,VAR7;
input [13:0] addr; input [63:0] VAR15; input VAR6; input VAR11; input VAR14;
output VAR1;
output VAR4;
output [63:0] VAR9; output [10:0] VAR10;
reg [76:0] VAR2[0:7]; reg [3:0] VAR13;
reg [76:0] VAR5;
reg VAR3;
wire VAR8;
always @... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_axi_basic_tx_pipeline.v | 22,433 | module MODULE1 #(
parameter VAR17 = 128, parameter VAR1 = "VAR55", parameter VAR4 = 1,
parameter VAR47 = (VAR17 == 128) ? 2 : 1, parameter VAR8 = VAR17 / 8 ) (
input [VAR17-1:0] VAR52, input VAR36, output VAR30, input [VAR8-1:0] VAR44, input VAR48, input [3:0] VAR59,
output [VAR17-1:0] VAR18, output VAR43, output VAR34... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pcie_brams_7x.v | 9,055 | module MODULE1
parameter [3:0] VAR25 = 4'h1, parameter [5:0] VAR11 = 6'h08, parameter VAR4 = "VAR22",
parameter VAR19 = 0,
parameter VAR13 = 1,
parameter VAR20 = 1,
parameter VAR7 = 1
)
(
input VAR23,
input VAR16,
input VAR6,
input [12:0] VAR14,
input [71:0] VAR24,
input VAR17,
input VAR2,
input [12:0] VAR18,
output [7... | gpl-2.0 |
KestrelComputer/gpia3 | bench/verilog/GPIA_BIT_IN.v | 3,404 | module MODULE1();
reg VAR6;
reg VAR8;
reg VAR7;
reg VAR4;
wire VAR11;
reg VAR10;
reg [7:0] VAR12;
VAR3 VAR13 (
.VAR2(VAR6),
.VAR14(VAR8),
.VAR1(VAR7),
.VAR9(VAR4),
.VAR5(VAR11)
);
always begin
VAR10 <= ~VAR10;
end
task VAR15;
begin @(negedge VAR10); @(posedge VAR10);
end
endtask | mpl-2.0 |
EmbeditElectronics/Python_for_PSoC | PSoC Creator/PSoC_2_Pi.cydsn/B_WS2811_v1_3/B_WS2811_v1_3.v | 13,902 | module MODULE1 (
VAR14,
VAR71,
VAR51,
VAR1,
clk,
reset
);
output VAR71;
output VAR14;
output VAR51;
output VAR1;
input clk;
input reset;
reg VAR9; reg [1:0] VAR48; reg [1:0] state; reg [2:0] VAR73; reg VAR40; reg VAR59;
wire VAR42; wire VAR21; wire VAR60; wire enable; wire VAR1; wire VAR36;
wire VAR17;
wire VAR22; wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4.behavioral.v | 1,392 | module MODULE1 (
VAR5,
VAR7,
VAR4,
VAR9,
VAR1
);
output VAR5;
input VAR7;
input VAR4;
input VAR9;
input VAR1;
supply1 VAR6;
supply0 VAR12;
supply1 VAR8 ;
supply0 VAR11 ;
wire VAR10;
and VAR3 (VAR10, VAR7, VAR4, VAR9, VAR1 );
buf VAR2 (VAR5 , VAR10 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/spare/build1/datamem.v | 2,478 | module MODULE1 (VAR2,VAR4,VAR3,clk,VAR1);
output [0:127] VAR2;
input [0:127] VAR4;
input [0:31] VAR3;
input clk;
input [0:1] VAR1;
reg [0:31] VAR2;
reg [0:127] MODULE1 [0:255];
begin
begin
begin
begin
begin
begin | mit |
itpcc/FPGA-IA-Journy-game | verilog/reset.v | 1,172 | module MODULE1(
input MODULE1,
input clk,
output reg VAR5,
output reg VAR3,
output reg VAR2,
output reg VAR10,
output reg VAR6,
output reg VAR1,
output reg VAR8,
output reg VAR9,
output reg VAR4,
output reg VAR7,
output reg VAR11,
output reg VAR12
);
always @ (posedge clk)
begin
if(MODULE1==1)
begin
VAR5=1'b0;
VAR3<=1'... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.v | 2,377 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3 ,
VAR10 ,
VAR11,
VAR7 ,
VAR8 ,
VAR4 ,
VAR5
);
output VAR2 ;
output VAR6 ;
input VAR3 ;
input VAR10 ;
input VAR11;
input VAR7 ;
input VAR8 ;
input VAR4 ;
input VAR5 ;
VAR1 VAR9 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4)... | apache-2.0 |
samyk/proxmark3 | fpga/lo_adc.v | 2,741 | module MODULE1(
VAR20,
VAR14, VAR1, VAR10, VAR21, VAR13, VAR7,
VAR16, VAR3,
VAR12, VAR4, VAR11, VAR19,
VAR6, VAR9,
VAR5
);
input VAR20;
output VAR14, VAR1, VAR10, VAR21, VAR13, VAR7;
input [7:0] VAR16;
output VAR3;
input VAR11;
output VAR12, VAR4, VAR19;
output VAR6;
input [7:0] VAR9;
input VAR5;
reg [7:0] VAR8;
reg [7... | gpl-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/FpuFpD_Add.v | 2,695 | module MODULE1(
clk,
enable,
VAR3,
VAR21,
VAR6,
VAR12
);
input clk;
input enable;
input VAR3;
input[63:0] VAR21;
input[63:0] VAR6;
output[63:0] VAR12;
reg VAR26;
reg VAR18;
reg VAR4;
reg[12:0] VAR17;
reg[12:0] VAR8;
reg[12:0] VAR2;
reg[12:0] VAR19;
reg[63:0] VAR7;
reg[63:0] VAR16;
reg[63:0] VAR11;
reg[63:0] VAR22;
reg[... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcin/sky130_fd_sc_ms__fahcin.pp.symbol.v | 1,325 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR9 ,
output VAR3,
output VAR7 ,
input VAR6 ,
input VAR5,
input VAR8,
input VAR4
);
endmodule | apache-2.0 |
jakubfi/mera400f | src/recv_bus.v | 1,338 | module MODULE1(
input VAR17,
input VAR1,
input VAR8,
input VAR18,
output reg VAR22,
input VAR15,
input VAR13,
input [0:3] VAR21,
input [0:15] VAR7,
input [0:15] VAR10,
input [0:7] VAR6,
output [0:7] VAR5,
output [0:7] VAR20,
output [0:15] VAR23,
output [0:15] VAR14
);
reg [0:7] VAR12;
reg [0:7] VAR16;
reg [0:15] VAR19;... | gpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_custom_round.v | 6,219 | module MODULE1(
VAR13, VAR32, VAR11, VAR10, VAR9, VAR1, VAR12, VAR4,
VAR26, VAR20, VAR33, VAR24, enable);
parameter VAR16 = 1;
parameter VAR28 = 0;
parameter VAR2 = 1;
parameter VAR7 = 0;
input VAR13, VAR32;
input VAR33, VAR26;
output VAR24, VAR20;
input enable;
input [27:0] VAR11;
input [8:0] VAR10; input VAR9;
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi.functional.pp.v | 1,939 | module MODULE1 (
VAR10,
VAR7,
VAR1 ,
VAR8 ,
VAR11 ,
VAR12 ,
VAR9
);
input VAR10;
input VAR7;
output VAR1 ;
input VAR8 ;
input VAR11 ;
input VAR12 ;
input VAR9 ;
wire VAR9 VAR3 ;
wire VAR5 ;
wire VAR14;
and VAR6 (VAR3 , VAR12, VAR8, VAR11 );
nor VAR13 (VAR5 , VAR9, VAR3 );
VAR15 VAR2 (VAR14, VAR5, VAR10, VAR7);
buf VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd/sky130_fd_sc_hs__tapvgnd.functional.pp.v | 1,179 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/arbl2.v | 12,148 | module MODULE1(
input clk
,input reset
,input logic VAR51
,output logic VAR114
,input VAR93 VAR83
,output logic VAR6
,input logic VAR41
,output VAR20 VAR79
,input VAR47
,output VAR87
,input VAR113 VAR121
,input logic VAR28
,output logic VAR9
,input VAR84 VAR38
,output logic VAR32
,input logic VAR64
,output VAR109 VAR48... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi.behavioral.pp.v | 2,070 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR11 ,
VAR2 ,
VAR1 ,
VAR4 ,
VAR14,
VAR15,
VAR7 ,
VAR9
);
output VAR5 ;
input VAR10 ;
input VAR11 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR14;
input VAR15;
input VAR7 ;
input VAR9 ;
wire VAR3 ;
wire VAR16 ;
wire VAR8;
and VAR17 (VAR3 , VAR10, VAR11, VAR2, VAR1 );
nor VAR18 (VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.symbol.v | 1,327 | module MODULE1 (
input VAR2,
input VAR1,
input VAR3,
input VAR6,
output VAR7 ,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-platform | artemis/slave/wb_artemis_ddr3/rtl/ddr3_controller.v | 12,999 | module MODULE1 (
input clk,
input rst,
input [27:0] VAR12,
input VAR6, input [27:0] VAR75,
input VAR60,
input VAR46,
input [31:0] VAR28,
output [1:0] VAR37,
input [1:0] VAR25,
output [23:0] VAR17,
output VAR85,
input VAR16,
output VAR15,
input VAR74,
output [23:0] VAR64,
output [31:0] VAR86,
output reg VAR4, output reg... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a.pp.symbol.v | 1,401 | module MODULE1 (
input VAR2 ,
input VAR9 ,
input VAR8 ,
input VAR4 ,
input VAR1 ,
output VAR3 ,
input VAR7 ,
input VAR10,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/nvme/nvme_host_ctrl_8lane-1.0.0/pcie_cntl_reg.v | 24,935 | module MODULE1 # (
parameter VAR80 = 128,
parameter VAR89 = 36
)
(
input VAR25,
input VAR116,
output VAR79,
output VAR62,
output VAR124,
input [VAR80-1:0] VAR39,
input VAR118,
output VAR122,
output [7:0] VAR17,
output [15:0] VAR2,
output [11:2] VAR114,
output [11:0] VAR19,
output [6:0] VAR27,
output [63:0] VAR51,
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3/sky130_fd_sc_hd__nor3.behavioral.pp.v | 1,844 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR14 ,
VAR5 ,
VAR2,
VAR1,
VAR8 ,
VAR13
);
output VAR11 ;
input VAR3 ;
input VAR14 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR8 ;
input VAR13 ;
wire VAR10 ;
wire VAR4;
nor VAR6 (VAR10 , VAR5, VAR3, VAR14 );
VAR12 VAR9 (VAR4, VAR10, VAR2, VAR1);
buf VAR7 (VAR11 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b.symbol.v | 1,285 | module MODULE1 (
input VAR7 ,
input VAR4,
output VAR5
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/subsys/e203_subsys_gfcm.v | 3,153 | module MODULE1(
input VAR9,
input VAR21,
input VAR12,
input VAR4 ,
input VAR24 ,
input VAR16 ,
output VAR22
);
wire VAR7 = ~VAR4;
wire VAR15 = VAR4;
localparam VAR14 = 3;
wire VAR18;
reg [VAR14-1:0] VAR10;
always @(posedge VAR24 or negedge VAR21)
begin:VAR8
if(VAR21 == 1'b0)
begin
VAR10[VAR14-1:0] <= {VAR14{1'b0}};
end... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311o/sky130_fd_sc_ls__a311o.functional.pp.v | 2,064 | module MODULE1 (
VAR14 ,
VAR10 ,
VAR18 ,
VAR4 ,
VAR2 ,
VAR16 ,
VAR15,
VAR3,
VAR13 ,
VAR6
);
output VAR14 ;
input VAR10 ;
input VAR18 ;
input VAR4 ;
input VAR2 ;
input VAR16 ;
input VAR15;
input VAR3;
input VAR13 ;
input VAR6 ;
wire VAR7 ;
wire VAR9 ;
wire VAR12;
and VAR11 (VAR7 , VAR4, VAR10, VAR18 );
or VAR5 (VAR9 , V... | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_phy_alt_mem_phy_pll_bb.v | 18,849 | module MODULE1 (
VAR10,
VAR12,
VAR11,
VAR2,
VAR4,
VAR6,
VAR3,
VAR7,
VAR8,
VAR1,
VAR5,
VAR9,
VAR14,
VAR13);
input VAR10;
input VAR12;
input [3:0] VAR11;
input VAR2;
input VAR4;
input VAR6;
output VAR3;
output VAR7;
output VAR8;
output VAR1;
output VAR5;
output VAR9;
output VAR14;
output VAR13;
tri0 VAR10;
tri0 [3:0] VAR... | gpl-3.0 |
FuzzyLogic/Trivium | hdl/ip/axi_trivium_v1_0_S00_AXI.v | 23,633 | module MODULE1 #
(
parameter integer VAR9 = 32,
parameter integer VAR10 = 6
)
(
input wire VAR53,
input wire VAR32,
input wire [VAR10 - 1:0] VAR61,
input wire [2:0] VAR66,
input wire VAR21,
output wire VAR44,
input wire [VAR9 - 1:0] VAR26,
input wire [(VAR9/8) - 1:0] VAR47,
input wire VAR25,
output wire VAR54,
output w... | lgpl-3.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_ic_ram.v | 4,243 | module MODULE1(
clk, rst,
VAR10, VAR9, VAR18,
addr, en, VAR11, VAR4, VAR7
);
parameter VAR17 = VAR19;
parameter VAR8 = VAR16;
input clk;
input rst;
input [VAR8-1:0] addr;
input en;
input [3:0] VAR11;
input [VAR17-1:0] VAR4;
output [VAR17-1:0] VAR7;
input VAR10;
input [VAR5 - 1:0] VAR18;
output VAR9;
assign VAR7 = {VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtn/sky130_fd_sc_lp__sdfrtn.functional.v | 2,089 | module MODULE1 (
VAR14 ,
VAR16 ,
VAR12 ,
VAR3 ,
VAR18 ,
VAR7
);
output VAR14 ;
input VAR16 ;
input VAR12 ;
input VAR3 ;
input VAR18 ;
input VAR7;
wire VAR1 ;
wire VAR5 ;
wire VAR8 ;
wire VAR17;
not VAR15 (VAR5 , VAR7 );
not VAR11 (VAR8 , VAR16 );
VAR9 VAR2 (VAR17, VAR12, VAR3, VAR18 );
VAR6 VAR10 VAR4 (VAR1 , VAR17, VA... | apache-2.0 |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/tri_mode_eth_mac_v5_2_mod.v | 5,333 | module MODULE1
(
input VAR49,
input VAR45,
input VAR31,
input VAR34,
output VAR2,
output [7:0] VAR33,
output VAR7,
output VAR11,
output VAR19,
output [27:0] VAR40,
output VAR51,
input VAR24,
output VAR22,
input [7:0] VAR12,
input VAR32,
input VAR8,
input VAR27,
output VAR37,
output VAR29,
output VAR41,
input [7:0] VAR1... | lgpl-3.0 |
pradeep9676/pradeep_9676 | sqrt.v | 2,524 | module MODULE1(VAR10 , VAR14);
input [30:0] VAR10;
output reg signed [16:0] VAR14;
reg [4:0] VAR3;
wire [4:0] VAR7;
wire valid;
VAR5 VAR6(.in({1'b0,VAR10}),.out(VAR7),.valid(valid));
reg [4:0] VAR4;
reg [30:0] VAR2,VAR11;
reg [30:0] VAR15;
reg [5:0] address;
reg [63:0] VAR9;
reg [31:0] VAR13[63:0];
reg [31:0] VAR1[63:0... | mit |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/Raster_Laser_Projector_Video_In_video_dma_controller_0.v | 7,553 | module MODULE1 (
clk,
reset,
VAR17,
VAR40,
VAR44,
VAR24,
VAR6,
VAR34,
VAR39,
VAR8,
VAR41,
VAR7,
VAR19,
VAR5,
VAR13,
VAR16,
VAR43,
VAR29
);
parameter VAR1 = 7; parameter VAR32 = 0; parameter VAR25 = 640; parameter VAR20 = 480;
parameter VAR2 = 18; parameter VAR3 = 9; parameter VAR42 = 8;
parameter VAR27 = 7;
parameter V... | gpl-3.0 |
esonghori/TinyGarble | circuit_synthesis/a23/a23_execute.v | 16,986 | module MODULE1 (
input VAR38,
input VAR29,
input [31:0] VAR58,
input [4:0] VAR26, output reg [31:0] VAR90,
output wire [31:0] VAR74,
output [31:0] VAR54, output reg VAR73,
output reg [3:0] VAR17,
output VAR104,
input [31:0] VAR24,
input [4:0] VAR25,
input [3:0] VAR71,
input VAR82,
input [3:0] VAR56,
input [3:0] VAR39,
... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int.v | 30,451 | module MODULE1 (
VAR74,
VAR105,
VAR39,
VAR3,
VAR49,
VAR98,
VAR4,
VAR50,
VAR61,
VAR62,
VAR91,
VAR66,
VAR5,
VAR67,
VAR16,
VAR96,
VAR65,
VAR72,
VAR54,
VAR38,
VAR88,
VAR24,
VAR46,
VAR42,
VAR107,
VAR13,
VAR69,
VAR35,
VAR63,
VAR19,
VAR8,
VAR89,
VAR36,
VAR104,
VAR31,
VAR2,
VAR79);
input [23:0] VAR74;
input VAR105;
input VAR39... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_8.behavioral.pp.v | 1,182 | module MODULE1( VAR5, VAR7, VAR1, VAR4 );
input VAR5;
inout VAR1, VAR4;
output VAR7;
VAR3 VAR2(.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR4(VAR4));
VAR3 VAR6(.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_2.behavioral.pp.v | 1,164 | module MODULE1( VAR3, VAR5, VAR7, VAR1 );
input VAR3;
inout VAR7, VAR1;
output VAR5;
VAR4 VAR2(.VAR3(VAR3),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1));
VAR4 VAR6(.VAR3(VAR3),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai_2.v | 2,334 | module MODULE2 (
VAR6 ,
VAR10 ,
VAR1 ,
VAR5 ,
VAR7 ,
VAR3 ,
VAR4,
VAR9
);
output VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR4;
input VAR9;
VAR2 VAR8 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
module MODUL... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.behavioral.v | 1,495 | module MODULE1( VAR3, VAR2, VAR4, VAR6 );
input VAR2, VAR3, VAR6;
output VAR4;
VAR7 VAR1(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR6(VAR6));
VAR7 VAR5(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32ai/sky130_fd_sc_hs__o32ai.pp.symbol.v | 1,365 | module MODULE1 (
input VAR1 ,
input VAR4 ,
input VAR8 ,
input VAR3 ,
input VAR5 ,
output VAR7 ,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
mashanz/FinalProject | Code/fpga/spartan3a/alu_min.v | 7,578 | module MODULE1( VAR1, VAR8, VAR4, VAR7, VAR6, VAR5, VAR2, VAR3);
input VAR1, VAR8, VAR4;
input [7:0]VAR3,VAR7,VAR6;
output [7:0]VAR5;
input [1:0]VAR2;
reg [7:0]VAR5;
always@(posedge VAR8)begin
if(VAR1) VAR5 = 0;
end
else begin
case(VAR3)
8'b00000001: VAR5 = 0;
8'b00000010: VAR5 = VAR7 + VAR6;
8'b00000011: VAR5 = VAR7 -... | gpl-3.0 |
jameshegarty/rigel | platform/camera/vsrc/StreamBuffer.v | 1,686 | module MODULE1(
input VAR27,
input VAR28,
input VAR7,
input VAR25,
input VAR17,
output VAR19,
input [7:0] din,
output [63:0] dout,
output VAR34,
input VAR38,
output VAR26,
output [10:0] VAR15
);
reg VAR14;
VAR20(VAR28, VAR14, 0, VAR25 ? 1 : VAR14)
wire VAR32;
wire VAR8;
wire [63:0] VAR16;
VAR36 #(.VAR6(3), .VAR22(6)) V... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_slice_init.v | 23,599 | module MODULE1(
clk ,
VAR88 ,
VAR9 ,
VAR26 ,
VAR17 ,
VAR7 ,
VAR23 ,
VAR42 ,
VAR25 ,
VAR78 ,
VAR79 ,
VAR34 ,
VAR6 ,
VAR92 ,
VAR76 ,
VAR86 ,
VAR52 ,
VAR36 ,
VAR53 ,
VAR30 ,
VAR89
);
input clk ; input VAR88 ; input VAR9 ; input VAR26 ; input [5:0] VAR17 ;
output VAR7 ; output VAR23 ; output [5:0] VAR42 ; output [6:0] VAR2... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v | 2,545 | module MODULE1
import VAR16::*; #(parameter VAR19(VAR12 ) , VAR5 = "VAR18"
, VAR9 = "VAR18"
, VAR8 = 1 )
(input [VAR9-1:0][VAR5-1:0][VAR8-1:0][VAR1:VAR17][VAR12-1:0] VAR6 , output [VAR9-1:0][VAR5-1:0][VAR8-1:0][VAR1:VAR17][VAR12-1:0] VAR15
, input [VAR3:VAR17][VAR9-1:0][VAR8-1:0][VAR12-1:0] VAR4
, output [VAR3:VAR17][V... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.behavioral.v | 1,964 | module MODULE1( VAR4, VAR6, VAR8, VAR7, VAR2 );
input VAR8, VAR7, VAR2, VAR4;
output VAR6;
VAR5 VAR1(.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR7(VAR7),.VAR2(VAR2));
VAR5 VAR3(.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR7(VAR7),.VAR2(VAR2)); | apache-2.0 |
darrylring/verilog | ad5541a.v | 3,129 | module MODULE1
(
input wire clk,
input wire VAR20,
input wire [15:0] VAR10,
input wire valid,
output wire ready,
output wire VAR13,
output wire din,
output wire VAR19,
output wire VAR16
);
localparam [1:0]
VAR24 = 3'd0,
VAR25 = 3'd1,
VAR11 = 3'd2,
VAR6 = 3'd3;
reg [1:0] VAR14, VAR9;
reg [6:0] VAR18, VAR3;
reg [15:0] VA... | mit |
TUM-LIS/faultify | software/host/davester_combinational_extractor/c432_wrap.v | 2,455 | module MODULE1(in,out,clk);
input [0:35] in;
output [0:6] out;
input clk;
VAR20 VAR12 (.VAR55(clk), .VAR90(in[0]), .VAR2(VAR56));
VAR20 VAR5 (.VAR55(clk), .VAR90(in[1]), .VAR2(VAR70));
VAR20 VAR43 (.VAR55(clk), .VAR90(in[2]), .VAR2(VAR57));
VAR20 VAR35 (.VAR55(clk), .VAR90(in[3]), .VAR2(VAR62));
VAR20 VAR15 (.VAR55(clk... | gpl-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_Pipistrello/src/cog_ctr.v | 3,829 | module MODULE1
(
input VAR19,
input VAR21,
input VAR5,
input VAR16,
input VAR18,
input VAR8,
input [31:0] VAR4,
input [31:0] VAR17,
output reg [32:0] VAR22,
output [31:0] VAR20,
output VAR3
);
reg [31:0] VAR2;
reg [31:0] VAR9;
always @(posedge VAR19 or negedge VAR5)
if (!VAR5)
VAR2 <= 32'b0;
else if (VAR16)
VAR2 <= VAR... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/8-way_4-parallel/src/lcdcon.v | 2,138 | module MODULE1 #(parameter VAR4 = 8)
(input wire VAR3,
input wire VAR2,
input wire [VAR4*4-1:0] VAR16,
input wire VAR1,
output reg VAR6,
output reg VAR7);
reg [(VAR4+1)*10-1:0] VAR9;
reg [11:0] VAR5;
reg [(VAR4+3):0] VAR11;
reg [VAR4*4-1:0] VAR14;
genvar VAR10;
generate
wire [(VAR4+1)*10-1:0] VAR8;
for (VAR10=0; VAR10<... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_link/bsg_link_osdr_phy.v | 2,016 | module MODULE1
,parameter VAR1 = 0)
(input VAR30
,input VAR22
,input [VAR2-1:0] VAR15
,output VAR5
,output [VAR2-1:0] VAR23
);
begin: VAR14 \
VAR17 VAR7 (.VAR8(in),.VAR18(out)); \
end
if (VAR1 >= VAR19) \
wire VAR4, VAR9, VAR13;
wire [VAR2-1:0] VAR27;
VAR24 VAR3
(.VAR18(VAR13),.VAR8(VAR4),.VAR6(VAR9));
VAR26 VAR10
(.VA... | bsd-3-clause |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_spdr.v | 17,146 | module MODULE1
(
input clk,
input VAR56,
input rst,
input [68:0] VAR33,
output [68:0] VAR75,
input [31:0] VAR51,
output reg VAR59,
output reg [31:0] VAR48,
output reg VAR83,
output VAR73,
input VAR20
);
parameter VAR79 = 0;
parameter VAR26 = 6'd62;
reg VAR65;
wire VAR18;
reg wr;
reg [3:0] VAR72;
reg [31:0] addr;
reg [3... | mit |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/dcache.v | 5,900 | module MODULE1
parameter VAR23=6)
(input VAR24,
input VAR32,
input [VAR18-1:0] VAR20,
input VAR4,
input VAR21,
input [3:0] VAR16,
input [31:0] VAR9,
output [31:0] VAR13,
output VAR12,
input [31:0] VAR5,
output [31:0] VAR19,
output [VAR18-1:0] VAR26,
output VAR10,
output VAR25,
output [3:0] VAR31 );
localparam VAR11 = V... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fetch/fetch_ref_chroma.v | 7,663 | module MODULE1 (
clk ,
VAR41 ,
VAR53 ,
VAR9 ,
VAR28 ,
VAR22 ,
VAR36 ,
VAR7 ,
VAR32 ,
VAR17 ,
VAR2 ,
VAR58 ,
VAR56 ,
VAR30
);
input [1-1:0] clk ; input [1-1:0] VAR41 ; input VAR53 ;
input [VAR5-1:0] VAR9 ;
input [VAR5-1:0] VAR28 ;
input [6-1:0] VAR22 ; input [6-1:0] VAR36 ; input [1-1:0] VAR7 ; input [1-1:0] VAR32 ; out... | gpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_cx4/dac.v | 7,313 | module MODULE1(
input VAR7,
input VAR53,
input VAR38,
input[10:0] VAR37,
input[7:0] VAR52,
input[7:0] VAR46,
input VAR42,
input [2:0] VAR44,
input [8:0] VAR6,
input VAR3,
input reset,
input VAR27,
output VAR57,
output VAR17,
output VAR22,
output VAR55,
output VAR15
);
reg[8:0] VAR59;
reg[8:0] VAR24;
wire[8:0] VAR9 = VA... | gpl-2.0 |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_vc_alloc_wf.v | 17,666 | module MODULE1
(clk, reset, VAR56, VAR85, VAR47, VAR10,
VAR1, VAR16, VAR19, VAR69, VAR80);
parameter VAR37 = 2;
parameter VAR35 = 2;
localparam VAR36 = VAR37 * VAR35;
parameter VAR38 = 1;
localparam VAR44 = VAR36 * VAR38;
parameter VAR74 = 5;
localparam VAR45 = VAR28(VAR74);
parameter VAR41 = VAR67;
parameter VAR8 = VA... | mit |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axis_data_fifo_4_0/synth/design_SWandHW_standalone_axis_data_fifo_4_0.v | 5,895 | module MODULE1 (
VAR16,
VAR21,
VAR6,
VAR39,
VAR45,
VAR18,
VAR30,
VAR13,
VAR40,
VAR12,
VAR7,
VAR38,
VAR9,
VAR14,
VAR20
);
input wire VAR16;
input wire VAR21;
input wire VAR6;
output wire VAR39;
input wire [31 : 0] VAR45;
input wire [3 : 0] VAR18;
input wire VAR30;
output wire VAR13;
input wire VAR40;
output wire [31 : 0... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.behavioral.pp.v | 2,990 | module MODULE1( VAR27, VAR1, VAR24, VAR11, VAR3, VAR4 );
input VAR1, VAR27, VAR24;
inout VAR3, VAR4;
output VAR11;
reg VAR26;
VAR6 VAR16(.VAR27(VAR27),.VAR1(VAR1),.VAR24(VAR24),.VAR11(VAR11),.VAR3(VAR3),.VAR4(VAR4),.VAR26(VAR26));
VAR6 VAR15(.VAR27(VAR27),.VAR1(VAR1),.VAR24(VAR24),.VAR11(VAR11),.VAR3(VAR3),.VAR4(VAR4),... | apache-2.0 |
sudov/options-accel | xillinux-eval-zedboard-1.1/vhdl/src/xillybus.v | 13,723 | module MODULE1(VAR246, VAR207, VAR281, VAR326, VAR160, VAR108, VAR188,
VAR167, VAR109, VAR154, VAR314, VAR221, VAR165, VAR92,
VAR61, VAR73, VAR79, VAR294, VAR295, VAR198, VAR110, VAR51,
VAR225, VAR263, VAR94, VAR280, VAR23, VAR226, VAR69, VAR212,
VAR155, VAR282, VAR36, VAR187, VAR178,
VAR190, VAR255, VAR15, VAR285,
VAR... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_wb_biu.v | 14,279 | module MODULE1(
clk, rst, VAR19,
VAR32, VAR10, VAR26, VAR5, VAR38, VAR7,
VAR37, VAR11, VAR23, VAR28, VAR36, VAR27,
VAR42,
VAR39, VAR3,
VAR31, VAR25, VAR44, VAR33, VAR16, VAR30, VAR12,
VAR8, VAR2, VAR20
);
parameter VAR1 = VAR34;
parameter VAR22 = VAR34;
input clk; input rst; input [1:0] VAR19;
input VAR32; input VAR10;... | gpl-3.0 |
sergev/vak-opensource | hardware/pdp11/alu.v | 10,300 | module MODULE1 (
input wire [9:0] VAR5, input wire [15:0] VAR3, input wire [15:0] VAR9, input wire [7:0] VAR7, output reg [15:0] VAR2, output reg [7:0] VAR4 );
wire [15:0] VAR11 = { VAR3[7], VAR3[7], VAR3[7], VAR3[7], VAR3[7], VAR3[7], VAR3[7], VAR3[7:0], 1'b0 };
always @(VAR5 or VAR3 or VAR9 or VAR7 or VAR2) begin
VAR... | apache-2.0 |
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