repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_axi_basic_top.v | 11,280 | module MODULE1 #(
parameter VAR14 = 128, parameter VAR49 = "VAR29", parameter VAR55 = "VAR48", parameter VAR38 = "VAR48", parameter VAR4 = 1,
parameter VAR20 = (VAR14 == 128) ? 2 : 1, parameter VAR26 = VAR14 / 8 ) (
input [VAR14-1:0] VAR10, input VAR8, output VAR21, input [VAR26-1:0] VAR60, input VAR33, input [3:0] VAR... | lgpl-3.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_axi_basic_rx_null_gen.v | 15,530 | module MODULE1 # (
parameter VAR28 = 128, parameter VAR25 = 1,
parameter VAR33 = VAR28 / 8 ) (
input [VAR28-1:0] VAR32, input VAR17, input VAR26, input VAR2, input [21:0] VAR4,
output VAR22, output VAR37, output [VAR33-1:0] VAR24, output VAR8, output reg [4:0] VAR27,
input VAR16, input VAR15 );
localparam VAR7 = (VAR28... | gpl-2.0 |
titorgalaxy/Titor | rtl/verilog/ps2/PS2.v | 2,657 | module MODULE1(
VAR6,
VAR11,
VAR14,
VAR21,
reset,
clk
);
inout VAR6;
inout VAR11;
output reg [VAR26-1:0] VAR14;
output reg VAR21;
input reset;
input clk;
localparam VAR23 = 10;
localparam VAR15 = 32'd1,
VAR4 = 32'd2;
wire VAR19;
wire VAR2;
wire [VAR28-1:0] VAR16;
wire VAR12;
reg [VAR28-1:0] state;
reg [VAR23-1:0] VAR27... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbp/sky130_fd_sc_lp__dfbbp.blackbox.v | 1,435 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR8 ,
VAR5 ,
VAR6 ,
VAR3
);
output VAR9 ;
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR6 ;
input VAR3;
supply1 VAR1;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and2/sky130_fd_sc_hvl__and2.behavioral.pp.v | 1,792 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR1 ,
VAR5,
VAR7,
VAR11 ,
VAR10
);
output VAR12 ;
input VAR3 ;
input VAR1 ;
input VAR5;
input VAR7;
input VAR11 ;
input VAR10 ;
wire VAR13 ;
wire VAR8;
and VAR2 (VAR13 , VAR3, VAR1 );
VAR4 VAR9 (VAR8, VAR13, VAR5, VAR7);
buf VAR6 (VAR12 , VAR8 );
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab2/laboratorio2/timer.v | 1,269 | module MODULE1(clk, rst, VAR6, VAR2, VAR1);
input clk;
input rst;
input VAR6;
input [3:0] VAR2;
output VAR1;
reg VAR3;
reg [3:0] VAR4;
wire VAR5;
begin
begin
begin
end
begin
begin
end | mit |
ShepardSiegel/ocpi | rtl/mkEDDPAdapter.v | 34,491 | module MODULE1(VAR195,
VAR106,
VAR129,
VAR49,
VAR196,
VAR189,
VAR191,
VAR178,
VAR80,
VAR134,
VAR78,
VAR26,
VAR14,
VAR59,
VAR47,
VAR120,
VAR58,
VAR142,
VAR83,
VAR36,
VAR113,
VAR51,
VAR60,
VAR177,
VAR156,
VAR176,
VAR193,
VAR55,
VAR154);
input VAR195;
input VAR106;
input [39 : 0] VAR129;
input VAR49;
output VAR196;
input ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn.behavioral.v | 1,318 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR3 ;
input VAR1;
supply1 VAR7;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
notif0 VAR8 (VAR6 , VAR3, VAR1 );
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_g2b.v | 2,241 | module MODULE1 #(
parameter VAR3 = 8) (
input [VAR3-1:0] din,
output [VAR3-1:0] dout);
function [VAR3-1:0] VAR1;
input [VAR3-1:0] VAR4;
integer VAR2;
begin
VAR1[VAR3-1] = VAR4[VAR3-1];
for (VAR2 = VAR3-1; VAR2 > 0; VAR2 = VAR2 -1) begin
VAR1[VAR2-1] = VAR1[VAR2] ^ VAR4[VAR2-1];
end
end
endfunction
assign dout = VAR1(di... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_CKINVDC_SLVT_SS_210930.v | 11,799 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha.functional.v | 1,415 | module MODULE1 (
VAR1,
VAR5 ,
VAR2 ,
VAR8
);
output VAR1;
output VAR5 ;
input VAR2 ;
input VAR8 ;
wire VAR9;
wire VAR10 ;
and VAR4 (VAR9, VAR2, VAR8 );
buf VAR7 (VAR1 , VAR9 );
xor VAR6 (VAR10 , VAR8, VAR2 );
buf VAR3 (VAR5 , VAR10 );
endmodule | apache-2.0 |
ainterr/mips_processor | reg_file.v | 1,053 | module MODULE1(rst, clk, VAR8, VAR1, VAR2, VAR4, VAR3,
VAR9, VAR6);
input rst, clk, VAR8;
input [1:0] VAR1, VAR2, VAR4;
input signed [8:0] VAR3;
output signed [8:0] VAR9, VAR6;
integer VAR7;
reg signed [8:0] VAR5 [3:0];
assign VAR9 = VAR5[VAR1];
assign VAR6 = VAR5[VAR2];
always@(posedge clk, posedge rst) begin
if(rst) ... | mit |
SymbiFlow/yosys | techlibs/gowin/cells_map.v | 6,101 | module \VAR62 (input VAR32, VAR16, output VAR27);
VAR62 VAR75 (.VAR32(VAR32), .VAR27(VAR27), .VAR42(VAR16));
wire VAR39 = 1;
endmodule
module \VAR59 (input VAR32, VAR16, output VAR27);
VAR48 VAR75 (.VAR32(VAR32), .VAR27(VAR27), .VAR42(VAR16));
wire VAR39 = 1;
endmodule
module \VAR51 (input VAR32, VAR16, VAR44, output V... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf_4.v | 1,993 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR5,
VAR4,
VAR1 ,
VAR6
);
output VAR3 ;
input VAR7 ;
input VAR5;
input VAR4;
input VAR1 ;
input VAR6 ;
VAR8 VAR2 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3,
VAR7
);
output VAR3;
input VAR7;
supply1 VAR5;
supply0 VAR4;... | apache-2.0 |
kyzhai/NUNY | src/hardware/bg4_new_bb.v | 5,008 | module MODULE1 (
address,
VAR2,
VAR1);
input [14:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ACA_II_N16_Q8_syn.v | 3,570 | module MODULE2 ( VAR65, VAR63, VAR16, VAR40, VAR31 );
input [8:0] VAR65;
input [8:0] VAR63;
output [8:0] VAR40;
input VAR16;
output VAR31;
wire VAR51, VAR49, VAR42, VAR10, VAR79, VAR14, VAR64, VAR61;
VAR20 VAR12 ( .VAR65(VAR65[3]), .VAR63(VAR63[3]), .VAR82(VAR42) );
VAR60 VAR39 ( .VAR9(VAR65[1]), .VAR38(VAR63[1]), .VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv.behavioral.pp.v | 1,748 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR2,
VAR5,
VAR1 ,
VAR11
);
output VAR12 ;
input VAR3 ;
input VAR2;
input VAR5;
input VAR1 ;
input VAR11 ;
wire VAR9 ;
wire VAR10;
not VAR4 (VAR9 , VAR3 );
VAR6 VAR7 (VAR10, VAR9, VAR2, VAR5);
buf VAR8 (VAR12 , VAR10 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/generatedata.v | 2,826 | module MODULE1();
integer VAR2;
integer VAR3;
reg [0:24] VAR1;
parameter VAR4 = 9'd255;
begin
begin | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v | 14,405 | module MODULE1
(
VAR12,
VAR19,
VAR42,
VAR15,
VAR29,
VAR33,
VAR46, VAR1,
VAR39,
VAR13,
VAR20,
VAR30,
VAR17,
VAR16,
VAR23,
VAR38,
VAR3,
VAR25,
VAR26,
VAR22,
VAR47,
VAR44,
VAR9
);
input VAR12;
input VAR19;
input [31:0] VAR42; output [31:0] VAR15;
input [31:0] VAR29;
input VAR33;
input VAR46;
output VAR1;
output VAR39;
inp... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_data_pipeline.v | 7,411 | module MODULE1(
parameter VAR6 = 1,
parameter VAR16 = 1,
parameter VAR5 = 256,
parameter VAR10 = 10,
parameter VAR1 = "VAR19")
( input VAR34,
input VAR33,
input VAR29,
input [VAR26-1:0] VAR7,
input VAR30,
input [VAR36(VAR26/32)-1:0] VAR24,
input VAR35,
input [VAR36(VAR26/32)-1:0] VAR20,
output VAR13,
input [(VAR26/32)-... | gpl-3.0 |
Jside/pdp1 | pdp1_shrot.v | 3,489 | module MODULE1(VAR4, VAR3, VAR12, VAR8, VAR1);
input [0:8] VAR4;
input VAR3;
input VAR12;
input [0:17] VAR8;
output [0:17] VAR1;
wire [0:3] VAR13;
wire [0:17] VAR2[0:9];
wire [0:17] VAR7[0:9];
wire [0:17] VAR10[0:9];
wire [0:17] VAR6[0:9];
wire [0:17] VAR5;
wire [0:17] VAR11;
wire [0:17] VAR15;
VAR9 lut(.VAR4(VAR4),
.V... | gpl-3.0 |
HackSlash/SparcCool | cpu/alu.v | 2,003 | module MODULE1(out,VAR2,VAR1,VAR3,VAR9); input[32:0]VAR2,VAR1; input[32:0]VAR3; output[32:0]out; reg[32:0]out;
inout VAR12 VAR6; input VAR9;
function read; input[5:0] VAR4;
begin
VAR6.VAR10=VAR4;
read=VAR6.out;
end
endfunction
function write; input[5:0] VAR4;
input[32:0] VAR7;
begin
VAR6.VAR11=VAR4;
VAR6.VAR8=1;
VAR6.V... | unlicense |
Elphel/x353 | control/extjtag.v | 4,383 | module MODULE1 (VAR15, VAR9, VAR17, VAR5, VAR16, VAR11, VAR2, VAR1,
VAR13, VAR12, VAR19,
state); input VAR15;
input VAR9;
input [31:0] VAR17;
output VAR5; output VAR16; output VAR11; output VAR2; output VAR1;
input VAR13;
input VAR12;
input VAR19; output state;
wire VAR10= VAR9;
wire [1:0] mux; wire VAR5;
wire VAR16;
w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlclkp/sky130_fd_sc_hd__dlclkp.pp.symbol.v | 1,270 | module MODULE1 (
input VAR7 ,
input VAR2,
output VAR3,
input VAR1 ,
input VAR5,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp.behavioral.v | 2,360 | module MODULE1 (
VAR6 ,
VAR2,
VAR19 ,
VAR25,
VAR9
);
output VAR6 ;
input VAR2;
input VAR19 ;
input VAR25;
input VAR9;
supply1 VAR16;
supply0 VAR11;
supply1 VAR20 ;
supply0 VAR17 ;
wire VAR23 ;
wire VAR1 ;
reg VAR5 ;
wire VAR21 ;
wire VAR12;
wire VAR13;
wire VAR4;
wire VAR7 ;
wire VAR10 ;
wire VAR15 ;
wire VAR8 ;
VAR24 ... | apache-2.0 |
alexforencich/xfcp | lib/uart/example/ML605/fpga/rtl/fpga_core.v | 4,237 | module MODULE1 (
input wire VAR22,
input wire VAR32,
input wire VAR2,
input wire VAR14,
input wire VAR4,
input wire VAR11,
input wire VAR46,
input wire [7:0] VAR39,
output wire VAR36,
output wire VAR7,
output wire VAR5,
output wire VAR40,
output wire VAR24,
output wire [7:0] VAR34,
input wire VAR29,
input wire [7:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcon/sky130_fd_sc_lp__fahcon.symbol.v | 1,358 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR2 ,
output VAR5,
output VAR9
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b.pp.symbol.v | 1,296 | module MODULE1 (
input VAR1 ,
input VAR7 ,
output VAR6 ,
input VAR2 ,
input VAR4,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n.symbol.v | 1,431 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR5
);
supply1 VAR6;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp.pp.symbol.v | 1,329 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR1 ,
input VAR3 ,
input VAR7,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way/src/riffa/mux.v | 5,119 | module MODULE2
parameter VAR1 = 4,
parameter VAR8 = 2,
parameter VAR9 = 32,
parameter VAR7 = "VAR11"
)
(
input [(VAR1)*VAR9-1:0] VAR14,
input [VAR8-1:0] VAR12,
output [VAR9-1:0] VAR2
);
generate
if(VAR7 == "VAR11") begin
MODULE3
.VAR1 (VAR1),
.VAR8 (VAR8),
.VAR9 (VAR9))
VAR4
(
.VAR2 (VAR2[VAR9-1:0]),
.VAR14 (VAR14[(VAR... | mit |
Bjay1435/capstone | Geoff/Geoff.ip_user_files/ip/blk_mem_gen_1/blk_mem_gen_1_stub.v | 1,346 | module MODULE1(VAR3, VAR4, VAR6, VAR2, VAR5, VAR1)
;
input VAR3;
input VAR4;
input [0:0]VAR6;
input [18:0]VAR2;
input [9:0]VAR5;
output [9:0]VAR1;
endmodule | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_8c_v1_00_a/hdl/verilog/cf_adc_if_1.v | 12,037 | module MODULE1 (
VAR67,
VAR27,
VAR18,
VAR63,
VAR7,
VAR9,
VAR76,
VAR22,
VAR32,
VAR77,
VAR53);
input VAR67;
input VAR27;
input VAR18;
input VAR63;
input VAR7;
input VAR9;
input [ 3:0] VAR76;
output VAR22;
output VAR32;
output [11:0] VAR77;
input VAR53;
reg VAR44 = 'd0;
reg VAR60 = 'd0;
reg VAR2 = 'd0;
reg VAR34 = 'd0;
re... | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_tempmon.v | 25,558 | module MODULE1 #
(
parameter VAR49 = 100, parameter VAR124 = 1465, parameter VAR29 = 1,
parameter VAR50 = 12'h8ac,
parameter VAR17 = 12'hca4
)
(
input clk, input rst, input VAR69, input VAR98, input [11:0] VAR16, output VAR1, output VAR70, output VAR94 );
localparam VAR96 = (VAR29 * 4096) / 504;
localparam VAR108 = ((V... | bsd-2-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/next_hop_ram.v | 18,078 | module MODULE1(clk, addr, VAR23, VAR19, VAR77, en, reset);
input clk;
input [12:2] addr;
input [31:0] VAR23;
output [31:0] VAR19;
input [3:0] VAR77;
input en;
input reset;
wire [3:0] VAR20;
VAR46 VAR66(
.VAR26 (VAR19[7:0]),
.VAR60 (),
.VAR43 (addr[12:2]),
.VAR16 (clk),
.VAR82 (VAR23[7:0]),
.VAR50 (VAR20[0]),
.VAR38 (en... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb.functional.pp.v | 1,988 | module MODULE1 (
VAR15 ,
VAR10 ,
VAR17 ,
VAR5 ,
VAR4 ,
VAR6,
VAR2,
VAR3 ,
VAR7
);
output VAR15 ;
input VAR10 ;
input VAR17 ;
input VAR5 ;
input VAR4 ;
input VAR6;
input VAR2;
input VAR3 ;
input VAR7 ;
wire VAR9 ;
wire VAR14 ;
wire VAR11;
nand VAR8 (VAR9 , VAR4, VAR5 );
or VAR1 (VAR14 , VAR17, VAR10, VAR9 );
VAR16 VAR13... | apache-2.0 |
peteasa/oh | src/axi/dv/aximaster_stub.v | 4,220 | module MODULE1 (
VAR31, VAR15, VAR33, VAR19, VAR27,
VAR22, VAR30, VAR3, VAR35,
VAR23, VAR24, VAR28, VAR32, VAR13,
VAR36, VAR9, VAR18, VAR4, VAR26,
VAR34, VAR17, VAR16, VAR5,
VAR8, VAR39, VAR29, VAR6,
VAR37, VAR12, VAR7, VAR25, VAR41,
VAR21, VAR14, VAR38, VAR20, VAR11,
VAR1, VAR2, VAR40
);
parameter VAR10 = 12;
input VA... | mit |
trevortheblack/NewLondo16 | Verilog/register_bank_madness.v | 7,640 | module MODULE1();
input VAR47, VAR85, VAR10;
input [4:0] VAR52;
input [3:0] VAR45, VAR26, VAR17;
input VAR46;
input [3:0] VAR73;
input [31:0] VAR15;
output reg [31:0] VAR90, VAR96;
output reg VAR39;
reg [3:0] VAR88, VAR81;
always @ begin
case(VAR88)
4'b0000: VAR92 = VAR61 & VAR43;
4'b0001: VAR92 = VAR44 & VAR43;
4'b001... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp.blackbox.v | 1,378 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR2 ,
VAR3 ,
VAR7
);
output VAR4 ;
output VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR7;
supply1 VAR5;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_noise.v | 2,341 | module MODULE1(
input rst,
input clk,
input [4:0] VAR5,
input [9:0] VAR3,
input VAR9,
output reg [10:0] out
);
reg VAR8;
reg [3:0] VAR7;
always @(posedge clk)
if( rst ) begin
VAR7 <= 5'b0;
end
else begin
if( VAR9 ) begin
if ( &VAR7 ) begin
VAR7 <= VAR5[4:1]; end
else VAR7 <= VAR7 + 1'b1;
VAR8 <= &VAR7;
end
else VAR8 <=... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.behavioral.pp.v | 1,407 | module MODULE1( VAR8, VAR4, VAR3, VAR7, VAR1, VAR9, VAR10 );
input VAR1, VAR7, VAR8, VAR3;
inout VAR9, VAR10;
output VAR4;
VAR2 VAR5(.VAR8(VAR8),.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR1(VAR1),.VAR9(VAR9),.VAR10(VAR10));
VAR2 VAR6(.VAR8(VAR8),.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR1(VAR1),.VAR9(VAR9),.VAR10(VAR10)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4_1.v | 2,253 | module MODULE2 (
VAR4 ,
VAR11 ,
VAR9 ,
VAR8 ,
VAR10 ,
VAR2,
VAR5,
VAR6 ,
VAR1
);
output VAR4 ;
input VAR11 ;
input VAR9 ;
input VAR8 ;
input VAR10 ;
input VAR2;
input VAR5;
input VAR6 ;
input VAR1 ;
VAR7 VAR3 (
.VAR4(VAR4),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a.pp.symbol.v | 1,401 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR6 ,
input VAR8 ,
input VAR10 ,
output VAR7 ,
input VAR2 ,
input VAR5,
input VAR3,
input VAR9
);
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_disp.v | 14,450 | module MODULE1(
input VAR37,
output VAR78,
input VAR16,
input VAR26,
input VAR34, output VAR69,
input VAR25,
input VAR30,
input VAR80,
input VAR8,
input [VAR61-1:0] VAR17,
input [VAR61-1:0] VAR87,
input [VAR50-1:0] VAR52,
input [VAR50-1:0] VAR20,
input VAR10,
input [VAR61-1:0] VAR18,
input [VAR71-1:0] VAR58,
input [VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.symbol.v | 1,619 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR4
);
supply1 VAR1 ;
supply0 VAR8 ;
supply1 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv.pp.symbol.v | 1,309 | module MODULE1 (
input VAR5 ,
output VAR4,
input VAR2 ,
input VAR3 ,
input VAR1
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.behavioral.pp.v | 1,259 | module MODULE1( VAR5, VAR6, VAR7, VAR8, VAR2 );
input VAR6, VAR5;
inout VAR8, VAR2;
output VAR7;
VAR4 VAR1(.VAR5(VAR5),.VAR6(VAR6),.VAR7(VAR7),.VAR8(VAR8),.VAR2(VAR2));
VAR4 VAR3(.VAR5(VAR5),.VAR6(VAR6),.VAR7(VAR7),.VAR8(VAR8),.VAR2(VAR2)); | apache-2.0 |
Lan-Hekary/ARM | register_file.v | 1,222 | module MODULE1(input clk,input VAR6,
input [3:0]VAR8,input [3:0]VAR5,input [3:0]VAR3,
input [31:0] VAR7,input [31:0] VAR2,
output [31:0]VAR4 ,output[31:0] VAR9
);
reg[31:0] VAR1[0:15];
always@(posedge clk)begin
if(VAR6) VAR1[VAR3]=VAR7;
if(VAR2) VAR1[15]=VAR2;
end
assign VAR4 = (VAR8 == 4'b1111) ? VAR2 : VAR1[VAR8];
as... | gpl-3.0 |
sabertazimi/hust-lab | digitalLogic/labs/timingSignalGenerator/src/timing_signal.v | 1,088 | module MODULE1
(
input clk,
input VAR6,
output [(VAR8-1):0] VAR2
);
wire VAR10, VAR11;
wire [(VAR8-1):0] VAR1, VAR9;
assign VAR2 = {VAR9[3], VAR1[1], VAR1[2]&VAR9[1], VAR1[3]&VAR9[2]};
VAR4 #(.VAR8(1)) VAR12 (
.clk(~clk),
.VAR6(VAR6),
.VAR12(VAR1[1]),
.VAR1(VAR10),
.VAR9(VAR11));
VAR3 #(VAR8) VAR5 (
.clk(~(~clk&VAR11))... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pipe_clock.v | 21,828 | module MODULE1 #
(
parameter VAR72 = "VAR113", parameter VAR84 = "VAR113", parameter VAR83= "VAR113", parameter VAR111 = 1, parameter VAR21 = 3, parameter VAR81 = 0, parameter VAR120 = 2, parameter VAR71 = 2, parameter VAR17 = 1, parameter VAR153 = 0
)
(
input VAR31,
input VAR144,
input [VAR111-1:0] VAR29,
input VAR49,... | gpl-3.0 |
kdgwill/Verilog_Servo_Example | Servo.v | 2,406 | module MODULE1 #(
parameter VAR5 = 50000000, parameter VAR7 = 256,
parameter VAR12 = 21, parameter VAR3 = 5, parameter VAR6 = 8,
parameter VAR11 = 8,
parameter VAR9 = 256,
parameter VAR4 = 13
)(
input clk,
input rst,
input [VAR4-1:0] VAR10,
output reg [VAR11-1:0] address,
output reg VAR14
);
wire[VAR12-1:0] VAR2;
wire[... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/tx_engine.v | 19,532 | module MODULE1 #(
parameter VAR58 = 64,
parameter VAR11 = VAR58 / 8
)(
input VAR35,
input VAR13,
input VAR23,
output reg [VAR58-1:0] VAR3,
output reg [VAR11-1:0] VAR5,
output reg VAR18,
output reg VAR57,
output VAR44,
input VAR34,
output reg VAR68,
input [2:0] VAR64,
input VAR24,
input VAR61,
input [1:0] VAR19,
input [... | mit |
blu006/de0-nano-clock | FPGA/count_hours.v | 1,551 | module MODULE1(
VAR11,
VAR9,
VAR7,
VAR2,
VAR12,
VAR8,
VAR15,
VAR1
);
input VAR11;
input VAR9;
input VAR7;
output [3:0] VAR2;
output [3:0] VAR12;
output reg VAR8;
output reg VAR15;
output reg VAR1;
wire VAR6;
reg VAR5;
reg VAR16;
reg VAR13;
VAR10 VAR5 <= 0;
VAR4 VAR3(
VAR5,
VAR13,
VAR2,
VAR6
);
VAR4 VAR14(
VAR5,
VAR6,
V... | bsd-2-clause |
HSID/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_gen.v | 5,850 | module MODULE1(
input clk,
input rst,
input VAR5,
input [63:0] VAR1,
input [31:0] VAR27,
input [31:0] VAR35,
input VAR3,
input VAR30,
input [63:0] VAR31,
input [2:0] VAR29,
input [15:0] VAR23,
output VAR34,
output [63:0] VAR32,
output VAR16,
input VAR24,
input [7:0] VAR6,
output [4:0] VAR7,
output [31:0] VAR25,
output ... | bsd-2-clause |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_log_s5_double.v | 247,351 | module MODULE1
(
VAR12,
VAR10,
VAR5,
VAR7,
VAR14,
VAR2) ;
input VAR12;
input VAR10;
input VAR5;
input [63:0] VAR7;
input [5:0] VAR14;
output [63:0] VAR2;
tri0 VAR12;
tri1 VAR10;
tri0 VAR5;
reg [0:0] VAR8;
reg [63:0] VAR1;
wire [6:0] VAR11;
wire VAR3;
wire [31:0] VAR4;
wire [447:0] VAR9;
wire [5:0] VAR6;
wire [383:0] VA... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/Counter.v | 1,613 | module MODULE1(
input wire clk, VAR3,
input wire VAR8,
output wire [3:0] VAR11, VAR4, VAR7, VAR10, VAR6, VAR1, VAR12, VAR5
);
reg [9:0] VAR9, VAR13;
reg [1:0] VAR14, VAR2;
begin
begin
begin
end
begin | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_dpram_256x32.v | 8,214 | module MODULE1(
VAR11, VAR6, VAR8, VAR35, VAR13, VAR27,
VAR40, VAR3, VAR25, VAR4, VAR9, VAR1
);
parameter VAR19 = 8;
parameter VAR24 = 32;
input VAR11; input VAR6; input VAR8; input VAR35; input [VAR19-1:0] VAR13; output [VAR24-1:0] VAR27; input VAR40; input VAR3; input VAR25; input VAR4; input [VAR19-1:0] VAR9; input ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp.behavioral.pp.v | 2,157 | module MODULE1 (
VAR15 ,
VAR21 ,
VAR8 ,
VAR4,
VAR19 ,
VAR5 ,
VAR20 ,
VAR2
);
output VAR15 ;
input VAR21 ;
input VAR8 ;
input VAR4;
input VAR19 ;
input VAR5 ;
input VAR20 ;
input VAR2 ;
wire VAR16 ;
wire VAR6 ;
reg VAR11 ;
wire VAR14 ;
wire VAR9;
wire VAR12 ;
wire VAR7 ;
wire VAR17 ;
wire VAR1 ;
not VAR13 (VAR6 , VAR9 )... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/general/sirv_gnrl_icbs.v | 57,658 | module MODULE3 # (
parameter VAR135 = 32,
parameter VAR84 = 64,
parameter VAR30 = 1,
parameter VAR60 = 0, parameter VAR180 = 1,
parameter VAR106 = 0,
parameter VAR93 = 4,
parameter VAR183 = 1,
parameter VAR76 = 2
) (
output VAR222,
input VAR311,
output [1-1:0] VAR255,
output [VAR135-1:0] VAR130,
output [VAR84-1:0] VAR7... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.behavioral.v | 8,998 | module MODULE1( VAR89, VAR13, VAR86, VAR71, VAR77 );
input VAR89, VAR13, VAR71, VAR86;
output VAR77;
reg VAR76;
VAR16 VAR87(.VAR89(VAR89),.VAR13(VAR13),.VAR86(VAR86),.VAR71(VAR71),.VAR77(VAR77),.VAR76(VAR76));
VAR16 VAR40(.VAR89(VAR89),.VAR13(VAR13),.VAR86(VAR86),.VAR71(VAR71),.VAR77(VAR77),.VAR76(VAR76));
not VAR69(VA... | apache-2.0 |
sergev/vak-opensource | hardware/basys3/abacus/seg_scroll.v | 1,078 | module MODULE1(
input clk,
input VAR5,
input [19:0] VAR3,
output [15:0] VAR1
);
reg [26:0] VAR2;
reg [23:0] VAR6;
always @(posedge VAR4 or posedge VAR5)
begin
if(VAR5==1)
begin
VAR6 [19:0] <= VAR3[19:0];
VAR6 [23:20] <= 'hC;
end
else
begin
VAR6 [19:0] <= VAR6[23:4];
VAR6 [23:20] <= VAR6[3:0];
end
end
assign VAR1[15:0] ... | apache-2.0 |
gigglesninja/digital-system-design | Lab5/ipcore_dir/mult12x12.v | 8,059 | module MODULE1 (
VAR63, VAR42, VAR50
);
output [23 : 0] VAR63;
input [11 : 0] VAR42;
input [11 : 0] VAR50;
wire \VAR18/VAR8 ;
wire \VAR18/VAR27 ;
wire \VAR24/VAR20<34>VAR54 ;
wire \VAR24/VAR20<33>VAR54 ;
wire \VAR24/VAR20<32>VAR54 ;
wire \VAR24/VAR20<31>VAR54 ;
wire \VAR24/VAR20<30>VAR54 ;
wire \VAR24/VAR20<29>VAR54 ;
... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/bank_mach.v | 31,023 | module MODULE1 #
(
parameter VAR69 = 100,
parameter VAR53 = "1T",
parameter VAR76 = 3,
parameter VAR160 = 2,
parameter VAR30 = "8",
parameter VAR94 = 12,
parameter VAR166 = 4,
parameter VAR9 = 5,
parameter VAR96 = 8,
parameter VAR156 = "VAR157",
parameter VAR162 = "VAR136",
parameter VAR97 = "VAR136",
parameter VAR142 ... | mit |
tommythorn/yari | shared/rtl/yari-core/stage_D.v | 14,859 | module MODULE1(input wire VAR65
,input wire VAR23 ,input wire [31:0] VAR71 ,input wire [31:0] VAR75 ,input wire [31:0] VAR54
,input wire VAR80
,input wire [ 5:0] VAR74
,input wire [31:0] VAR8
,input wire [31:0] VAR28
,input wire VAR40
,input wire [ 5:0] VAR91
,input wire [31:0] VAR94
,output reg VAR18 = 0
,output reg V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2.pp.blackbox.v | 1,260 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR7 ,
VAR4,
VAR2,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR4;
input VAR2;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/z80/tv80s.v | 4,935 | module MODULE1 (
VAR12, VAR15, VAR20, VAR10, VAR3, VAR21, VAR13, VAR7, VAR25, dout,
VAR23, clk, VAR5, VAR14, VAR30, VAR32, VAR27
);
parameter VAR1 = 0; parameter VAR26 = 1; parameter VAR28 = 1;
input VAR23;
input clk;
input VAR5;
input VAR14;
input VAR30;
input VAR32;
output VAR12;
output VAR15;
output VAR20;
output VA... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_onchip_memory2_0.v | 2,985 | module MODULE1 (
address,
VAR14,
VAR3,
clk,
VAR8,
reset,
VAR35,
write,
VAR26,
VAR34
)
;
parameter VAR28 = "VAR12.VAR23";
output [ 31: 0] VAR34;
input [ 8: 0] address;
input [ 3: 0] VAR14;
input VAR3;
input clk;
input VAR8;
input reset;
input VAR35;
input write;
input [ 31: 0] VAR26;
wire VAR25;
wire [ 31: 0] VAR34;
wir... | gpl-3.0 |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/Raster_Laser_Projector_Clock_Generators.v | 12,013 | module MODULE1
(
VAR5,
VAR1,
VAR3,
VAR2) ;
input VAR5;
input VAR1;
input [0:0] VAR3;
output [0:0] VAR2;
tri0 VAR5;
tri1 VAR1;
reg [0:0] VAR8;
reg [0:0] VAR7;
reg [0:0] VAR10;
wire VAR9;
wire VAR4;
wire VAR6; | gpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_altdqdqs.v | 6,981 | module MODULE1 (
VAR12,
VAR45,
VAR36,
VAR89,
VAR46,
VAR76,
VAR25,
VAR31,
VAR26,
VAR27,
VAR62,
VAR86,
VAR3,
VAR73,
VAR59,
VAR4,
VAR60,
VAR56,
VAR94,
VAR20,
VAR23,
VAR53,
VAR2,
VAR93,
VAR10,
VAR8,
VAR84,
VAR1,
VAR22,
VAR33,
VAR83,
VAR81,
VAR37,
VAR71,
VAR43,
VAR14,
VAR44,
VAR55
);
input [7-1:0] VAR55;
input VAR12;
input ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/mig_7series_v1_2.v | 44,556 | module MODULE1 #
(
parameter VAR138 = 3,
parameter VAR206 = 1,
parameter VAR140 = 10,
parameter VAR246 = 1,
parameter VAR46 = 1,
parameter VAR237 = 1,
parameter VAR39 = 5,
parameter VAR236 = 6,
parameter VAR105 = 8,
parameter VAR103 = 8,
parameter VAR142 = 64,
parameter VAR240 = 8,
parameter VAR166 = 3,
parameter VAR14... | lgpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/altera_avalon_mm_bridge.v | 11,983 | module MODULE1
parameter VAR45 = 32,
parameter VAR17 = 8,
parameter VAR55 = 2,
parameter VAR28 = 10,
parameter VAR50 = 1,
parameter VAR37 = 1,
parameter VAR2 = 1,
parameter VAR4 = VAR45 / VAR17
)
(
input clk,
input reset,
output VAR47,
output [VAR45-1:0] VAR36,
output VAR3,
output [VAR55-1:0] VAR5,
input [VAR50-1:0] VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.behavioral.v | 1,429 | module MODULE1( VAR1, VAR4, VAR2 );
input VAR4, VAR1;
output VAR2;
VAR6 VAR3(.VAR1(VAR1),.VAR4(VAR4),.VAR2(VAR2));
VAR6 VAR5(.VAR1(VAR1),.VAR4(VAR4),.VAR2(VAR2)); | apache-2.0 |
tmolteno/TART | hardware/FPGA/wishbone/rtl/wb_store.v | 3,864 | module MODULE1
input VAR1,
input VAR10,
output reg VAR15 = 1'b0,
output reg VAR14 = 1'b0,
output VAR11,
input VAR4,
input VAR5,
input VAR3,
input VAR20,
output [VAR6:0] VAR16,
input VAR18,
output reg VAR2 = 1'b0
);
reg [VAR6:0] VAR13 = {VAR8{1'b0}};
wire [VAR8:0] VAR7 = VAR13 + 1;
wire VAR12 = !VAR20 && !VAR3 && (VAR14... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2/sky130_fd_sc_ls__nand2.pp.blackbox.v | 1,266 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR2 ,
VAR1,
VAR5,
VAR3 ,
VAR6
);
output VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2.behavioral.v | 1,440 | module MODULE1 (
VAR1,
VAR6
);
output VAR1;
input VAR6;
supply1 VAR3;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR7 ;
wire VAR4;
not VAR8 (VAR4, VAR6 );
buf VAR9 (VAR1 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b.behavioral.v | 1,510 | module MODULE1 (
VAR2 ,
VAR12 ,
VAR5 ,
VAR8 ,
VAR4
);
output VAR2 ;
input VAR12 ;
input VAR5 ;
input VAR8 ;
input VAR4;
supply1 VAR1;
supply0 VAR9;
supply1 VAR10 ;
supply0 VAR6 ;
wire VAR14 ;
wire VAR7;
not VAR13 (VAR14 , VAR4 );
nor VAR3 (VAR7, VAR12, VAR5, VAR8, VAR14);
buf VAR11 (VAR2 , VAR7 );
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/i_m_areg.v | 1,204 | module MODULE1( clk,
rst,
VAR3,
VAR1,
VAR7,
VAR4,
VAR2
);
input clk;
input rst;
input [47:0] VAR3;
input VAR1;
input VAR7;
output [47:0] VAR4;
output VAR2;
reg VAR6;
reg [47:0] VAR5;
always@(posedge clk)
begin
if(rst||VAR7)
VAR5<=48'h0000;
end
else if(VAR1)
VAR5<=VAR3;
end
always@(posedge clk)
begin
if(rst||VAR7)
VAR6<... | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOS_Sys/synthesis/submodules/NIOS_Sys_onchip_memory2_0.v | 3,074 | module MODULE1 (
address,
VAR28,
VAR34,
clk,
VAR4,
reset,
VAR27,
write,
VAR17,
VAR11
)
;
parameter VAR19 = "MODULE1.VAR8";
output [ 31: 0] VAR11;
input [ 11: 0] address;
input [ 3: 0] VAR28;
input VAR34;
input clk;
input VAR4;
input reset;
input VAR27;
input write;
input [ 31: 0] VAR17;
wire VAR9;
wire [ 31: 0] VAR11;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a.behavioral.pp.v | 1,998 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR14 ,
VAR10 ,
VAR6,
VAR5,
VAR12 ,
VAR2
);
output VAR4 ;
input VAR8 ;
input VAR14 ;
input VAR10 ;
input VAR6;
input VAR5;
input VAR12 ;
input VAR2 ;
wire VAR16 ;
wire VAR1 ;
wire VAR11;
or VAR9 (VAR16 , VAR14, VAR8 );
and VAR7 (VAR1 , VAR16, VAR10 );
VAR3 VAR13 (VAR11, VAR1, VAR6, VAR5);... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_log.v | 149,313 | module MODULE2 (
enable, VAR25,
VAR15,
VAR19,
VAR1);
input enable, VAR25;
input VAR15;
input [31:0] VAR19;
output [31:0] VAR1;
wire [31:0] VAR9;
wire [31:0] VAR1 = VAR9[31:0];
VAR10 VAR8 ( .VAR2(VAR15),
.reset(~VAR25),
.enable(enable),
.VAR5(VAR19[31]),
.VAR24(VAR19[30:23]),
.VAR23(VAR19[22:0]),
.VAR17(VAR9[31]),
.VAR2... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy_phy_alt_mem_phy_pll_bb.v | 19,287 | module MODULE1 (
VAR3,
VAR1,
VAR11,
VAR8,
VAR2,
VAR10,
VAR7,
VAR4,
VAR12,
VAR13,
VAR6,
VAR14,
VAR5,
VAR9,
VAR15);
input VAR3;
input VAR1;
input [3:0] VAR11;
input VAR8;
input VAR2;
input VAR10;
output VAR7;
output VAR4;
output VAR12;
output VAR13;
output VAR6;
output VAR14;
output VAR5;
output VAR9;
output VAR15;
tri0 ... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/rtl/eth_mac_phy_10g_rx.v | 4,898 | module MODULE1 #
(
parameter VAR3 = 64,
parameter VAR21 = (VAR3/8),
parameter VAR18 = (VAR3/32),
parameter VAR4 = 4'h6,
parameter VAR17 = 16'h6666,
parameter VAR13 = 0,
parameter VAR27 = 96,
parameter VAR31 = (VAR13 ? VAR27 : 0) + 1,
parameter VAR32 = 0,
parameter VAR5 = 0,
parameter VAR14 = 0,
parameter VAR26 = 0,
par... | mit |
swanyboy2/VideoSync | video_sync.v | 2,508 | module MODULE1(
input VAR17,
output VAR10,
output VAR15,
output VAR14,
output VAR18, output reg [8:0] VAR12,
output reg [8:0] VAR23);
parameter VAR13 = 320;
parameter VAR2 = 4;
parameter VAR3 = 48;
parameter VAR24 = 28;
parameter VAR7 = 240;
parameter VAR9 = 1;
parameter VAR4 = 15;
parameter VAR5 = 4;
parameter VAR8 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o.behavioral.v | 1,567 | module MODULE1 (
VAR10 ,
VAR6,
VAR9,
VAR14,
VAR2,
VAR8
);
output VAR10 ;
input VAR6;
input VAR9;
input VAR14;
input VAR2;
input VAR8;
supply1 VAR3;
supply0 VAR4;
supply1 VAR11 ;
supply0 VAR12 ;
wire VAR13 ;
wire VAR15;
and VAR1 (VAR13 , VAR14, VAR6, VAR9 );
or VAR5 (VAR15, VAR13, VAR8, VAR2);
buf VAR7 (VAR10 , VAR15 );... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.behavioral.v | 1,170 | module MODULE1( VAR5, VAR1, VAR4 );
input VAR5, VAR1;
output VAR4;
VAR3 VAR2(.VAR5(VAR5),.VAR1(VAR1),.VAR4(VAR4));
VAR3 VAR6(.VAR5(VAR5),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/bashkiria-2m/src/b2m_kbd.v | 4,991 | module MODULE1(
input clk,
input reset,
input VAR8,
input VAR2,
input[8:0] addr,
output reg VAR11,
output reg[7:0] VAR9);
reg[7:0] VAR12[10:0];
always @(addr,VAR12) begin
if (addr[8])
VAR9 =
(VAR12[8] & {8{addr[0]}})|
(VAR12[9] & {8{addr[1]}})|
(VAR12[10] & {8{addr[2]}});
end
else
VAR9 =
(VAR12[0] & {8{addr[0]}})|
(VAR... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/bw_clk_cl_fpu_cmp.v | 1,753 | module MODULE1 (
VAR5,
VAR3,
VAR8,
VAR7,
VAR4,
VAR14,
VAR11,
VAR13,
VAR10,
VAR12,
VAR9,
VAR6
);
output VAR5;
output VAR3;
output VAR8;
output VAR7;
input VAR4;
input VAR14;
input VAR11;
input VAR13;
input VAR10;
input VAR12;
input VAR9;
input VAR6;
VAR1 VAR2 (
.VAR7 (VAR7 ),
.VAR5 (VAR5 ),
.VAR3 (VAR3 ),
.VAR8 (VAR8 ),... | gpl-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/uart16550/uart_top.v | 11,863 | module MODULE1 (
VAR12,
VAR2, VAR31, VAR27, VAR30, VAR5, VAR40, VAR39, VAR10, VAR16,
VAR21,
VAR19, VAR23,
VAR3, VAR18, VAR43, VAR32, VAR22, VAR4
, VAR8
);
parameter VAR17 = VAR44;
parameter VAR37 = VAR49;
input VAR12;
input VAR2;
input [VAR37-1:0] VAR31;
input [VAR17-1:0] VAR27;
output [VAR17-1:0] VAR30;
input VAR5;
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv.behavioral.v | 1,640 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR7,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR7;
input VAR5;
wire VAR9 ;
wire VAR6;
not VAR3 (VAR9 , VAR2 );
VAR8 VAR10 (VAR6, VAR9, VAR7, VAR5);
buf VAR4 (VAR1 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fah/sky130_fd_sc_hd__fah.functional.pp.v | 2,616 | module MODULE1 (
VAR22,
VAR5 ,
VAR19 ,
VAR2 ,
VAR24 ,
VAR3,
VAR9,
VAR18 ,
VAR12
);
output VAR22;
output VAR5 ;
input VAR19 ;
input VAR2 ;
input VAR24 ;
input VAR3;
input VAR9;
input VAR18 ;
input VAR12 ;
wire VAR10 ;
wire VAR20 ;
wire VAR21 ;
wire VAR26 ;
wire VAR11 ;
wire VAR1 ;
wire VAR15;
xor VAR7 (VAR10 , VAR19, VA... | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_counter_v1_0/axis_counter.v | 1,316 | module MODULE1 #
(
parameter integer VAR9 = 32,
parameter integer VAR6 = 32
)
(
input wire VAR7,
input wire VAR5,
input wire [VAR6-1:0] VAR2,
output wire [VAR9-1:0] VAR11,
output wire VAR12
);
reg [VAR6-1:0] VAR1, VAR8;
reg VAR4, VAR3;
wire VAR10;
always @(posedge VAR7)
begin
if(~VAR5)
begin
VAR1 <= {(VAR6){1'b0}};
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3b/sky130_fd_sc_lp__and3b.functional.pp.v | 1,961 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR9 ,
VAR1 ,
VAR12,
VAR2,
VAR5 ,
VAR3
);
output VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR12;
input VAR2;
input VAR5 ;
input VAR3 ;
wire VAR13 ;
wire VAR4 ;
wire VAR14;
not VAR7 (VAR13 , VAR8 );
and VAR15 (VAR4 , VAR1, VAR13, VAR9 );
VAR10 VAR11 (VAR14, VAR4, VAR12, VAR2);
b... | apache-2.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/alu_flags.v | 1,248 | module MODULE1
(
input [VAR3-1:0] VAR1,
input [VAR3-1:0] VAR4,
input [3:0] VAR6,
output VAR7,
output VAR2,
output VAR5
);
wire [VAR3-1:0] sum, VAR9;
wire VAR8, VAR10;
assign {VAR8, sum} = VAR1 + VAR4; assign {VAR10, VAR9} = VAR1 - VAR4;
assign VAR7 = (VAR1 == VAR4);
assign VAR2 = (VAR6 == 4'd5) ? ((VAR1[VAR3-1] & VAR4[... | mit |
ultraembedded/riscv | core/riscv/riscv_issue.v | 20,569 | module MODULE1
parameter VAR19 = 1
,parameter VAR211 = 1
,parameter VAR108 = 1
,parameter VAR103 = 1
,parameter VAR1 = 0
)
(
input VAR139
,input VAR38
,input VAR57
,input [ 31:0] VAR106
,input [ 31:0] VAR40
,input VAR169
,input VAR184
,input VAR214
,input VAR86
,input VAR222
,input VAR228
,input VAR128
,input VAR42
,in... | bsd-3-clause |
asicguy/gplgpu | hdl/vga/vga_hint.v | 4,875 | module MODULE1
(
input VAR5, input VAR26, input VAR34, input VAR7, input VAR17, input [3:0] VAR4, input [31:0] VAR30, input [22:0] VAR2, input VAR9, input [31:0] VAR3, input VAR13,
output reg [31:0] VAR11, output reg [31:0] VAR20, output reg [22:0] VAR24, output VAR28, output reg VAR14, output reg [3:0] VAR10, output r... | gpl-3.0 |
pavel-demin/red-pitaya-notes | cores/axis_ram_writer_v1_0/axis_ram_writer.v | 5,102 | module MODULE1 #
(
parameter integer VAR21 = 20,
parameter integer VAR16 = 6,
parameter integer VAR13 = 32,
parameter integer VAR25 = 64,
parameter integer VAR28 = 64,
parameter integer VAR46 = 512
)
(
input wire VAR5,
input wire VAR52,
input wire [VAR13-1:0] VAR62,
output wire [VAR21-1:0] VAR8,
output wire [VAR16-1:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp.pp.blackbox.v | 1,269 | module MODULE1 (
VAR1,
VAR2,
VAR3 ,
VAR5,
VAR4,
VAR6 ,
VAR7
);
output VAR1;
input VAR2;
input VAR3 ;
input VAR5;
input VAR4;
input VAR6 ;
input VAR7 ;
endmodule | apache-2.0 |
qeedquan/fpga | de2-115/my_first_fpga/cntmux.v | 3,744 | module MODULE1 (
VAR10,
VAR6,
sel,
VAR17);
input [3:0] VAR10;
input [3:0] VAR6;
input sel;
output [3:0] VAR17;
wire [3:0] VAR13;
wire [3:0] VAR12 = VAR6[3:0];
wire [3:0] VAR17 = VAR13[3:0];
wire [3:0] VAR14 = VAR10[3:0];
wire [7:0] VAR11 = {VAR12, VAR14};
wire VAR4 = sel;
wire VAR20 = VAR4;
VAR5 VAR8 (
.VAR18 (VAR11),
... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/mc_phy.v | 56,478 | module MODULE1
parameter VAR131 = 4'b1111,
parameter VAR29 = 4'b0000,
parameter VAR244 = 4'b0000,
parameter VAR26 = 4'b0000,
parameter VAR206 = 4'b0000,
parameter VAR87 = 4'hc,
parameter VAR209 = 4'hf,
parameter VAR142 = 4'hf,
parameter VAR139 = 4'hf,
parameter VAR186 = 4'hf,
parameter VAR137 = 48'hdffdfffedfff,
parame... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_1.behavioral.pp.v | 2,782 | module MODULE1( VAR26, VAR16, VAR22, VAR9, VAR15, VAR11 );
input VAR22, VAR16, VAR26;
inout VAR15, VAR11;
output VAR9;
reg VAR14;
VAR23 VAR17(.VAR26(VAR26),.VAR16(VAR16),.VAR22(VAR22),.VAR9(VAR9),.VAR15(VAR15),.VAR11(VAR11),.VAR14(VAR14));
VAR23 VAR8(.VAR26(VAR26),.VAR16(VAR16),.VAR22(VAR22),.VAR9(VAR9),.VAR15(VAR15),.... | apache-2.0 |
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