repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Raamakrishnan/MyProc | MyProc2/Proc.v | 5,079 | module MODULE1 (
input clk, input VAR11, output reg VAR87
,input wire VAR43
);
wire [VAR22 - 1:0] VAR78;
wire [VAR22 - 3:0] VAR40;
wire [VAR22 - 1:0] VAR79;
wire [VAR22 - 3:0] VAR85;
wire VAR29;
wire [VAR22 - 3:0] VAR12;
VAR51 VAR51(.clk(clk), .VAR11(VAR11), .VAR58(VAR78), .VAR91(VAR40), .VAR29(VAR29), .VAR12(VAR12));
... | mit |
ILoveSpeccy/Aeon-Lite | cores/radio-86rk/src/k580ww55.v | 1,452 | module MODULE1(
input clk, input reset, input[1:0] addr, input VAR1,
input[7:0] VAR7, output reg[7:0] VAR5,
input[7:0] VAR9, output reg[7:0] VAR2,
input[7:0] VAR4, output reg[7:0] VAR3,
input[7:0] VAR6, output reg[7:0] VAR8);
always begin
case (addr)
2'b00: VAR5 = VAR9;
2'b01: VAR5 = VAR4;
2'b10: VAR5 = VAR6;
2'b11: VA... | gpl-3.0 |
fpgaminer/sha1_collider | hdl/sha1.v | 3,556 | module MODULE2 (
input clk,
input [511:0] VAR3,
output reg [159:0] VAR30
);
reg [31:0] VAR28;
reg [511:0] VAR23;
always @ (posedge clk)
begin
VAR28 <= 32'hC3D2E1F0 + 32'h5A827999 + VAR3[VAR8(0)];
VAR23 <= VAR3;
end
genvar VAR14;
generate
for (VAR14 = 0; VAR14 < 80; VAR14=VAR14+1) begin : VAR16
wire [511:0] VAR9, VAR32;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn.pp.symbol.v | 1,490 | module MODULE1 (
input VAR7 ,
output VAR10 ,
output VAR4 ,
input VAR5,
input VAR6 ,
input VAR8 ,
input VAR2 ,
input VAR9 ,
input VAR3 ,
input VAR1
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_1.behavioral.pp.v | 1,236 | module MODULE1( VAR7, VAR2, VAR3, VAR6, VAR1 );
input VAR7, VAR2;
inout VAR6, VAR1;
output VAR3;
VAR4 VAR5(.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1));
VAR4 VAR8(.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn.symbol.v | 1,431 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR4,
input VAR5
);
supply1 VAR6;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/alt_mem_ddrx_mm_st_converter.v | 10,706 | module MODULE1 # (
parameter
VAR20 = 3,
VAR41 = 25,
VAR16 = 32,
VAR8 = 8,
VAR10 = 4,
VAR23 = 0
)
(
VAR29, VAR31,
VAR30, VAR45,
VAR63, VAR47, VAR60, VAR13, VAR64, VAR15, VAR58, VAR57, VAR62, VAR17,
VAR4, VAR53, VAR28, VAR18,
VAR14,
VAR3,
VAR32,
VAR34,
VAR59,
VAR39,
VAR54,
VAR44,
VAR40,
VAR22,
VAR65,
VAR36,
VAR25,
VAR55,... | gpl-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/genrefresh.v | 2,349 | module MODULE1 (
VAR1,
VAR5,
VAR4,
VAR6
);
parameter VAR2 = 20000;
parameter VAR3 = 15;
input VAR1;
input VAR5;
output VAR4;
input VAR6;
reg [VAR3-1:0] counter;
reg VAR4 = 0;
always @(posedge VAR1)
begin
if (~VAR5)
begin
counter <= 0;
VAR4 <= 0;
end
else
begin
if (counter == VAR2)
begin
counter <= 0;
VAR4 <= 1;
end
els... | lgpl-3.0 |
ptracton/wb_soc_template | rtl/adv_debug_sys/Hardware/adv_dbg_if/bench/full_system/onchip_ram_top.v | 9,454 | module MODULE1 (
VAR29, VAR48,
VAR21, VAR38, VAR35, VAR58, VAR15, VAR19,
VAR49, VAR39, VAR51
);
function integer VAR14;
input [31:0] VAR59;
for (VAR14=0; VAR59>0; VAR14=VAR14+1)
VAR59 = VAR59>>1;
endfunction
parameter VAR54 = 32;
parameter VAR33 = 4096;
parameter VAR9 = "VAR16";
parameter VAR26 = (VAR33 / (VAR54/8)); p... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_119.v | 1,515 | module MODULE2 (
VAR11,
VAR12
);
input [31:0] VAR11;
output [31:0]
VAR12;
wire [31:0]
VAR3,
VAR9,
VAR1,
VAR14,
VAR13,
VAR8,
VAR4,
VAR10,
VAR7;
assign VAR3 = VAR11;
assign VAR13 = VAR14 - VAR1;
assign VAR14 = VAR1 << 5;
assign VAR4 = VAR8 - VAR3;
assign VAR8 = VAR13 << 4;
assign VAR7 = VAR10 - VAR4;
assign VAR10 = VAR3 ... | mit |
nliu96/openHMC_Altera | src/crc_accu.v | 14,358 | module MODULE1 #(parameter VAR8=4)(
input wire clk ,
input wire VAR1 ,
input wire [VAR8-1:0] VAR7 ,
input wire [(VAR8*32)-1:0] din ,
input wire [VAR8-1:0] valid ,
output reg [31:0] VAR2
);
integer if;
reg [31:0] VAR6 [VAR8:0];
wire [31:0] in [VAR8-1:0];
genvar VAR5;
generate
for(VAR5=0;VAR5<VAR8;VAR5=VAR5+1) begin : VA... | lgpl-3.0 |
mosukiton/mipsprocessor | Mips_single_cycle.srcs/sources_1/new/execute.v | 1,774 | module MODULE1(
output [31:0] VAR19, VAR8, VAR28,
output [4:0] VAR23,
output VAR14, VAR13, VAR7, VAR21, VAR26,
input [31:0] VAR10, VAR24, VAR20, VAR9,
input [4:0] VAR17, rd,
input [2:0] VAR1,
input VAR11, VAR15, VAR2, VAR12, VAR3, VAR6
);
wire [31:0] VAR25, VAR16;
alu VAR22(
.VAR19( VAR19 ),
.VAR18( VAR26 ),
.VAR27( VA... | gpl-3.0 |
SymbiFlow/prjxray-experiments-archive-2017 | fixedpnr/top_fdce_inv.v | 1,777 | module MODULE1(input clk, VAR1, VAR7, VAR10, output VAR5);
VAR11 VAR8 (
.VAR2(clk),
.VAR6(VAR1),
.VAR4(VAR7),
.VAR9(VAR10),
.VAR3(VAR5)
);
endmodule | isc |
olofk/oh | elink/hdl/etx.v | 8,996 | module MODULE1(
VAR25, VAR24, VAR44, VAR9, VAR52,
VAR7, VAR43, VAR23, VAR32, VAR36, VAR37,
VAR21, VAR11, VAR26, VAR48, VAR10,
VAR29,
VAR50, VAR13, VAR2, VAR54, VAR31,
VAR45, VAR17, VAR39, VAR56,
VAR20, VAR19, VAR53, VAR15, VAR18
);
parameter VAR1 = 32;
parameter VAR42 = 32;
parameter VAR22 = 104;
parameter VAR3 = 6;
pa... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp.functional.pp.v | 2,000 | module MODULE1 (
VAR4 ,
VAR14 ,
VAR6 ,
VAR12 ,
VAR5,
VAR11 ,
VAR8 ,
VAR1 ,
VAR15
);
output VAR4 ;
output VAR14 ;
input VAR6 ;
input VAR12 ;
input VAR5;
input VAR11 ;
input VAR8 ;
input VAR1 ;
input VAR15 ;
wire VAR13;
wire VAR3;
not VAR16 (VAR3 , VAR5 );
VAR2 VAR17 VAR9 (VAR13 , VAR12, VAR6, VAR3, , VAR11, VAR8);
buf V... | apache-2.0 |
drom/quark | v/core.v | 3,655 | module MODULE1 (
VAR20,
VAR10,
VAR15, VAR27, VAR19, VAR14, VAR25, VAR11, VAR22, VAR28, VAR5, VAR18, VAR30, VAR13, VAR23,
clk, VAR12
);
input clk, VAR12;
input [63:0] VAR20;
input [1:0] VAR10;
output [3:0] VAR15, VAR27, VAR19, VAR14, VAR25, VAR11, VAR22, VAR28, VAR5, VAR18, VAR30, VAR13, VAR23;
reg [63:0] VAR1;
reg [31:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrckapwr/sky130_fd_sc_hd__lpflow_isobufsrckapwr.blackbox.v | 1,481 | module MODULE1 (
VAR4 ,
VAR5,
VAR2
);
output VAR4 ;
input VAR5;
input VAR2 ;
supply1 VAR3;
supply1 VAR8 ;
supply0 VAR6 ;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtp/sky130_fd_sc_hd__dlxtp.blackbox.v | 1,292 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3
);
output VAR2 ;
input VAR6 ;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
cpulabs/mist1032isa | src/core/pipeline_control/pipeline_control_irq_call.v | 8,606 | module MODULE1(
input wire VAR72,
input wire VAR75,
input wire VAR35,
input wire [31:0] VAR60,
input wire [31:0] VAR28,
input wire [31:0] VAR68,
input wire [31:0] VAR66,
input wire [31:0] VAR44,
input wire VAR52,
input wire [6:0] VAR3,
output wire VAR21,
output wire [31:0] VAR10,
output wire VAR34,
output wire [31:0] V... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.functional.pp.v | 1,410 | module MODULE1( VAR11, VAR13, VAR6, VAR19, VAR16, VAR22, VAR12, VAR2, VAR14 );
input VAR12, VAR22, VAR11, VAR6, VAR13, VAR16;
inout VAR2, VAR14;
output VAR19;
wire VAR17;
not VAR4( VAR17, VAR13 );
wire VAR18;
not VAR9( VAR18, VAR16 );
wire VAR15;
and VAR3( VAR15, VAR17, VAR18, VAR12 );
wire VAR20;
and VAR10( VAR20, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.v | 2,408 | module MODULE2 (
VAR2 ,
VAR6,
VAR8,
VAR4 ,
VAR7 ,
VAR9,
VAR3,
VAR1 ,
VAR11
);
output VAR2 ;
input VAR6;
input VAR8;
input VAR4 ;
input VAR7 ;
input VAR9;
input VAR3;
input VAR1 ;
input VAR11 ;
VAR10 VAR5 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR11(VAR... | apache-2.0 |
m-labs/milkymist | cores/dmx/rtl/dmx_dpram.v | 1,303 | module MODULE1 #(
parameter VAR9 = 9,
parameter VAR3 = 8
) (
input clk,
input [VAR9-1:0] VAR10,
input VAR7,
input [VAR3-1:0] VAR4,
output reg [VAR3-1:0] do,
input [VAR9-1:0] VAR6,
input VAR8,
input [VAR3-1:0] VAR1,
output reg [VAR3-1:0] VAR11
);
reg [VAR3-1:0] VAR5[0:(1 << VAR9)-1];
always @(posedge clk) begin
if(VAR7)... | lgpl-3.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/start_for_CvtColoudo.v | 3,003 | module MODULE2 (
clk,
VAR22,
VAR16,
VAR23,
VAR14);
parameter VAR5 = 32'd1;
parameter VAR3 = 32'd3;
parameter VAR1 = 32'd5;
input clk;
input [VAR5-1:0] VAR22;
input VAR16;
input [VAR3-1:0] VAR23;
output [VAR5-1:0] VAR14;
reg[VAR5-1:0] VAR6 [0:VAR1-1];
integer VAR24;
always @ (posedge clk)
begin
if (VAR16)
begin
for (VAR... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_005.v | 1,527 | module MODULE2 (
VAR9,
VAR14
);
input [31:0] VAR9;
output [31:0]
VAR14;
wire [31:0]
VAR8,
VAR3,
VAR6,
VAR2,
VAR1,
VAR7,
VAR12,
VAR13,
VAR11;
assign VAR8 = VAR9;
assign VAR7 = VAR6 << 2;
assign VAR13 = VAR1 << 5;
assign VAR2 = VAR8 << 7;
assign VAR11 = VAR12 + VAR13;
assign VAR3 = VAR8 << 8;
assign VAR6 = VAR8 + VAR3;
a... | mit |
ppnipuna/Asynchronous_FIFO | rtl/fifo_top.v | 2,138 | module MODULE1
parameter VAR34 = 32,
VAR7 = 32,
VAR41 = 5
)
(
input wire write, VAR35, VAR37, read, VAR15, VAR12,
input wire [VAR7-1:0] VAR38,
output wire [VAR7-1:0] VAR42,
output wire VAR1, VAR11
);
function [VAR41:0] VAR2;
input [VAR41:0] VAR40;
reg [VAR41:0] VAR9;
integer VAR14;
begin
VAR9[VAR41] = VAR40 [VAR41];
fo... | mit |
olgirard/openmsp430 | core/synthesis/actel/src/smartgen/pmem.v | 10,775 | module MODULE1(VAR64,VAR49,VAR31,VAR69,VAR51,VAR15,VAR28,VAR3);
input [7:0] VAR64;
output [7:0] VAR49;
input VAR31, VAR69;
input [11:0] VAR51, VAR15;
input VAR28, VAR3;
wire VAR1, VAR54;
VAR1 VAR86(.VAR39(VAR1));
VAR54 VAR40(.VAR39(VAR54));
VAR2 VAR41(.VAR44(VAR51[11]), .VAR52(VAR51[10]),
.VAR89(VAR51[9]), .VAR7(VAR51[... | bsd-3-clause |
wgwozdz/Spartan_LCD | lcd.v | 2,228 | module MODULE1 (
input clk,
output reg VAR1,
output reg VAR4,
output reg VAR9,
output reg [7:4] VAR3,
output [4:0] VAR6,
input [7:0] VAR2
);
parameter VAR13 = 24;
parameter VAR7 = 17; parameter VAR14 = 11; parameter VAR10 = 6'b010000;
reg [VAR13:0] VAR11 = 0;
reg [5:0] VAR8 = VAR10;
reg VAR15 = 1; reg VAR12 = 0;
assign... | unlicense |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_16b_es_v1_00_a/hdl/verilog/cf_h2v_hdmi.v | 16,741 | module MODULE1 (
VAR83,
VAR73,
VAR7, VAR10, VAR12, VAR53, VAR16, VAR75, VAR4, VAR68, VAR32, VAR67, VAR104, VAR93,
VAR94,
VAR107, VAR108, VAR38,
VAR11,
VAR27,
VAR18,
VAR62,
VAR3,
VAR98,
VAR1,
VAR110,
VAR40,
VAR65,
VAR45);
input VAR83;
input [15:0] VAR73;
output VAR7;
output VAR10;
output [15:0] VAR12;
output VAR53;
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4.behavioral.pp.v | 1,768 | module MODULE1 (
VAR10,
VAR1,
VAR3 ,
VAR5 ,
VAR13 ,
VAR2 ,
VAR11
);
input VAR10;
input VAR1;
output VAR3 ;
input VAR5 ;
input VAR13 ;
input VAR2 ;
input VAR11 ;
wire VAR9 ;
wire VAR6;
nor VAR12 (VAR9 , VAR5, VAR13, VAR2, VAR11 );
VAR7 VAR4 (VAR6, VAR9, VAR10, VAR1);
buf VAR8 (VAR3 , VAR6 );
endmodule | apache-2.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/X6000_ztex_comm4/hdl/fpgaminer_top.v | 4,251 | module MODULE1 (
input VAR17
);
localparam VAR6 = 100;
localparam VAR7 = 200;
localparam VAR50 = 50;
localparam VAR12 = 250;
wire VAR28;
VAR37 VAR31 ( .VAR41 (VAR17), .VAR10 (VAR28));
reg [255:0] VAR47 = 0;
reg [95:0] VAR11 = 0;
reg [31:0] VAR49 = 32'd253, VAR40 = 32'd0;
wire VAR35;
wire VAR1, VAR48, VAR2;
VAR43 # (
.V... | gpl-3.0 |
titorgalaxy/Titor | rtl/verilog/core/Splitter.v | 2,510 | module MODULE1 (
VAR2,
VAR36,
VAR3,
VAR39,
VAR6,
VAR20,
VAR5,
VAR17,
VAR8,
VAR28,
VAR35,
VAR1
);
input [VAR43-1 :0] VAR2;
output reg [VAR42-1 :0] VAR36;
output reg [VAR38-1 :0] VAR3;
output reg [VAR25-1 :0] VAR39;
output reg [VAR22-1 :0] VAR6;
output reg [VAR16-1 :0] VAR20;
output reg [VAR30-1 :0] VAR5;
output reg [VAR... | gpl-3.0 |
YurongYou/MIPS_CPU | MEM.v | 1,513 | module MODULE1 (
input rst,
input VAR12,
input[VAR1-1:0] VAR7,
input[VAR1-1:0] VAR19,
input[VAR1-1:0] VAR3,
input VAR9,
input VAR6,
input[VAR1-1:0] VAR21,
input[VAR8-1:0] VAR4,
output[VAR1-1:0] VAR10,
output[VAR1-1:0] VAR18,
output reg[VAR28-1:0] VAR26
);
wire[VAR1-1:0] VAR5;
wire[VAR28-1:0] VAR14;
wire[VAR28-1:0] VAR2... | mpl-2.0 |
545/Atari7800 | core/ag_6502/trunk/fighter/videoctl.v | 1,534 | module MODULE1(
input clk,
output reg VAR7 = 1,
output reg VAR1 = 1,
output VAR6,
output reg [10:1] VAR5 = 0,
output reg [9:1] VAR3 = 0);
integer VAR9 = 0, VAR8 = 0;
reg VAR4 = 0, VAR2 = 0;
assign VAR6 = VAR4 & VAR2;
always @(posedge VAR1) begin
VAR8 <= VAR8 + 1;
VAR3 <= VAR4?VAR3 + 1: 0;
case (VAR8)
2: VAR7 = 1;
31: V... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_1.behavioral.pp.v | 1,388 | module MODULE1( VAR8, VAR5, VAR7, VAR1, VAR3, VAR9, VAR6 );
input VAR8, VAR5, VAR7, VAR1;
inout VAR9, VAR6;
output VAR3;
VAR10 VAR2(.VAR8(VAR8),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR3(VAR3),.VAR9(VAR9),.VAR6(VAR6));
VAR10 VAR4(.VAR8(VAR8),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR3(VAR3),.VAR9(VAR9),.VAR6(VAR6)); | apache-2.0 |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab/mem_beh.v | 4,664 | module MODULE1(addr,VAR2,VAR4, VAR6, VAR3);
parameter VAR5 = 4096;
input [31:0] addr, VAR2;
output [31:0] VAR4;
reg [31:0] VAR4;
input VAR6, VAR3;
reg [31:0] memory [VAR5-1:0];
integer VAR1;
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a_4.v | 2,411 | module MODULE2 (
VAR10 ,
VAR12 ,
VAR1 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR4,
VAR3,
VAR11 ,
VAR6
);
output VAR10 ;
input VAR12 ;
input VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR3;
input VAR11 ;
input VAR6 ;
VAR9 VAR2 (
.VAR10(VAR10),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4... | apache-2.0 |
timofonic/fpga_nes | hw/src/cart/cart.v | 4,221 | module MODULE1
(
input wire VAR1,
input wire [39:0] VAR15, input wire VAR9,
input wire VAR17, input wire [14:0] VAR6, input wire VAR23, input wire [ 7:0] VAR27, output wire [ 7:0] VAR5,
input wire [13:0] VAR24, input wire VAR13, input wire [ 7:0] VAR28, output wire [ 7:0] VAR3, output wire VAR11, output wire VAR22 );
w... | bsd-2-clause |
dtysky/FPGA-Imaging-Library | Geometry/Rotate/HDL/Rotate.srcs/sources_1/new/CosLUT.v | 18,447 | module MODULE1(VAR3, VAR1);
input[8 : 0] VAR3;
output[19 : 0] VAR1;
reg[19 : 0] VAR2;
assign VAR1 = VAR2;
always@(*) begin
case(VAR3)
0 : VAR2 <= 20'b01000000000000000000;
1 : VAR2 <= 20'b00111111111111011000;
2 : VAR2 <= 20'b00111111111101100000;
3 : VAR2 <= 20'b00111111111010011000;
4 : VAR2 <= 20'b001111111101100000... | lgpl-2.1 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo36_mux.v | 3,176 | module MODULE1
(input clk, input reset, input VAR19,
input [35:0] VAR30, input VAR35, output VAR5,
input [35:0] VAR1, input VAR27, output VAR10,
output [35:0] VAR16, output VAR31, input VAR24);
wire [35:0] VAR11, VAR3;
wire VAR28, VAR15, VAR17, VAR6;
VAR2 #(.VAR18(36)) VAR34
(.clk(clk), .reset(reset), .VAR19(VAR19),
.V... | gpl-2.0 |
tommythorn/yari | shared/rtl/target/Cycore-ep1c12c6/main.v | 4,682 | module MODULE1(
input wire clk,
output wire VAR22,
input wire VAR66,
input wire VAR19,
output wire VAR42,
output wire VAR62,
output wire [17:0] VAR55,
inout wire [15:0] VAR67,
output wire VAR11,
output wire VAR69,
output wire VAR25,
output wire VAR18,
output wire VAR48,
output wire [17:0] VAR3,
inout wire [15:0] VAR68,... | gpl-2.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_sysid_qsys_0.v | 1,415 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR1;
input VAR2;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1491173463 : 0;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfsbp/sky130_fd_sc_hs__dfsbp.behavioral.pp.v | 2,247 | module MODULE1 (
VAR18 ,
VAR4 ,
VAR11 ,
VAR15 ,
VAR17 ,
VAR6 ,
VAR16
);
input VAR18 ;
input VAR4 ;
output VAR11 ;
output VAR15 ;
input VAR17 ;
input VAR6 ;
input VAR16;
wire VAR2 ;
wire VAR3 ;
reg VAR19 ;
wire VAR9 ;
wire VAR1;
wire VAR13 ;
wire VAR20 ;
wire VAR5 ;
wire VAR7 ;
not VAR10 (VAR3 , VAR1 );
VAR8 VAR21 (VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufbuf/sky130_fd_sc_ls__bufbuf.behavioral.v | 1,341 | module MODULE1 (
VAR1,
VAR7
);
output VAR1;
input VAR7;
supply1 VAR4;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR6 ;
wire VAR8;
buf VAR3 (VAR8, VAR7 );
buf VAR9 (VAR1 , VAR8 );
endmodule | apache-2.0 |
mballance/wb_dma | rtl/wb_dma_wb_if.v | 7,155 | module MODULE1(clk, rst,
VAR37, VAR3, VAR27, VAR46, VAR6, VAR8,
VAR45, VAR28, VAR25, VAR44,
VAR39, VAR31, VAR40, VAR16, VAR41, VAR10,
VAR30, VAR34, VAR43, VAR14,
VAR7, VAR20, VAR11, VAR36, VAR24, VAR23,
VAR38, VAR9, VAR4, VAR26, VAR15,
VAR35, VAR42, VAR12, VAR22, VAR29,
VAR18, VAR33, VAR1
);
parameter VAR5 = 0;
input c... | apache-2.0 |
praveendath92/securePUF | source/Nonoverlapping_Template.v | 1,610 | module MODULE1(
input wire clk,
input wire rst,
input wire rand,
output reg VAR7
);
parameter VAR10 = 8, VAR13 = 256, VAR6 = 4, VAR1 = 4'b1100, VAR2 = 253, VAR14 = 4, VAR8 = 46288;
reg [7:0] VAR11, VAR9;
reg [5:0] VAR15;
reg [2:0] VAR5;
reg [21:0] VAR4;
reg [VAR6-1:0] VAR12;
always @(posedge clk)
if (rst) begin
VAR11 <... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0.v | 38,097 | module MODULE1 (
input wire VAR81, input wire VAR138, input wire VAR57, output wire VAR275, output wire VAR147, output wire VAR151, output wire VAR21, output wire [13:0] VAR188, output wire [1:0] VAR224, output wire [0:0] VAR15, output wire [0:0] VAR42, output wire [0:0] VAR61, output wire [0:0] VAR219, output wire [0:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.v | 2,477 | module MODULE2 (
VAR7 ,
VAR4,
VAR6,
VAR10 ,
VAR11 ,
VAR3,
VAR8,
VAR9 ,
VAR2
);
output VAR7 ;
input VAR4;
input VAR6;
input VAR10 ;
input VAR11 ;
input VAR3;
input VAR8;
input VAR9 ;
input VAR2 ;
VAR5 VAR1 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi.blackbox.v | 1,298 | module MODULE1 (
VAR3 ,
VAR5,
VAR1,
VAR4
);
output VAR3 ;
input VAR5;
input VAR1;
input VAR4;
supply1 VAR2;
supply0 VAR6;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_mult_createroundvectors.v | 6,245 | module MODULE1(input wire clk,
input wire [53:0] VAR3,
input wire [VAR4-1+1:0] VAR11,
output reg [53:0] VAR6, VAR9, VAR5);
reg [53:0] VAR12;
reg [53:0] VAR10;
reg [53:0] VAR8;
reg VAR1;
reg VAR7;
always @(posedge clk) begin
VAR12 <= 54'b000000000000000000000000001111111111111111111111111111;
VAR10 <= 54'b00000000000000... | gpl-3.0 |
manu3193/TextEditor | SVN/text_editor_keyboard_controller.v | 4,137 | module MODULE1(
input VAR6,
input VAR18,
input VAR12,
inout VAR28,
inout VAR20,
output reg [7:0] VAR15,
output reg VAR3
);
reg [1:0] state;
localparam
VAR25 = 2'b00,
VAR7 = 2'b01,
VAR4 = 2'b10,
VAR14 = 2'VAR9;
wire [7:0] VAR8;
wire VAR1;
reg [7:0] VAR27;
reg VAR5;
reg [7:0] VAR26;
wire VAR23;
VAR17 VAR11(
.VAR13(VAR18)... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_xres4v2/sky130_fd_io__top_xres4v2.functional.v | 7,414 | module MODULE1 ( VAR23, VAR15, VAR9, VAR27,
VAR12, VAR1, VAR32, VAR29, VAR42, VAR8, VAR7, VAR21,
VAR10, VAR17, VAR5
);
wire VAR19;
output VAR15;
inout VAR12;
inout VAR1;
inout VAR32;
input VAR10;
input VAR42;
input VAR8;
input VAR7;
input VAR21;
inout VAR17;
input VAR5;
supply1 VAR43;
supply1 VAR3;
supply1 VAR34;
suppl... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ba/sky130_fd_sc_lp__o21ba_2.v | 2,316 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR1 ,
VAR8,
VAR9,
VAR10,
VAR7 ,
VAR4
);
output VAR2 ;
input VAR6 ;
input VAR1 ;
input VAR8;
input VAR9;
input VAR10;
input VAR7 ;
input VAR4 ;
VAR5 VAR3 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 ... | apache-2.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/associative_comparator.v | 2,341 | module MODULE1
(
input [VAR18-1:0] VAR7,
input VAR3,
input VAR15,
input VAR17,
input VAR13,
input VAR5,
input VAR4,
input VAR6,
input VAR25,
input [VAR18-1:0] VAR20,
input [VAR18-1:0] VAR2,
input [VAR18-1:0] VAR21,
input [VAR18-1:0] VAR8,
input [VAR18-1:0] VAR22,
input [VAR18-1:0] VAR16,
input [VAR18-1:0] VAR23,
input ... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v | 11,618 | module MODULE1(
clk, rst,
VAR9, VAR16, VAR29, VAR12, VAR23,
VAR27, VAR24, VAR19, VAR20, VAR21,
VAR11, VAR13, VAR5, VAR18, VAR26, VAR31,
VAR28, VAR7, VAR4
);
input clk;
input rst;
input VAR9;
input VAR16;
input VAR29;
input VAR12;
input [3:0] VAR23;
input VAR27;
input VAR24;
input VAR19;
input [31:0] VAR20;
output [31:0... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_1/zqynq_lab_1_design_axi_timer_0_1_stub.v | 2,630 | module MODULE1(VAR2, VAR11, VAR13,
VAR22, VAR25, interrupt, VAR15, VAR17, VAR23, VAR3, VAR8,
VAR16, VAR19, VAR18, VAR1, VAR12, VAR7,
VAR24, VAR4, VAR10, VAR9, VAR20, VAR6,
VAR21, VAR14, VAR5)
;
input VAR2;
input VAR11;
output VAR13;
output VAR22;
output VAR25;
output interrupt;
input VAR15;
input VAR17;
input VAR23;
in... | mit |
kyzhai/NUNY | src/hardware/eight_new2.v | 6,411 | module MODULE1 (
address,
VAR14,
VAR16);
input [9:0] address;
input VAR14;
output [11:0] VAR16;
tri1 VAR14;
wire [11:0] VAR31;
wire [11:0] VAR16 = VAR31[11:0];
VAR38 VAR37 (
.VAR6 (address),
.VAR48 (VAR14),
.VAR44 (VAR31),
.VAR25 (1'b0),
.VAR32 (1'b0),
.VAR36 (1'b1),
.VAR50 (1'b0),
.VAR33 (1'b0),
.VAR3 (1'b1),
.VAR35 (... | gpl-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/dac.v | 11,548 | module MODULE1(
input VAR60,
input VAR55,
input VAR24,
input[10:0] VAR8,
input[7:0] VAR10,
input[7:0] VAR34,
input [19:0] VAR18,
input VAR26,
input VAR42,
input [2:0] VAR35,
input [2:0] VAR54,
input [8:0] VAR22,
input VAR56,
input reset,
input VAR3,
output VAR58,
output VAR51,
output VAR1,
output VAR36,
output VAR5
);
... | gpl-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_ilmb_bram_if_cntlr_0/system_ilmb_bram_if_cntlr_0_stub.v | 2,128 | module MODULE1(VAR9, VAR20, VAR2, VAR15,
VAR10, VAR11, VAR7, VAR5, VAR3, VAR18, VAR4, VAR6,
VAR1, VAR16, VAR12, VAR19, VAR13, VAR14, VAR8, VAR17)
;
input VAR9;
input VAR20;
input [0:31]VAR2;
input [0:31]VAR15;
input VAR10;
input VAR11;
input VAR7;
input [0:3]VAR5;
output [0:31]VAR3;
output VAR18;
output VAR4;
output VA... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/aemb/aeMB_regf.v | 6,526 | module MODULE1 (
VAR15, VAR14, VAR27, VAR41, VAR19,
VAR8, VAR33, VAR26, VAR7, VAR13, VAR37, VAR6, VAR28, VAR34, VAR2,
VAR5, VAR31, VAR24, VAR10, VAR39, VAR21
);
output [31:0] VAR15, VAR14;
output [31:0] VAR27;
input [5:0] VAR8;
input [4:0] VAR33, VAR26, VAR7, VAR13;
input [1:0] VAR37;
input [31:2] VAR6;
input [31:0] VA... | mit |
bkboggy/MIPS | CONTROL.v | 1,215 | module MODULE1(input [5:0] VAR2, output reg [1:0] VAR1, output reg [2:0] VAR3,
output reg [3:0] VAR5);
always @ *
begin
case (VAR2)
6'b000000: begin
VAR1 <= 2'b10;
VAR3 <= 3'b000;
VAR5 <= 4'b1100;
end
6'b100011: begin
VAR1 <= 2'b11;
VAR3 <= 3'b010;
VAR5 <= 4'b0001;
end
6'b101011: begin
VAR1 <= 2'VAR7;
VAR3 <= 3'b001;
V... | mit |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/5852a5c011d089ce/design_1_rst_ps7_0_100M_0_stub.v | 1,843 | module MODULE1(VAR5, VAR6, VAR9,
VAR8, VAR10, VAR2, VAR3, VAR7,
VAR1, VAR4)
;
input VAR5;
input VAR6;
input VAR9;
input VAR8;
input VAR10;
output VAR2;
output [0:0]VAR3;
output [0:0]VAR7;
output [0:0]VAR1;
output [0:0]VAR4;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b.functional.v | 1,814 | module MODULE1 (
VAR10,
VAR3,
VAR12 ,
VAR4 ,
VAR6
);
input VAR10;
input VAR3;
output VAR12 ;
input VAR4 ;
input VAR6 ;
wire VAR12 VAR11 ;
wire VAR1 ;
wire VAR5;
not VAR2 (VAR11 , VAR6 );
or VAR13 (VAR1 , VAR11, VAR4 );
VAR8 VAR7 (VAR5, VAR1, VAR10, VAR3);
buf VAR9 (VAR12 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr.functional.pp.v | 1,940 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR12 ,
VAR8 ,
VAR1,
VAR7 ,
VAR9
);
output VAR2 ;
input VAR5 ;
input VAR12 ;
input VAR8 ;
input VAR1;
input VAR7 ;
input VAR9 ;
wire VAR6 ;
wire VAR10;
buf VAR3 (VAR6 , VAR5 );
VAR4 VAR11 (VAR10, VAR6, VAR1, VAR8);
buf VAR13 (VAR2 , VAR10 );
endmodule | apache-2.0 |
aap/pdp6 | verilog/modules_50.v | 2,584 | module MODULE1(
input wire clk,
output wire VAR6
);
reg [19:0] VAR5 = 0;
assign VAR6 = VAR5 == 833333;
always @(posedge clk)
if(VAR6)
VAR5 <= 0;
else
VAR5 <= VAR5 + 20'b1;
endmodule
module MODULE5(
input wire clk,
output wire VAR6
);
reg [19:0] VAR5 = 0;
assign VAR6 = VAR5 == 789900;
always @(posedge clk)
if(VAR6)
VAR5... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_clock_pair_generator.v | 3,429 | module MODULE1
(
VAR21,
VAR16,
VAR23) ;
input [0:0] VAR21;
output [0:0] VAR16;
output [0:0] VAR23;
wire [0:0] VAR3;
wire [0:0] VAR15;
wire [0:0] VAR22;
wire [0:0] VAR5;
wire [0:0] VAR13;
wire [0:0] VAR10;
VAR7 VAR19
(
.VAR12(VAR5),
.VAR4(VAR3[0:0]),
.VAR20(),
.VAR2(VAR13)
,
.VAR1(1'b0),
.VAR26({14{1'b0}}),
.VAR9({14{1'... | lgpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_24.v | 17,291 | module MODULE1 (
clk,
reset,
VAR139,
VAR32,
VAR75,
VAR30,
VAR69
);
parameter VAR119 = 18;
parameter VAR62 = 24;
parameter VAR56 = 12;
localparam VAR85 = 25;
input clk;
input reset;
input VAR139;
input VAR32;
input [VAR119-1:0] VAR75; output VAR30;
output [VAR119-1:0] VAR69;
localparam VAR25 = 18; localparam VAR37 = 36;... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/verilog/feedforward_fadd_32ns_32ns_32_5_full_dsp.v | 1,936 | module MODULE1
VAR2 = 0,
VAR15 = 5,
VAR1 = 32,
VAR19 = 32,
VAR27 = 32
)(
input wire clk,
input wire reset,
input wire VAR5,
input wire [VAR1-1:0] VAR25,
input wire [VAR19-1:0] VAR23,
output wire [VAR27-1:0] dout
);
wire VAR22;
wire VAR17;
wire VAR16;
wire [31:0] VAR10;
wire VAR24;
wire [31:0] VAR20;
wire VAR4;
wire [31... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_pr_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_sn.symbol.v | 1,559 | module MODULE1 (
input VAR5 ,
output VAR7 ,
input VAR8 ,
input VAR1 ,
input VAR4 ,
input VAR3 ,
input VAR6,
input VAR2 ,
input VAR9
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21oi/sky130_fd_sc_hd__a21oi_4.v | 2,261 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR5,
VAR7,
VAR8 ,
VAR9
);
output VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR7;
input VAR8 ;
input VAR9 ;
VAR2 VAR10 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE1 (... | apache-2.0 |
juan199/Lab_Digitales | exp4/LCD_controller.v | 4,351 | module MODULE1(
input wire clk,
input wire [3:0] VAR17,
input wire VAR10,
input wire VAR18,
output reg VAR3,
output reg [3:0] VAR22,
output reg VAR21,
output reg VAR5,
output wire VAR7,
output wire VAR19
);
assign VAR19 = 1;
assign VAR7 = 0;
reg [7:0] VAR9;
reg [7:0] VAR20;
reg [31:0] VAR11;
reg VAR6;
reg [7:0] VAR12;
... | lgpl-3.0 |
kevintownsend/convey_spmv | caeCnySpmv/verilog/cae_pers.v | 24,236 | module MODULE1 (
input VAR21,
input clk,
input VAR163,
input VAR26,
input VAR70,
input [1:0] VAR29,
input VAR159,
output VAR51,
output VAR202,
input [31:0] VAR48,
input [63:0] VAR53,
input VAR22,
output [17:0] VAR222,
output [15:0] VAR126,
output [63:0] VAR216,
output VAR13,
output VAR77,
output VAR110,
output VAR224, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3_1.v | 2,057 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR8 ,
VAR7 ,
VAR5,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR7 ;
input VAR5;
input VAR2;
VAR3 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR4,
VAR1,
VAR8,
VAR7
);
output VAR4;
input VAR1;
input VAR8;
in... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/verilog/feedforward_AXILiteS_s_axi.v | 9,350 | module MODULE1
VAR32 = 5,
VAR24 = 32
)(
input wire VAR30,
input wire VAR11,
input wire VAR23,
input wire [VAR32-1:0] VAR39,
input wire VAR22,
output wire VAR5,
input wire [VAR24-1:0] VAR17,
input wire [VAR24/8-1:0] VAR56,
input wire VAR55,
output wire VAR8,
output wire [1:0] VAR25,
output wire VAR51,
input wire VAR37,
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.behavioral.v | 1,121 | module MODULE1( VAR3, VAR2 );
input VAR3;
output VAR2;
VAR4 VAR5(.VAR3(VAR3),.VAR2(VAR2));
VAR4 VAR1(.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_118.v | 1,465 | module MODULE2 (
VAR1,
VAR7
);
input [31:0] VAR1;
output [31:0]
VAR7;
wire [31:0]
VAR4,
VAR8,
VAR3,
VAR6,
VAR9,
VAR10,
VAR5,
VAR2;
assign VAR4 = VAR1;
assign VAR2 = VAR5 << 1;
assign VAR6 = VAR4 << 4;
assign VAR9 = VAR3 + VAR6;
assign VAR10 = VAR9 << 8;
assign VAR5 = VAR3 + VAR10;
assign VAR8 = VAR4 << 3;
assign VAR3 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai.pp.symbol.v | 1,408 | module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR3 ,
input VAR9 ,
input VAR5 ,
output VAR10 ,
input VAR1 ,
input VAR4,
input VAR2,
input VAR7
);
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_spram_64x24.v | 8,917 | module MODULE1(
VAR16, VAR32, VAR6,
clk, rst, VAR10, VAR23, VAR12, addr, VAR1, VAR37
);
parameter VAR35 = 6;
parameter VAR15 = 24;
input VAR16;
input [VAR21 - 1:0] VAR6;
output VAR32;
input clk; input rst; input VAR10; input VAR23; input VAR12; input [VAR35-1:0] addr; input [VAR15-1:0] VAR1; output [VAR15-1:0] VAR37;
w... | gpl-3.0 |
maltanar/spmv-vector-cache | proj/ip/AXIAccelWrapper/AXIAccelWrapper.v | 4,522 | module MODULE1(input clk, input reset,
output VAR143,
input VAR96,
input [31:0] VAR42,
input [2:0] VAR124,
output VAR128,
input VAR29,
input [31:0] VAR160,
input [3:0] VAR21,
input VAR38,
output VAR85,
output[1:0] VAR82,
output VAR22,
input VAR11,
input [31:0] VAR127,
input [2:0] VAR32,
input VAR84,
output VAR125,
outp... | bsd-3-clause |
ZiCog/P8X32A_Emulation | P8X32A_DE0_Nano/cog_ram.v | 1,306 | module MODULE1
(
input clk,
input VAR2,
input VAR6,
input [8:0] VAR3,
input [31:0] VAR5,
output reg [31:0] VAR4
);
reg [511:0] [31:0] VAR1;
always @(posedge clk)
begin
if (VAR2 && VAR6)
VAR1[VAR3] <= VAR5;
if (VAR2)
VAR4 <= VAR1[VAR3];
end
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.behavioral.v | 6,154 | module MODULE1( VAR23, VAR22, VAR13, VAR45, VAR55 );
input VAR13, VAR23, VAR22, VAR45;
output VAR55;
reg VAR34;
VAR42 VAR32(.VAR23(VAR23),.VAR22(VAR22),.VAR13(VAR13),.VAR45(VAR45),.VAR55(VAR55),.VAR34(VAR34));
VAR42 VAR40(.VAR23(VAR23),.VAR22(VAR22),.VAR13(VAR13),.VAR45(VAR45),.VAR55(VAR55),.VAR34(VAR34));
and VAR59(VA... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_arbiter.v | 7,167 | module MODULE1(
input VAR82,
input reset,
output VAR26,
input VAR16,
input [7:0] VAR7,
output VAR4,
output [7:0] VAR69,
input [7:0] VAR36,
input [1:0] VAR90,
input VAR39,
input VAR71,
input VAR84,
input VAR91,
input VAR52,
output VAR29,
input VAR96,
output VAR23,
input VAR107,
input [7:0] VAR1,
output VAR103,
output [7... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/altera_up_video_alpha_blender_normal.v | 8,137 | module MODULE1 (
VAR5,
VAR25,
VAR16,
VAR2,
VAR31
);
input [29: 0] VAR5;
input [39: 0] VAR25;
output [ 9: 0] VAR16;
output [ 9: 0] VAR2;
output [ 9: 0] VAR31;
wire [ 9: 0] VAR4;
wire [17: 0] VAR10;
wire [17: 0] VAR7;
wire [17: 0] VAR12;
wire [17: 0] VAR29;
wire [17: 0] VAR32;
wire [17: 0] VAR8;
assign VAR16 = {1'b0, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp.behavioral.pp.v | 1,863 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1 ,
VAR8,
VAR12,
VAR11 ,
VAR5
);
output VAR6 ;
input VAR3 ;
input VAR1 ;
input VAR8;
input VAR12;
input VAR11 ;
input VAR5 ;
wire VAR2 ;
wire VAR9;
VAR7 VAR4 (VAR2 , VAR3, VAR8, VAR12 );
VAR7 VAR13 (VAR9, VAR1, VAR8, VAR12 );
notif1 VAR10 (VAR6 , VAR2, VAR9);
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/oddr.v | 3,901 | module MODULE1 #
(
parameter VAR44 = "VAR10",
parameter VAR18 = "VAR12",
parameter VAR42 = 1
)
(
input wire clk,
input wire [VAR42-1:0] VAR4,
input wire [VAR42-1:0] VAR26,
output wire [VAR42-1:0] VAR9
);
genvar VAR34;
generate
if (VAR44 == "VAR45") begin
for (VAR34 = 0; VAR34 < VAR42; VAR34 = VAR34 + 1) begin : MODULE1... | mit |
cpulabs/mist1032isa | src/core/load_store_pipe_arbiter.v | 2,603 | module MODULE1(
output wire VAR38,
input wire VAR12,
output wire [1:0] VAR34, output wire [3:0] VAR39,
output wire VAR14, output wire [13:0] VAR15,
output wire [1:0] VAR2,
output wire [2:0] VAR8,
output wire [31:0] VAR24,
output wire [31:0] VAR41,
output wire [31:0] VAR13,
input wire VAR40,
input wire [11:0] VAR4,
inpu... | bsd-2-clause |
Beck-Sisyphus/EE471 | Lab4/sourceCode/InstrucDecoder.v | 2,716 | module MODULE1 (VAR12[31:26],VAR1, VAR20, VAR5,VAR16,VAR8,VAR19,VAR21,VAR18);
input [31:26] VAR12;
output reg VAR1,VAR20, VAR5,VAR16,VAR8,VAR19,VAR21,VAR18;
parameter VAR14=6'b101100,VAR4=6'b100000, VAR11=6'b100010, VAR2=6'b100100, VAR7=6'b100101, VAR9=6'b100110, VAR10=6'b101010,
VAR22=6'b000000, VAR3=6'b100011, VAR17=... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_clkgn_ddiv.v | 3,385 | module MODULE1 (
VAR15, VAR19, VAR16, VAR10, VAR4,
VAR1, VAR9, VAR8, VAR2, VAR13, VAR6,
VAR5, VAR3, VAR18
);
input VAR1;
input VAR9;
input VAR8;
input VAR2;
input [14:0] VAR13 ;
input VAR6;
input VAR5;
output VAR15;
output VAR19;
output VAR16;
output VAR10;
input VAR18;
input VAR3;
output VAR4;
VAR12 pos(
.VAR17 (VAR15... | gpl-2.0 |
bargei/NoC264 | NoC264_3x3/mkRouterInputArbitersStatic.v | 11,654 | module MODULE1(VAR2,
VAR14,
VAR10,
VAR7,
VAR1,
VAR17,
VAR6,
VAR9,
VAR4,
VAR15,
VAR13,
VAR11,
VAR8,
VAR16,
VAR3,
VAR12,
VAR5);
input VAR2;
input VAR14;
input [4 : 0] VAR10;
output [4 : 0] VAR7;
input VAR1;
input [4 : 0] VAR17;
output [4 : 0] VAR6;
input VAR9;
input [4 : 0] VAR4;
output [4 : 0] VAR15;
input VAR13;
input ... | mit |
secworks/sha1 | src/rtl/sha1_core.v | 12,367 | module MODULE1(
input wire clk,
input wire VAR5,
input wire VAR56,
input wire VAR38,
input wire [511 : 0] VAR49,
output wire ready,
output wire [159 : 0] VAR53,
output wire VAR32
);
parameter VAR30 = 32'h67452301;
parameter VAR42 = 32'hefcdab89;
parameter VAR31 = 32'h98badcfe;
parameter VAR41 = 32'h10325476;
parameter ... | bsd-2-clause |
jotego/jt12 | hdl/adpcm/jt10_adpcmb_gain.v | 1,296 | module MODULE1(
input VAR1,
input clk, input VAR3,
input [ 7:0] VAR6, input signed [15:0] VAR2,
output reg signed [15:0] VAR7
);
wire signed [15:0] VAR5 = {8'd0, VAR6};
wire signed [31:0] VAR4 = VAR2 * VAR5;
always @(posedge clk) if(VAR3)
VAR7 <= VAR4[23:8];
endmodule | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_1c_v1_00_a/hdl/verilog/user_logic.v | 7,632 | module MODULE1 (
VAR43,
VAR15,
VAR33,
VAR27,
VAR14,
VAR41,
VAR31,
VAR19,
VAR13,
VAR42,
VAR2,
VAR11,
VAR16,
VAR1,
VAR35,
VAR6,
VAR45,
VAR38,
VAR18,
VAR22,
VAR20,
VAR29,
VAR25,
VAR28,
VAR26,
VAR34,
VAR17,
VAR47,
VAR5,
VAR36,
VAR24);
parameter VAR39 = 32;
parameter VAR10 = 32;
parameter VAR4 = 0;
input VAR43;
input VAR15;... | mit |
scalable-networks/ext | uhd/fpga/usrp1/sdr_lib/rx_buffer.v | 6,399 | module MODULE1
( input VAR58,
input VAR3,
output [15:0] VAR71,
input VAR45,
output reg VAR10,
output reg VAR9,
input VAR15,
input VAR8,
input reset, input VAR42,
input wire [3:0] VAR67,
input wire [15:0] VAR4,
input wire [15:0] VAR23,
input wire [15:0] VAR48,
input wire [15:0] VAR52,
input wire [15:0] VAR1,
input wire ... | gpl-2.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_mmr.v | 8,834 | module MODULE1(
input rst,
input clk, input [7:0] din,
input write,
input VAR115,
output reg VAR81,
output reg VAR44,
output reg VAR61,
output reg VAR48,
output reg [4:0] VAR119,
output reg [7:0] VAR6,
output reg [1:0] VAR106,
output reg [6:0] VAR5,
output reg [6:0] VAR74,
output reg VAR73,
output reg [9:0] VAR90,
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp.functional.v | 1,538 | module MODULE1 (
VAR5,
VAR8,
VAR3
);
output VAR5;
input VAR8;
input VAR3 ;
wire VAR4 ;
wire VAR9;
not VAR7 (VAR9 , VAR3 );
VAR6 VAR2 (VAR4 , VAR8, VAR9 );
and VAR1 (VAR5 , VAR4, VAR3 );
endmodule | apache-2.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/adv_adc.v | 7,539 | module MODULE1 (VAR5, reset, VAR21, VAR23, VAR10, din, dout, VAR6, VAR18, VAR13,
VAR3, VAR15, VAR14, VAR12, VAR11, VAR2);
input VAR21, dout, VAR5, reset;
output reg VAR6;
output reg VAR23, din, VAR10;
output reg [11:0] VAR18, VAR13, VAR3, VAR15, VAR14, VAR12, VAR11, VAR2;
parameter VAR7 = 8'd16;
parameter VAR25 = 4'd8;... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb_dec.v | 6,323 | module MODULE1
(input clk,
input rst,
input VAR59,
input VAR72,
input [8:0] VAR46, input VAR44,
input [VAR64-1:0] VAR7,
output reg VAR65,
output reg [VAR64-1:0] VAR34);
localparam VAR28 = 17;
localparam VAR39 = VAR64 + 3;
wire [VAR28-1:0] VAR25;
wire VAR18;
VAR67 #(.VAR63(VAR64),.VAR68(VAR28)) VAR53
(.clk(clk),.reset(r... | gpl-2.0 |
kevintownsend/convey_spmv | caeCnySpmv/verilog/cae_clock.v | 2,639 | module MODULE1 (
input clk,
input VAR37,
input VAR24,
output VAR12,
output VAR23,
output VAR31
);
generate if (VAR11 == 0) begin : VAR1
assign VAR12 = clk;
assign VAR23 = 1'b1;
assign VAR31 = VAR37;
end else begin : VAR39
wire VAR27;
VAR43 VAR33 (.VAR54(VAR12), .VAR25(VAR27));
if (VAR20 == "hc-1") begin : VAR47
VAR29 #... | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_sprs.v | 16,508 | module MODULE1(
clk, rst,
VAR4, VAR58, flag, VAR30, VAR81, VAR54,
VAR51, VAR79, VAR55, VAR61, VAR85,
VAR80, VAR60, VAR16, VAR71,
VAR65, VAR36, VAR9, VAR45, VAR49, VAR15, VAR76, VAR23,
VAR48, VAR5, VAR62, VAR38, VAR78,
VAR47, VAR35, VAR68,
VAR34, VAR26, VAR77,
VAR28, VAR84, VAR53, VAR25,
VAR1, VAR17, VAR46,
VAR18, VAR24... | gpl-2.0 |
BoolLi/Pollard-s-p-1-algorithm | PrimeList.v | 2,365 | module MODULE1(input clk, input [12:0] VAR12, output reg ready, output wire [8:0] VAR14
);
reg VAR13;
reg VAR10;
reg [12:0] VAR1;
reg [12:0] VAR11;
reg VAR19;
reg VAR7;
reg VAR4;
wire VAR15;
wire [8:0] VAR8;
memory VAR5 (
.VAR2(clk), .VAR13(VAR13), .VAR3(VAR1), .VAR18(VAR8), .VAR6(VAR14) );
VAR9 VAR17 (
.clk(clk),
.VAR... | mit |
d16-processor/d16 | verilog/src/sound.v | 3,038 | module MODULE2(
input clk,
input rst,
input en,
input VAR4,
input [15:0] VAR21,
output VAR3,
output [3:0] VAR13);
wire VAR12,VAR2,VAR24,VAR14;
wire VAR6, VAR7, VAR9, VAR23;
reg [3:0] VAR18 = 0;
reg [4:0] VAR20 = 0;
assign VAR13 = {VAR14,VAR24,VAR2,VAR12};
assign VAR3 = VAR18[3];
reg [13:0] VAR17 = 0;
reg [13:0] VAR16 =... | mit |
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