repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha.behavioral.pp.v | 2,194 | module MODULE1 (
VAR15,
VAR19 ,
VAR18 ,
VAR16 ,
VAR17,
VAR9,
VAR2 ,
VAR3
);
output VAR15;
output VAR19 ;
input VAR18 ;
input VAR16 ;
input VAR17;
input VAR9;
input VAR2 ;
input VAR3 ;
wire VAR11 ;
wire VAR13;
wire VAR10 ;
wire VAR6 ;
and VAR7 (VAR11 , VAR18, VAR16 );
VAR14 VAR4 (VAR13, VAR11, VAR17, VAR9);
buf VAR1 (VA... | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaWriteWordReg.v | 1,668 | module MODULE1
(
input wire reset,
output wire [15:0] out, output wire VAR9,
input wire [11:0] VAR4, inout wire [7:0] VAR2 );
parameter VAR11 = 0;
wire VAR6 = (VAR11 == VAR4[11:4]);
wire write = VAR6 & VAR4[2];
assign VAR9 = write & select == 1'h1;
reg select;
always @(posedge VAR4[0])
begin
if( reset | ~VAR6)
select <... | gpl-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/mega/ram_16x512.v | 7,530 | module MODULE1 (
address,
VAR51,
VAR48,
VAR30,
VAR23,
VAR47,
VAR9);
input [8:0] address;
input [1:0] VAR51;
input VAR48;
input VAR30;
input [15:0] VAR23;
input VAR47;
output [15:0] VAR9;
tri1 [1:0] VAR51;
tri1 VAR48;
tri1 VAR30;
wire [15:0] VAR52;
wire [15:0] VAR9 = VAR52[15:0];
VAR55 VAR12 (
.VAR35 (address),
.VAR20 (... | bsd-3-clause |
AntonovAlexander/activecore | designs/rtl/sigma_tile/hw/mul_div/riscv_divider.v | 5,326 | module MODULE1
(
input VAR15
,input VAR10
,input VAR21
,input VAR13
,input VAR12
,input VAR20
,input VAR25
,input [ 31:0] VAR4
,input [ 31:0] VAR22
,output VAR17
,output [ 31:0] VAR26
);
reg VAR16;
reg [31:0] VAR19;
wire VAR23 = (VAR13) ||
(VAR12) ||
(VAR20) ||
(VAR25);
wire VAR5 = (VAR13) || (VAR20);
wire VAR9 = (VAR1... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp_macc_r.v | 4,719 | module MODULE1(
VAR28, VAR24, VAR33,
VAR23, VAR6, VAR4,
VAR17, VAR32, VAR26,
VAR14, VAR22, VAR35, VAR13, VAR20
);
output [129:0] VAR28; output VAR24;
output VAR33;
input VAR23; input VAR6; input VAR4; input VAR17; input VAR32;
input [129:0] VAR26; input [129:0] VAR14;
input [129:0] VAR22;
input VAR35;
input VAR13;
inpu... | gpl-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_gsu/gsu_umult.v | 4,398 | module MODULE1 (
VAR16,
VAR14,
VAR5);
input [7:0] VAR16;
input [7:0] VAR14;
output [15:0] VAR5;
wire [15:0] VAR3;
wire [15:0] VAR5 = VAR3[15:0];
VAR7 VAR1 (
.VAR16 (VAR16),
.VAR14 (VAR14),
.VAR5 (VAR3),
.VAR19 (1'b0),
.VAR12 (1'b1),
.VAR17 (1'b0),
.VAR6 (1'b0),
.sum (1'b0));
VAR1.VAR4 = "VAR2=5",
VAR1.VAR18 = "VAR11",... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pe_pp_pg_n/sky130_fd_sc_hs__udp_dff_pe_pp_pg_n.symbol.v | 1,485 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR1 ,
input VAR7 ,
input VAR3,
input VAR2 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b_2.v | 2,000 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR6 ,
VAR1,
VAR7
);
output VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR1;
input VAR7;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3 ,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR2 ;
input VAR6;
supply1 VAR1;
supply0 VAR7;
VAR5 VAR4... | apache-2.0 |
MarcoVogt/basil | firmware/modules/spi/spi.v | 1,593 | module MODULE1
parameter VAR27 = 16'h0000,
parameter VAR16 = 16'h0000,
parameter VAR5 = 16,
parameter VAR3 = 2
)
(
input wire VAR22,
input wire VAR9,
input wire [VAR5-1:0] VAR7,
inout wire [7:0] VAR4,
input wire VAR19,
input wire VAR15,
input wire VAR24,
output wire VAR18,
input wire VAR14,
output wire VAR11,
input wir... | bsd-3-clause |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/Descale_pipeline.v | 1,747 | module MODULE1(
input [31:0] VAR21,
input [31:0] VAR13,
input [31:0] VAR8,
input [31:0] VAR16,
input [7:0] VAR14,
input VAR17,
input VAR18,
input reset,
input VAR11,
output [31:0] VAR2,
output [31:0] VAR15,
output [31:0] VAR12,
output VAR1,
output [7:0] VAR6
);
wire VAR20;
wire [7:0] VAR22;
wire [31:0] VAR23;
VAR10 VAR... | apache-2.0 |
GLADICOS/CRCAHB | rtl/crc_ip.v | 4,559 | module MODULE1
(
output [31:0] VAR31,
output VAR29,
output VAR18,
input [31:0] VAR7,
input [31:0] VAR20,
input [ 2:0] VAR23,
input [ 1:0] VAR28,
input VAR1,
input VAR16,
input VAR30,
input VAR15,
input VAR9
);
wire [31:0] VAR22;
wire [31:0] VAR2;
wire [31:0] VAR5;
wire [ 7:0] VAR13;
wire VAR19;
wire VAR32;
wire [31:0] ... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_altdqdqs.v | 6,780 | module MODULE1 (
VAR39,
VAR86,
VAR16,
VAR29,
VAR35,
VAR24,
VAR30,
VAR61,
VAR4,
VAR71,
VAR84,
VAR26,
VAR49,
VAR33,
VAR91,
VAR67,
VAR52,
VAR54,
VAR62,
VAR8,
VAR14,
VAR44,
VAR12,
VAR2,
VAR28,
VAR1,
VAR19,
VAR88,
VAR42,
VAR38,
VAR3,
VAR66,
VAR69,
VAR87,
VAR78,
VAR73
);
input [7-1:0] VAR73;
input VAR39;
input VAR86;
input V... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/rtl_model/rf_2p_be.v | 3,767 | module MODULE1 (
VAR5 ,
VAR19 ,
VAR1 ,
VAR7 ,
VAR16 ,
VAR10 ,
VAR8 ,
VAR13 ,
VAR18
);
parameter VAR12=32;
parameter VAR6=8;
parameter VAR4=(VAR12>>3);
input VAR5; input VAR19; input [VAR6-1:0] VAR1; output [VAR12-1:0] VAR7;
input VAR16; input VAR10; input [VAR4-1:0] VAR8; input [VAR6-1:0] VAR13; input [VAR12-1:0] VAR18... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b.pp.symbol.v | 1,332 | module MODULE1 (
input VAR1 ,
input VAR9 ,
input VAR8 ,
input VAR6 ,
output VAR7 ,
input VAR5 ,
input VAR3,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
rohit91/HDMI2USB | hdl/edid/edidrom.v | 2,035 | module MODULE1 (clk,VAR2,VAR4);
input clk;
input [7:0] VAR2;
output [7:0] VAR4;
reg [7:0] VAR4 ;
reg[7:0] VAR5 [1023:0] ;
VAR1 VAR3("..
always @ (posedge clk)
begin
VAR4 <= VAR5[VAR2];
end
endmodule | bsd-2-clause |
cornell-zhang/datuner | designs/quartus/processor/lab5.v | 1,164 | module MODULE1(VAR27, VAR17, VAR15, VAR21, VAR10, VAR9, VAR14, VAR5, VAR25, VAR19, VAR26, VAR12, VAR22, VAR11, VAR3, VAR1, VAR16, VAR20, VAR2);
input VAR27;
input VAR17;
input [7:0] VAR15;
input [7:0] VAR21;
input [7:0] VAR10;
input VAR9;
output [7:0] VAR14;
output [7:0] VAR5;
output [15:0] VAR25;
output [7:0] VAR19;
o... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o_2.v | 2,339 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR4,
VAR6,
VAR5 ,
VAR2
);
output VAR3 ;
input VAR10 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR4;
input VAR6;
input VAR5 ;
input VAR2 ;
VAR1 VAR11 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o.pp.blackbox.v | 1,405 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR2 ,
VAR7 ,
VAR5 ,
VAR1 ,
VAR6,
VAR4
);
output VAR3 ;
input VAR8 ;
input VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR6;
input VAR4;
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/soc_template.v | 8,859 | module MODULE1 (
VAR116,
VAR106, VAR82, VAR6
) ;
input VAR106;
input VAR82;
input VAR6;
output wire VAR116;
wire VAR70;
wire VAR51;
wire VAR14 = VAR70;
wire VAR130 = VAR51;
assign VAR47 = VAR14;
assign VAR108 = VAR130;
wire VAR55 = 1;
wire VAR131 = 0;
assign VAR13 = 0;
assign VAR9 = 0;
assign VAR165 =0;
assign VAR123 =... | mit |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_m06_regslice_14/synth/system_m06_regslice_14.v | 10,976 | module MODULE1 (
VAR12,
VAR56,
VAR107,
VAR105,
VAR83,
VAR82,
VAR36,
VAR113,
VAR52,
VAR54,
VAR101,
VAR95,
VAR57,
VAR73,
VAR28,
VAR100,
VAR16,
VAR11,
VAR88,
VAR7,
VAR23,
VAR98,
VAR47,
VAR94,
VAR64,
VAR14,
VAR63,
VAR10,
VAR15,
VAR86,
VAR21,
VAR78,
VAR114,
VAR76,
VAR81,
VAR70,
VAR19,
VAR68,
VAR46,
VAR27
);
input wire VAR12... | bsd-2-clause |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GDAN8M8P1_syn.v | 7,543 | module MODULE1 ( VAR69, VAR147, VAR167, VAR200 );
input [15:0] VAR147;
input [15:0] VAR167;
output [16:0] VAR200;
input VAR69;
wire VAR189, VAR229, VAR79, VAR119, VAR163, VAR53, VAR224, VAR28, VAR277, VAR37, VAR155, VAR25, VAR95, VAR71,
VAR227, VAR66, VAR105, VAR116, VAR255, VAR109, VAR250, VAR193, VAR120, VAR258, VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode.pp.symbol.v | 1,221 | module MODULE1 (
input VAR2,
input VAR4 ,
input VAR1 ,
input VAR3 ,
input VAR5
);
endmodule | apache-2.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_altpll_0.v | 10,973 | module MODULE1
(
VAR5,
VAR8,
VAR2,
VAR10) ;
input VAR5;
input VAR8;
input [0:0] VAR2;
output [0:0] VAR10;
tri0 VAR5;
tri1 VAR8;
reg [0:0] VAR7;
reg [0:0] VAR4;
reg [0:0] VAR3;
wire VAR1;
wire VAR6;
wire VAR9; | gpl-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/dbg_port_chk.v | 63,247 | module MODULE1 () ;
wire VAR17 ;
wire VAR42 ;
wire VAR129 ;
wire VAR159 ;
wire VAR140 ;
wire VAR208 ;
wire VAR67 ;
wire VAR26 ;
reg [47:0] VAR169 [31:0] ;
reg [5:0] VAR91 ;
reg [5:0] VAR75 ;
reg [5:0] VAR207 ;
reg [5:0] VAR36 ;
reg [5:0] VAR144 ;
reg [5:0] VAR80 ;
reg VAR79 ;
wire VAR190 ;
wire VAR47 ;
wire VAR131 ;
wi... | gpl-2.0 |
tta/gnuradio-tta | gr-radar-mono/src/fpga/lib/radar_tx.v | 1,682 | module MODULE1(VAR5,VAR13,VAR4,VAR3,
VAR11,VAR6,VAR16,
VAR2,VAR17);
input VAR5;
input VAR13;
input VAR4;
input VAR3;
input [15:0] VAR11;
input [31:0] VAR6;
input [31:0] VAR16;
output [13:0] VAR2;
output [13:0] VAR17;
wire [15:0] VAR12, VAR1;
reg [31:0] VAR8;
always @(posedge VAR5)
if (VAR13 | ~VAR4)
VAR8 <= VAR6;
else
... | gpl-3.0 |
CospanDesign/nysa-sata | rtl/link/sata_link_layer_write.v | 15,587 | module MODULE1 (
input rst, input clk,
input VAR43,
output VAR23,
input en,
output VAR87,
input VAR103,
input VAR72,
input VAR88,
input VAR16,
input VAR94,
input VAR83,
input VAR107,
input VAR104,
input VAR13,
input VAR29,
input VAR93,
output reg VAR28,
output [31:0] VAR108,
output VAR12,
input [31:0] VAR100,
input [3:... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_4/syn/verilog/convolve_kernel_fcud.v | 1,880 | module MODULE1
VAR15 = 2,
VAR10 = 5,
VAR7 = 32,
VAR12 = 32,
VAR14 = 32
)(
input wire clk,
input wire reset,
input wire VAR25,
input wire [VAR7-1:0] VAR1,
input wire [VAR12-1:0] VAR13,
output wire [VAR14-1:0] dout
);
wire VAR19;
wire VAR9;
wire VAR23;
wire [31:0] VAR4;
wire VAR16;
wire [31:0] VAR24;
wire VAR20;
wire [31... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a.behavioral.v | 1,521 | module MODULE1 (
VAR9 ,
VAR12,
VAR4,
VAR8,
VAR14
);
output VAR9 ;
input VAR12;
input VAR4;
input VAR8;
input VAR14;
supply1 VAR5;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR2 ;
wire VAR13;
or VAR11 (VAR2 , VAR4, VAR12, VAR8 );
and VAR1 (VAR13, VAR2, VAR14 );
buf VAR6 (VAR9 , VAR13 );
endmodule | apache-2.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_2/synth/design_1_auto_pc_2.v | 10,688 | module MODULE1 (
VAR16,
VAR44,
VAR24,
VAR7,
VAR21,
VAR15,
VAR115,
VAR102,
VAR87,
VAR41,
VAR63,
VAR90,
VAR59,
VAR107,
VAR47,
VAR65,
VAR97,
VAR25,
VAR46,
VAR27,
VAR86,
VAR69,
VAR5,
VAR114,
VAR35,
VAR78,
VAR60,
VAR51,
VAR94,
VAR56,
VAR26,
VAR42,
VAR61,
VAR112,
VAR55,
VAR66,
VAR73,
VAR53,
VAR64
);
input wire VAR16;
input w... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21o/sky130_fd_sc_hs__a21o_1.v | 2,121 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR3,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR3;
input VAR5;
VAR1 VAR6 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR8 ,
VAR7,
VAR4,
VAR2
);
output VAR8 ;
input VAR7;
input VAR4;
... | apache-2.0 |
eecsninja/duinocube-core | common/core.v | 16,873 | module MODULE1(
clk, reset, int,
VAR109, VAR208, VAR187, VAR216, VAR136, VAR123, VAR3,
VAR110, VAR200, VAR4, VAR180, VAR99, VAR11, VAR145,
VAR114, VAR182, VAR14);
input clk; input reset;
input int;
input VAR187; input VAR109; input VAR208; input [1:0] VAR216; input [VAR120-1:0] VAR136; input [VAR113-1:0] VAR123; output... | gpl-3.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/QMFIR_uart_top.v | 5,477 | module MODULE1(
VAR6,
VAR65, clk, VAR11
);
output VAR6;
input VAR65;
input clk;
input VAR11;
wire VAR11;
wire [15:0] VAR41;
wire VAR46; wire [13:0] VAR68; wire [31:0] VAR53; wire VAR20; wire VAR17; wire [23:0] VAR39;
reg [23:0] VAR55;
wire [15:0] VAR64;
wire [15:0] VAR31;
wire [15:0] VAR30;
wire [15:0] VAR62;
wire [15:... | gpl-2.0 |
Murailab-arch/magukara | cores/fifo9togmii/rtl/crc.v | 2,742 | module MODULE1 (
input VAR14,
input VAR8,
input VAR6,
input [7:0] VAR2,
input VAR5,
input VAR12,
output [31:0] VAR4,
output reg VAR7
);
reg [31:0] VAR1;
reg [3:0] VAR9;
function[31:0] VAR3;
input[7:0] VAR13;
input[31:0] VAR11;
reg[31:0] VAR10;
begin
VAR10[0]=VAR11[24]^VAR11[30]^VAR13[1]^VAR13[7];
VAR10[1]=VAR11[25]^VAR... | gpl-3.0 |
SymbiFlow/fpga-tool-perf | third_party/picorv32_wrappers/picorv32_wrap.v | 1,565 | module MODULE1(input wire clk, input wire VAR1, input wire VAR19, output wire do);
localparam integer VAR24 = 101;
localparam integer VAR13 = 307;
reg [VAR24-1:0] din;
wire [VAR13-1:0] dout;
reg [VAR24-1:0] VAR10;
reg [VAR13-1:0] VAR20;
always @(posedge clk) begin
VAR10 <= {VAR10, VAR19};
VAR20 <= {VAR20, VAR10[VAR24-1... | isc |
Marcoslz22/Tercer_Proyecto | MUX.v | 1,115 | module MODULE1(
input clk,
input [7:0] VAR5,
input [5:0] VAR7,
input [5:0] VAR1,
input [4:0] VAR6,
input [4:0] VAR4,
input [3:0] VAR9,
input [6:0] VAR3,
output reg [7:0] VAR8,
output reg [7:0] VAR2,
output reg [7:0] VAR10
);
always @(posedge clk)
if (VAR5 == 8'h6C || VAR5 == 8'h75)
begin
VAR8 <= VAR7;
VAR2 <= VAR1;
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai_1.v | 2,441 | module MODULE2 (
VAR12 ,
VAR7 ,
VAR4 ,
VAR1 ,
VAR8 ,
VAR2 ,
VAR9,
VAR5,
VAR10 ,
VAR6
);
output VAR12 ;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR9;
input VAR5;
input VAR10 ;
input VAR6 ;
VAR3 VAR11 (
.VAR12(VAR12),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai_m.v | 2,421 | module MODULE2 (
VAR10 ,
VAR4 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR8,
VAR3,
VAR11 ,
VAR1
);
output VAR10 ;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR8;
input VAR3;
input VAR11 ;
input VAR1 ;
VAR5 VAR12 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VA... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sa1/main.v | 35,620 | module MODULE1(
output [22:0] VAR381,
output VAR280,
input VAR422,
output VAR108,
input VAR57,
output [21:0] VAR381,
output VAR235,
output VAR348,
output VAR464,
output VAR227,
output VAR305,
input VAR291,
input VAR94,
input [23:0] VAR241,
input VAR253,
input VAR395,
input VAR105,
inout [7:0] VAR245,
input VAR145,
inpu... | gpl-2.0 |
laoreja/MineSweeperM | code/central_module3.v | 14,013 | module MODULE1(
input [6:1]VAR12,
output reg [7:0]VAR23,
input VAR4, input [25:0] VAR3,
input reset, input VAR5,
input VAR31,
input VAR11,
input VAR15,
input VAR10, input VAR8, input wire [3:0]VAR6,
input wire [3:0]VAR17,
output reg [3:0]VAR2,
output reg [3:0]VAR25,
output reg [2:0]state,
output [3:0]VAR20
);
reg [3:0]... | gpl-3.0 |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_comb_alloc_sep_if.v | 19,608 | module MODULE1
(clk, reset, VAR76, VAR82, VAR55, VAR47,
VAR112, VAR110, VAR35, VAR3,
VAR84, VAR5, VAR41, VAR93);
parameter VAR85 = 2;
parameter VAR66 = 2;
localparam VAR13 = VAR85 * VAR66;
parameter VAR77 = 1;
localparam VAR115 = VAR13 * VAR77;
parameter VAR42 = 5;
localparam VAR2 = VAR21(VAR42);
parameter VAR11 = VAR3... | mit |
kwantam/multiexp-a5gx | ocram/e_ram.v | 9,683 | module MODULE1 (
VAR4,
VAR50,
VAR27,
VAR11,
VAR63,
VAR51,
VAR44,
VAR54);
input VAR4;
input VAR50;
input [31:0] VAR27;
input [11:0] VAR11;
input VAR63;
input [11:0] VAR51;
input VAR44;
output [31:0] VAR54;
tri0 VAR4;
tri1 VAR50;
tri1 VAR63;
tri0 VAR44;
wire [31:0] VAR24;
wire [31:0] VAR54 = VAR24[31:0];
VAR34 VAR35 (
.V... | gpl-3.0 |
CeesWolfs/ceespu | src/gpu/hdmi_encoder.v | 4,262 | module MODULE1 (
input clk,
input rst,
output reg VAR15,
output reg [3:0] VAR33,
output reg [3:0] VAR30,
output reg VAR41,
output reg [10:0] VAR27,
output reg [9:0] VAR57,
input [7:0] VAR38,
input [7:0] VAR67,
input [7:0] VAR21
);
localparam VAR73 = 2'h2;
localparam VAR49 = 1'h1;
localparam VAR22 = 9'h1e0;
localparam V... | mit |
fallen/milkymist-mmu | cores/hpdmc_ddr32/rtl/spartan6/hpdmc_iodelay4.v | 2,392 | module MODULE1 #(
parameter VAR22 = 30
) (
input [3:0] VAR14,
output [3:0] VAR23,
input [3:0] VAR24,
output [3:0] VAR6,
input [3:0] VAR20,
output [3:0] VAR5,
input VAR9,
input VAR21,
input VAR1,
input VAR18,
input VAR2,
input VAR17,
input VAR8
);
VAR10 #(
.VAR3("VAR15"),
.VAR25("VAR16"),
.VAR4("VAR13"),
.VAR22(VAR22)
)... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_ps_pp_sn/sky130_fd_sc_hs__udp_dff_ps_pp_sn.blackbox.v | 1,394 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR1 ,
VAR4 ,
VAR5 ,
VAR6
);
output VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR4 ;
input VAR5 ;
input VAR6;
endmodule | apache-2.0 |
HashRatio/mm-hashratio | verilog/superkdf9/components/lm32_top/lm32_mc_arithmetic.v | 10,581 | module MODULE1 (
VAR13,
VAR12,
VAR20,
VAR31,
VAR36,
VAR6,
VAR8,
VAR18,
VAR32,
VAR9,
VAR16,
VAR2,
VAR37,
VAR34,
VAR26
);
input VAR13; input VAR12; input VAR20; input VAR31; VAR10 VAR23
input VAR36; input VAR6; VAR27
input VAR8; VAR27
input VAR18; input VAR32; input VAR9; VAR27
input [VAR7] VAR16;
input [VAR7] VAR2;
outp... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp.pp.symbol.v | 1,311 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR5 ,
input VAR6 ,
input VAR7,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/DecOp4_0.v | 24,811 | module MODULE1(
clk,
VAR260,
VAR318,
VAR347,
VAR143,
VAR12,
VAR97,
VAR106,
VAR349,
VAR274
);
parameter VAR215 = 0; parameter VAR23 = 0; parameter VAR301 = 1;
input clk; input[47:0] VAR260; input[15:0] VAR318;
output[6:0] VAR347;
output[6:0] VAR143;
output[6:0] VAR12;
output[31:0] VAR97;
output[3:0] VAR106;
output[3:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4.symbol.v | 1,321 | module MODULE1 (
input VAR8,
input VAR3,
input VAR6,
input VAR7,
output VAR9
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_serdes_in.v | 6,305 | module MODULE1 #(
parameter VAR31 = 0,
parameter VAR19 = 0,
parameter VAR54 = 8,
parameter VAR8 = 16,
parameter VAR32 = 0,
parameter VAR28 = "VAR18") (
input rst,
input clk,
input VAR42,
input VAR49,
input [ 7:0] VAR79,
input VAR29,
output [(VAR8-1):0] VAR35,
output [(VAR8-1):0] VAR47,
output [(VAR8-1):0] VAR51,
output... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,036 | module MODULE1
(
VAR10,
VAR27,
VAR19) ;
input [0:0] VAR10;
output [0:0] VAR27;
output [0:0] VAR19;
wire [0:0] VAR21;
wire [0:0] VAR17;
wire [0:0] VAR23;
wire [0:0] VAR26;
wire [0:0] VAR4;
wire [0:0] VAR34;
wire [0:0] VAR12;
wire [0:0] VAR22;
wire [0:0] VAR20;
wire [0:0] VAR2;
VAR11 VAR32
(
.VAR18(VAR34),
.VAR31(VAR21[0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai.blackbox.v | 1,403 | module MODULE1 (
VAR9 ,
VAR5,
VAR1,
VAR10,
VAR6,
VAR2
);
output VAR9 ;
input VAR5;
input VAR1;
input VAR10;
input VAR6;
input VAR2;
supply1 VAR3;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4.symbol.v | 1,252 | module MODULE1 (
input VAR6,
input VAR4,
input VAR3,
input VAR2,
output VAR5
);
supply1 VAR1;
supply0 VAR7;
endmodule | apache-2.0 |
chebykinn/university | circuitry/lab4/src/hdl/pipeline.v | 9,187 | module MODULE1 ( input wire clk,
input wire rst,
output VAR71,
output [31:0] VAR98,
input [31:0] VAR112,
input VAR45,
output wire VAR1,
output wire VAR75,
output wire [31:0] VAR25,
output wire [31:0] VAR109,
input wire [31:0] VAR91 );
wire [1:0] VAR37;
wire VAR54;
wire [31:0] VAR67;
wire [31:0] VAR106;
wire [31:0] VAR6... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/AXI4LiteSlaveInterface.v | 5,962 | module MODULE1
(
parameter VAR22 = 32,
parameter VAR4 = 32
)
(
VAR10 ,
VAR23 ,
VAR34 ,
VAR14 ,
VAR1 ,
VAR31 ,
VAR33 ,
VAR6 ,
VAR32 ,
VAR19 ,
VAR30 ,
VAR15 ,
VAR29 ,
VAR18 ,
VAR20 ,
VAR11 ,
VAR12 ,
VAR35 ,
VAR8 ,
VAR16 ,
VAR24 ,
VAR5 ,
VAR2 ,
VAR25 ,
VAR3 ,
VAR27 ,
VAR17 ,
VAR9 ,
VAR7
);
input VAR10 ;
input VAR23 ;
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpadv2/sky130_fd_io__top_power_hvc_wpadv2.blackbox.v | 1,611 | module MODULE1 (
VAR17 ,
VAR10,
VAR12
);
inout VAR17 ;
inout VAR10;
inout VAR12;
supply1 VAR15 ;
supply1 VAR14 ;
supply0 VAR13;
supply1 VAR3 ;
supply1 VAR11 ;
supply1 VAR8 ;
supply1 VAR4 ;
supply1 VAR2 ;
supply1 VAR16 ;
supply1 VAR7 ;
supply0 VAR5 ;
supply0 VAR9 ;
supply0 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
walkthetalk/fsref | ip/fsmotor/src/fsmotor.v | 5,155 | module MODULE1 #
(
parameter integer VAR47 = 3,
parameter integer VAR46 = 0
) (
output wire VAR22,
input wire VAR58,
input wire VAR49,
input wire [VAR47-1:0] VAR20,
input wire VAR8,
input wire VAR6,
output wire VAR51,
input wire VAR2,
input wire VAR55,
input wire [VAR47-1:0] VAR56,
input wire VAR13,
input wire VAR33,
o... | gpl-3.0 |
kwantam/multiexp-a5gx | pll/pll_core.v | 17,259 | module MODULE1 (
input wire VAR4, input wire rst, output wire VAR2, output wire VAR1 );
VAR5 VAR3 (
.VAR4 (VAR4), .rst (rst), .VAR2 (VAR2), .VAR1 (VAR1) );
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp.pp.symbol.v | 1,531 | module MODULE1 (
input VAR11 ,
output VAR5 ,
output VAR1 ,
input VAR10,
input VAR7 ,
input VAR9 ,
input VAR4 ,
input VAR3 ,
input VAR2 ,
input VAR6 ,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fah/sky130_fd_sc_lp__fah.functional.pp.v | 2,616 | module MODULE1 (
VAR4,
VAR21 ,
VAR17 ,
VAR2 ,
VAR7 ,
VAR12,
VAR15,
VAR3 ,
VAR18
);
output VAR4;
output VAR21 ;
input VAR17 ;
input VAR2 ;
input VAR7 ;
input VAR12;
input VAR15;
input VAR3 ;
input VAR18 ;
wire VAR9 ;
wire VAR1 ;
wire VAR11 ;
wire VAR13 ;
wire VAR20 ;
wire VAR16 ;
wire VAR25;
xor VAR26 (VAR9 , VAR17, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a_2.v | 2,248 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR3 ,
VAR2 ,
VAR10,
VAR5,
VAR1 ,
VAR8
);
output VAR7 ;
input VAR9 ;
input VAR3 ;
input VAR2 ;
input VAR10;
input VAR5;
input VAR1 ;
input VAR8 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
terriblefire/tf328 | rtl/gayle.v | 2,921 | module MODULE1(
input VAR4,
input VAR3,
input VAR9,
input VAR6,
input VAR27,
input VAR8,
output VAR35,
input VAR17,
input [1:0] VAR29,
input VAR36,
output VAR24
);
parameter VAR5 = 4'hd;
reg VAR26 = 1'b0;
reg [3:0] VAR11 = VAR5;
reg VAR28 = 1'b0;
reg VAR31 = 1'b0;
reg VAR32 = 1'b0;
localparam VAR34 = {1'b1,2'h1,1'b1};
... | gpl-2.0 |
zhanglongqi/LED_Blinking_on_ZedBoard | zynq_Gpio.srcs/sources_1/ipshared/xilinx.com/axi_register_slice_v2_1/03a8e0ba/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v | 17,400 | module MODULE1 #
(
parameter VAR1 = "VAR10",
parameter VAR9 = 32,
parameter VAR14 = 32'h00000000
)
(
input wire VAR12,
input wire VAR4,
input wire [VAR9-1:0] VAR16,
input wire VAR3,
output wire VAR13,
output wire [VAR9-1:0] VAR11,
output wire VAR19,
input wire VAR15
);
generate
if (VAR14 == 32'h00000000) begin
assign V... | gpl-2.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/mig_wrap_mig_7series_0_0.v | 10,505 | module MODULE1 (
inout [63:0] VAR9,
inout [7:0] VAR3,
inout [7:0] VAR12,
output [13:0] VAR51,
output [2:0] VAR37,
output VAR57,
output VAR19,
output VAR76,
output VAR71,
output [0:0] VAR65,
output [0:0] VAR75,
output [0:0] VAR30,
output [0:0] VAR14,
output [7:0] VAR26,
output [0:0] VAR70,
input VAR74,
input VAR56,
outp... | mit |
GREO/GNU-Radio | usrp/fpga/toplevel/mrfm/biquad_6stage.v | 4,871 | module MODULE1 (input VAR36, input reset, input VAR40,
input VAR31, input [6:0] VAR34, input [31:0] VAR20,
input wire [15:0] VAR23, output reg [15:0] VAR52);
wire [5:0] VAR39, VAR21;
wire [4:0] VAR55, VAR48;
reg [4:0] VAR54, VAR3, VAR8;
wire [15:0] VAR43, VAR32, VAR2, VAR10;
wire VAR24;
reg VAR51;
wire [30:0] VAR19;
wi... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_ddrx_state_machine.v | 129,300 | module MODULE1
VAR274 = 4,
VAR65 = 6, VAR31 = "VAR85",
VAR129 = 4,
VAR232 = 8,
VAR40 = 0,
VAR270 = 0, VAR103 = 0, VAR138 = 0, VAR204 = 1, VAR205 = 0,
VAR95 = 1,
VAR215 = 0,
VAR4 = 1,
VAR227 = 2,
VAR94 = 3, VAR45 = 13, VAR53 = 10, VAR198 = 2,
VAR222 = 3,
VAR276 = 13,
VAR272 = 10
)
(
VAR193,
VAR17,
VAR230,
VAR49,
VAR266,... | gpl-3.0 |
cpulabs/mist1032isa | src/core/pipeline_control/interrupt_control.v | 5,005 | module MODULE1(
input wire VAR12,
input wire VAR6,
input wire VAR14,
input wire [5:0] VAR4,
input wire VAR21,
input wire VAR25,
input wire [1:0] VAR1,
input wire [31:0] VAR2,
input wire VAR28,
input wire [5:0] VAR5,
output wire VAR7,
input wire VAR13,
input wire [6:0] VAR32,
input wire [31:0] VAR16,
input wire [31:0] V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.v | 2,519 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR7 ,
VAR1 ,
VAR5 ,
VAR3,
VAR12 ,
VAR9 ,
VAR8 ,
VAR2
);
output VAR10 ;
input VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR3;
input VAR12 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
VAR6 VAR11 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR12... | apache-2.0 |
freecores/zet86 | rtl-model/rotate.v | 4,956 | module MODULE3 (
input [15:0] VAR3,
input [ 4:0] VAR9,
input [ 1:0] VAR17, input VAR29,
input VAR24,
output [15:0] out,
output VAR8,
input VAR6,
output VAR10
);
wire [4:0] VAR23, VAR20, VAR16, VAR12, VAR21;
wire [3:0] VAR5, VAR19, VAR11, VAR25, VAR14;
wire [7:0] VAR15;
wire [15:0] VAR13;
wire VAR4, VAR28;
wire VAR22;
M... | gpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/fourDeepRollingAverage.v | 1,676 | module MODULE1 (
input clk,
input signed [12:0] in,
output reg signed [12:0] out = 13'd0);
reg [1:0] VAR9 = 2'b00;
reg [1:0] VAR2 = 2'b00, VAR3 = 2'b00, VAR5 = 2'b00, VAR4 = 2'b00;
reg signed [14:0] VAR6 = 15'd0, VAR7 = 15'd0, VAR8 = 15'd0, VAR1 = 15'd0;
always @(posedge clk) begin
if(VAR9 == 2'b11) VAR9 <= 2'b00;
end
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn.blackbox.v | 1,354 | module MODULE1 (
VAR8 ,
VAR1,
VAR2 ,
VAR7
);
output VAR8 ;
input VAR1;
input VAR2 ;
input VAR7 ;
supply1 VAR3;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_pkg_sn/sky130_fd_sc_hs__udp_dff_pr_pp_pkg_sn.symbol.v | 1,532 | module MODULE1 (
input VAR6 ,
output VAR1 ,
input VAR7 ,
input VAR4 ,
input VAR8 ,
input VAR9 ,
input VAR5,
input VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/example_design/PIO_EP.v | 8,388 | module MODULE1 #(
parameter VAR18 = 64,
parameter VAR16 = VAR18 / 8 ) (
input clk,
input VAR29,
input VAR65,
output [VAR18-1:0] VAR58,
output [VAR16-1:0] VAR39,
output VAR76,
output VAR25,
output VAR32,
input [VAR18-1:0] VAR20,
input [VAR16-1:0] VAR2,
input VAR24,
input VAR81,
output VAR4,
input [21:0] VAR8,
output VAR... | lgpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/BRAM2.v | 3,809 | module MODULE1(VAR10,
VAR14,
VAR4,
VAR5,
VAR15,
VAR17,
VAR18,
VAR11,
VAR7,
VAR3,
VAR21,
VAR9
);
parameter VAR1 = 0;
parameter VAR12 = 1;
parameter VAR6 = 1;
parameter VAR8 = 1;
input VAR10;
input VAR14;
input VAR4;
input [VAR12-1:0] VAR5;
input [VAR6-1:0] VAR15;
output [VAR6-1:0] VAR17;
input VAR18;
input VAR11;
input ... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_odt_gen.v | 14,639 | module MODULE1
VAR13 = 2,
VAR7 = 1,
VAR3 = 2, VAR28 = 2,
VAR6 = 1,
VAR27 = 4,
VAR14 = 4,
VAR37 = 3,
VAR33 = 3,
VAR1 = 4,
VAR4 = 4
)
(
VAR17,
VAR15,
VAR32,
VAR40,
VAR5,
VAR26,
VAR43,
VAR8,
VAR34,
VAR19,
VAR10,
VAR31,
VAR44,
VAR30,
VAR25
);
input VAR17;
input VAR15;
input [VAR33 -1:0] VAR32;
input [VAR14 -1:0] VAR40;
inp... | lgpl-3.0 |
mda-ut/Tempest | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_select_i2c_clk.v | 2,303 | module MODULE1 (
address,
VAR6,
clk,
VAR4,
VAR9,
VAR1,
VAR2,
VAR8
)
;
output VAR2;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR4;
input VAR9;
input [ 31: 0] VAR1;
wire VAR7;
reg VAR3;
wire VAR2;
wire VAR5;
wire [ 31: 0] VAR8;
assign VAR7 = 1;
assign VAR5 = {1 {(address == 0)}} & VAR3;
a... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.functional.pp.v | 1,469 | module MODULE1( VAR7, VAR18, VAR4, VAR17, VAR1, VAR5, VAR8 );
input VAR4, VAR18, VAR17, VAR1;
inout VAR5, VAR8;
output VAR7;
wire VAR10;
not VAR3( VAR10, VAR4 );
wire VAR12;
not VAR15( VAR12, VAR18 );
wire VAR13;
and VAR2( VAR13, VAR10, VAR12 );
wire VAR16;
not VAR9( VAR16, VAR17 );
wire VAR6;
not VAR11( VAR6, VAR1 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.behavioral.pp.v | 2,839 | module MODULE1 (
VAR23 ,
VAR14,
VAR5 ,
VAR6 ,
VAR24
);
output VAR23 ;
input VAR14;
input VAR5 ;
input VAR6 ;
input VAR24;
wire VAR15 ;
wire VAR21 ;
wire VAR12;
wire VAR20 ;
wire VAR26 ;
wire VAR25 ;
wire VAR18 ;
wire VAR29 ;
VAR7 VAR10 (.VAR9(VAR15) , .VAR17(VAR21), .VAR24(VAR24), .VAR14(VAR14), .VAR5(VAR5), .VAR6(VAR6... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_ps_pp_sn/sky130_fd_sc_hs__udp_dff_ps_pp_sn.symbol.v | 1,449 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR4 ,
input VAR5 ,
input VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
PyLCARS/PythonUberHDL | myHDL_ComputerFundamentals/Memorys/fifo_mem.v | 5,915 | module MODULE1 (
wr,
rd,
VAR15,
VAR33,
VAR21,
VAR27,
VAR39,
VAR10,
VAR20,
clk,
VAR19,
VAR12
);
input wr;
input rd;
input [7:0] VAR15;
output VAR33;
wire VAR33;
output VAR21;
wire VAR21;
output VAR27;
wire VAR27;
output VAR39;
wire VAR39;
output VAR10;
wire VAR10;
output [7:0] VAR20;
wire [7:0] VAR20;
input clk;
input V... | bsd-3-clause |
marmolejo/zet | cores/zet/rtl/zet_decode.v | 3,941 | module MODULE1 (
input clk,
input rst,
input [7:0] VAR49,
input [7:0] VAR7,
input VAR12,
input VAR38,
input VAR24,
input VAR4,
input VAR36,
input VAR23,
input VAR13,
output VAR22,
output VAR1,
output VAR17,
output VAR21,
output VAR48,
output VAR19,
input [2:0] VAR26,
input VAR34,
input VAR37,
output VAR32,
output reg V... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/example_design/rtl/traffic_gen/tg_status.v | 4,732 | module MODULE1 #(
parameter VAR2 = 100,
parameter VAR15 = 32
)
(
input VAR17 ,
input VAR6 ,
input VAR11,
input VAR13 ,
input [VAR15-1:0] VAR14,
input [VAR15-1:0] VAR5 ,
input [31:0] VAR4 ,
input [5:0] VAR8 ,
input VAR10 ,
input VAR1,
input VAR9,
output reg [64 + (2*VAR15 - 1):0] VAR12,
output VAR7
);
reg VAR3;
reg VAR1... | lgpl-3.0 |
genkilife/miaow | src/verilog/rtl/sgpr/sgpr.v | 12,016 | module MODULE1(
VAR2,
VAR146,
VAR132,
VAR61,
VAR126,
VAR73,
VAR193,
VAR81,
VAR213,
VAR78,
VAR203,
VAR59,
VAR190,
VAR177,
VAR138,
VAR115,
VAR215,
VAR125,
VAR72,
VAR144,
VAR7,
VAR157,
VAR33,
VAR107,
VAR32,
VAR189,
VAR169,
VAR133,
VAR41,
VAR109,
VAR116,
VAR37,
VAR93,
VAR163,
VAR35,
VAR201,
VAR69,
VAR161,
VAR142,
VAR86,
VA... | bsd-3-clause |
kernelpanics/Grad | Expanded-Hyperbolic-CORDIC/Verilog/Exponential/multiplier.v | 1,739 | module MODULE1 #(parameter VAR9=32, VAR10=8'd127)(
input wire clk,
input wire [VAR9-1:0] VAR8, input wire [VAR9-1:0] VAR2, output wire [VAR9-1:0] VAR1 );
wire [22:0] VAR5, VAR13; wire [7:0] VAR3,VAR11;
assign VAR5 = VAR8[22:0];
assign VAR13 = VAR2[22:0];
assign VAR3 = VAR8[30:23];
assign VAR11 = VAR2[30:23];
reg [22:0]... | gpl-3.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v | 1,925 | module MODULE1 (
output wire [14:0] VAR11, output wire [2:0] VAR18, output wire VAR15, output wire VAR10, output wire VAR8, output wire VAR4, output wire VAR12, output wire VAR17, output wire VAR3, output wire VAR5, inout wire [31:0] VAR14, inout wire [3:0] VAR1, inout wire [3:0] VAR7, output wire VAR16, output wire [3... | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/jtag_uart_0.v | 23,077 | module MODULE3 (
clk,
VAR81,
VAR41,
valid
)
;
input clk;
input [ 7: 0] VAR81;
input VAR41;
input valid;
reg [31:0] VAR34; VAR71 VAR34 =
always @(posedge clk) begin
if (valid && VAR41) begin
("%VAR21", ((VAR81 == 8'hd) ? 8'ha : VAR81));
VAR59 (VAR34);
end
end
endmodule
module MODULE6 (
clk,
VAR76,
VAR35,
VAR4,
VAR8,
VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.functional.pp.v | 1,190 | module MODULE1( VAR10, VAR3, VAR2, VAR8, VAR7, VAR9 );
input VAR10, VAR3;
inout VAR7, VAR9;
output VAR2, VAR8;
and VAR5( VAR2, VAR10, VAR3 );
wire VAR11;
not VAR6( VAR11, VAR3 );
wire VAR1;
and VAR15( VAR1, VAR11, VAR10 );
wire VAR12;
not VAR16( VAR12, VAR10 );
wire VAR13;
and VAR14( VAR13, VAR12, VAR3 );
or VAR4( VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3/sky130_fd_sc_hs__and3.behavioral.v | 1,702 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR1 ,
VAR11 ,
VAR3,
VAR6
);
output VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR11 ;
input VAR3;
input VAR6;
wire VAR9 ;
wire VAR8;
and VAR10 (VAR9 , VAR11, VAR7, VAR1 );
VAR5 VAR2 (VAR8, VAR9, VAR3, VAR6);
buf VAR12 (VAR4 , VAR8 );
endmodule | apache-2.0 |
kielfriedt/ece472 | lab2/add4_LA.v | 1,250 | module MODULE1(VAR12, VAR5, VAR3, sum, VAR16, VAR9, VAR10);
input [3:0] VAR12, VAR5;
input VAR3;
output [3:0] sum;
output VAR16;
output VAR9, VAR10;
wire [2:0] VAR13;
wire [3:0] VAR6, VAR2;
VAR7 VAR15(VAR12[0], VAR5[0], VAR3, sum[0], VAR6[0], VAR2[0]);
VAR7 VAR4(VAR12[1], VAR5[1], VAR13[0], sum[1], VAR6[1], VAR2[1]);
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3b/sky130_fd_sc_ls__and3b_2.v | 2,218 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR7 ,
VAR3 ,
VAR10,
VAR8,
VAR2 ,
VAR6
);
output VAR1 ;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR10;
input VAR8;
input VAR2 ;
input VAR6 ;
VAR5 VAR9 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/altera_mult_add_g9u2.v | 15,369 | module MODULE1
(
VAR88,
VAR182,
VAR51,
VAR125,
VAR12) ;
input VAR88;
input VAR182;
input [15:0] VAR51;
input [15:0] VAR125;
output [15:0] VAR12;
tri0 VAR88;
tri1 VAR182;
tri0 [15:0] VAR51;
tri0 [15:0] VAR125;
wire [15:0] VAR35;
VAR167 VAR198
(
.VAR88(VAR88),
.VAR79(),
.VAR182(VAR182),
.VAR51(VAR51),
.VAR125(VAR125),
.V... | gpl-2.0 |
cmos3511/cmos_linux | python/pj/proj/rtl/LP/genpp32.v | 6,608 | module MODULE1(VAR13,VAR2,VAR28,VAR40,VAR25,VAR27,VAR19,VAR29,
VAR33,VAR11,VAR23,VAR14,VAR20,VAR37,VAR6,VAR35,VAR30,VAR5,VAR32);
output [VAR18:0] VAR13; output [VAR18:0] VAR2; output [VAR18:0] VAR28; output [VAR18:0] VAR40; output [VAR18:0] VAR25; output [VAR18:0] VAR27; output [VAR18:0] VAR19; output [VAR18:0] VAR29; ... | gpl-3.0 |
orbancedric/DeepGate | src/core/sig_368p.v | 13,921 | module MODULE1(
input [9:0] VAR3,
output wire [7:0] VAR5
);
reg [9:0] VAR1;
reg [8:0] VAR2;
reg [168:0] VAR4;
reg [8:0] VAR6;
assign VAR5 = VAR6[7:0];
always@(*) begin
if(VAR3[9])
VAR1 = ~VAR3 + 1'b1;
end
else
VAR1 = VAR3;
VAR4[0] = VAR1[6] & VAR1[2] & VAR1[1];
VAR4[1] = VAR1[6] & VAR1[3];
VAR4[2] = VAR1[6] & VAR1[4];
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4bb/sky130_fd_sc_ms__nor4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR2 ,
input VAR3 ,
input VAR1 ,
input VAR7 ,
output VAR8 ,
input VAR9 ,
input VAR5,
input VAR6,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai.pp.blackbox.v | 1,408 | module MODULE1 (
VAR3 ,
VAR8,
VAR2,
VAR4 ,
VAR7 ,
VAR6,
VAR1,
VAR9 ,
VAR5
);
output VAR3 ;
input VAR8;
input VAR2;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR1;
input VAR9 ;
input VAR5 ;
endmodule | apache-2.0 |
LorhanSohaky/UFSCar | 2017/lab_cd/aula9/maquina/maquina.v | 2,553 | module MODULE2 ( VAR14, VAR10, VAR12, VAR3, VAR24, VAR25, VAR21, VAR7, VAR17 );
input VAR14, VAR10, VAR12, VAR3, VAR24, VAR17;
output VAR25, VAR21;
output [6:0] VAR7;
reg [1:0] VAR11;
reg [4:0] VAR15;
reg [6:0] VAR16;
reg VAR13, VAR6;
parameter VAR19 = 2'b00, VAR9 = 2'b01, VAR23 = 2'b10, VAR8 = 2'b11;
VAR4 VAR11 = VAR1... | mit |
genkilife/miaow | src/verilog/rtl/issue/vgpr_comparator.v | 5,320 | module MODULE1
(
VAR43,
VAR33, VAR24, VAR20,
VAR29, VAR6, VAR11, VAR36,
VAR39
);
wire VAR14, VAR10, VAR9, VAR19,
VAR13, VAR26;
input [3:0] VAR33;
wire [3:0] VAR30, VAR16, VAR40;
wire [2:0] VAR34, VAR1, VAR18;
input [VAR15-1:0] VAR24;
input [13:0] VAR20, VAR29, VAR6;
input [12:0] VAR11, VAR36, VAR39;
output [VAR27-1:0] ... | bsd-3-clause |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/misc/gamma_table.v | 32,945 | module MODULE1(
VAR3,
VAR6,
VAR1,
VAR8,
VAR5,
VAR9
);
input VAR3;
input VAR6;
input [ 2:0] VAR1;
input [VAR2-1:0] VAR8;
input VAR5;
output reg [VAR2-1:0] VAR9 = {VAR2{1'b0}};
reg [VAR2+2:0] VAR4 = {(VAR2+3){1'b0}};
reg VAR7 = 1'b0;
always @(posedge VAR3 or negedge VAR6)
if (!VAR6) begin
VAR9 <= {(VAR2){1'b0}};
VAR4 <= ... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pipe_sync.v | 27,168 | module MODULE1 #
(
parameter VAR78 = "VAR6", parameter VAR71 = "VAR20", parameter VAR101 = "VAR80", parameter VAR48 = 0, parameter VAR45 = 0, parameter VAR66 = 1, parameter VAR35 = 3, parameter VAR52 = 0, parameter VAR76 = 0
)
(
input VAR14,
input VAR54,
input VAR95,
input VAR31,
input VAR67,
input VAR60,
input VAR49,
... | gpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_acl_iface_acl_kernel_interface.v | 60,109 | module MODULE1 (
input wire VAR80, input wire VAR170, output wire VAR323, output wire [31:0] VAR254, output wire VAR93, input wire [0:0] VAR278, input wire [31:0] VAR208, input wire [13:0] VAR284, input wire VAR222, input wire VAR341, input wire [3:0] VAR283, input wire VAR152, input wire VAR203, input wire [63:0] VAR3... | mit |
jouyang3/FMCW | DSP/Radar_DSP/FPGA/windowing.v | 2,939 | module MODULE1(
input [11:0] VAR29,
input [11:0] VAR27,
input clk,
output reg[11:0] VAR11,
output reg[11:0] VAR5,
output reg VAR7,
output reg [3:0] state,
output reg VAR32
);
reg [10:0] VAR25;
wire [10:0] VAR31, VAR33;
wire [7:0] VAR6, VAR4;
reg [3:0] VAR15; reg [13:0] VAR22;
reg VAR28, VAR34, VAR30,
VAR24, VAR26;
reg ... | gpl-3.0 |
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