repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/synthesis/submodules/tracking_camera_system_timer_0.v | 6,890 | module MODULE1 (
address,
VAR30,
clk,
VAR11,
VAR24,
VAR25,
irq,
VAR12
)
;
output irq;
output [ 15: 0] VAR12;
input [ 2: 0] address;
input VAR30;
input clk;
input VAR11;
input VAR24;
input [ 15: 0] VAR25;
wire VAR26;
wire VAR21;
wire VAR32;
reg [ 3: 0] VAR18;
wire VAR10;
reg VAR31;
wire VAR3;
wire [ 31: 0] VAR29;
reg [ ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s.behavioral.v | 1,441 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
supply1 VAR7;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR6 ;
wire VAR4;
buf VAR1 (VAR4, VAR2 );
buf VAR3 (VAR5 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai.functional.pp.v | 2,048 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR3 ,
VAR9 ,
VAR14 ,
VAR11,
VAR6,
VAR12 ,
VAR15
);
output VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR9 ;
input VAR14 ;
input VAR11;
input VAR6;
input VAR12 ;
input VAR15 ;
wire VAR13 ;
wire VAR2 ;
wire VAR5;
or VAR10 (VAR13 , VAR3, VAR7 );
nand VAR1 (VAR2 , VAR14, VAR13, VAR9 );
VAR17 VAR... | apache-2.0 |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_execution_unit.v | 17,449 | module MODULE1 (
VAR83, VAR12, VAR35, VAR6, VAR17, VAR1, VAR15, VAR82, VAR51, VAR85, VAR9,
VAR75, VAR91, VAR22, VAR25, VAR30, VAR54, VAR19, VAR46, VAR67, VAR13, VAR45, VAR71, VAR84, VAR18, VAR92, VAR32, VAR43, VAR95, VAR65, VAR53, VAR62, VAR69 );
output VAR83; output [15:0] VAR12; output VAR35; output [15:0] VAR6; outp... | bsd-3-clause |
drichmond/riffa | fpga/riffa_hdl/tx_engine_classic.v | 40,216 | module MODULE1
parameter VAR134 = 1,
parameter VAR170 = 1,
parameter VAR153 = 256,
parameter VAR117 = "VAR171")
( input VAR55,
input VAR75, input VAR176, output VAR3,
output VAR72,
input [VAR121-1:0] VAR82,
input VAR7,
output [VAR56-1:0] VAR107,
output VAR138,
output VAR158,
output [VAR185(VAR56/32)-1:0] VAR39,
output ... | bsd-3-clause |
spesialstyrker/boula | gen/PCIe/example_design/PIO_EP_MEM_ACCESS.v | 12,457 | module MODULE1 (
clk,
VAR41,
VAR63, VAR46, VAR8,
VAR6, VAR23, VAR32, VAR71, VAR15
);
input clk;
input VAR41;
input [10:0] VAR63;
input [3:0] VAR46;
output [31:0] VAR8;
input [10:0] VAR6;
input [7:0] VAR23;
input [31:0] VAR32;
input VAR71;
output VAR15;
wire [31:0] VAR8;
reg [31:0] VAR17;
wire [31:0] VAR34, VAR45, VAR4,... | gpl-2.0 |
fallen/milkymist-mmu | cores/asfifo/rtl/asfifo.v | 2,768 | module MODULE1 #(
parameter VAR28 = 8,
parameter VAR26 = 4,
parameter VAR21 = (1 << VAR26)
) (
output [VAR28-1:0] VAR6,
output reg VAR7,
input VAR19,
input VAR14,
input [VAR28-1:0] VAR3,
output reg VAR10,
input VAR4,
input VAR5,
input rst
);
reg [VAR28-1:0] VAR8[VAR21-1:0];
wire [VAR26-1:0] VAR20, VAR16;
wire VAR17;
wi... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2.pp.blackbox.v | 1,263 | module MODULE1 (
VAR2,
VAR4,
VAR3 ,
VAR1
);
input VAR2;
input VAR4;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
sam-falvo/kestrel | cores/Nexys-2/Kestrel-2/rtl/verilog/NEXYS2.v | 18,587 | module MODULE1(
output [2:0] VAR178,
output [2:0] VAR133,
output [2:1] VAR18,
output VAR14,
output VAR131,
output VAR159,
output VAR191,
output VAR189,
output VAR130,
output VAR28,
output VAR54,
output VAR91,
output VAR23,
output VAR13,
output VAR65,
output VAR38,
output VAR120,
input VAR200,
input VAR145,
input VAR88,... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi_1.v | 2,352 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR10,
VAR2,
VAR6 ,
VAR11
);
output VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR10;
input VAR2;
input VAR6 ;
input VAR11 ;
VAR8 VAR1 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn.behavioral.v | 2,779 | module MODULE1 (
VAR25 ,
VAR5 ,
VAR8 ,
VAR19 ,
VAR29 ,
VAR18
);
output VAR25 ;
output VAR5 ;
input VAR8 ;
input VAR19 ;
input VAR29 ;
input VAR18;
supply1 VAR10;
supply0 VAR13;
supply1 VAR6 ;
supply0 VAR30 ;
wire VAR11 ;
wire VAR28 ;
wire VAR14 ;
wire VAR2 ;
wire VAR21 ;
wire VAR15;
wire VAR17 ;
reg VAR12 ;
wire VAR22 ... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gl_fdbk.v | 4,783 | module MODULE4(VAR80 ,VAR28 );
output VAR80 ;
input VAR28 ;
wire VAR9 ;
wire VAR37 ;
wire VAR59 ;
wire VAR58 ;
wire VAR15 ;
VAR8 VAR63 (
.VAR13 (VAR15 ),
.VAR20 (VAR9 ) );
VAR26 VAR85 (
.VAR13 (VAR37 ),
.VAR20 (VAR59 ) );
VAR8 VAR44 (
.VAR13 (VAR80 ),
.VAR20 (VAR9 ) );
VAR26 VAR34 (
.VAR13 (VAR58 ),
.VAR20 (VAR59 ) );
... | gpl-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkDM_Abstract_Commands.v | 58,760 | module MODULE2(VAR27,
VAR120,
VAR31,
VAR23,
VAR123,
VAR47,
VAR114,
VAR54,
VAR254,
VAR75,
VAR58,
VAR177,
VAR52,
VAR266,
VAR193,
VAR6,
VAR170,
VAR265,
VAR115,
VAR226,
VAR231,
VAR201,
VAR125,
VAR239,
VAR202,
VAR142,
VAR159,
VAR10,
VAR218,
VAR258);
input VAR27;
input VAR120;
input VAR31;
output VAR23;
input [6 : 0] VAR123;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap_8.v | 1,870 | module MODULE2 (
VAR5,
VAR2,
VAR1 ,
VAR3
);
input VAR5;
input VAR2;
input VAR1 ;
input VAR3 ;
VAR6 VAR4 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR5;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR3 ;
VAR6 VAR4 ();
endmodule | apache-2.0 |
drichmond/riffa | fpga/xilinx/kc705/riffa_wrapper_kc705.v | 38,589 | module MODULE1
parameter VAR347 = 128,
parameter VAR39 = 256,
parameter VAR331 = 5,
parameter VAR333 = "VAR115")
( input [VAR347-1:0] VAR252,
input [(VAR347/8)-1:0] VAR50,
input VAR52,
input VAR77,
output VAR231,
input [VAR41-1:0] VAR306,
output VAR289,
output VAR68,
output [VAR347-1:0] VAR325,
output [(VAR347/8)-1:0] ... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.behavioral.v | 8,258 | module MODULE1( VAR3, VAR2, VAR7, VAR6, VAR4, VAR1, VAR5 );
input VAR5, VAR1, VAR3, VAR7, VAR2, VAR4;
output VAR6;
VAR9 VAR10(.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7),.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR5(VAR5));
VAR9 VAR8(.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7),.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/pre_i/DC_Plannar.v | 3,712 | module MODULE1(
VAR19,
clk,
VAR3,
VAR6,
VAR11,
VAR28,
VAR2,
VAR10,
VAR18,
VAR4,
VAR14,
VAR21,
VAR26,
VAR17,
VAR27,
VAR29,
VAR9
);
parameter VAR20=21;
parameter VAR1=0;
parameter VAR25=288;
parameter VAR24=1152;
parameter VAR12=4608;
parameter VAR8=32;
parameter VAR22=32;
parameter VAR13=32;
input VAR19;
input clk;
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv.symbol.v | 1,242 | module MODULE1 (
input VAR4,
output VAR1
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
lbl-cal/StanfordNoC | router/src/clib/c_gather.v | 2,557 | module MODULE1
(VAR1, VAR2);
parameter VAR9 = 32;
function integer VAR7(input [0:VAR9-1] VAR4);
integer VAR6;
begin
VAR7 = 0;
for(VAR6 = 0; VAR6 < VAR9; VAR6 = VAR6 + 1)
VAR7 = VAR7 + VAR4[VAR6];
end
endfunction
parameter [0:VAR9-1] VAR5 = {VAR9{1'b1}};
localparam VAR3 = VAR7(VAR5);
input [0:VAR9-1] VAR1;
output [0:VAR... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.functional.v | 1,585 | module MODULE1( VAR15, VAR5, VAR2, VAR18 );
input VAR5, VAR15, VAR2;
output VAR18;
wire VAR1;
not VAR12( VAR1, VAR2 );
wire VAR10;
and VAR16( VAR10, VAR1, VAR5, VAR15 );
wire VAR14;
not VAR8( VAR14, VAR15 );
wire VAR11;
and VAR9( VAR11, VAR14, VAR5, VAR2 );
wire VAR4;
not VAR3( VAR4, VAR5 );
wire VAR7;
and VAR17( VAR7,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv_2.v | 2,011 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR1,
VAR5,
VAR6 ,
VAR8
);
output VAR7 ;
input VAR4 ;
input VAR1;
input VAR5;
input VAR6 ;
input VAR8 ;
VAR3 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR7,
VAR4
);
output VAR7;
input VAR4;
supply1 VAR1;
supply0 VAR5;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbn/sky130_fd_sc_ls__dlxbn.behavioral.v | 2,107 | module MODULE1 (
VAR17 ,
VAR19 ,
VAR1 ,
VAR2
);
output VAR17 ;
output VAR19 ;
input VAR1 ;
input VAR2;
supply1 VAR4;
supply0 VAR18;
supply1 VAR14 ;
supply0 VAR12 ;
wire VAR10 ;
wire VAR3 ;
wire VAR8;
wire VAR13 ;
reg VAR9 ;
wire VAR5 ;
wire 1 ;
not VAR7 (VAR10 , VAR8 );
VAR15 VAR16 (VAR3 , VAR13, VAR10, VAR9, VAR4, VAR... | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_master_secure.v | 19,062 | module MODULE1 #(
parameter VAR4 = 0,
parameter VAR6 = 50000,
parameter VAR14 = 2
) (
input wire VAR18, input wire VAR35, output wire [31:0] VAR32, input wire [31:0] VAR27, output wire VAR21, output wire VAR37, output wire [31:0] VAR7, input wire VAR8, input wire VAR46, output wire [3:0] VAR31, output wire VAR22 );
wir... | gpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/dotp_wrapper_tom_sv.v | 6,117 | module MODULE1 (
VAR129,
VAR77,
VAR43,
VAR133,
VAR1,
VAR65,
VAR117, VAR14, VAR137, VAR47,
b0, b1, VAR80, VAR123,
VAR55
);
input VAR129;
input VAR77;
input VAR43;
input VAR133;
output VAR1;
output VAR65;
input [511:0] VAR117;
input [511:0] VAR14;
input [511:0] VAR137;
input [511:0] VAR47;
input [511:0] b0;
input [511:0]... | mit |
cliffordwolf/yosys | techlibs/nexus/cells_map.v | 3,947 | module \VAR53 (input VAR47, VAR54, VAR15, output VAR31);
parameter VAR5 = 1'VAR16;
wire VAR33 = 1'b1;
generate
if (VAR5 === 1'b1)
VAR34 #(.VAR7("VAR29")) VAR8 (.VAR47(VAR47), .VAR12(VAR54), .VAR44(VAR15), .VAR26(1'b0), .VAR31(VAR31));
else
VAR50 #(.VAR7("VAR29")) VAR8 (.VAR47(VAR47), .VAR12(VAR54), .VAR44(VAR15), .VAR5... | isc |
olgirard/opengfx430 | core/rtl/verilog/ogfx_backend.v | 11,453 | module MODULE1 (
VAR20, VAR44,
VAR1, VAR7,
VAR11, VAR4, VAR2
VAR13, VAR35,
VAR31, VAR17, VAR14, VAR16, VAR5, VAR45,
VAR34,
VAR28, VAR24, VAR2
VAR18, VAR37,
VAR21, VAR36, VAR38,
VAR6, VAR9, VAR46, VAR3, VAR32 );
output [15:0] VAR20; output VAR44;
output [VAR22:0] VAR1; output VAR7;
output [VAR8:0] VAR11; output VAR4; VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai.functional.v | 2,104 | module MODULE1 (
VAR8,
VAR3,
VAR14 ,
VAR10 ,
VAR11 ,
VAR15 ,
VAR18 ,
VAR16
);
input VAR8;
input VAR3;
output VAR14 ;
input VAR10 ;
input VAR11 ;
input VAR15 ;
input VAR18 ;
input VAR16 ;
wire VAR18 VAR12 ;
wire VAR18 VAR4 ;
wire VAR2 ;
wire VAR9;
or VAR5 (VAR12 , VAR18, VAR15 );
or VAR6 (VAR4 , VAR11, VAR10 );
nand VAR... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_jtag_dc_streaming.v | 8,630 | module MODULE1 (
clk,
VAR13,
VAR31,
VAR54,
VAR53
);
input clk;
input VAR13;
input VAR31;
input VAR54;
output VAR53;
parameter VAR2 = 3;
reg VAR53;
wire VAR30;
reg VAR71;
VAR19 #(.VAR9(VAR2)) VAR14 (
.clk(clk),
.VAR13(VAR13),
.din(VAR31),
.dout(VAR30)
);
always @ (posedge clk or negedge VAR13)
if (~VAR13)
VAR71 <= 1'b0;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi_1.v | 2,457 | module MODULE1 (
VAR7 ,
VAR12 ,
VAR2 ,
VAR8 ,
VAR5 ,
VAR3 ,
VAR4,
VAR6,
VAR1 ,
VAR10
);
output VAR7 ;
input VAR12 ;
input VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR6;
input VAR1 ;
input VAR10 ;
VAR11 VAR9 (
.VAR7(VAR7),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VA... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/iprepo/repo/xilinx_com_hls_set_1_0/hdl/verilog/set_assign_val.v | 13,665 | module MODULE1 (
VAR6,
VAR2,
VAR48,
VAR92,
VAR16,
VAR72,
VAR80,
VAR13,
VAR20,
VAR35,
VAR32,
VAR69,
VAR1,
VAR7,
VAR41,
VAR34,
VAR71,
VAR42,
VAR12,
VAR9,
VAR74,
VAR90,
VAR10,
VAR45,
VAR82,
VAR8,
VAR15,
VAR83,
VAR29,
VAR37,
VAR91,
VAR24,
VAR97,
VAR87,
VAR19,
VAR57,
VAR23,
VAR21,
VAR67,
VAR40,
VAR36,
VAR88,
VAR63,
VAR79,
V... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_src1_data_stream_0_V.v | 3,990 | module MODULE1
VAR11 = "VAR24",
VAR1 = 8,
VAR28 = 15,
VAR12 = 20000
)
(
input wire clk,
input wire reset,
output wire VAR21,
input wire VAR6,
input wire VAR22,
input wire [VAR1-1:0] VAR17,
output wire VAR3,
input wire VAR27,
input wire VAR10,
output wire [VAR1-1:0] VAR23
);
reg [VAR1-1:0] VAR20[0:VAR12-1];
reg [VAR1-1:... | gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab09/lab09/Code/IO/port/Counter_3_IO.v | 4,155 | module MODULE1(input clk,
input rst,
input VAR9,
input VAR26,
input VAR5,
input VAR10,
input [31:0] VAR3,
input [1:0] VAR8,
output VAR11,
output VAR4,
output VAR7,
output [31:0] VAR19
);
reg [32:0] VAR18,VAR17,VAR1;
reg [31:0] VAR14,VAR13,VAR25;
reg [23:0] VAR6;
reg VAR21,VAR20,VAR2,VAR23,VAR16,VAR12,VAR15,VAR22,VAR24;... | gpl-3.0 |
theapi/de1-soc | ps2/rtl/verilog/ascii.v | 10,700 | module MODULE1 (
input clk,
input VAR9,
input [7:0] VAR18,
output [7:0] MODULE1
);
reg [7:0] VAR7;
reg [1:0] VAR19 = 2'b00;
assign MODULE1 = VAR7;
reg VAR4 = 0;
reg VAR6 = 0;
reg [1:0] VAR5 = 2'b00;
wire VAR12;
reg [7:0] VAR16;
reg [7:0] VAR20 [2:0];
reg [1:0] VAR11 = 2'b00;
reg [1:0] VAR24 = 2'b00;
reg VAR21 = 0;
reg ... | mit |
dvanmali/Superscalar_Pipeline_Processor | cache_wb.v | 11,841 | module MODULE1(clk,VAR27,VAR33,VAR33,VAR19,VAR4,VAR44,VAR13,VAR28,address,VAR12,VAR10,VAR29,VAR35,VAR42,VAR30,VAR21,VAR14,VAR31,VAR9,VAR34,VAR39,VAR7,VAR15,VAR24);
input clk, VAR27,VAR33,VAR33,VAR19,VAR4,VAR44,VAR13,VAR28;
input [31:0] address, VAR12, VAR10,VAR29;
input [127:0] VAR34; input [127:0] VAR15;
output reg VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32oi/sky130_fd_sc_hs__a32oi.behavioral.v | 2,132 | module MODULE1 (
VAR5 ,
VAR18 ,
VAR16 ,
VAR4 ,
VAR3 ,
VAR14 ,
VAR1,
VAR2
);
output VAR5 ;
input VAR18 ;
input VAR16 ;
input VAR4 ;
input VAR3 ;
input VAR14 ;
input VAR1;
input VAR2;
wire VAR3 VAR9 ;
wire VAR3 VAR6 ;
wire VAR8 ;
wire VAR7;
nand VAR12 (VAR9 , VAR16, VAR18, VAR4 );
nand VAR11 (VAR6 , VAR14, VAR3 );
and VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o_1.v | 2,337 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR8 ,
VAR9 ,
VAR11 ,
VAR3,
VAR6,
VAR10 ,
VAR2
);
output VAR1 ;
input VAR7 ;
input VAR8 ;
input VAR9 ;
input VAR11 ;
input VAR3;
input VAR6;
input VAR10 ;
input VAR2 ;
VAR5 VAR4 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi_2.v | 2,352 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR10 ,
VAR2 ,
VAR4 ,
VAR1,
VAR8,
VAR7 ,
VAR9
);
output VAR6 ;
input VAR5 ;
input VAR10 ;
input VAR2 ;
input VAR4 ;
input VAR1;
input VAR8;
input VAR7 ;
input VAR9 ;
VAR11 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_uartgpioport.v | 2,182 | module MODULE1(
input VAR6,
input reset,
input VAR12,
output VAR1,
input VAR7,
output VAR14,
output VAR2,
output VAR13,
output VAR4,
output VAR11,
input VAR3,
output VAR5,
output VAR10,
output VAR15,
output VAR8,
output VAR9
);
assign VAR1 = VAR7;
assign VAR14 = 1'h0;
assign VAR2 = 1'h0;
assign VAR13 = 1'h1;
assign VAR... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/wb/rtl/wb_async_reg.v | 7,784 | module MODULE1 #
(
parameter VAR7 = 32, parameter VAR45 = 32, parameter VAR48 = (VAR7/8) )
(
input wire VAR3,
input wire VAR47,
input wire [VAR45-1:0] VAR24, input wire [VAR7-1:0] VAR38, output wire [VAR7-1:0] VAR12, input wire VAR35, input wire [VAR48-1:0] VAR18, input wire VAR57, output wire VAR55, output wire VAR22,... | mit |
siamumar/TinyGarbled | circuit_synthesis/mips/Lite_MIPS.v | 4,226 | module MODULE1
(
parameter VAR11 = 32,
parameter VAR53 = 6
)
(
clk,
rst,
VAR65,
VAR71,
VAR22
);
localparam VAR3 = 2**VAR53;
input clk;
input rst;
input [VAR3*VAR11-1:0] VAR65;
input [VAR3*VAR11-1:0] VAR71;
output [VAR3*VAR11-1:0] VAR22;
wire [VAR3*VAR11-1:0] VAR41;
wire [VAR3*VAR11-1:0] VAR66;
wire [VAR3*VAR11-1:0] VAR... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/packet_memory.v | 1,456 | module MODULE1(
clk,
VAR18,
VAR24,
VAR22,
VAR19,
VAR33,
VAR21,
VAR28,
VAR5,
VAR39
);
input clk;
input VAR18; input [10:3] VAR24;
input [63:0] VAR22;
output [63:0] VAR19;
input [7:0] VAR33;
input [10:2] VAR21;
input [31:0] VAR28;
output [31:0] VAR5;
input [3:0] VAR39;
reg [63:0] VAR19;
reg [31:0] VAR5;
reg VAR23;
reg VA... | mit |
jacgoudsmit/P8X32A_Emulation | Altera/cog.v | 17,325 | module MODULE1
(
input VAR20,
input VAR90, input VAR13,
input VAR30,
input VAR54, input [27:0] VAR60,
input VAR41,
input VAR45, output VAR12,
output VAR17,
output VAR44,
output [1:0] VAR104,
output [15:0] VAR63,
output [31:0] VAR95,
input [31:0] VAR58,
input VAR92,
input VAR38,
input [31:0] VAR4,
input [7:0] VAR72, out... | gpl-3.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/mem.v | 5,927 | module MODULE1(
input wire[31:0] VAR16,
input wire[31:0] VAR33,
input wire[31:0] VAR40,
input wire[2:0] VAR4,
input wire VAR23,
input wire[31:0] VAR15,
input wire VAR25,
input wire[3:0] VAR24,
input wire[31:0] VAR52,
input wire[3:0] VAR34,
input wire VAR42,
input wire VAR63,
input wire VAR3,
input wire[4:0] VAR68,
inpu... | unlicense |
qeedquan/fpga | de2-115/uart_echo/3_uart_tx.v | 2,272 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR2,
input wire VAR14,
input wire [7:0] din,
output reg VAR17,
output wire VAR19
);
parameter VAR4 = 8;
parameter VAR15 = 16;
localparam VAR13 = 0;
localparam VAR11 = 1;
localparam VAR20 = 2;
localparam VAR8 = 3;
reg [1:0] VAR18, VAR5;
reg [3:0] VAR10, VAR1... | mit |
hoangt/NOCulator | hring/hw/buffered/src/whr_top.v | 15,111 | module MODULE1
(clk, reset, VAR26, VAR33, VAR17,
VAR118, VAR95, VAR56, VAR134,
VAR6);
parameter VAR104 = 8;
parameter VAR133 = 4;
parameter VAR1 = 4;
localparam VAR64 = VAR43(VAR1);
parameter VAR71 = 2;
localparam VAR130 = VAR71 * VAR64;
parameter VAR59 = 1;
parameter VAR20 = VAR15;
localparam VAR123
= ((VAR20 == VAR15... | mit |
freecores/tiny_tate_bilinear_pairing | group_size_is_151_bits/rtl/pe.v | 4,652 | module MODULE6(clk, reset, VAR9, d0, d1, d2, out);
input clk;
input reset;
input [10:0] VAR9;
input [197:0] d0;
input [VAR14:0] d1, d2;
output [VAR14:0] out;
reg [197:0] VAR30;
reg [VAR14:0] VAR46, VAR56, VAR37;
wire [1:0] VAR21, VAR38, VAR4;
wire [VAR14:0] MODULE5, VAR48, VAR42,
VAR18, VAR50, VAR5, VAR24, VAR16, VAR59... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtn/sky130_fd_sc_ms__dlrtn.blackbox.v | 1,354 | module MODULE1 (
VAR5 ,
VAR8,
VAR1 ,
VAR6
);
output VAR5 ;
input VAR8;
input VAR1 ;
input VAR6 ;
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_non_blocking.v | 16,327 | module MODULE1
import VAR129::*;
, parameter VAR8(VAR100)
, parameter VAR8(VAR73)
, parameter VAR8(VAR93)
, parameter VAR8(VAR103)
, parameter VAR8(VAR158)
, parameter VAR8(VAR4)
, parameter VAR76=VAR122(VAR88,VAR100,VAR73)
, parameter VAR27=VAR192(VAR100)
)
(
input VAR178
, input VAR6
, input VAR114
, input [VAR76-1:0... | bsd-3-clause |
Cognoscan/BoostDSP | verilog/src/smallFilters/SmallBsf.v | 3,982 | module MODULE1 #(
parameter VAR11 = 16, parameter VAR4 = 10, parameter VAR9 = 18, parameter VAR8 = 1 )
(
input clk, input rst, input en, input signed [VAR11-1:0] VAR1, output signed [VAR11-1:0] VAR10 );
reg signed [VAR11+VAR4-1:0] VAR13;
reg signed [VAR11+VAR9-1:0] VAR15;
reg signed [VAR11-1:0] VAR14;
wire signed [VAR1... | apache-2.0 |
jakubfi/mera400f | src/cpu.v | 13,453 | module MODULE1(
input VAR75,
input VAR140,
input VAR145,
input VAR244,
input VAR76, VAR221,
input [0:15] VAR219,
input VAR298, VAR245, VAR157, VAR112,
input VAR80, VAR146, VAR164, VAR173, VAR16, VAR124, VAR306, VAR197,
input VAR98, VAR240, VAR188, VAR282,
input VAR300, VAR33, VAR217, VAR253, VAR257, VAR54, VAR280,
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s_1.v | 2,160 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR8,
VAR7,
VAR4 ,
VAR2
);
output VAR6 ;
input VAR3 ;
input VAR8;
input VAR7;
input VAR4 ;
input VAR2 ;
VAR1 VAR5 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR8;
supply0 VAR7;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b.behavioral.pp.v | 1,880 | module MODULE1 (
VAR2,
VAR7,
VAR1 ,
VAR3 ,
VAR12 ,
VAR11 ,
VAR5
);
input VAR2;
input VAR7;
output VAR1 ;
input VAR3 ;
input VAR12 ;
input VAR11 ;
input VAR5 ;
wire VAR5 VAR13 ;
wire VAR14 ;
wire VAR15;
not VAR6 (VAR13 , VAR5 );
or VAR8 (VAR14 , VAR13, VAR11, VAR12, VAR3 );
VAR10 VAR4 (VAR15, VAR14, VAR2, VAR7);
buf VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_lvc_wpad/sky130_fd_io__top_ground_lvc_wpad.symbol.v | 1,752 | module MODULE1 (
inout VAR19 ,
inout VAR5,
inout VAR12
);
supply0 VAR14;
supply0 VAR9;
supply1 VAR3 ;
supply1 VAR13 ;
supply1 VAR7 ;
supply0 VAR4 ;
supply0 VAR15 ;
supply1 VAR8 ;
supply1 VAR2 ;
supply1 VAR18 ;
supply1 VAR10 ;
supply1 VAR1 ;
supply1 VAR16 ;
supply0 VAR17 ;
supply0 VAR11 ;
supply0 VAR20 ;
supply0 VAR6 ;
... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/verilog/ANN_fpext_32ns_64_1.v | 1,097 | module MODULE1
VAR3 = 4,
VAR13 = 1,
VAR9 = 32,
VAR4 = 64
)(
input wire [VAR9-1:0] VAR8,
output wire [VAR4-1:0] dout
);
wire VAR14;
wire [31:0] VAR1;
wire VAR15;
wire [63:0] VAR12;
VAR5 VAR10 (
.VAR2 ( VAR14 ),
.VAR16 ( VAR1 ),
.VAR6 ( VAR15 ),
.VAR7 ( VAR12 )
);
assign VAR14 = 1'b1;
assign VAR1 = VAR8==='VAR11 ? 'b0 : ... | gpl-3.0 |
romovs/xula-lib-verilog | camera/CameraSetup.v | 6,004 | module MODULE1 (VAR12, VAR32, VAR1, VAR27, VAR24);
parameter VAR36 = 24000000; parameter VAR28 = 8'h42;
input VAR12; input VAR32; output reg VAR1; output VAR27; inout VAR24;
localparam VAR19 = 100000; localparam VAR16 = 300;
localparam integer VAR20 = (VAR36/1000)*VAR16;
localparam VAR29 = VAR36/VAR19/2;
reg [VAR11(VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b_2.v | 2,127 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR2,
VAR8
);
output VAR3 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR2;
input VAR8;
VAR4 VAR5 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR3 ,
VAR6 ,
VAR7 ,
VAR1
);
output VAR3 ;
input VAR6 ;
input VAR... | apache-2.0 |
CospanDesign/nysa-artemis-platform | artemis/slave/wb_nysa_artemis_platform/cores/artemis_ddr3.v | 4,141 | module MODULE1 (
input VAR24,
input VAR128,
output VAR16,
output VAR90,
output rst,
inout [7:0] VAR111,
output [13:0] VAR62,
output [2:0] VAR79,
output VAR89,
output VAR93,
output VAR107,
output VAR37,
output VAR120,
output VAR130,
output VAR106,
inout VAR91,
inout VAR85,
inout VAR40,
inout VAR98,
output VAR43,
output ... | gpl-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_LOALPL7_syn.v | 6,713 | module MODULE1 ( VAR156, VAR20, VAR144, VAR77 );
input [15:0] VAR20;
input [15:0] VAR144;
output [16:0] VAR77;
input VAR156;
wire VAR74, VAR123, VAR27, VAR190, VAR131, VAR218, VAR240, VAR105, VAR140, VAR104, VAR83, VAR154, VAR35, VAR141,
VAR94, VAR212, VAR244, VAR54, VAR204, VAR45, VAR184, VAR250, VAR134, VAR195, VAR22... | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/top_module.v | 2,932 | module MODULE1(
input VAR12,
input reset,
input VAR42,
input VAR9,
input VAR36,
input VAR3,
input VAR7,
output VAR11,
output VAR1,
output VAR34,
output[15:0] VAR24,
output [15:0] VAR35
);
wire VAR21;
wire VAR17, VAR22, VAR5, VAR27, VAR33, VAR4, VAR30;
wire[15:0] VAR31, VAR14, VAR32, VAR8, VAR43;
wire[15:0] VAR13, VAR37... | mit |
scalable-networks/ext | uhd/fpga/usrp2/udp/fifo19_rxrealign.v | 1,995 | module MODULE1
(input clk, input reset, input VAR6,
input [18:0] VAR7, input VAR1, output VAR3,
output [18:0] VAR10, output VAR8, input VAR5);
reg VAR2;
localparam VAR4 = 0;
localparam VAR9 = 1;
assign VAR10[18] = VAR7[18];
assign VAR10[17] = VAR7[17];
assign VAR10[16] = (VAR2==VAR4) | (VAR7[17] & VAR7[16]); assign VAR... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v | 1,975 | module MODULE1 #( parameter VAR1(VAR6 )
, parameter VAR1(VAR5 )
, parameter VAR1(VAR2 )
, parameter VAR7 =
, parameter VAR12 =
)
( input VAR9
, input VAR3
, input [VAR7-1:0] VAR4
, input [VAR7-1:0] VAR8
, output logic [VAR12-1:0] VAR11
);
VAR10 @(posedge VAR9)
begin
if (VAR3)
VAR11 <= VAR5;
end
else
VAR11 <= VAR11 - VA... | bsd-3-clause |
DougFirErickson/parallella-hw | boards/archive/gen1.1/fpga/hdl/mux4.v | 1,327 | module MODULE1(
out,
VAR1, VAR9, VAR4, VAR5, VAR7, VAR6, VAR3, VAR2
);
parameter VAR8=99;
input [VAR8-1:0] VAR1;
input [VAR8-1:0] VAR9;
input [VAR8-1:0] VAR4;
input [VAR8-1:0] VAR5;
input VAR7;
input VAR6;
input VAR3;
input VAR2;
output [VAR8-1:0] out;
assign out[VAR8-1:0] = ({(VAR8){VAR7}} & VAR1[VAR8-1:0] |
{(VAR8){V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2.functional.v | 1,703 | module MODULE1 (
VAR2,
VAR4,
VAR7 ,
VAR3 ,
VAR11
);
input VAR2;
input VAR4;
output VAR7 ;
input VAR3 ;
input VAR11 ;
wire VAR6 ;
wire VAR9;
xor VAR5 (VAR6 , VAR11, VAR3 );
VAR1 VAR8 (VAR9, VAR6, VAR2, VAR4);
buf VAR10 (VAR7 , VAR9 );
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/Finished_Cmd_FIFO.v | 13,387 | module MODULE1(
clk,
rst,
din,
VAR328,
VAR370,
dout,
VAR58,
VAR29
);
input clk;
input rst;
input [127 : 0] din;
input VAR328;
input VAR370;
output [127 : 0] dout;
output VAR58;
output VAR29;
VAR409 #(
.VAR151(0),
.VAR322(0),
.VAR269(0),
.VAR91(0),
.VAR170(0),
.VAR179(0),
.VAR349(0),
.VAR362(32),
.VAR304(1),
.VAR352(1),... | gpl-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v | 18,247 | module MODULE1 (
input wire VAR15, input wire VAR81, input wire [29:0] VAR29, output wire VAR46, input wire [4:0] VAR39, input wire [31:0] VAR6, input wire VAR17, output wire [255:0] VAR96, output wire VAR3, input wire VAR68, input wire [255:0] VAR1, input wire VAR78, output wire [24:0] VAR18, output wire VAR31, output... | mit |
AngelTerrones/Antares | Hardware/verilog/antares_alu.v | 15,831 | module MODULE1 #(parameter VAR44 = 1,
parameter VAR51 = 1,
parameter VAR39 = 1
)(
input clk,
input rst,
input [31:0] VAR38,
input [31:0] VAR57,
input [4:0] VAR29,
input VAR34,
input VAR27,
output VAR23,
output reg [31:0] VAR19,
output VAR53,
output reg VAR1
);
reg [63:0] VAR46; reg VAR17; reg VAR59;
wire [31:0] VAR14; ... | mit |
peteasa/oh | src/pic/hdl/pic.v | 8,576 | module MODULE1 #( parameter VAR24 = 32, parameter VAR27 = 10, parameter VAR39 = 1 )
(
input clk, input VAR26, input VAR33, input [5:0] VAR32, input [31:0] VAR44, output reg [VAR24-1:0] VAR3, output reg [VAR27-1:0] VAR28, output reg [VAR27-1:0] VAR52, output reg [VAR27-1:0] VAR21, input [VAR27-1:0] VAR14, input [VAR24-1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp_0.v | 2,130 | module MODULE2 (
VAR6 ,
VAR3 ,
VAR1 ,
VAR7,
VAR9,
VAR2 ,
VAR5
);
output VAR6 ;
input VAR3 ;
input VAR1 ;
input VAR7;
input VAR9;
input VAR2 ;
input VAR5 ;
VAR8 VAR4 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR6 ,
VAR3 ,
VAR1
);
output VAR6... | apache-2.0 |
katherinejlu/ece3400 | code dump/Lab3_team1/DE0_NANO.v | 5,431 | module MODULE1(
VAR28,
VAR21,
VAR29,
VAR25,
VAR8,
VAR7,
VAR17,
VAR13,
);
localparam VAR24 = 25000000;
input VAR28;
output [7:0] VAR21;
input [1:0] VAR29;
input [3:0] VAR25;
inout [33:0] VAR8;
input [1:0] VAR7;
inout [33:0] VAR17;
input [1:0] VAR13;
reg VAR27;
wire reset; reg address;
wire [9:0] VAR20; wire [9:0] VAR30;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/maj3/sky130_fd_sc_hd__maj3_1.v | 2,174 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR4 ,
VAR9 ,
VAR2,
VAR10,
VAR5 ,
VAR7
);
output VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR2;
input VAR10;
input VAR5 ;
input VAR7 ;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/new/main.v | 1,381 | module MODULE1 (
input VAR14,
output reset,
output VAR9, output VAR15,
output VAR3,
output VAR7,
output VAR13,
output VAR5,
output VAR2,
output VAR4
);
wire [31 : 0] VAR6;
VAR10 VAR1(.VAR6(VAR6));
assign VAR13 = VAR6[0];
assign VAR7 = VAR6[1];
assign reset = VAR6[2];
assign VAR9 = VAR6[3];
assign VAR15 = VAR6[4];
assig... | mit |
linuxbest/lzs | encode/rtl/verilog/encode.v | 4,079 | module MODULE1(
VAR9, VAR32, VAR17, VAR7,
VAR16, rst, VAR27, VAR23, VAR30, clk, VAR26
);
parameter VAR12 = 20;
input clk;
input VAR26; input [63:0] VAR30; input VAR23; input VAR27; input rst; input VAR16;
output [15:0] VAR7; output VAR17; output VAR32; output VAR9;
wire VAR29; wire [3:0] VAR24; wire [12:0] VAR15; wire ... | gpl-2.0 |
jotego/jt51 | hdl/jt51.v | 10,214 | module MODULE1(
input rst, input clk, input VAR68, input VAR56, input VAR44, input VAR38, input VAR36,
input [7:0] din, output [7:0] dout, output VAR18,
output VAR99,
output VAR62, output VAR5, output signed [15:0] VAR104,
output signed [15:0] VAR2,
output signed [15:0] VAR91,
output signed [15:0] VAR37
);
wire [9:0] V... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/ui/ui_rd_data.v | 18,401 | module MODULE1 #
(
parameter VAR71 = 100,
parameter VAR75 = 256,
parameter VAR9 = "VAR53",
parameter VAR61 = "VAR40"
)
(
VAR51, VAR73, VAR1, VAR39,
VAR70, VAR57, VAR90, VAR85,
rst, clk, VAR27, VAR26, VAR32, VAR17,
VAR18, VAR78, VAR35
);
input rst;
input clk;
output wire VAR51;
output wire [3:0] VAR73;
reg [5:0] VAR91;
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fah/sky130_fd_sc_hs__fah_4.v | 2,156 | module MODULE2 (
VAR4,
VAR8 ,
VAR6 ,
VAR2 ,
VAR3 ,
VAR7,
VAR9
);
output VAR4;
output VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR7;
input VAR9;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR4,
VAR8 ,
VAR6 ,
VAR2 ,
VAR3
)... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/jtag_tap/jtag_tap.v | 21,096 | module MODULE1( VAR22,
VAR16,
VAR17,
VAR58,
VAR8,
VAR26,
VAR29,
VAR15,
VAR11,
VAR41,
VAR12,
VAR57,
VAR14,
VAR9,
VAR52,
VAR50, VAR43, VAR51 );
input VAR22; input VAR16; input VAR17; input VAR58; output VAR8; output VAR26;
output VAR29;
output VAR15;
output VAR11;
output VAR41;
output VAR12;
output VAR57;
output VAR14;
o... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_ddrx_addr_cmd.v | 14,700 | module MODULE1
VAR31 = 1,
VAR35 = 1, VAR51 = 13, VAR46 = 13, VAR17 = 10, VAR37 = 3, VAR47 = "VAR49",
VAR5 = 10,
VAR53 = 0,
VAR57 = 2
)
(
VAR12,
VAR7,
VAR42,
VAR29,
VAR36,
VAR11,
VAR40,
VAR22,
VAR24,
VAR1,
VAR28,
VAR55,
VAR15,
VAR45,
VAR32,
VAR25, VAR34,
VAR33,
VAR21,
VAR56,
VAR44,
VAR2,
VAR27,
VAR30,
VAR4,
VAR3,
VAR18
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcin/sky130_fd_sc_hd__fahcin.pp.symbol.v | 1,325 | module MODULE1 (
input VAR5 ,
input VAR1 ,
input VAR3 ,
output VAR7,
output VAR8 ,
input VAR6 ,
input VAR2,
input VAR4,
input VAR9
);
endmodule | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/rj45_led_controller.v | 6,185 | module MODULE1(
input wire clk, input wire reset,
input wire VAR19,
input wire VAR6,
input wire [31:0] VAR22,
output reg [31:0] VAR5,
input wire [25:0] address,
output wire VAR9,
output wire VAR20,
output wire VAR4,
output wire VAR8,
output wire VAR17
);
localparam VAR1 = 3'd0,
VAR12 = 3'd1,
VAR16 = 4'd2;
localparam VA... | gpl-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_BeMicroCV/cog_ctr.v | 3,673 | module MODULE1
(
input VAR15,
input VAR8,
input VAR14,
input VAR22,
input VAR6,
input VAR16,
input [31:0] VAR4,
input [31:0] VAR1,
output reg [32:0] VAR10,
output [31:0] VAR5,
output VAR13
);
reg [31:0] VAR12;
reg [31:0] VAR20;
always @(posedge VAR15 or negedge VAR14)
if (!VAR14)
VAR12 <= 32'b0;
else if (VAR22)
VAR12 <... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3_2.v | 2,174 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR10,
VAR1,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR10;
input VAR1;
input VAR9 ;
input VAR3 ;
VAR4 VAR2 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/video.v | 4,606 | module MODULE1(
input VAR22,
output VAR16,
output VAR9,
output VAR1,
output VAR15,
output [7:0] VAR26,
output [7:0] VAR24,
output [7:0] VAR10,
output [15:0] VAR28,
input [7:0] VAR11,
input [15:0] VAR12
);
parameter VAR23 = 80;
parameter VAR8 = 100;
reg [10:0] VAR27 = 0;
reg [9:0] VAR6 = 0;
reg [10:0] VAR14;
reg [9:0] V... | gpl-3.0 |
Lan-Hekary/ARM | alu2.v | 1,616 | module MODULE1(input wire [31:0] VAR1,input wire [31:0]VAR7,
input wire [1:0] VAR5,
output reg[31:0] VAR2,output wire[3:0]VAR3);
reg [31:0]sum;
reg VAR6;
wire [31:0]VAR4=~VAR7;
always@(*) begin
if(VAR5[0]) {VAR6,sum}=VAR1+VAR4+1;
end
else {VAR6,sum}=VAR1+VAR7;
case (VAR5)
2'b00: VAR2=sum;
2'b01: VAR2=sum;
2'b10: VAR2=V... | gpl-3.0 |
loonquawl/fermiac | vga/VerilogSandbox.v | 7,888 | typedef enum {VAR15,read,write} VAR64;
typedef enum {VAR88,ready} VAR84;
module MODULE1
parameter VAR55=7, parameter VAR28=20,
parameter VAR74=8,
parameter VAR66=16,
parameter VAR2=18,
parameter VAR80=32,
parameter VAR91=16,
parameter VAR90=32,
parameter VAR70=1
)
(
input clk,
inout [VAR80-1:0] VAR51,
inout [VAR91-1:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111oi/sky130_fd_sc_hd__a2111oi.behavioral.v | 1,599 | module MODULE1 (
VAR13 ,
VAR6,
VAR9,
VAR12,
VAR3,
VAR4
);
output VAR13 ;
input VAR6;
input VAR9;
input VAR12;
input VAR3;
input VAR4;
supply1 VAR5;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR2 ;
wire VAR7 ;
wire VAR15;
and VAR11 (VAR7 , VAR6, VAR9 );
nor VAR14 (VAR15, VAR12, VAR3, VAR4, VAR7);
buf VAR1 (VAR13 , VAR15 );
... | apache-2.0 |
eda-globetrotter/PicenoDecoders | final/src/tosynth Folder/regfileww.v | 1,953 | module MODULE1(VAR8, VAR2, VAR3, VAR11, VAR13, VAR7,
VAR10, VAR1, VAR4, VAR12, clk);
output [0:127] VAR8, VAR2;
input [0:127] VAR3;
input clk;
input VAR4;
input VAR10, VAR1;
input [0:4] VAR7, VAR11, VAR13;
input [0:15] VAR12;
reg [0:127] VAR8, VAR2;
reg [0:127] VAR9 [0:31];
reg [0:127] VAR5, VAR6;
always @(posedge clk)... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_1.behavioral.v | 2,924 | module MODULE1( VAR19, VAR17, VAR4, VAR8 );
input VAR17, VAR19, VAR4;
output VAR8;
reg VAR22;
VAR24 VAR11(.VAR19(VAR19),.VAR17(VAR17),.VAR4(VAR4),.VAR8(VAR8),.VAR22(VAR22));
VAR24 VAR10(.VAR19(VAR19),.VAR17(VAR17),.VAR4(VAR4),.VAR8(VAR8),.VAR22(VAR22));
buf VAR18(VAR23,VAR4);
not VAR13(VAR21,VAR17);
and VAR9(VAR3,VAR4,... | apache-2.0 |
xiedidan/gpsdo-alpha | FreqCounter/FreqCounter.v | 1,401 | module MODULE1(VAR7, clk, VAR5, ready, VAR12, VAR8, VAR6);
input VAR7, clk, VAR5, VAR12, VAR8;
output VAR6;
output ready;
wire [31:0] sum;
wire [31:0] VAR1;
MODULE2 MODULE2(VAR7, clk, VAR5, sum);
MODULE4 MODULE1(VAR7, VAR5, VAR8, sum, VAR1);
MODULE3 MODULE3(VAR7, VAR1, VAR12, VAR8, VAR6);
assign ready = VAR5;
endmodule... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Lab2/laboratorio2/lab2_labkit.v | 2,174 | module MODULE1(clk, rst, VAR25, VAR18, VAR35,
VAR22, VAR31, VAR17, VAR23, VAR28, VAR6,
VAR32, VAR1, VAR10, VAR19, VAR5, VAR13,VAR16, VAR15);
input clk;
input rst;
input VAR25;
input VAR18;
input VAR35;
input VAR22;
input VAR31;
input VAR17;
input VAR23;
input VAR28;
input VAR6;
output wire [6:0] VAR15;
output wire VAR3... | mit |
iamllama/EE2020 | ee2020.cache/ip/b67405368c510ef2/dds_compiler_0_stub.v | 1,539 | module MODULE1(VAR3, VAR4,
VAR5, VAR1, VAR2)
;
input VAR3;
input VAR4;
input [23:0]VAR5;
output VAR1;
output [15:0]VAR2;
endmodule | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_rx_v1_00_a/hdl/verilog/axi_hdmi_rx.v | 13,296 | module MODULE1 (
VAR36,
VAR51,
VAR106,
VAR139,
VAR136,
VAR83,
VAR21,
VAR107,
VAR133,
VAR3,
VAR104,
VAR113,
VAR19,
VAR58,
VAR119,
VAR100,
VAR142,
VAR110,
VAR94,
VAR28,
VAR123,
VAR37,
VAR48,
VAR41,
VAR98,
VAR135,
VAR2,
VAR128);
parameter VAR39 = 32'hffffffff;
parameter VAR74 = 32'h00000000;
parameter VAR25 = 1234;
localp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp.functional.pp.v | 2,018 | module MODULE1 (
VAR14,
VAR3 ,
VAR13,
VAR1 ,
VAR9,
VAR10,
VAR15 ,
VAR16
);
output VAR14;
input VAR3 ;
input VAR13;
input VAR1 ;
input VAR9;
input VAR10;
input VAR15 ;
input VAR16 ;
wire VAR12 ;
wire VAR4 ;
wire VAR2 ;
wire VAR11;
not VAR18 (VAR4 , VAR12 );
not VAR5 (VAR2 , VAR1 );
nor VAR7 (VAR11, VAR13, VAR3 );
VAR6 V... | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/tc_cfg_bus_ifc.v | 7,292 | module MODULE1
(clk, reset, VAR6, VAR28, VAR10, VAR42, VAR17,
VAR22, VAR20, VAR18, req, write, VAR7, VAR23,
VAR27, VAR2, VAR3);
parameter VAR30 = 10;
parameter VAR41 = 6;
localparam VAR1 = VAR30 + VAR41;
parameter VAR36 = 2;
parameter VAR26 = 32;
parameter VAR38 = VAR8;
input clk;
input reset;
input [0:VAR36*VAR30-1] V... | mit |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/syn/src/commschannel.v | 11,723 | module MODULE1();
wire VAR5; wire [1:0] VAR35; wire [1:0] VAR32; wire VAR6; wire [1:0] VAR28;
reg VAR36[0:255];
reg VAR2;
reg [7:0] VAR30;
reg VAR13;
reg VAR22;
reg [7:0] VAR4;
reg [1:0] VAR14;
reg [7:0] VAR3;
wire [1:0] VAR19;
wire [1:0] VAR34;
reg VAR24;
reg [7:0] VAR9;
reg [1:0] VAR29;
reg [1:0] VAR27;
reg VAR21;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe.functional.v | 1,058 | module MODULE1 ();
endmodule | apache-2.0 |
agural/FPGA-Oscilloscope | FPGA/db/ip/qsys-nios/qsys-nios.v | 16,718 | module MODULE1-VAR100 (
input wire VAR71 );
wire VAR101; wire VAR132; wire [31:0] VAR38; wire [11:0] VAR108; wire VAR18; wire VAR72; wire [31:0] VAR69; wire VAR104; wire VAR99; wire [3:0] VAR19; wire VAR130; wire [31:0] VAR94; wire [8:0] VAR65; wire VAR41; wire VAR29; wire [31:0] VAR3; wire VAR125; wire [3:0] VAR15; wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b.functional.v | 1,886 | module MODULE1 (
VAR14,
VAR12,
VAR7 ,
VAR15 ,
VAR2 ,
VAR1 ,
VAR4
);
input VAR14;
input VAR12;
output VAR7 ;
input VAR15 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
wire VAR4 VAR13 ;
wire VAR8 ;
wire VAR11;
not VAR10 (VAR13 , VAR15 );
nand VAR3 (VAR8 , VAR4, VAR1, VAR2, VAR13 );
VAR9 VAR5 (VAR11, VAR8, VAR14, VAR12);
buf V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_psa_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_sn.symbol.v | 1,590 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR2 ,
input VAR9 ,
input VAR3 ,
input VAR7 ,
input VAR5,
input VAR8 ,
input VAR1
);
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/clkgen.v | 3,982 | module MODULE1
(
input VAR71,
input VAR30,
output VAR94,
output VAR18,
output VAR31,
input VAR89,
output VAR64,
output VAR34,
output VAR46,
output VAR5,
output VAR28
);
wire VAR75;
assign VAR75 = VAR30;
assign VAR94 = ~VAR75;
assign VAR64 = VAR89;
wire VAR14;
wire VAR3;
wire VAR45;
wire VAR47;
wire VAR86, VAR29;
wire V... | gpl-2.0 |
skarpenko/ultiparc | rtl/src/fabric2_control.v | 4,176 | module MODULE1 #(
parameter VAR11 = 11
)
(
clk,
VAR7,
VAR19,
VAR12,
VAR16,
VAR2,
VAR8,
VAR3,
VAR1,
VAR25,
VAR22,
VAR9,
VAR13,
VAR24,
VAR14
);
input wire clk;
input wire VAR7;
input wire VAR19;
input wire VAR12;
input wire VAR16;
input wire VAR2;
input wire [VAR11-1:0] VAR8;
input wire [VAR11-1:0] VAR3;
output wire [VAR... | bsd-2-clause |
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