repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
tvelliott/dsp_ice | firmware/fpga/src/spi_master.v | 3,058 | module MODULE1 (
input clk,
input rst,
input VAR2,
output VAR14,
output VAR5,
input VAR8,
input[7:0] VAR4,
output[7:0] VAR6,
output VAR3,
output VAR10
);
localparam VAR13=3;
localparam VAR9 = 3'd0,
VAR7 = 3'd1;
reg [2:0] state;
reg [7:0] VAR11;
reg [VAR13-1:0] VAR1;
assign VAR5 = (VAR1[VAR13-1] && state!=VAR9);
reg VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp.blackbox.v | 1,262 | module MODULE1 (
VAR5 ,
VAR1,
VAR4
);
output VAR5 ;
input VAR1;
input VAR4 ;
supply1 VAR7;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_wdata_mux.v | 6,887 | module MODULE1 #
(
parameter VAR40 = "none", parameter integer VAR4 = 1, parameter integer VAR29 = 1, parameter integer VAR38 = 1, parameter integer VAR16 = 0 )
(
input wire VAR7,
input wire VAR37,
input wire [VAR29*VAR4-1:0] VAR9,
input wire [VAR29-1:0] VAR15,
input wire [VAR29-1:0] VAR19,
output wire [VAR29-1:0] VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor2/sky130_fd_sc_ls__xor2.symbol.v | 1,291 | module MODULE1 (
input VAR6,
input VAR1,
output VAR5
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
KestrelComputer/gpia3 | rtl/verilog/GPIA_DWORD.v | 1,327 | module MODULE1(
input VAR14,
input VAR15,
input [1:0] VAR2,
input [63:0] VAR4,
input [7:0] VAR13,
output [63:0] VAR11
);
VAR1 VAR12(
.VAR14(VAR14),
.VAR15(VAR15),
.VAR2(VAR2),
.VAR4(VAR4[7:0]),
.VAR13(VAR13[0]),
.VAR11(VAR11[7:0])
);
VAR1 VAR9(
.VAR14(VAR14),
.VAR15(VAR15),
.VAR2(VAR2),
.VAR4(VAR4[15:8]),
.VAR13(VAR13[... | mpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/write_signal_breakout.v | 5,188 | module MODULE1 (
VAR14, VAR15,
VAR10,
VAR13,
VAR6,
VAR8,
VAR5,
VAR7,
VAR11,
VAR12, VAR3, VAR1,
VAR2,
VAR9
);
parameter VAR4 = 256;
input [VAR4-1:0] VAR14;
output wire [255:0] VAR15;
output wire [63:0] VAR10;
output wire [31:0] VAR13;
output wire VAR6;
output wire VAR8;
output wire VAR5;
output wire VAR7;
output wire [7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp.functional.pp.v | 1,730 | module MODULE1 (
VAR5,
VAR10,
VAR7 ,
VAR13,
VAR9,
VAR11 ,
VAR1
);
output VAR5;
input VAR10;
input VAR7 ;
input VAR13;
input VAR9;
input VAR11 ;
input VAR1 ;
wire VAR12 ;
wire VAR8;
not VAR6 (VAR8 , VAR7 );
VAR4 VAR3 (VAR12 , VAR10, VAR8, , VAR13, VAR9);
and VAR2 (VAR5 , VAR12, VAR7 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_nand.v | 1,588 | if (VAR7 && (VAR18==VAR11)) \
begin: VAR16 \
VAR17 VAR8 (.VAR12(VAR1),.VAR2(VAR13),.VAR14); \
end
module MODULE1 #(parameter VAR5(VAR18)
, parameter VAR7=0
)
(input [VAR18-1:0] VAR1
, input [VAR18-1:0] VAR13
, output [VAR18-1:0] VAR14
);
begin :VAR9
end
VAR4 assert(VAR7==0) else ("## %VAR20 VAR15 VAR10 VAR6 VAR19 VAR3 ... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp_macc_l.v | 4,719 | module MODULE1(
VAR27, VAR24, VAR21,
VAR29, VAR33, VAR20,
VAR16, VAR30, VAR14,
VAR28, VAR4, VAR23, VAR6, VAR12
);
output [129:0] VAR27; output VAR24;
output VAR21;
input VAR29; input VAR33; input VAR20; input VAR16; input VAR30;
input [129:0] VAR14; input [129:0] VAR28;
input [129:0] VAR4;
input VAR23;
input VAR6;
inpu... | gpl-2.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/sipo.v | 5,889 | module MODULE1(VAR3, VAR10, VAR14, VAR5, VAR13, clk);
output [7:0] VAR3;
output VAR10;
input VAR14;
input clk;
input VAR13;
input VAR5;
reg VAR10; reg [7:0] VAR3; reg [7:0] VAR6; reg VAR11; reg VAR4; reg VAR9; reg VAR8; reg VAR12; reg VAR1; reg VAR7; reg VAR2;
always @(~VAR13)
begin
VAR10<=1'd0;
VAR3<=8'd0;
VAR6<=8'd0;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv_16.v | 2,050 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR7,
VAR6,
VAR1 ,
VAR8
);
output VAR5 ;
input VAR3 ;
input VAR7;
input VAR6;
input VAR1 ;
input VAR8 ;
VAR4 VAR2 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR7;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.symbol.v | 1,451 | module MODULE1 (
input VAR1,
input VAR3,
input VAR7 ,
input VAR5 ,
output VAR6
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai.functional.pp.v | 2,086 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR9 ,
VAR2 ,
VAR7 ,
VAR18 ,
VAR5,
VAR8,
VAR15 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR18 ;
input VAR5;
input VAR8;
input VAR15 ;
input VAR4 ;
wire VAR17 ;
wire VAR12 ;
wire VAR10;
or VAR16 (VAR17 , VAR9, VAR1 );
nand VAR14 (VAR12 , VAR7, VAR2,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a_4.v | 2,422 | module MODULE2 (
VAR3 ,
VAR2 ,
VAR1 ,
VAR12 ,
VAR7 ,
VAR9 ,
VAR4,
VAR6,
VAR10 ,
VAR5
);
output VAR3 ;
input VAR2 ;
input VAR1 ;
input VAR12 ;
input VAR7 ;
input VAR9 ;
input VAR4;
input VAR6;
input VAR10 ;
input VAR5 ;
VAR11 VAR8 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VA... | apache-2.0 |
valptek/v586 | board_specific_files/esa11/hdmi.v | 4,450 | module MODULE1(
input VAR25,
input VAR43, output [2:0] VAR36, VAR38,
output VAR24, VAR40
);
reg [9:0] VAR44, VAR6;
reg VAR29, VAR56, VAR45;
always @(posedge VAR43 or negedge VAR25) if (~VAR25) VAR45 <= 0; else VAR45 <= (VAR44<640) && (VAR6<480);
always @(posedge VAR43 or negedge VAR25) if (~VAR25) VAR44 <= 0; else VAR4... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/vfabric_sdiv.v | 3,075 | module MODULE1(VAR10, VAR2,
VAR1, VAR18, VAR22,
VAR27, VAR38, VAR11,
VAR32, VAR19, VAR15,
VAR24, VAR12, VAR30);
parameter VAR37 = 32;
parameter VAR23 = 32;
parameter VAR6 = 64;
input VAR10, VAR2;
input [VAR37-1:0] VAR1;
input [VAR37-1:0] VAR27;
input VAR18, VAR38;
output VAR22, VAR11;
output [VAR37-1:0] VAR32, VAR24;
o... | mit |
oere/progressive-learning-platform | reference/hw/verilog/mod_gpio.v | 2,868 | module MODULE1(rst, clk, VAR1, VAR4, VAR9, VAR10, VAR5, din, VAR3, dout, VAR7);
input rst;
input clk;
input VAR1,VAR4;
input [31:0] VAR9, VAR10;
input [1:0] VAR5;
input [31:0] din;
output [31:0] VAR3, dout;
inout [15:0] VAR7;
wire [31:0] VAR12, VAR11;
assign VAR3 = VAR12;
assign dout = VAR11;
reg [15:0] VAR6 = 16'h0000... | gpl-3.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/altera_avalon_st_idle_remover.v | 2,628 | module MODULE1 (
input clk,
input VAR1,
output reg VAR10,
input VAR6,
input [7: 0] VAR8,
input VAR7,
output reg VAR2,
output reg [7: 0] VAR5
);
reg VAR9;
wire VAR4, VAR3;
assign VAR3 = (VAR8 == 8'h4a);
assign VAR4 = (VAR8 == 8'h4d);
always @(posedge clk or negedge VAR1) begin
if (!VAR1) begin
VAR9 <= 0;
end else begin
... | gpl-3.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_qmem_top.v | 10,399 | module MODULE1(
clk, rst,
VAR59, VAR44, VAR30,
VAR52,
VAR24,
VAR33,
VAR11,
VAR60,
VAR29,
VAR25,
VAR12,
VAR46,
VAR49,
VAR55,
VAR40,
VAR10,
VAR14,
VAR9,
VAR47,
VAR26,
VAR18,
VAR67,
VAR51,
VAR42,
VAR68,
VAR43,
VAR3,
VAR64,
VAR57,
VAR15,
VAR20,
VAR62,
VAR13,
VAR50,
VAR56,
VAR35,
VAR65,
VAR17,
VAR61,
VAR32,
VAR54,
VAR66,
VA... | gpl-3.0 |
esonghori/TinyGarbled | circuit_synthesis/a23/a23_gc_main.v | 1,907 | module MODULE1
parameter VAR9 = 64 , parameter VAR17 = 64 , parameter VAR7 = 64 , parameter VAR27 = 64 , parameter VAR12 = 64 )
(
input clk,
input rst,
input [VAR9*32-1:0] VAR21,
input [VAR17 *32-1:0] VAR4,
input [VAR7 *32-1:0] VAR22,
output [VAR27 *32-1:0] VAR20,
output VAR23
);
wire [31:0] VAR25;
wire [31:0] VAR11;
w... | gpl-3.0 |
alanachtenberg/CSCE-350 | Project3/SingleCycleProc.v | 6,341 | module MODULE1(VAR16, VAR27, VAR41, VAR43);
input VAR27, VAR16;
input [31:0] VAR41;
output [31:0] VAR43;
wire [31:0] VAR39;
wire [31:0] VAR30;
wire [31:0] VAR10, VAR26;
wire VAR52;
wire VAR34, VAR25, VAR4, VAR28, VAR8, VAR24, VAR17, VAR44, VAR13;
wire [31:0]VAR12; wire [31:0] VAR49, VAR3;
VAR46 VAR20(VAR39, VAR39, VAR2... | gpl-2.0 |
ElegantLin/My-CPU | project_4/project_4.srcs/sources_1/imports/Chapter11/mem.v | 14,343 | module MODULE1(
input wire rst,
input wire[VAR52] VAR22,
input wire VAR21,
input wire[VAR2] VAR51,
input wire[VAR2] VAR14,
input wire[VAR2] VAR23,
input wire VAR36,
input wire[VAR48] VAR35,
input wire[VAR2] VAR30,
input wire[VAR2] VAR8,
input wire[VAR2] VAR13,
input wire VAR27,
input wire VAR39,
input wire VAR25,
input... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.behavioral.v | 1,336 | module MODULE1( VAR5, VAR4, VAR1, VAR7, VAR2 );
input VAR2, VAR7, VAR1, VAR5;
output VAR4;
VAR6 VAR8(.VAR5(VAR5),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR2(VAR2));
VAR6 VAR3(.VAR5(VAR5),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR2(VAR2)); | apache-2.0 |
ASP-SoC/ASP-SoC | libASP/grpPlatform/unitPlatformHps/synlayQuartus/subsystemA/Platform_bb.v | 5,609 | module MODULE1 (
VAR24,
VAR65,
VAR72,
VAR9,
VAR14,
VAR27,
VAR55,
VAR18,
VAR64,
VAR35,
VAR37,
VAR53,
VAR23,
VAR16,
VAR74,
VAR93,
VAR50,
VAR36,
VAR94,
VAR25,
VAR78,
VAR31,
VAR71,
VAR58,
VAR41,
VAR22,
VAR15,
VAR30,
VAR17,
VAR91,
VAR39,
VAR46,
VAR54,
VAR90,
VAR43,
VAR61,
VAR45,
VAR33,
VAR56,
VAR48,
VAR85,
VAR67,
VAR8,
VAR6... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputisolatch/sky130_fd_sc_lp__inputisolatch.pp.symbol.v | 1,359 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR1,
input VAR3 ,
input VAR5 ,
input VAR7 ,
input VAR4
);
endmodule | apache-2.0 |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/altera_reset_controller.v | 12,329 | module MODULE1
parameter VAR56 = 6,
parameter VAR52 = 0,
parameter VAR65 = 0,
parameter VAR42 = 0,
parameter VAR8 = 0,
parameter VAR11 = 0,
parameter VAR32 = 0,
parameter VAR57 = 0,
parameter VAR63 = 0,
parameter VAR35 = 0,
parameter VAR37 = 0,
parameter VAR47 = 0,
parameter VAR36 = 0,
parameter VAR54 = 0,
parameter VA... | apache-2.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/altera_avalon_st_idle_remover.v | 1,834 | module MODULE1 (
input clk,
input VAR9,
output reg VAR4,
input VAR10,
input [7: 0] VAR8,
input VAR3,
output reg VAR5,
output reg [7: 0] VAR2
);
reg VAR6;
wire VAR7, VAR1;
assign VAR1 = (VAR8 == 8'h4a);
assign VAR7 = (VAR8 == 8'h4d);
always @(posedge clk or negedge VAR9) begin
if (!VAR9) begin
VAR6 <= 0;
end else begin
... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fpu/bsg_fpu_mul.v | 10,488 | module MODULE1
(
input VAR84
, input VAR46
, input VAR12
, input VAR10
, input [VAR71+VAR35:0] VAR18
, input [VAR71+VAR35:0] VAR44
, output logic VAR110
, output logic VAR114
, output logic [VAR71+VAR35:0] VAR58
, output logic VAR57
, output logic VAR55
, output logic VAR111
, output logic VAR2
, input VAR14 );
logic V... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/bank_mach.v | 30,087 | module MODULE1 #
(
parameter VAR159 = 100,
parameter VAR36 = "1T",
parameter VAR96 = 3,
parameter VAR167 = 2,
parameter VAR161 = "8",
parameter VAR135 = 12,
parameter VAR116 = 4,
parameter VAR75 = 5,
parameter VAR40 = 8,
parameter VAR22 = "VAR150",
parameter VAR82 = "VAR111",
parameter VAR83 = "VAR111",
parameter VAR16... | lgpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_write_datapath.v | 10,985 | module MODULE1(
VAR11,
VAR14,
VAR46,
VAR35,
VAR44,
VAR36,
VAR73,
VAR13,
VAR40,
VAR67,
VAR47,
VAR33,
VAR60
);
parameter VAR32 = "";
parameter VAR23 = "";
parameter VAR55 = "";
parameter VAR24 = "";
parameter VAR3 = "";
parameter VAR50 = "";
parameter VAR77 = "";
parameter VAR25 = "";
parameter VAR26 = "";
parameter VAR1... | gpl-3.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_clock_module.v | 7,053 | module MODULE1 #
(
parameter VAR26 = 2,
parameter VAR13 = 1,
parameter VAR4 = 3.2,
parameter VAR1 = 4,
parameter VAR5 = 2,
parameter VAR48 = 4,
parameter VAR49 = 2
)
(
VAR42,
VAR62,
VAR20,
VAR46,
VAR9
);
input VAR42;
input VAR62;
output VAR20;
output VAR46;
output VAR9;
wire VAR2;
wire VAR18;
wire VAR25;
wire VAR51;
wi... | gpl-3.0 |
rfotino/consolite-hardware | proj/ipcore_dir/s6_lpddr_ram/user_design/rtl/mcb_controller/iodrp_mcb_controller.v | 15,423 | module MODULE1(
input wire [7:0] VAR43,
input wire [7:0] VAR64,
output reg [7:0] VAR20 = 0,
input wire VAR62,
input wire VAR11,
output wire VAR59,
input wire VAR34,
input wire [4:0] VAR51,
input wire VAR54,
input wire VAR42,
output reg VAR7,
output wire VAR28, output reg VAR9,
output reg VAR52,
input wire VAR32, output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb.pp.symbol.v | 1,301 | module MODULE1 (
input VAR2 ,
input VAR3 ,
input VAR1 ,
input VAR4 ,
output VAR5 ,
input VAR7,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a_1.v | 2,411 | module MODULE2 (
VAR7 ,
VAR11 ,
VAR3 ,
VAR9 ,
VAR10 ,
VAR1 ,
VAR2,
VAR4,
VAR12 ,
VAR5
);
output VAR7 ;
input VAR11 ;
input VAR3 ;
input VAR9 ;
input VAR10 ;
input VAR1 ;
input VAR2;
input VAR4;
input VAR12 ;
input VAR5 ;
VAR6 VAR8 (
.VAR7(VAR7),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai.symbol.v | 1,394 | module MODULE1 (
input VAR5 ,
input VAR4 ,
input VAR3,
output VAR7
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | rtl/mor1kx/mor1kx_ctrl_cappuccino.v | 52,677 | module MODULE1
parameter VAR135 = 32,
parameter VAR170 = {{(VAR135-13){1'b0}},
parameter VAR58 = "VAR299",
parameter VAR233 = "VAR299",
parameter VAR213 = "VAR299",
parameter VAR293 = "VAR201",
parameter VAR136 = 5,
parameter VAR104 = 9,
parameter VAR234 = 2,
parameter VAR204 = "VAR201",
parameter VAR217 = 6,
parameter... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/registers.v | 26,602 | module MODULE1
parameter VAR108 = 12,
parameter VAR58 = 512, parameter VAR51 = "VAR155",
parameter VAR80 = 2,
parameter VAR30 = 32,
parameter VAR87 = "VAR169",
parameter VAR21= 1,
parameter VAR131= 1)
(
input VAR145,
input VAR104,
input [VAR81-1:0] VAR16,
input VAR6,
input VAR161,
input [VAR85(VAR81/32)-1:0] VAR167,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b.pp.blackbox.v | 1,294 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR1 ,
VAR2,
VAR7
);
output VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR1 ;
input VAR2;
input VAR7;
endmodule | apache-2.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | cores/unoptimized_virtual_wire_top.v | 4,855 | module MODULE1 (
input VAR35
);
localparam VAR6 = VAR3;
localparam VAR6 = 0;
localparam [5:0] VAR40 = (6'd1 << VAR6);
localparam [31:0] VAR10 = (32'd1 << (7 - VAR6)) + 32'd1;
reg [255:0] state = 0;
reg [511:0] VAR9 = 0;
reg [31:0] VAR14 = 32'h00000000;
wire VAR41;
VAR52 # (
.VAR30 (VAR43),
.VAR48 (VAR29),
.VAR18 (VAR31... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31ai/sky130_fd_sc_ms__o31ai_4.v | 2,335 | module MODULE2 (
VAR11 ,
VAR6 ,
VAR4 ,
VAR7 ,
VAR2 ,
VAR9,
VAR1,
VAR8 ,
VAR10
);
output VAR11 ;
input VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR9;
input VAR1;
input VAR8 ;
input VAR10 ;
VAR3 VAR5 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VA... | apache-2.0 |
sirchuckalot/zet-ng | rtl/zet_front_prefetch_umi.v | 2,953 | module MODULE1 (
input clk,
input rst,
output [19:0] VAR12,
input [15:0] VAR11,
output reg VAR9,
output VAR4,
input VAR8,
input VAR7,
input VAR5,
input [15:0] VAR6,
input [15:0] VAR3,
output reg [15:0] VAR15,
output reg [15:0] VAR10,
output reg [15:0] VAR14,
output reg VAR13,
input VAR2
);
wire VAR1;
assign VAR1 = VAR7... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_006bits.v | 1,917 | module MODULE1 (
clk,
VAR21, VAR23, VAR12, VAR26, VAR22, VAR29, VAR17, VAR13,
sum,
);
input clk;
input [VAR19+0-1:0] VAR21, VAR23, VAR12, VAR26, VAR22, VAR29, VAR17, VAR13;
output [VAR19 :0] sum;
reg [VAR19 :0] sum;
wire [VAR19+3-1:0] VAR6;
wire [VAR19+2-1:0] VAR27, VAR2;
wire [VAR19+1-1:0] VAR32, VAR7, VAR34, VAR11;
r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi.functional.v | 1,626 | module MODULE1 (
VAR5 ,
VAR8,
VAR9,
VAR12 ,
VAR3
);
output VAR5 ;
input VAR8;
input VAR9;
input VAR12 ;
input VAR3 ;
wire VAR11 ;
wire VAR6 ;
wire VAR7;
and VAR10 (VAR11 , VAR12, VAR3 );
nor VAR4 (VAR6 , VAR8, VAR9 );
nor VAR2 (VAR7, VAR6, VAR11);
buf VAR1 (VAR5 , VAR7 );
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ethmac/eth_txethmac.v | 17,144 | module MODULE1 (VAR75, VAR90, VAR30, VAR84, VAR37, VAR88, VAR79,
VAR34, VAR51, VAR35, VAR94, VAR85, VAR12, VAR50, VAR15, VAR13,
VAR62, VAR8, VAR46, VAR49, VAR33, VAR17,
VAR61, VAR19, VAR2, VAR9, VAR48, VAR28, VAR45, VAR56,
VAR1, VAR83, VAR66, VAR14, VAR93,
VAR77, VAR82, VAR57, VAR63
);
parameter VAR18 = 1;
input VAR75;... | mit |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_linescanner_image_capture_unit_0_1/synth/image_processing_2d_design_linescanner_image_capture_unit_0_1.v | 4,093 | module MODULE1 (
enable,
VAR8,
VAR11,
VAR6,
VAR14,
VAR4,
VAR3,
VAR1,
VAR10,
VAR13,
VAR12,
VAR15,
VAR2,
VAR9
);
input wire enable;
input wire [7 : 0] VAR8;
output wire VAR11;
output wire VAR6;
output wire VAR14;
input wire VAR4;
input wire VAR3;
input wire VAR1;
input wire VAR10;
output wire VAR13;
input wire VAR12;
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv.functional.v | 1,671 | module MODULE1 (
VAR2,
VAR5,
VAR8 ,
VAR4
);
input VAR2;
input VAR5;
output VAR8 ;
input VAR4 ;
wire VAR6 ;
wire VAR3;
not VAR10 (VAR6 , VAR4 );
VAR7 VAR9 (VAR3, VAR6, VAR2, VAR5);
buf VAR1 (VAR8 , VAR3 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/src_coregen/lpm_mult.v | 225,194 | module MODULE1 (
VAR133, VAR50, clk, VAR21, VAR119, VAR20
);
input VAR133;
input VAR50;
input clk;
input [32 : 0] VAR21;
input [32 : 0] VAR119;
output [65 : 0] VAR20;
wire \VAR43/VAR145/VAR74.VAR92/VAR77.VAR153.VAR10.VAR62/VAR144[0] ;
wire \VAR43/VAR145/VAR74.VAR92/VAR77.VAR153.VAR10.VAR62/VAR144[1] ;
wire \VAR43/VAR14... | mit |
solowandererY2K/FPGA-Quantum-Compiler | src/gate_rom_bb.v | 5,234 | module MODULE1 (
address,
VAR2,
VAR1);
input [7:0] address;
input VAR2;
output [39:0] VAR1;
tri1 VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp.pp.blackbox.v | 1,375 | module MODULE1 (
VAR3,
VAR1 ,
VAR2 ,
VAR4 ,
VAR6 ,
VAR7 ,
VAR5
);
input VAR3;
input VAR1 ;
input VAR2 ;
output VAR4 ;
output VAR6 ;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux2/sky130_fd_sc_hvl__mux2.behavioral.pp.v | 1,912 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR11,
VAR4,
VAR3 ,
VAR13
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR11;
input VAR4;
input VAR3 ;
input VAR13 ;
wire VAR15 ;
wire VAR10;
VAR12 VAR14 (VAR15 , VAR1, VAR6, VAR7 );
VAR2 VAR5 (VAR10, VAR15, VAR11, VAR4);
buf VAR8 (VAR9 , VAR10 );
endmodule | apache-2.0 |
aabdelfattah/alhaitham-hardware | Sdram_Control/Sdram_Control.v | 16,911 | module MODULE1 (
VAR141,
VAR27,
VAR11,
VAR93,
VAR140,
VAR109,
VAR118,
VAR136,
VAR2,
VAR121,
VAR68,
VAR52,
VAR76,
VAR99,
VAR45,
VAR14,
VAR17,
VAR57,
VAR84,
VAR6,
VAR88,
VAR105,
VAR19,
VAR106,
VAR69,
VAR113,
VAR70,
VAR61,
VAR87,
VAR56,
VAR111,
VAR96,
VAR107,
VAR31,
VAR127,
VAR102,
VAR95,
VAR100,
VAR13,
VAR58
);
input VAR... | gpl-3.0 |
mballance/oc_wb_ip | rtl/wb_uart/uart_transmitter.v | 12,443 | module MODULE1 (clk, VAR12, VAR41, VAR29, VAR36, enable, VAR6, VAR15, VAR21, VAR10, VAR3);
input clk;
input VAR12;
input [7:0] VAR41;
input VAR29;
input [7:0] VAR36;
input enable;
input VAR10;
input VAR3; output VAR6;
output [2:0] VAR15;
output [VAR16-1:0] VAR21;
reg [2:0] VAR15;
reg [4:0] counter;
reg [2:0] VAR27; reg... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3.functional.pp.v | 1,768 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR9,
VAR2
);
output VAR8 ;
input VAR10 ;
input VAR9;
input VAR2;
wire VAR5 ;
wire VAR1;
not VAR6 (VAR5 , VAR10 );
VAR4 VAR3 (VAR1, VAR5, VAR9, VAR2);
buf VAR7 (VAR8 , VAR1 );
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/six_three_comp.v | 2,835 | module MODULE1 (VAR1,sum);
input [5:0] VAR1;
output [2:0] sum;
reg [2:0] sum ;
always @(VAR1) begin
case (VAR1)
0: sum=0;
1: sum=1;
2: sum=1;
3: sum=2;
4: sum=1;
5: sum=2;
6: sum=2;
7: sum=3;
8: sum=1;
9: sum=2;
10: sum=2;
11: sum=3;
12: sum=2;
13: sum=3;
14: sum=3;
15: sum=4;
16: sum=1;
17: sum=2;
18: sum=2;
19: sum=3... | mit |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/fifo_w32_d3_A.v | 2,988 | module MODULE2 (
clk,
VAR7,
VAR20,
VAR4,
VAR27);
parameter VAR9 = 32'd32;
parameter VAR17 = 32'd2;
parameter VAR23 = 3'd3;
input clk;
input [VAR9-1:0] VAR7;
input VAR20;
input [VAR17-1:0] VAR4;
output [VAR9-1:0] VAR27;
reg[VAR9-1:0] VAR13 [0:VAR23-1];
integer VAR14;
always @ (posedge clk)
begin
if (VAR20)
begin
for (VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a.blackbox.v | 1,356 | module MODULE1 (
VAR4 ,
VAR8,
VAR3,
VAR5,
VAR7
);
output VAR4 ;
input VAR8;
input VAR3;
input VAR5;
input VAR7;
supply1 VAR1;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_ctrl.v | 26,978 | module MODULE1(
clk, rst,
VAR78, VAR54, VAR94, VAR28, VAR37, VAR77, VAR38, VAR57,
VAR20, VAR42, VAR63, VAR17, VAR4, VAR16, VAR1, VAR81, VAR35, VAR72,
VAR47, VAR11, VAR105, VAR14, VAR21, VAR44, VAR23,
VAR80, VAR70,
VAR30, VAR10, VAR65, VAR22, VAR2, VAR41,
VAR104, VAR89, VAR100, VAR90, VAR12, VAR43
);
input clk;
input rs... | gpl-3.0 |
ehab93/MIPS-Processor | ALU/alu.v | 4,090 | module MODULE1 (
input [3:0] VAR40,
input signed [31:0] VAR13, VAR7,
output signed [31:0] VAR18,
output VAR25);
wire VAR16;
wire [30:0] VAR21;
VAR10 VAR39 (.VAR40(VAR40), .VAR29(VAR18[0 ]), .VAR13(VAR13[0 ]), .VAR7(VAR7[0 ]), .VAR19(1'b0 ), .VAR23(VAR21[0 ]), .VAR37(VAR16 ));
VAR10 VAR3 (.VAR40(VAR40), .VAR29(VAR18[1 ]... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/host_interface/pcie_ingress.v | 19,437 | module MODULE1 (
input clk,
input rst,
output reg VAR99,
input [31:0] VAR40,
input [3:0] VAR31,
input VAR15,
input VAR28,
output reg [31:0] VAR45,
output reg [31:0] VAR81,
output reg [31:0] VAR103,
output reg [31:0] VAR42,
output reg [31:0] VAR60,
output reg [31:0] VAR17,
output reg [31:0] VAR27,
output reg VAR53,
outp... | mit |
walkthetalk/fsref | ip/heater/src/heater.v | 3,007 | module MODULE1 # (
parameter integer VAR18 = 12,
parameter integer VAR5 = 32
) (
input wire clk,
input wire VAR27,
input wire VAR28,
output wire VAR2,
output wire en,
output wire VAR21,
input wire [15:0] VAR9,
input wire [4:0] VAR14,
output wire VAR10,
input wire VAR16,
output wire [2-1 :0] VAR26,
output wire [VAR18-1:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.pp.blackbox.v | 1,359 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR1 ,
VAR4 ,
VAR3,
VAR8,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR3;
input VAR8;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_pm.v | 7,468 | module MODULE1(
clk, rst, VAR10, VAR22, VAR30, VAR21, VAR14,
VAR23, VAR9, VAR18, VAR7, VAR2,
VAR5, VAR19, VAR4, VAR13, VAR8
);
input clk; input rst; input VAR10; input VAR22; input [31:0] VAR30; input [31:0] VAR21; output [31:0] VAR14;
input VAR9; output [3:0] VAR23; output VAR18; output VAR7; output VAR2; output VAR5;... | mit |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_fifo_byte_async.v | 2,258 | module MODULE1
(
input VAR20,
input VAR13,
input VAR4,
input [7:0] din,
input VAR17,
output VAR15,
output [7:0] dout,
input VAR12,
output VAR18
);
reg [1:0] VAR7;
reg [3:0] VAR11;
reg [3:0] VAR19;
reg [3:0] VAR5;
reg [1:0] VAR6;
reg [3:0] VAR8;
reg [3:0] VAR9;
reg [3:0] VAR3;
always @ (posedge VAR13)
VAR7 <= VAR6;
alwa... | mit |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/System_Control_Unit.v | 6,309 | module MODULE1
(
input wire VAR4, input wire VAR22, input wire [7:0] VAR6,
output wire VAR8, output wire VAR21, output wire VAR13,
output wire [3:0] VAR19,
output wire VAR26 );
parameter integer VAR14 = 100;
parameter integer VAR10 = 10;
parameter integer VAR16 = VAR1(VAR14);
parameter VAR29 = 1'b1;
parameter VAR20 = 1... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_logic_op.v | 2,690 | module MODULE1 (
VAR1,
VAR3,
VAR5,
VAR6
);
input [VAR7] VAR1;
input [VAR2] VAR3;
input [VAR2] VAR5;
output [VAR2] VAR6;
reg [VAR2] VAR6;
integer VAR8;
always @(*)
begin
for(VAR8 = 0; VAR8 < VAR4; VAR8 = VAR8 + 1)
VAR6[VAR8] = VAR1[{VAR5[VAR8], VAR3[VAR8]}];
end
endmodule | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gclk_inv_192x.v | 1,296 | module MODULE1 (
VAR2,
VAR1 );
output VAR2;
input VAR1;
assign VAR2 = ~( VAR1 );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o_4.v | 2,437 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR10 ,
VAR11 ,
VAR5 ,
VAR2 ,
VAR7,
VAR4,
VAR1 ,
VAR12
);
output VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR11 ;
input VAR5 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR1 ;
input VAR12 ;
VAR6 VAR9 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7... | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/bless_age/arbitor.v | 8,866 | module MODULE2 (
input VAR47 VAR58,
input VAR47 VAR50,
input VAR47 VAR13,
input VAR47 VAR24,
input VAR47 VAR45,
input VAR21 VAR30,
input VAR21 VAR38,
input VAR21 VAR48,
input VAR21 VAR20,
input VAR21 VAR28,
input clk,
output reg VAR25 VAR41,
output VAR25 VAR6);
wire [1:0] VAR46, VAR36, VAR19, VAR33;
VAR4 VAR7(.VAR37(VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.functional.v | 1,440 | module MODULE1 (
VAR6 ,
VAR3,
VAR7 ,
VAR1 ,
VAR4
);
output VAR6 ;
input VAR3;
input VAR7 ;
input VAR1 ;
input VAR4 ;
wire VAR10 ;
wire VAR2;
not VAR5 (VAR10 , VAR3 );
nand VAR8 (VAR2, VAR4, VAR1, VAR7, VAR10);
buf VAR9 (VAR6 , VAR2 );
endmodule | apache-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/rfa/rfa.v | 3,983 | module MODULE1(
VAR15, VAR14,
VAR21, VAR26,
VAR11, VAR35,
VAR27, VAR24,
VAR38,
VAR37, clk, rst, VAR13, VAR29,
VAR12, VAR19,
VAR34, VAR9,
VAR28, VAR20, VAR32,
VAR8
);
input clk;
input rst;
input VAR8;
output VAR37;
input VAR13, VAR29, VAR12,
VAR19, VAR34, VAR9,
VAR28, VAR20, VAR32;
output VAR15, VAR14, VAR21,
VAR26, VAR... | bsd-3-clause |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/out_skew_dcm.v | 6,620 | module MODULE1
( input VAR12,
input VAR32,
output VAR24,
output VAR52,
input VAR36,
output VAR4
);
assign VAR13 = VAR12;
wire VAR27;
wire VAR6;
VAR46 VAR54
(.VAR15 (VAR27),
.VAR29 (VAR32));
VAR7 #(.VAR22("VAR26")) VAR49
(.VAR15(VAR6),
.VAR29(VAR27));
wire VAR23;
wire VAR48;
wire [7:0] VAR11;
wire VAR28;
wire VAR3;
VAR1... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out.v | 2,489 | module MODULE1 #(parameter VAR9(VAR21)
, parameter VAR9(VAR15)
, parameter VAR7 = VAR15)
(input VAR1
, input VAR25
, input VAR22
, input [VAR21-1:0] VAR11
, output VAR20
, output logic [VAR7-1:0] VAR2
, output logic [VAR7-1:0][VAR21-1:0] VAR10
, input [VAR16(VAR7+1)-1:0] VAR8
);
localparam VAR24 = VAR15 * 2;
logic [VAR... | bsd-3-clause |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/oq_regs_ctrl.v | 35,161 | module MODULE1
parameter VAR59 = 13,
parameter VAR112 = 8,
parameter VAR6 = 8,
parameter VAR48 = VAR87(VAR6),
parameter VAR134 = 17,
parameter VAR75 = VAR87(VAR134),
parameter VAR13 = 2048/VAR112, parameter VAR116 = 60/VAR112 + 1,
parameter VAR34 = VAR87((2**VAR59)/VAR116),
parameter VAR105 = 11,
parameter VAR5 = VAR10... | apache-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_stub.v | 2,436 | module MODULE1(VAR1, VAR17, VAR13, VAR15, VAR7, VAR8, VAR4, VAR5, VAR19, VAR18, VAR6, VAR12, VAR16, VAR3, VAR2, VAR11, VAR10, VAR9, VAR14)
;
input VAR1;
input [7:0]VAR17;
input VAR13;
output VAR15;
input [31:0]VAR7;
input VAR8;
output VAR4;
input VAR5;
output [63:0]VAR19;
output [15:0]VAR18;
output VAR6;
input VAR12;
o... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o.blackbox.v | 1,346 | module MODULE1 (
VAR5 ,
VAR7,
VAR4,
VAR8,
VAR2,
VAR6
);
output VAR5 ;
input VAR7;
input VAR4;
input VAR8;
input VAR2;
input VAR6;
supply1 VAR3;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.symbol.v | 1,408 | module MODULE1 (
input VAR2 ,
output VAR4 ,
input VAR1,
input VAR5 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.v | 2,395 | module MODULE2 (
VAR10 ,
VAR2 ,
VAR11 ,
VAR4,
VAR6 ,
VAR1 ,
VAR8 ,
VAR5 ,
VAR7
);
output VAR10 ;
input VAR2 ;
input VAR11 ;
input VAR4;
input VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
VAR3 VAR9 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b.behavioral.v | 1,442 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR1;
supply1 VAR6;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR11 ;
wire VAR8;
not VAR9 (VAR11 , VAR1 );
or VAR12 (VAR8, VAR11, VAR4 );
buf VAR5 (VAR3 , VAR8 );
endmodule | apache-2.0 |
BoulaZa5/32bit-alu | alu.v | 4,307 | module MODULE2 (input signed [31:0] VAR4, input signed [31:0] VAR1, input [3:0] VAR5, input [4:0] VAR3, output signed [31:0] VAR2);
assign VAR2 = VAR5 == 0 ? VAR4 + VAR1 :
VAR5 == 1 ? VAR4 - VAR1 :
VAR5 == 2 ? VAR4 & VAR1 :
VAR5 == 3 ? VAR4 | VAR1 :
VAR5 == 4 ? VAR4 << VAR3 :
VAR5 == 5 ? VAR4 >> VAR3 :
VAR5 == 6 ? VAR4... | unlicense |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/verif/mesh_3x3/flit_sink.v | 7,257 | module MODULE1
(clk, reset, VAR42, VAR41, VAR87);
parameter VAR43 = 0;
parameter VAR92 = 50;
parameter VAR40 = 64;
parameter VAR18 = 8;
localparam VAR74 = VAR30(VAR18);
localparam VAR16 = VAR40 / VAR18;
localparam VAR8 = VAR30(VAR16 + 1);
parameter VAR82 = VAR25;
parameter VAR38 = VAR67;
localparam VAR32
= (VAR38 == VA... | gpl-2.0 |
olajep/oh | src/pic/dv/dut_pic.v | 3,617 | module MODULE1(
VAR23, VAR39, VAR20, VAR12, VAR38,
VAR34, VAR30, VAR15, VAR11, VAR1, VAR19, VAR26, VAR31,
VAR28, VAR25
);
parameter VAR4 = 32;
parameter VAR48 = 12'h810;
parameter VAR43 = 12;
parameter VAR36 = 6;
parameter VAR5 = 2*VAR4 + 40;
parameter VAR33 = 1;
parameter VAR29 = 10;
input VAR15;
input VAR11;
input VA... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_bridge_v1_06_a/hdl/verilog/radio_bridge.v | 7,250 | module MODULE1
(
VAR32,
VAR34,
VAR76,
VAR14,
VAR40,
VAR52,
VAR67,
VAR21,
VAR45,
VAR58,
VAR2,
VAR43,
VAR22,
VAR55,
VAR42,
VAR84,
VAR48,
VAR26,
VAR74,
VAR38,
VAR47,
VAR3,
VAR85,
VAR28,
VAR39,
VAR16,
VAR23,
VAR64,
VAR78,
VAR69,
VAR9,
VAR6,
VAR8,
VAR10,
VAR44,
VAR19,
VAR80,
VAR66,
VAR81,
VAR29,
VAR79,
VAR31,
VAR62,
VAR50,
... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp_1.v | 2,459 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR4 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR2,
VAR3,
VAR12 ,
VAR10
);
output VAR11 ;
output VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR2;
input VAR3;
input VAR12 ;
input VAR10 ;
VAR8 VAR6 (
.VAR11(VAR11),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai_2.v | 2,361 | module MODULE2 (
VAR2 ,
VAR10 ,
VAR9 ,
VAR4 ,
VAR3 ,
VAR1,
VAR7,
VAR5 ,
VAR11
);
output VAR2 ;
input VAR10 ;
input VAR9 ;
input VAR4 ;
input VAR3 ;
input VAR1;
input VAR7;
input VAR5 ;
input VAR11 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VA... | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_spram_1024x8.v | 10,300 | module MODULE1(
VAR28, VAR17, VAR27,
clk, rst, VAR31, VAR7, VAR15, addr, VAR3, VAR38
);
parameter VAR5 = 10;
parameter VAR21 = 8;
input VAR28;
input [VAR11 - 1:0] VAR27;
output VAR17;
input clk; input rst; input VAR31; input VAR7; input VAR15; input [VAR5-1:0] addr; input [VAR21-1:0] VAR3; output [VAR21-1:0] VAR38;
ass... | gpl-2.0 |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ipshared/8c13/hdl/verilog/processing_system7_v5_5_trace_buffer.v | 8,668 | module MODULE1 #
(
parameter integer VAR31 = 128,
parameter integer VAR3 = 0,
parameter integer VAR19 = 12
)
(
input wire VAR13,
input wire VAR18,
input wire VAR1,
input wire [3:0] VAR8,
input wire [31:0] VAR22,
output wire VAR6,
output wire [3:0] VAR30,
output wire [31:0] VAR9
);
function integer VAR16 (input integer ... | mit |
CeesWolfs/ceespu | src/gpu/ceespu_gpu.v | 2,946 | module MODULE1(
input VAR17,
input VAR2,
input [3:0] VAR28,
input [24:0] VAR14,
input [31:0] VAR32,
input [9:0] VAR36,
input [8:0] VAR15,
output [7:0] VAR18,
output [7:0] VAR39,
output [7:0] VAR21
);
wire [6:0] VAR10; wire [4:0] VAR35; wire [11:0] VAR33;
wire [7:0] VAR3;
reg [2:0] VAR26; reg [3:0] VAR27; wire [13:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i.functional.pp.v | 1,934 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR7 ,
VAR14 ,
VAR9,
VAR3,
VAR4 ,
VAR15
);
output VAR1 ;
input VAR10 ;
input VAR7 ;
input VAR14 ;
input VAR9;
input VAR3;
input VAR4 ;
input VAR15 ;
wire VAR12;
wire VAR2;
VAR11 VAR6 (VAR12, VAR10, VAR7, VAR14 );
VAR13 VAR8 (VAR2, VAR12, VAR9, VAR3);
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s.pp.symbol.v | 1,358 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR2 ,
input VAR1,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
LordRafa/Sobel-FPGA | Project_With_Cache/ip/SIS/AGrises.v | 2,435 | module MODULE1 (
input clk,
input rst,
output [VAR16-1:0] VAR8,
output VAR11,
input wire [VAR9:0] VAR3,
input wire [VAR16-1:0] VAR2,
output VAR5,
input wire [VAR9:0] VAR1,
input VAR15,
output VAR6
);
parameter VAR16=32;
parameter VAR12 = 256;
parameter VAR9 = 8;
reg [1:0] VAR4;
wire VAR7;
reg [1:0] VAR13;
reg [14:0] VA... | gpl-2.0 |
masc-ucsc/cmpe220fall16 | rtl/DC_1_databank.v | 3,163 | module MODULE1 #(parameter VAR21 = 36, VAR9 =512, VAR29=0)
( input clk
,input reset
,input VAR36
,input VAR13
,output VAR34
,input write
,input[2:0] VAR5
,input VAR23
,input [4:0] VAR27,input [35:0] VAR24,input [4:0] VAR7
,input VAR31
,output VAR10
,input [6:0] VAR14
,input VAR2
,output VAR25
,input VAR32
,output VAR22... | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T10-shif-register/shift4.v | 1,300 | module MODULE1(input wire clk, output reg [3:0] VAR11);
parameter VAR7 = 21; parameter VAR6 = 1;
wire VAR10;
reg VAR5 = 0;
wire VAR3;
VAR8 #(.VAR4(VAR7))
VAR9 (
.VAR2(clk),
.VAR1(VAR10)
);
always @(posedge(VAR10)) begin
VAR5 <= 1;
end
always @(posedge(VAR10)) begin
if (VAR5 == 0) VAR11 <= VAR6;
end
else
VAR11 <= {VAR11... | gpl-2.0 |
takeshineshiro/fpga_linear_128 | HW_SW_bb.v | 5,069 | module MODULE1 (
address,
VAR2,
VAR1);
input [7:0] address;
input VAR2;
output [127:0] VAR1;
endmodule | mit |
monotone-RK/FACE | IEICE-Trans/16-way/src/riffa/pipeline.v | 9,798 | module MODULE1
parameter VAR11 = 10,
parameter VAR6 = 10,
parameter VAR7 = 1
)
(
input VAR18,
input VAR14,
input [VAR6-1:0] VAR27,
input VAR32,
output VAR31,
output [VAR6-1:0] VAR17,
output VAR26,
input VAR13
);
generate
if (VAR7 & VAR11 > 2) begin
MODULE3
.VAR12 (1),
.VAR4 (1),
.VAR11 (VAR11),
.VAR6 (VAR6))
VAR8
(
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp.functional.pp.v | 1,947 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR14 ,
VAR1 ,
VAR13 ,
VAR4,
VAR2,
VAR11 ,
VAR6
);
output VAR12 ;
input VAR7 ;
input VAR14 ;
input VAR1 ;
input VAR13 ;
input VAR4;
input VAR2;
input VAR11 ;
input VAR6 ;
wire VAR16 ;
wire VAR3;
VAR10 VAR9 (VAR3, VAR14, VAR1, VAR13 );
VAR17 VAR8 VAR15 (VAR16 , VAR3, VAR7, , VAR4, VAR2);
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd/sky130_fd_sc_lp__tapvgnd.symbol.v | 1,269 | module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/MySource/ads62p44_spi.v | 2,966 | module MODULE1(
output reg VAR9,
output reg VAR2,
input rst,
input clk,
output reg VAR4,
input [2:0] VAR6
);
wire [6:0] VAR1=7'd12;function [15:0] VAR7;
input [5:0] addr;
begin
case(addr) 6'd0 :VAR7 = {8'h00,6'd0,1'b1,1'b1}; 6'd1 :VAR7 = {8'h10,2'b00,6'd0}; 6'd2 :VAR7 = {8'h11,2'd0,2'd0,2'd0,2'd0}; 6'd3 :VAR7 = {8'h12,... | gpl-2.0 |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_auto_pc_0/synth/triangle_intersect_auto_pc_0.v | 13,171 | module MODULE1 (
VAR54,
VAR12,
VAR23,
VAR53,
VAR82,
VAR33,
VAR15,
VAR68,
VAR60,
VAR65,
VAR95,
VAR67,
VAR74,
VAR76,
VAR109,
VAR98,
VAR64,
VAR22,
VAR104,
VAR26,
VAR3,
VAR41,
VAR96,
VAR37,
VAR42,
VAR1,
VAR28,
VAR79,
VAR39,
VAR110,
VAR106,
VAR93,
VAR4,
VAR29,
VAR45,
VAR14,
VAR7,
VAR16,
VAR113,
VAR108,
VAR25,
VAR2,
VAR70,
V... | mit |
cpulabs/mist1032sa | src/core/l1_data/l1_data_cache.v | 14,834 | module MODULE1(
input wire VAR41,
input wire VAR94,
input wire VAR102,
input wire VAR18,
input wire VAR103,
input wire [31:0] VAR69,
input wire VAR95,
output wire VAR4,
input wire [1:0] VAR6,
input wire [3:0] VAR3,
input wire VAR91,
input wire [31:0] VAR82,
input wire [1:0] VAR75,
input wire [31:0] VAR83,
input wire [3... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.v | 2,154 | module MODULE1 (
VAR6,
VAR9,
VAR3 ,
VAR1,
VAR7,
VAR5 ,
VAR8
);
output VAR6;
input VAR9;
input VAR3 ;
input VAR1;
input VAR7;
input VAR5 ;
input VAR8 ;
VAR2 VAR4 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR6,
VAR9,
VAR3
);
output VAR6;
inpu... | apache-2.0 |
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