repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s.blackbox.v | 1,288 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR3;
supply0 VAR1;
endmodule | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/icache.v | 2,217 | module MODULE1(
input clk
,input reset
,input VAR13
,output VAR6
,input VAR30 VAR21
,output VAR20
,input VAR7
,output VAR5 VAR29
,input VAR26
,output VAR4
,input VAR28 VAR34
,input VAR23
,output VAR19
,input VAR3 VAR9
,output VAR31 VAR8
,output VAR33
,input VAR24
,output VAR18 VAR14
,output VAR25
,input VAR11
,output V... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9739a/axi_ad9739a_channel.v | 23,675 | module MODULE1 (
VAR6,
VAR68,
VAR103,
VAR16,
VAR48,
VAR45,
VAR135,
VAR38,
VAR13,
VAR2,
VAR46,
VAR47,
VAR98,
VAR114,
VAR31,
VAR26,
VAR120,
VAR91,
VAR122,
VAR107,
VAR96,
VAR30,
VAR133,
VAR83,
VAR126,
VAR69,
VAR128,
VAR94,
VAR109,
VAR100,
VAR34,
VAR40);
parameter VAR4 = 32'h0;
parameter VAR99 = 0;
input VAR6;
input VAR68;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.symbol.v | 1,538 | module MODULE1 (
input VAR6 ,
output VAR5 ,
output VAR10 ,
input VAR8,
input VAR1 ,
input VAR11 ,
input VAR9
);
supply1 VAR2;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlclkp/sky130_fd_sc_hd__dlclkp.functional.pp.v | 1,730 | module MODULE1 (
VAR8,
VAR2,
VAR9 ,
VAR12,
VAR7,
VAR3 ,
VAR6
);
output VAR8;
input VAR2;
input VAR9 ;
input VAR12;
input VAR7;
input VAR3 ;
input VAR6 ;
wire VAR11 ;
wire VAR1;
not VAR4 (VAR1 , VAR9 );
VAR10 VAR5 (VAR11 , VAR2, VAR1, , VAR12, VAR7);
and VAR13 (VAR8 , VAR11, VAR9 );
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/ALUNeuronalNetwork.v | 3,698 | module MODULE1 #(parameter VAR49 = 4, VAR6 = 2, VAR22 = 1, VAR26 = 1)
(VAR14,reset,VAR28, VAR38,VAR39,VAR42,VAR13,VAR2,VAR18,VAR43,VAR12,VAR16,VAR36,VAR9,
VAR8,VAR51,VAR5,VAR37,VAR11,VAR27,VAR1,VAR20,VAR35,VAR48,VAR3,VAR32,VAR50,
VAR4,VAR15,VAR7,VAR17);
input VAR14, reset, VAR28,VAR38,VAR39;
input [4:0] VAR2;
input sig... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrtp/sky130_fd_sc_hvl__dfrtp.pp.symbol.v | 1,406 | module MODULE1 (
input VAR8 ,
output VAR6 ,
input VAR2,
input VAR7 ,
input VAR5 ,
input VAR1 ,
input VAR3 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi_lp.v | 2,465 | module MODULE2 (
VAR1 ,
VAR5 ,
VAR6 ,
VAR11 ,
VAR8 ,
VAR4 ,
VAR12,
VAR2,
VAR3 ,
VAR9
);
output VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR11 ;
input VAR8 ;
input VAR4 ;
input VAR12;
input VAR2;
input VAR3 ;
input VAR9 ;
VAR7 VAR10 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR12(V... | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/Logica_Bola.v | 2,350 | module MODULE1(
input VAR4,
input reset,
input VAR3,
input VAR1,
input VAR6,
output reg [9:0] VAR2,
output reg [8:0] VAR8 );
reg VAR5;
reg VAR7;
begin
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/NVMeHostController_v2_0_0/ba7abda2/src/pcie_tx_dma.v | 5,352 | module MODULE1 # (
parameter VAR16 = 128,
parameter VAR52 = 36,
parameter VAR34 = 64
)
(
input VAR6,
input VAR33,
input [2:0] VAR28,
input VAR53,
input [33:0] VAR7,
output VAR58,
output VAR54,
output [7:0] VAR38,
output [11:2] VAR60,
output [VAR52-1:2] VAR46,
input VAR40,
input VAR12,
input VAR25,
output [VAR16-1:0] VA... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/hif_sm.v | 6,196 | module MODULE1
(
input VAR32,
input VAR19, input VAR12,
input VAR34, input VAR18, input VAR30, input VAR20, input VAR21, input VAR13, input VAR28, input VAR17, input VAR31, input VAR29,
output VAR26, output VAR35, output VAR2, output reg VAR25,
output VAR4,
output VAR1,
output VAR9
);
parameter VAR10 = 2'b00,
VAR22 = 2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi_2.v | 2,134 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR5 ,
VAR7 ,
VAR4,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR6;
VAR3 VAR8 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR1 ,
VAR2,
VAR5,
VAR7
);
output VAR1 ;
input VAR2;
input VAR5;
... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/mult.v | 26,744 | module MODULE1
(
VAR64,
VAR24,
VAR70,
VAR62,
VAR58,
VAR12,
VAR48) ;
input VAR64;
input [31:0] VAR24;
input [31:0] VAR70;
output VAR62;
output VAR58;
output [31:0] VAR12;
output VAR48;
reg VAR35;
reg VAR3;
reg VAR29;
reg VAR28;
reg VAR26;
reg VAR27;
reg VAR17;
reg VAR6;
reg [9:0] VAR39;
reg [9:0] VAR15;
reg VAR51;
reg V... | apache-2.0 |
efabless/openlane | designs/151/src/backup_mem.v | 3,276 | (VAR2) > 2**30 ? 31 : \
(VAR2) > 2**29 ? 30 : \
(VAR2) > 2**28 ? 29 : \
(VAR2) > 2**27 ? 28 : \
(VAR2) > 2**26 ? 27 : \
(VAR2) > 2**25 ? 26 : \
(VAR2) > 2**24 ? 25 : \
(VAR2) > 2**23 ? 24 : \
(VAR2) > 2**22 ? 23 : \
(VAR2) > 2**21 ? 22 : \
(VAR2) > 2**20 ? 21 : \
(VAR2) > 2**19 ? 20 : \
(VAR2) > 2**18 ? 19 : \
(VAR2) >... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/6d8f288943408fbb/zynq_design_1_rst_ps7_0_100M_0_stub.v | 1,880 | module MODULE1(VAR8, VAR4, VAR9,
VAR3, VAR2, VAR10, VAR7, VAR5,
VAR1, VAR6)
;
input VAR8;
input VAR4;
input VAR9;
input VAR3;
input VAR2;
output VAR10;
output [0:0]VAR7;
output [0:0]VAR5;
output [0:0]VAR1;
output [0:0]VAR6;
endmodule | mit |
bbrown1867/ObjectTracking | hw/common/measure_position.v | 3,207 | module MODULE1 #(
parameter VAR5 = 11,
parameter VAR1 = 10,
parameter VAR10 = 640,
parameter VAR6 = 480,
parameter VAR17 = 40
)( input clk,
input wire [(VAR5-1):0] VAR18,
input wire [(VAR5-1):0] VAR16,
input wire [(VAR1-1):0] VAR7,
output wire [(VAR5-1):0] VAR4,
output wire [(VAR5-1):0] VAR8,
output wire VAR9,
input wi... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.behavioral.pp.v | 1,182 | module MODULE1( VAR6, VAR5, VAR2, VAR7 );
input VAR6;
inout VAR2, VAR7;
output VAR5;
VAR3 VAR1(.VAR6(VAR6),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7));
VAR3 VAR4(.VAR6(VAR6),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/hps_sdram_p0_acv_ldc.v | 3,407 | module MODULE1
(
VAR36,
VAR23,
VAR28,
VAR22,
VAR11,
VAR18,
VAR13,
VAR10,
VAR3
);
parameter VAR25 = "";
parameter VAR35 = 0;
parameter VAR26 = "false";
parameter VAR32 = "false";
input VAR36;
input VAR23;
input VAR28;
input [VAR25-1:0] VAR22;
output VAR11;
output VAR18;
output VAR13;
output VAR10;
output VAR3;
wire VAR2... | mit |
cpulabs/mist1032isa | src/core/execute/execute_logic_decoder.v | 1,585 | module MODULE1(
input wire [4:0] VAR1,
output wire [4:0] VAR2
);
function [4:0] VAR3;
input [4:0] VAR4;
begin
case(VAR4)
default
begin
VAR3 = 5'h00;
end
endcase
end
endfunction
assign VAR2 = VAR3(VAR1);
endmodule | bsd-2-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_mto_slice.v | 2,639 | module MODULE1(
VAR9,
clk, VAR8, VAR14, VAR10
);
input clk;
input VAR8;
input VAR14;
input VAR10;
output VAR9;
wire VAR9;
wire VAR13;
wire timeout;
wire VAR6;
wire VAR7;
wire VAR4;
wire VAR1;
assign VAR4 = VAR14;
assign VAR6 = VAR10 | VAR13;
assign VAR1 = VAR14;
assign VAR7 = VAR13 & (VAR8 | timeout);
assign VAR9 = VAR... | gpl-2.0 |
richard42/CoCo3FPGA | PH2_CLK.v | 5,127 | module MODULE2
(
VAR1,
VAR16,
VAR7,
VAR20) ;
input [1:0] VAR1;
input VAR16;
input [3:0] VAR7;
output VAR20;
tri0 [1:0] VAR1;
tri1 VAR16;
tri0 [3:0] VAR7;
wire VAR5;
wire [1:0] VAR21;
wire [3:0] VAR17;
VAR4 VAR10
(
.VAR1(VAR21),
.VAR16(VAR16),
.VAR7(VAR17),
.VAR20(VAR5)
,
.VAR18(1'b1),
.VAR8(1'b1)
);
VAR10.VAR13 = "VAR... | bsd-3-clause |
elegabriel/myzju | junior1/CA/LAB/lab1/single_cpu/reg32.v | 1,452 | module MODULE1(clk,rst,VAR11,VAR4,VAR9,VAR1,VAR7,VAR3,VAR10,VAR6,VAR13
);
input wire clk,rst,VAR11;
input wire [4:0] VAR4, VAR9,VAR1, VAR7;
input wire [31:0] VAR3;
output wire [31:0] VAR10, VAR6, VAR13;
reg [31:0] VAR5 [31:0];
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
VAR5[0] <=32'b0;VAR5[1] <=32'b0;VAR... | gpl-2.0 |
redfern314/RFIDuino | verilog/display_data.v | 4,009 | module MODULE1(
input clk,
input [15:0] VAR11,
output reg [3:0] VAR10,
output reg [7:0] VAR6
);
integer VAR5;
reg [1:0] state;
integer VAR4;
integer VAR7;
integer VAR8;
integer VAR2;
integer VAR9;
integer VAR12;
integer VAR3;
integer VAR1; | gpl-3.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/i2c/i2c_master_top.v | 10,141 | module MODULE1(
VAR14, VAR2, VAR43, VAR50, VAR38, VAR26,
VAR32, VAR39, VAR37, VAR13, VAR6,
VAR28, VAR52, VAR23, VAR40, VAR9, VAR15 );
parameter VAR1 = 1'b0;
input VAR14; input VAR2; input VAR43; input [2:0] VAR50; input [7:0] VAR38; output [7:0] VAR26; input VAR32; input VAR39; input VAR37; output VAR13; output VAR6;
r... | gpl-3.0 |
mashanz/FinalProject | Code/fpga/spartan3a/controller.v | 11,022 | module MODULE1(
VAR23, VAR45, VAR42, VAR16, VAR43, VAR56, VAR4, VAR17,
VAR49, VAR40, VAR25, VAR10, VAR32, VAR18, VAR54, VAR59,
VAR38, VAR6,
VAR47, VAR15, reset, VAR55, VAR9, VAR48, VAR53, VAR13, VAR19, VAR3
);
input VAR47, VAR15;
input reset;
input VAR55, VAR9, VAR48, VAR53, VAR13, VAR19;
input VAR3;
output reg VAR23;
... | gpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaF_dma2/common/mem512b.v | 1,463 | module MODULE1(
VAR6, VAR3,
VAR2, VAR5,
VAR4,
clk
);
input [8:0] VAR6;
input [8:0] VAR3;
input [7:0] VAR2;
output reg [7:0] VAR5;
input VAR4;
input clk;
reg [7:0] VAR1[0:511];
always @(posedge clk)
begin
VAR5 <= VAR1[VAR6];
if( VAR4 ) begin
VAR1[VAR3] <= VAR2;
end
end
endmodule | gpl-3.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/15bdd5a11717248e/design_1_xlconcat_0_0_stub.v | 1,316 | module MODULE1(VAR2, VAR1, dout)
;
input [0:0]VAR2;
input [0:0]VAR1;
output [1:0]dout;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2_2.v | 1,970 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR7 ,
VAR3,
VAR6
);
output VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR3;
input VAR6;
VAR4 VAR1 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR2,
VAR5,
VAR7
);
output VAR2;
input VAR5;
input VAR7;
supply1 VAR3;
supply0 VAR6;
VAR4 VAR1 (
.... | apache-2.0 |
jmesmon/trifles | verilog/barrel.v | 1,303 | module MODULE2
(input [VAR19-1:0] in,
input [VAR4(VAR19)-1:0] VAR9,
input VAR2,
input [1:0] type,
output [VAR19-1:0] out);
wire [VAR19-1:0] VAR7[VAR4(VAR19)-1:0], VAR12[VAR4(VAR19)-1:0], VAR17[VAR4(VAR19):0];
assign VAR17[0] = in;
assign out = VAR17[VAR4(VAR19)-1];
generate
genvar VAR16;
for(VAR16 = 0; VAR16 < VAR4(VAR... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_ifu_minidec.v | 3,136 | module MODULE1(
input [VAR27-1:0] VAR38,
output VAR35,
output VAR30,
output [VAR9-1:0] VAR19,
output [VAR9-1:0] VAR39,
output VAR6,
output VAR32 ,
output VAR41 ,
output VAR20 ,
output VAR13 ,
output VAR2 ,
output VAR14,
output VAR1,
output VAR31,
output VAR21,
output VAR7,
output [VAR9-1:0] VAR17,
output [VAR25-1:0] VA... | apache-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/controller.v | 1,772 | module MODULE1(
input wire clk,
input wire reset,
inout wire VAR27,
inout wire VAR25,
input wire [7:0] VAR10,
output wire [2:0] VAR19,
output wire [2:0] VAR7,
output wire [1:0] VAR24,
output wire VAR3,
output wire VAR2,
output wire [4:0] VAR15
);
wire VAR30;
wire [9:0] VAR4;
wire [8:0] VAR13;
wire VAR23;
wire [31:0] VA... | mit |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/ppu/n64a_vdemux.v | 4,022 | module MODULE1(
VAR1,
VAR3,
VAR9,
VAR20,
VAR11,
VAR5,
VAR7,
VAR10,
VAR12
);
input VAR1;
input VAR3;
input VAR9;
input [VAR19-1:0] VAR20;
input [ 2:0] VAR11;
output reg VAR5 = 1'b0;
output [VAR23] VAR7;
output reg VAR10 = 1'b0;
output reg [VAR6] VAR12 = {VAR13{1'b0}};
wire VAR14 = VAR11[ 2];
wire VAR15 = VAR11[ 1];
wire... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/BRAMPopControl.v | 3,808 | module MODULE1
(
parameter VAR15 = 8 ,
parameter VAR9 = 32
)
(
VAR3 ,
VAR7 ,
VAR11 ,
VAR14 ,
VAR1 ,
VAR13 ,
VAR5 ,
VAR6 ,
VAR10 ,
VAR4
);
input VAR3 ;
input VAR7 ;
input [VAR15 - 1:0] VAR11 ;
input VAR14 ;
output [VAR9 - 1:0] VAR1 ;
output VAR13 ;
input VAR5 ;
output [VAR15 - 1:0] VAR6 ;
input [VAR9 - 1:0] VAR10 ;
outp... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_ln_s5.v | 1,307 | module MODULE1 (
enable, VAR6,
VAR10,
VAR4,
VAR3);
input enable, VAR6;
input VAR10;
input [31:0] VAR4;
output [31:0] VAR3;
wire [31:0] VAR1;
wire [31:0] VAR3 = VAR1[31:0];
VAR2 VAR8 ( .clk(VAR10),
.VAR5(1'b0),
.en(enable),
.VAR9(VAR4),
.VAR7(VAR1));
endmodule | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_rng/rtl/bw_rng.v | 1,651 | module MODULE1 (
VAR6, VAR9,
VAR2, VAR7, VAR8, VAR5, VAR3
);
input VAR2;
input VAR7;
input [2:0] VAR8;
input VAR5;
input VAR3 ;
output VAR6;
output VAR9;
integer VAR4;
reg VAR1;
reg VAR9;
reg VAR6;
begin
begin | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/controller/rank_mach.v | 11,024 | module MODULE1 #
(
parameter VAR1 = "8",
parameter VAR46 = 4,
parameter VAR52 = "VAR27",
parameter VAR45 = 40,
parameter VAR11 = 4,
parameter VAR21 = 2,
parameter VAR30 = 5,
parameter VAR35 = 30,
parameter VAR9 = 8,
parameter VAR53 = 4,
parameter VAR33 = 4,
parameter VAR41 = 20,
parameter VAR6 = 16,
parameter VAR2 = 2,... | lgpl-3.0 |
LSaldyt/qnp | output/vs/var25_multi.v | 1,853 | module MODULE1 (VAR17, VAR30, VAR24, VAR19, VAR26, VAR11, VAR13, VAR3, VAR23, VAR1, VAR15, VAR8, VAR6, VAR12, VAR16, VAR28, VAR9, VAR10, VAR18, VAR7, VAR5, VAR2, VAR25, VAR4, VAR20, valid);
input VAR17, VAR30, VAR24, VAR19, VAR26, VAR11, VAR13, VAR3, VAR23, VAR1, VAR15, VAR8, VAR6, VAR12, VAR16, VAR28, VAR9, VAR10, VAR... | mit |
alexforencich/hdg2000 | fpga/rtl/ddr2_clock.v | 3,700 | module MODULE1
(
input wire VAR39,
input wire VAR68,
output wire VAR31,
output wire VAR40,
output wire VAR8,
output wire VAR70
);
wire VAR23;
wire VAR41;
wire VAR26;
wire VAR60;
VAR3 #
(
.VAR73 ("VAR53"),
.VAR9 (4.000),
.VAR36 (4.000),
.VAR43 (1),
.VAR12 (1),
.VAR63 (10),
.VAR65 (1),
.VAR49 (1),
.VAR75 (1),
.VAR14 (0.0... | mit |
bigeagle/riffa | fpga/riffa_hdl/channel_64.v | 9,863 | module MODULE1 #(
parameter VAR14 = 9'd64,
parameter VAR94 = 2, parameter VAR23 = 1024,
parameter VAR101 = 512,
parameter VAR103 = 1024,
parameter VAR80 = VAR43((VAR14/32)+1)
)
(
input VAR102,
input VAR26,
input [2:0] VAR67, input [2:0] VAR72,
input [31:0] VAR39, input [VAR14-1:0] VAR42,
output VAR37, input VAR7, input... | bsd-3-clause |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/verilog/feedforward_fpext_32ns_64_1.v | 1,121 | module MODULE1
VAR9 = 4,
VAR5 = 1,
VAR11 = 32,
VAR6 = 64
)(
input wire [VAR11-1:0] VAR1,
output wire [VAR6-1:0] dout
);
wire VAR16;
wire [31:0] VAR3;
wire VAR13;
wire [63:0] VAR4;
VAR15 VAR10 (
.VAR14 ( VAR16 ),
.VAR7 ( VAR3 ),
.VAR2 ( VAR13 ),
.VAR12 ( VAR4 )
);
assign VAR16 = 1'b1;
assign VAR3 = VAR1==='VAR8 ? 'b0 : ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n_1.v | 2,382 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR8,
VAR9 ,
VAR1 ,
VAR6 ,
VAR5
);
output VAR3 ;
input VAR7 ;
input VAR8;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR3 ,
VAR7 ,
VAR8
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver/sky130_fd_sc_lp__busdriver_20.v | 2,189 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR1,
VAR2,
VAR4,
VAR5 ,
VAR6
);
output VAR9 ;
input VAR8 ;
input VAR1;
input VAR2;
input VAR4;
input VAR5 ;
input VAR6 ;
VAR7 VAR3 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR9 ,
VAR8 ,
VAR1
);
output VAR9 ;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_12.behavioral.pp.v | 1,251 | module MODULE1( VAR7, VAR2, VAR6, VAR1, VAR5 );
input VAR7, VAR2;
inout VAR1, VAR5;
output VAR6;
VAR4 VAR3(.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6),.VAR1(VAR1),.VAR5(VAR5));
VAR4 VAR8(.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6),.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
tmolteno/TART | hardware/FPGA/fifo/fifo16n.v | 5,487 | module MODULE1 (
VAR23,
VAR14,
VAR22,
VAR13,
VAR5,
VAR11,
VAR12,
VAR17,
VAR10
);
parameter VAR24 = 8;
input VAR23;
input VAR14;
input VAR22;
output [VAR24-1:0] VAR13;
input VAR5;
input VAR11;
input [VAR24-1:0] VAR12;
output VAR17;
output VAR10;
reg [VAR8:0] VAR15 = 0;
reg [VAR8:0] VAR19 = 0;
wire [VAR8:0] VAR25;
wire [... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.behavioral.v | 1,964 | module MODULE1( VAR8, VAR6, VAR7, VAR3, VAR1 );
input VAR1, VAR3, VAR7, VAR8;
output VAR6;
VAR2 VAR4(.VAR8(VAR8),.VAR6(VAR6),.VAR7(VAR7),.VAR3(VAR3),.VAR1(VAR1));
VAR2 VAR5(.VAR8(VAR8),.VAR6(VAR6),.VAR7(VAR7),.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp.functional.pp.v | 1,863 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR1 ,
VAR12,
VAR5 ,
VAR2 ,
VAR9 ,
VAR3
);
output VAR4 ;
input VAR8 ;
input VAR1 ;
input VAR12;
input VAR5 ;
input VAR2 ;
input VAR9 ;
input VAR3 ;
wire VAR13;
wire VAR7;
not VAR11 (VAR7 , VAR12 );
VAR14 VAR10 VAR6 (VAR13 , VAR1, VAR8, VAR7, , VAR5, VAR2);
buf VAR15 (VAR4 , VAR13 );
endmo... | apache-2.0 |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/bus_interface.v | 2,405 | module MODULE1(
input clk,
input rst,
input [7:0] VAR23,
input [7:0] VAR26,
input VAR18,
input VAR9,
inout VAR10,
inout [7:0] VAR5,
output VAR29,
input VAR19,
input VAR13,
output [7:0] VAR7,
output VAR1,
output VAR28,
input VAR16,
input [7:0] VAR32,
input VAR34,
input VAR20,
output [7:0] VAR15);
parameter VAR22 = 0;
pa... | apache-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/altera_jtag_sld_node.v | 6,704 | module MODULE1 (
VAR49,
VAR16,
VAR47,
VAR66,
VAR14,
VAR25,
VAR61,
VAR80,
VAR34,
VAR5,
VAR19,
VAR27,
VAR29
);
parameter VAR39 = 20;
localparam VAR75 = (1000/VAR39)/2;
localparam VAR11 = 3;
input [VAR11 - 1:0] VAR49;
input VAR16;
output reg [VAR11 - 1:0] VAR47;
output VAR66;
output reg VAR14 = 1'b0;
output VAR25;
output ... | gpl-3.0 |
brabect1/risc8 | hdl/verilog/alu.v | 2,435 | module MODULE1 (
VAR13,
VAR2,
VAR11,
VAR6,
VAR3,
VAR1,
VAR12
);
input [3:0] VAR13; input [7:0] VAR2; input [7:0] VAR11; output [7:0] VAR6; input VAR3;
output VAR1;
output VAR12;
reg VAR1;
reg VAR12;
reg [7:0] VAR6;
reg VAR4;
parameter [3:0] VAR15 = 4'b0000;
parameter [3:0] VAR17 = 4'b1000;
parameter [3:0] VAR10 = 4'b00... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41o/sky130_fd_sc_ms__a41o.behavioral.pp.v | 2,058 | module MODULE1 (
VAR16 ,
VAR13 ,
VAR15 ,
VAR10 ,
VAR6 ,
VAR2 ,
VAR14,
VAR17,
VAR8 ,
VAR12
);
output VAR16 ;
input VAR13 ;
input VAR15 ;
input VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR14;
input VAR17;
input VAR8 ;
input VAR12 ;
wire VAR1 ;
wire VAR7 ;
wire VAR5;
and VAR18 (VAR1 , VAR13, VAR15, VAR10, VAR6 );
or VAR11 ... | apache-2.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_SW.v | 1,870 | module MODULE1 (
address,
clk,
VAR6,
VAR5,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR6;
input VAR5;
wire VAR2;
wire [ 7: 0] VAR4;
wire [ 7: 0] VAR1;
reg [ 31: 0] VAR3;
assign VAR2 = 1;
assign VAR1 = {8 {(address == 0)}} & VAR4;
always @(posedge clk or negedge VAR5)
begin
if (VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi.behavioral.pp.v | 2,070 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR1 ,
VAR13 ,
VAR8 ,
VAR15 ,
VAR9,
VAR2,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR11 ;
input VAR1 ;
input VAR13 ;
input VAR8 ;
input VAR15 ;
input VAR9;
input VAR2;
input VAR6 ;
input VAR4 ;
wire VAR17 ;
wire VAR5 ;
wire VAR12;
and VAR18 (VAR17 , VAR11, VAR1, VAR13, VAR8 );
nor VAR7 (VAR5 ... | apache-2.0 |
phase4ground/DVB-receiver | modem/rfnoc-modem/rfnoc/fpga-src/noc_block_apskmodulator.v | 10,925 | module MODULE1 #(
parameter VAR76 = 64'h1F860BEBEC67AA56,
parameter VAR2 = 11,
parameter VAR132 = 4)
(
input VAR118, input VAR3,
input VAR42, input VAR8,
input [63:0] VAR104, input VAR65, input VAR22, output VAR75,
output [63:0] VAR53, output VAR40, output VAR72, input VAR131,
output [63:0] VAR16
);
wire [31:0] VAR4;
w... | gpl-3.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/MultiplyState.v | 2,509 | module MODULE1(
input [32:0] VAR14,
input [32:0] VAR5,
input [35:0] VAR2,
input [35:0] VAR17,
input [31:0] VAR24,
input [1:0] VAR27,
input VAR30,
input VAR18,
input [7:0] VAR22,
input VAR23,
input [1:0] VAR26,
output reg [1:0] VAR12,
output reg [35:0] VAR31,
output reg [35:0] VAR20,
output reg [31:0] VAR11,
output reg ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi.pp.symbol.v | 1,408 | module MODULE1 (
input VAR9 ,
input VAR5 ,
input VAR3 ,
input VAR10 ,
input VAR1 ,
output VAR7 ,
input VAR4 ,
input VAR8,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc_16.v | 2,325 | module MODULE1 (
VAR6 ,
VAR5,
VAR3 ,
VAR2 ,
VAR4 ,
VAR9 ,
VAR1
);
output VAR6 ;
input VAR5;
input VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR1 ;
VAR8 VAR7 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR6 ,
VAR5,
VAR3
);
output VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtp/sky130_fd_sc_ms__dlxtp.blackbox.v | 1,292 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR7 ;
input VAR4;
supply1 VAR2;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/diode/sky130_fd_sc_hs__diode.functional.pp.v | 1,200 | module MODULE1 (
VAR4,
VAR1 ,
VAR3 ,
VAR2 ,
VAR5
);
input VAR4;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_p_pp_pg_n/sky130_fd_sc_hs__udp_dff_p_pp_pg_n.symbol.v | 1,413 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR3 ,
input VAR2,
input VAR1 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2b/sky130_fd_sc_hdll__or2b_1.v | 2,143 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4 ,
VAR1,
VAR8,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR1;
input VAR8;
input VAR6 ;
input VAR5 ;
VAR9 VAR7 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR2 ,
VAR3 ,
VAR4
);
output VAR2... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v | 3,891 | module MODULE1 #
(
parameter integer VAR1 = 4,
parameter integer VAR5 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR1-1:0] VAR15 ,
input wire [VAR5-1:0] VAR27 ,
input wire [7:0] VAR22 ,
input wire [2:0] VAR12 ,
input wire [1:0] VAR4 ,
input wire VAR23 ,
output wire VAR7 ,
output wire VAR24 ,
output wire [... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.behavioral.pp.v | 2,576 | module MODULE1( VAR2, VAR1, VAR7, VAR8, VAR3, VAR4 );
input VAR1, VAR2, VAR7;
inout VAR3, VAR4;
output VAR8;
VAR6 VAR9(.VAR2(VAR2),.VAR1(VAR1),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3),.VAR4(VAR4));
VAR6 VAR5(.VAR2(VAR2),.VAR1(VAR1),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbp/sky130_fd_sc_ms__dlrbp.blackbox.v | 1,407 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR9,
VAR2 ,
VAR6
);
output VAR5 ;
output VAR1 ;
input VAR9;
input VAR2 ;
input VAR6 ;
supply1 VAR4;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
omicronns/studies-sys-rek | de1-soc/Sdram_Control/control_interface.v | 8,614 | module MODULE1(
VAR5,
VAR7,
VAR21,
VAR1,
VAR2,
VAR12,
VAR22,
VAR18,
VAR20,
VAR9,
VAR19,
VAR10,
VAR8,
VAR4,
VAR17,
VAR3,
VAR13
);
input VAR5; input VAR7; input [2:0] VAR21; input [VAR6-1:0] VAR1; input VAR2; input VAR12; input VAR22; output VAR18; output VAR20; output VAR9; output VAR19; output VAR10; output VAR8; outpu... | mit |
AngelTerrones/MUSB | Hardware/musb/musb_shifter.v | 5,387 | module MODULE1(
input [31:0] VAR11, input [4:0] VAR2, input VAR6, input VAR1, output [31:0] VAR8 );
reg [31:0] VAR13; reg [31:0] VAR4; reg [31:0] VAR10;
wire VAR5;
wire [31:0] VAR7;
assign VAR5 = (VAR1) ? VAR11[31] : 1'b0; assign VAR7 = (VAR6) ? VAR13 : VAR11; assign VAR8 = (VAR6) ? VAR10 : VAR4;
integer VAR12;
integer... | mit |
benreynwar/fpga-sdrlib | verilog/fpgamath/multiply_complex.v | 1,647 | module MODULE1
parameter VAR20 = 32
)
(
input wire clk,
input wire VAR21,
input wire signed [VAR20-1:0] VAR16,
input wire signed [VAR20-1:0] VAR5,
output wire signed [VAR20-1:0] VAR18
);
wire signed [VAR20/2-1:0] VAR8;
wire signed [VAR20/2-1:0] VAR2;
wire signed [VAR20/2-1:0] VAR19;
wire signed [VAR20/2-1:0] VAR22;
ass... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_2.behavioral.pp.v | 6,220 | module MODULE1( VAR5, VAR34, VAR36, VAR8, VAR42, VAR31, VAR28 );
input VAR34, VAR5, VAR36, VAR8;
inout VAR31, VAR28;
output VAR42;
reg VAR23;
VAR37 VAR48(.VAR5(VAR5),.VAR34(VAR34),.VAR36(VAR36),.VAR8(VAR8),.VAR42(VAR42),.VAR31(VAR31),.VAR28(VAR28),.VAR23(VAR23));
VAR37 VAR9(.VAR5(VAR5),.VAR34(VAR34),.VAR36(VAR36),.VAR8... | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkOCApp4B_scenario2.v | 50,683 | module MODULE1(VAR123,
VAR355,
VAR77,
VAR332,
VAR19,
VAR371,
VAR279,
VAR356,
VAR225,
VAR227,
VAR304,
VAR69,
VAR103,
VAR51,
VAR208,
VAR127,
VAR317,
VAR361,
VAR218,
VAR119,
VAR108,
VAR86,
VAR205,
VAR347,
VAR87,
VAR181,
VAR101,
VAR201,
VAR178,
VAR324,
VAR11,
VAR190,
VAR389,
VAR281,
VAR191,
VAR162,
VAR24,
VAR198,
VAR314,
V... | lgpl-3.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/dds/dds_stub.v | 1,529 | module MODULE1(VAR7, VAR2, VAR5, VAR4, VAR1, VAR3, VAR6)
;
input VAR7;
input VAR2;
input [39:0]VAR5;
output VAR4;
output [31:0]VAR1;
output VAR3;
output [39:0]VAR6;
endmodule | gpl-2.0 |
ktaube/fpga-vga-snake | clock_div.v | 2,657 | module MODULE1(VAR3,
VAR1,
VAR23,
VAR26);
input VAR3;
output VAR1;
output VAR23;
output VAR26;
wire VAR28;
wire VAR19;
wire VAR10;
wire VAR27;
wire VAR4;
assign VAR4 = 0;
assign VAR23 = VAR10;
assign VAR26 = VAR19;
VAR16 VAR56 (.VAR34(VAR28),
.VAR14(VAR1));
VAR2 VAR47 (.VAR34(VAR3),
.VAR14(VAR10));
VAR16 VAR35 (.VAR34(... | gpl-2.0 |
golfit/QcmCapBoardMain | CapBoardDriver.v | 1,182 | module MODULE1(VAR2,state,VAR1);
input VAR2;
input [3:0] state;
output [7:0] VAR1;
assign VAR1[3:0]={4{VAR2}} & state;
assign VAR1[7:4]=(~VAR1[3:0]) & state;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.symbol.v | 2,556 | module MODULE1 (
input VAR8 ,
output VAR36 ,
input VAR11 ,
output VAR22 ,
input VAR15 ,
inout VAR17 ,
inout VAR20 ,
inout VAR1 ,
inout VAR18 ,
inout VAR9 ,
inout VAR10 ,
input VAR27 ,
input VAR37 ,
input VAR12 ,
input [2:0] VAR19 ,
input VAR3 ,
input VAR31 ,
input VAR28 ,
input VAR16 ,
input VAR7,
input VAR34 ,
input V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp_1.v | 2,577 | module MODULE2 (
VAR7 ,
VAR10 ,
VAR8 ,
VAR2 ,
VAR3 ,
VAR1,
VAR4 ,
VAR9 ,
VAR6 ,
VAR11
);
output VAR7 ;
output VAR10 ;
input VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR1;
input VAR4 ;
input VAR9 ;
input VAR6 ;
input VAR11 ;
VAR5 VAR12 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_p/sky130_fd_sc_lp__udp_dff_p.blackbox.v | 1,202 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR2;
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_pcie_pipe_misc.v | 8,089 | module MODULE1 #
(
parameter VAR23 = 0 )
(
input wire VAR28 , input wire VAR9 , input wire VAR26 , input wire VAR14 , input wire [2:0] VAR29 , input wire VAR5 ,
output wire VAR15 , output wire VAR17 , output wire VAR25 , output wire VAR18 , output wire [2:0] VAR8 , output wire VAR19 ,
input wire VAR2 , input wire VAR24... | mit |
r2apu/Labo_Digitales | L3/miniALU_L3/MiniAlu.v | 4,665 | module MODULE1
(
input wire VAR8,
input wire VAR17,
output wire [7:0] VAR15
);
wire [15:0] VAR28,VAR23;
reg VAR27,VAR25;
wire [27:0] VAR47;
wire [3:0] VAR13;
reg signed [15:0] VAR43;
wire [7:0] VAR12,VAR1,VAR5, VAR46, VAR36;
wire [15:0] VAR32,VAR40,VAR20,VAR33;
VAR9 VAR3
(
.VAR37( VAR28 ),
.VAR44( VAR47 )
);
VAR18 VAR4... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv.behavioral.pp.v | 1,873 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR10 ,
VAR13 ,
VAR6,
VAR2 ,
VAR1
);
output VAR3 ;
input VAR9 ;
input VAR10 ;
input VAR13 ;
input VAR6;
input VAR2 ;
input VAR1 ;
wire VAR12;
wire VAR5 ;
VAR11 VAR4 (VAR12, VAR9, VAR10, VAR13 );
buf VAR7 (VAR5 , VAR12 );
VAR11 VAR8 (VAR3 , VAR5, VAR6, VAR13);
endmodule | apache-2.0 |
briburrell/amica | device/scrypt_salsa8/ztex_ufm1_15y1.v | 10,688 | module MODULE1 (VAR100, reset, select, VAR85, VAR42, VAR114, VAR75, VAR4, VAR113, VAR31, VAR119, read, write);
input VAR100, select, reset, VAR85, VAR42, VAR114, VAR75, VAR4, VAR113, VAR31, VAR119;
input [7:0] read;
output [7:0] write;
function integer VAR25; input integer VAR127;
begin
VAR127 = VAR127-1;
for (VAR25=0;... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.behavioral.v | 18,312 | module MODULE1( VAR253, VAR71, VAR163, VAR258, VAR268, VAR44 );
input VAR258, VAR163, VAR268, VAR253, VAR71;
output VAR44;
reg VAR29;
VAR73 VAR20(.VAR253(VAR253),.VAR71(VAR71),.VAR163(VAR163),.VAR258(VAR258),.VAR268(VAR268),.VAR44(VAR44),.VAR29(VAR29));
VAR73 VAR292(.VAR253(VAR253),.VAR71(VAR71),.VAR163(VAR163),.VAR258... | apache-2.0 |
chaohu/Daily-Learning | Verilog/lab4/lab4_2/lab4_2.srcs/sources_1/new/lab4_2.v | 1,072 | module MODULE1(
input VAR17,VAR23,VAR8,VAR13,VAR14,
output wire [VAR1-1:0] VAR4
);
parameter VAR1 = 8;
wire [VAR1-1:0] VAR25,VAR12,VAR22,VAR7,VAR19,VAR6,VAR20,VAR9;
VAR18 #(VAR1)
VAR10(VAR25,VAR6,VAR20),
VAR3(1,VAR12,VAR9);
VAR24 #(VAR1)
VAR15(VAR20,0,VAR17,VAR22),
VAR26(VAR6,0,VAR23,VAR7),
VAR2(VAR12,VAR9,VAR8,VAR19);... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai.behavioral.v | 1,564 | module MODULE1 (
VAR12 ,
VAR7,
VAR3,
VAR4,
VAR8
);
output VAR12 ;
input VAR7;
input VAR3;
input VAR4;
input VAR8;
supply1 VAR11;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR1 ;
wire VAR10 ;
wire VAR6;
or VAR14 (VAR10 , VAR3, VAR7 );
nand VAR5 (VAR6, VAR8, VAR10, VAR4);
buf VAR13 (VAR12 , VAR6 );
endmodule | apache-2.0 |
jncronin/jca | cpu/vga.v | 7,033 | module MODULE1(clk, VAR23, VAR56, VAR57, VAR38, VAR25, VAR53, VAR6, VAR58, addr, VAR63);
input clk;
output reg VAR23;
output reg VAR56;
output reg VAR57;
output reg VAR38;
output reg VAR25;
input VAR53;
input VAR6;
input VAR58;
input [11:0] addr;
inout [7:0] VAR63;
reg [10:0] VAR62 = 11'd0; reg [9:0] VAR13 = 10'd0;
par... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v | 2,163 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR3,
VAR5,
VAR8 ,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR3;
input VAR5;
input VAR8 ;
input VAR1 ;
VAR6 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
supply1 VAR3;
supply0 VAR5;... | apache-2.0 |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_phy_write.v | 17,160 | module MODULE1 #
(
parameter VAR40 = 72,
parameter VAR51 = 1,
parameter VAR4 = 0,
parameter VAR65 = 5,
parameter VAR36 = 0,
parameter VAR71 = 1,
parameter VAR54 = 1,
parameter VAR67 = 1
)
(
input VAR24,
input VAR13,
input VAR19,
input [(2*VAR40)-1:0] VAR41,
input [(2*VAR40/8)-1:0] VAR11,
input VAR12,
input VAR23,
input... | mit |
sam-falvo/kestrel | cores/MGIA/rtl/verilog/vram.v | 10,033 | module MODULE1(
input VAR36,
input VAR37,
input [12:0] VAR140,
input VAR58,
input VAR47,
output VAR30,
output [15:0] VAR102,
input [12:0] VAR2,
input [15:0] VAR60,
output [15:0] VAR64,
input VAR52,
output VAR53,
input VAR46
);
reg VAR98;
reg VAR82;
wire [15:0] VAR8, VAR5, VAR134, VAR23, VAR99, VAR120, VAR48, VAR93;
wir... | mpl-2.0 |
which0326/ca_project2 | code/CPU.v | 5,858 | module MODULE1
(
VAR49,
VAR64,
VAR128,
VAR8,
VAR14,
VAR86,
VAR131,
VAR72,
VAR108
);
input VAR49;
input VAR64;
input VAR128;
input [256-1:0] VAR8;
input VAR14;
output [256-1:0] VAR86;
output [32-1:0] VAR131;
output VAR72;
output VAR108;
wire [31:0] VAR59, VAR70;
wire VAR79;
wire VAR39;
assign VAR79 = VAR69.VAR24 | (VAR6... | cc0-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtn/sky130_fd_sc_ls__sdfrtn.pp.blackbox.v | 1,470 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR10 ,
VAR4,
VAR5 ,
VAR1 ,
VAR2 ,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR10 ;
input VAR4;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
skalldri/mips-verilog | memory/memory.v | 2,513 | module MODULE1 (clk, addr, din, dout, VAR2, VAR7, VAR8, enable);
parameter VAR5 = 1024;
parameter VAR9 = 32'h80020000;
input clk;
input [31:0] addr;
input [31:0] din;
input [1:0] VAR2;
input VAR7; input enable;
output VAR8;
output [31:0] dout;
reg [31:0] VAR6;
wire [31:0] dout = VAR6;
wire VAR8;
reg [7:0] VAR10[0:VAR5]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbn/sky130_fd_sc_ls__dlrbn_1.v | 2,480 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR8,
VAR11 ,
VAR3 ,
VAR7 ,
VAR5 ,
VAR6 ,
VAR2
);
output VAR1 ;
output VAR4 ;
input VAR8;
input VAR11 ;
input VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR2 ;
VAR10 VAR9 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_frame_join_4.v | 13,634 | module MODULE1 #
(
parameter VAR52 = 1,
parameter VAR70 = 16
)
(
input wire clk,
input wire rst,
input wire [7:0] VAR12,
input wire VAR49,
output wire VAR26,
input wire VAR69,
input wire VAR35,
input wire [7:0] VAR45,
input wire VAR65,
output wire VAR30,
input wire VAR71,
input wire VAR57,
input wire [7:0] VAR28,
input... | mit |
cbakalis/vmm_boards_firmware | sources/sources_1/xadc/mmfe8_xadc/xadc_read.v | 13,787 | module MODULE1
(
input VAR34,
input rst,
input VAR52,
input [4:0] VAR28,
input VAR24,
input VAR10,
input [4:0] VAR20,
input [15:0] VAR5,
input VAR37,
input VAR19,
output VAR12,
output [11:0] VAR11,
output VAR6,
output [6:0] VAR38,
output VAR41,
output VAR31,
output [15:0] VAR17,
output VAR43,
output [3:0] VAR44
);
wire... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.v | 2,366 | module MODULE2 (
VAR6 ,
VAR4,
VAR2 ,
VAR7 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR9
);
output VAR6 ;
input VAR4;
input VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
VAR8 VAR10 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE2... | apache-2.0 |
subailong/miaow | src/verilog/rtl/vgpr/reg_64page_1024x32b_3r_1w_fpga.v | 2,309 | module MODULE1
(
VAR4, VAR12, VAR2,
VAR26, VAR22, VAR5, VAR10, VAR30, VAR29,
VAR19, clk, VAR27
);
output [8191:0] VAR4;
output [2047:0] VAR12;
output [2047:0] VAR2;
input [9:0] VAR26;
input [9:0] VAR22;
input [9:0] VAR5;
input [9:0] VAR10;
input [63:0] VAR30;
input [3:0] VAR29;
input [8191:0] VAR19;
input clk;
input VA... | bsd-3-clause |
sorgelig/ZX_Spectrum-128K_MIST | mouse.v | 2,169 | module MODULE1
(
input VAR7,
input reset,
input [24:0] VAR10,
input [2:0] addr,
output sel,
output [7:0] dout
);
assign dout = VAR1;
assign sel = VAR11;
reg [1:0] VAR9;
reg VAR8;
reg [11:0] VAR5;
reg [11:0] VAR12;
wire [11:0] VAR13 = VAR5 + {{4{VAR10[4]}},VAR10[15:8]};
wire [11:0] VAR6 = VAR12 + {{4{VAR10[5]}},VAR10[23... | gpl-2.0 |
jaechoon2/FPGA-Imaging-Library | LocalFilter/RankFilter/HDL/RankFilter.srcs/sources_1/new/RankFilter.v | 8,919 | module MODULE1(
clk,
VAR10,
VAR24,
VAR25,
VAR16,
VAR13,
VAR18);
parameter[0 : 0] VAR12 = 0;
parameter[3 : 0] VAR22 = 3;
parameter[3 : 0] VAR5 = 8;
parameter[2 : 0] VAR2 = 2;
parameter VAR7 = 4;
input clk;
input VAR10;
input[VAR7 - 1 : 0] VAR24;
input VAR25;
input [VAR5 * VAR22 * VAR22 - 1 : 0] VAR16;
output VAR13;
outp... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.blackbox.v | 1,485 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR3 ,
VAR11 ,
VAR5 ,
VAR4 ,
VAR6
);
output VAR8 ;
output VAR1 ;
input VAR3 ;
input VAR11 ;
input VAR5 ;
input VAR4 ;
input VAR6;
supply1 VAR9;
supply0 VAR2;
supply1 VAR10 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n.behavioral.v | 1,497 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR10
);
output VAR5 ;
input VAR2 ;
input VAR10;
supply1 VAR6;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR3 ;
wire VAR9;
not VAR8 (VAR9 , VAR10 );
or VAR4 (VAR5 , VAR2, VAR9 );
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_if.v | 7,073 | module MODULE1(
clk, rst,
VAR9, VAR23, VAR10, VAR17, VAR6,
VAR8, VAR18, VAR7, VAR1,
VAR2, VAR3, VAR22, VAR4,
VAR12, VAR20, VAR14
);
input clk;
input rst;
input [31:0] VAR9;
input VAR23;
input VAR10;
input [31:0] VAR17;
input [3:0] VAR6;
input VAR8;
output [31:0] VAR18;
output [31:0] VAR7;
input VAR1;
output VAR2;
input... | gpl-3.0 |
m-labs/milkymist | cores/sysctl/rtl/sysctl_icap.v | 2,144 | module MODULE1(
input VAR14,
input VAR6,
output reg ready,
input VAR23,
input [15:0] VAR13,
input VAR7,
input write
);
reg VAR5;
reg VAR18;
reg VAR11;
reg [15:0] VAR3;
reg VAR17;
reg VAR16;
always @(posedge VAR14) begin
if(VAR11) begin
VAR3[0] <= VAR13[7];
VAR3[1] <= VAR13[6];
VAR3[2] <= VAR13[5];
VAR3[3] <= VAR13[4];
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.behavioral.v | 1,860 | module MODULE1 (
VAR13 ,
VAR12 ,
VAR9 ,
VAR2,
VAR1
);
output VAR13 ;
input VAR12 ;
input VAR9 ;
input VAR2;
input VAR1;
wire VAR13 VAR7 ;
wire VAR6 ;
wire VAR11;
not VAR5 (VAR7 , VAR12 );
and VAR3 (VAR6 , VAR7, VAR9 );
VAR4 VAR8 (VAR11, VAR6, VAR2, VAR1);
buf VAR10 (VAR13 , VAR11 );
endmodule | apache-2.0 |
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