repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp_2.v | 2,345 | module MODULE2 (
VAR5 ,
VAR9 ,
VAR10 ,
VAR1,
VAR3 ,
VAR6 ,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR1;
input VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR2 ;
VAR7 VAR8 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv_2.v | 2,036 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR6,
VAR4,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR5 ;
input VAR6;
input VAR4;
input VAR7 ;
input VAR2 ;
VAR1 VAR3 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8,
VAR5
);
output VAR8;
input VAR5;
supply1 VAR6;
supply0 VAR4;... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_s01_regslice_0/synth/OpenSSD2_s01_regslice_0.v | 14,871 | module MODULE1 (
VAR28,
VAR37,
VAR103,
VAR46,
VAR43,
VAR86,
VAR1,
VAR105,
VAR21,
VAR12,
VAR61,
VAR72,
VAR92,
VAR97,
VAR107,
VAR50,
VAR14,
VAR5,
VAR19,
VAR64,
VAR54,
VAR101,
VAR35,
VAR26,
VAR22,
VAR42,
VAR85,
VAR79,
VAR41,
VAR73,
VAR45,
VAR100,
VAR60,
VAR87,
VAR99,
VAR23,
VAR69,
VAR9,
VAR39,
VAR16,
VAR68,
VAR49,
VAR108,... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_interpolator_8pel.v | 16,603 | module MODULE1 (
VAR15 ,
VAR63 ,
VAR89 ,
VAR76 ,
VAR53 ,
VAR10 ,
VAR6 ,
VAR75 ,
VAR46 ,
VAR62 ,
VAR81 ,
VAR11 ,
VAR16 ,
VAR92 ,
VAR72 ,
VAR38 ,
VAR32 ,
VAR5 ,
VAR56 ,
VAR69 ,
VAR29 ,
VAR52 ,
VAR73 ,
VAR100 ,
VAR107 ,
VAR91 ,
VAR20 ,
VAR60 ,
VAR59 ,
VAR90 ,
VAR99 ,
VAR68 ,
VAR24 ,
VAR22 ,
VAR34 ,
VAR27 ,
VAR51 ,
VAR48 ,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufbuf/sky130_fd_sc_hs__bufbuf.pp.symbol.v | 1,225 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/block_SDP.v | 7,882 | module MODULE1
parameter VAR27 = 24, parameter VAR63 = VAR27-1,
parameter VAR74 = 120'h0,
parameter VAR15 = 120'h0,
parameter VAR23 = 120'h0,
parameter VAR67 = 120'h0,
parameter VAR75 = VAR51*2, parameter VAR37 = VAR75-1,
parameter VAR80 = VAR75*4, parameter VAR47 = VAR80-1,
parameter VAR69 = 12, parameter VAR78 = 4, p... | lgpl-3.0 |
karatekid/ultrasonic-fountain | hardware/src/mojo_com.v | 1,163 | module MODULE1 #(
parameter VAR8 = 64 )(
input clk,
input rst,
input VAR13,
input VAR3,
input VAR10,
output VAR6,
output [8*VAR8-1:0] VAR18,
output VAR24,
output VAR19,
input [8*VAR8-1:0] VAR15,
output VAR7
);
parameter VAR12 = VAR23(VAR8);
wire [VAR12-1:0] VAR22;
wire [7:0] VAR17, VAR14;
wire write, VAR25, VAR16;
VAR1... | gpl-3.0 |
Ribeiro/sd2snes | verilog/sd2snes_obc1/dac.v | 3,710 | module MODULE1(
input VAR44,
input VAR45,
input VAR10,
input[10:0] VAR30,
input[7:0] VAR9,
input[7:0] VAR2,
input VAR31,
input VAR29,
input reset,
output VAR22,
output VAR14,
output VAR42,
output VAR39,
output VAR4
);
reg[8:0] VAR46;
wire[8:0] VAR25 = VAR46;
wire[31:0] VAR15;
assign VAR4 = VAR46[8];
reg[7:0] VAR12;
reg... | gpl-2.0 |
anderson1008/NOCulator | hring/hw/bless_mc/swAlloc.v | 7,805 | module MODULE2 (
VAR54,
VAR8,
VAR52,
VAR21,
VAR19,
VAR23,
VAR1,
VAR32,
VAR33
);
input [VAR18-1:0] VAR54;
input [VAR17-2:0] VAR8, VAR52, VAR21, VAR19;
output [VAR17-2:0] VAR23, VAR1, VAR32, VAR33;
generate
if (VAR31 == 1'b0) begin : VAR34
wire [VAR17-2:0] VAR4 [1:3];
wire [VAR18-1:0] VAR27 [1:3];
VAR35 VAR16(
.VAR54 (VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_2.functional.v | 1,158 | module MODULE1( VAR4, VAR1, VAR9 );
input VAR1, VAR4;
output VAR9;
wire VAR5;
and VAR3( VAR5, VAR1, VAR4 );
wire VAR12;
not VAR8( VAR12, VAR1 );
wire VAR11;
not VAR7( VAR11, VAR4 );
wire VAR6;
and VAR2( VAR6, VAR12, VAR11 );
or VAR10( VAR9, VAR5, VAR6 );
endmodule | apache-2.0 |
misomosi/FM-Synthesizer | Digital Synth/ComponentLibrary.cydsn/Sawtooth_Generator_v1_0/Sawtooth_Generator_v1_0.v | 26,286 | module MODULE3 (
VAR44,
clk,
VAR48,
VAR33,
VAR62,
ready
);
parameter [7:0] VAR29 = 8'd8;
output reg [7:0] VAR44;
input wire clk;
input wire [7:0] VAR48;
input wire VAR33;
output wire VAR62;
output wire ready;
localparam VAR45 = 2'b00;
localparam VAR37 = 2'b01;
reg state;
wire [7:0] VAR65;
assign ready = state == VAR45;... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_1.behavioral.v | 1,245 | module MODULE1( VAR4, VAR5, VAR7, VAR6 );
input VAR4, VAR5, VAR7;
output VAR6;
VAR3 VAR1(.VAR4(VAR4),.VAR5(VAR5),.VAR7(VAR7),.VAR6(VAR6));
VAR3 VAR2(.VAR4(VAR4),.VAR5(VAR5),.VAR7(VAR7),.VAR6(VAR6)); | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_xcv_ram32x8d.v | 10,843 | module MODULE1
(
VAR43,
VAR11,
VAR33,
VAR10,
VAR32,
VAR38,
VAR39
);
output [7:0] VAR43;
output [7:0] VAR11;
input [4:0] VAR33;
input [4:0] VAR32;
input [7:0] VAR10;
input VAR38;
input VAR39;
wire [7:0] VAR1;
wire [7:0] VAR16;
wire [7:0] VAR27;
wire [7:0] VAR46;
wire VAR41 ;
wire VAR31 ;
assign VAR43 = VAR32[4] ? VAR27 ... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_hcmd_nlb.v | 6,288 | module MODULE1 # (
parameter VAR30 = 19,
parameter VAR27 = 7
)
(
input clk,
input VAR11,
input VAR10,
input [VAR27-1:0] VAR33,
input [VAR30-1:0] VAR17,
output VAR38,
input VAR60,
input [VAR27-1:0] VAR50,
input [VAR30-1:0] VAR31,
output VAR19,
input [VAR27-1:0] VAR9,
output [VAR30-1:0] VAR8
);
localparam VAR29 = 2'b01;
... | gpl-3.0 |
sh-chris110/chris | FPGA/HPS/Qsys/hps_design/synthesis/submodules/hps_sdram_p0_iss_probe.v | 1,740 | module MODULE1 (
VAR22
);
parameter VAR18 = 1;
parameter VAR5 = "VAR9";
input [VAR18-1:0] VAR22;
VAR4 VAR12 (
.VAR23 (VAR22),
.VAR11 ()
,
.VAR25 (),
.VAR31 (),
.VAR3 (),
.VAR17 (),
.VAR26 (),
.VAR8 (),
.VAR21 (),
.VAR29 (),
.VAR33 (),
.VAR19 (),
.VAR20 (),
.VAR1 (),
.VAR27 (),
.VAR24 (),
.VAR10 (),
.VAR13 (),
.VAR32 ()... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_pwrgood_pp_g/sky130_fd_sc_hvl__udp_pwrgood_pp_g.symbol.v | 1,289 | module MODULE1 (
input VAR2 ,
output VAR3,
input VAR1
);
endmodule | apache-2.0 |
JakeMercer/mac | MAC/rtl/mac/mac_fifo/mac_fifo.v | 7,866 | module MODULE1 #(
parameter VAR5 = 32,
parameter VAR24 = 8,
parameter VAR21 = 12
)(
input wire reset,
input wire [VAR5-1:0] VAR2,
input wire VAR37,
input wire VAR28,
input wire VAR25,
input wire VAR6,
output wire [VAR24-1:0] VAR26,
input wire VAR34,
input wire VAR1,
output wire VAR20,
output wire VAR30,
input wire VAR1... | mit |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_no_overflow.v | 1,508 | module MODULE1 (VAR5, reset, enable, VAR19, VAR3);
parameter VAR11 = VAR24;
parameter VAR12 = 1;
parameter VAR4 = 0;
parameter VAR16 = ((1<<VAR12)-1);
parameter VAR15 = VAR9;
parameter VAR2 = VAR1;
parameter VAR13 = VAR17;
parameter VAR18 = VAR21;
parameter VAR14 = VAR23;
parameter VAR6 = VAR7;
input VAR5, reset, enabl... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211o/sky130_fd_sc_ls__a211o.behavioral.pp.v | 2,032 | module MODULE1 (
VAR5 ,
VAR17 ,
VAR3 ,
VAR6 ,
VAR4 ,
VAR13,
VAR11,
VAR2 ,
VAR10
);
output VAR5 ;
input VAR17 ;
input VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR13;
input VAR11;
input VAR2 ;
input VAR10 ;
wire VAR12 ;
wire VAR16 ;
wire VAR14;
and VAR15 (VAR12 , VAR17, VAR3 );
or VAR7 (VAR16 , VAR12, VAR4, VAR6 );
VAR8 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp.blackbox.v | 1,448 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR7 ,
VAR6 ,
VAR4 ,
VAR3
);
output VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR4 ;
input VAR3;
supply1 VAR2;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_gtx_es_if.v | 27,440 | module MODULE1 (
VAR56,
VAR49,
VAR15,
VAR7,
VAR35,
VAR66,
VAR55,
VAR4,
VAR71,
VAR36,
VAR44,
VAR41,
VAR27,
VAR92,
VAR64,
VAR23,
VAR58,
VAR2,
VAR48,
VAR34,
VAR50,
VAR81,
VAR38,
VAR62);
input VAR56;
input VAR49;
input VAR15;
input VAR7;
input [ 4:0] VAR35;
input [11:0] VAR66;
input [11:0] VAR55;
input [11:0] VAR4;
input [... | mit |
rohit91/novena-sd-fpga | novena-sd.srcs/sources_1/ip/clk_wiz_v3_5_0/bclk_dll.v | 5,772 | module MODULE1
( input VAR17,
output VAR21,
input VAR9,
output VAR39
);
assign VAR23 = VAR17;
wire VAR32;
wire VAR45;
wire [7:0] VAR18;
wire VAR40;
wire VAR1;
wire VAR37;
VAR12
.VAR29 (2),
.VAR6 (2),
.VAR14 ("VAR27"),
.VAR33 (7.518),
.VAR15 ("VAR43"),
.VAR42 ("VAR43"),
.VAR44 ("VAR25"),
.VAR3 (0),
.VAR47 ("VAR27"))
VAR... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_rf.v | 10,015 | module MODULE1(
clk, rst,
VAR48, VAR22, VAR55, VAR52, VAR41, VAR34,
VAR10, VAR5, VAR11, VAR19, VAR23, VAR36, VAR40,
VAR8, VAR39, VAR45, VAR32, VAR49
);
parameter VAR7 = VAR30;
parameter VAR35 = VAR51;
input clk;
input rst;
input VAR48;
input VAR22;
input [VAR35-1:0] VAR55;
input [VAR7-1:0] VAR52;
input VAR41;
input VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxbp/sky130_fd_sc_hd__dfxbp.functional.pp.v | 1,767 | module MODULE1 (
VAR13 ,
VAR14 ,
VAR8 ,
VAR9 ,
VAR2,
VAR3,
VAR12 ,
VAR1
);
output VAR13 ;
output VAR14 ;
input VAR8 ;
input VAR9 ;
input VAR2;
input VAR3;
input VAR12 ;
input VAR1 ;
wire VAR4;
VAR11 VAR7 VAR10 (VAR4 , VAR9, VAR8, , VAR2, VAR3);
buf VAR5 (VAR13 , VAR4 );
not VAR6 (VAR14 , VAR4 );
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/fpu/hardlogic/fir.v | 2,620 | module MODULE1(VAR43,
reset,
VAR52,
VAR16,
VAR51,
VAR8,
VAR26,
out
);
input VAR43;
input reset;
input [VAR3-1:0] VAR52;
input [VAR3-1:0] VAR16;
input [VAR3-1:0] VAR51;
input [VAR3-1:0] VAR8;
input [VAR3-1:0] VAR26;
output [VAR3-1:0] out;
wire [VAR3-1:0] VAR48;
wire [VAR3-1:0] VAR4;
wire [VAR3-1:0] VAR25;
wire [VAR3-1:0... | mit |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/dual_ps2_ioadapter_v1_00_a/hdl/verilog/dual_ps2_ioadapter.v | 2,703 | module MODULE1 (
VAR17, VAR13, VAR1, VAR11, VAR12, VAR18, VAR2, VAR4, VAR14, VAR15, VAR10, VAR5, VAR3, VAR16, VAR8, VAR6, VAR19, VAR9, VAR20, VAR7 );
output VAR17;
output VAR13;
input VAR1;
input VAR11;
output VAR12;
output VAR18;
input VAR2;
input VAR4;
input VAR14;
output VAR15;
output VAR10;
input VAR5;
output VAR3;... | gpl-3.0 |
zhangly/azpr_cpu | rtl/bus/rtl/bus.v | 7,599 | module MODULE1 (
input wire clk, input wire reset,
output wire [VAR58] VAR9, output wire VAR4, input wire VAR35, input wire [VAR53] VAR36, input wire VAR47, input wire VAR3, input wire [VAR58] VAR29, output wire VAR38, input wire VAR52, input wire [VAR53] VAR8, input wire VAR22, input wire VAR30, input wire [VAR58] VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.behavioral.pp.v | 1,167 | module MODULE1( VAR4, VAR3, VAR5, VAR1 );
input VAR4;
inout VAR5, VAR1;
output VAR3;
VAR6 VAR7(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5),.VAR1(VAR1));
VAR6 VAR2(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.behavioral.pp.v | 1,316 | module MODULE1( VAR8, VAR6, VAR3, VAR9, VAR7, VAR4 );
input VAR8, VAR6, VAR3;
inout VAR7, VAR4;
output VAR9;
VAR5 VAR1(.VAR8(VAR8),.VAR6(VAR6),.VAR3(VAR3),.VAR9(VAR9),.VAR7(VAR7),.VAR4(VAR4));
VAR5 VAR2(.VAR8(VAR8),.VAR6(VAR6),.VAR3(VAR3),.VAR9(VAR9),.VAR7(VAR7),.VAR4(VAR4)); | apache-2.0 |
martinmiranda14/Digitales | Lab_6/clkdiv/clkdiv.cache/ip/cdfdc0ad26be34f0/clk_wiz_0_stub.v | 1,305 | module MODULE1(VAR1, reset, VAR2, VAR3)
;
output VAR1;
input reset;
output VAR2;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b.behavioral.pp.v | 1,978 | module MODULE1 (
VAR2 ,
VAR17 ,
VAR15 ,
VAR3 ,
VAR7 ,
VAR4,
VAR5,
VAR8 ,
VAR9
);
output VAR2 ;
input VAR17 ;
input VAR15 ;
input VAR3 ;
input VAR7 ;
input VAR4;
input VAR5;
input VAR8 ;
input VAR9 ;
wire VAR13 ;
wire VAR1 ;
wire VAR14;
not VAR12 (VAR13 , VAR7 );
or VAR10 (VAR1 , VAR13, VAR3, VAR15, VAR17 );
VAR16 VAR11... | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/bench/verilog/eth_phy.v | 41,421 | module MODULE1 (
VAR54,
VAR28,
VAR62,
VAR22,
VAR35,
VAR37,
VAR44,
VAR17,
VAR63,
VAR12,
VAR59,
VAR26,
VAR60,
VAR15
);
input VAR54;
output VAR28;
input [3:0] VAR62;
input VAR22;
input VAR35;
output VAR37;
output [3:0] VAR44;
output VAR17;
output VAR63;
output VAR12;
output VAR59;
input VAR26;
inout VAR60;
input [31:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3.pp.blackbox.v | 1,330 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR2 ,
VAR3 ,
VAR1,
VAR7,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR3 ;
input VAR1;
input VAR7;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Add-Subt/shift_mux.v | 1,224 | module MODULE1
(
input wire [VAR14-1:0] VAR4,
input wire VAR3,
input wire VAR12,
output wire [VAR14-1:0] VAR8
);
genvar VAR13;
generate for (VAR13=0; VAR13<=VAR14-1 ; VAR13=VAR13+1) begin
localparam VAR5=(2**VAR15)+VAR13;
case (VAR5>VAR14-1)
1'b1:begin
VAR11 #(.VAR9(1)) VAR6(
.VAR7(VAR3),
.VAR1 (VAR4[VAR13]),
.VAR10 (V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp.functional.v | 1,245 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
wire VAR3;
not VAR5 (VAR3, VAR4 );
buf VAR1 (VAR2 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4_4.v | 2,275 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR10,
VAR3,
VAR9 ,
VAR7
);
output VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR10;
input VAR3;
input VAR9 ;
input VAR7 ;
VAR11 VAR8 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor3/sky130_fd_sc_lp__xnor3.functional.pp.v | 1,828 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR13 ,
VAR14 ,
VAR5,
VAR10,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR12 ;
input VAR13 ;
input VAR14 ;
input VAR5;
input VAR10;
input VAR7 ;
input VAR2 ;
wire VAR11 ;
wire VAR1;
xnor VAR3 (VAR11 , VAR12, VAR13, VAR14 );
VAR4 VAR9 (VAR1, VAR11, VAR5, VAR10);
buf VAR6 (VAR8 , VAR1 );
endmodul... | apache-2.0 |
Tao-J/nexys3MIPSSoC | mux4to1_5.v | 1,074 | module MODULE1(
input wire sel,
input wire [4:0] VAR1,
input wire [4:0] VAR4,
input wire [4:0] VAR5,
input wire [4:0] VAR3,
output reg [4:0] VAR2
);
always @(*)
case(sel)
2'b00: VAR2<=VAR1;
2'b01: VAR2<=VAR4;
2'b10: VAR2<=VAR5;
2'b11: VAR2<=VAR3;
endcase
endmodule | gpl-3.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/amber25/a25_alu.v | 7,554 | module MODULE1 (
input [31:0] VAR9,
input [31:0] VAR10,
input VAR4,
input VAR12,
input [8:0] VAR21,
output [31:0] VAR26,
output [3:0] VAR29
);
wire [31:0] VAR35, VAR15, VAR27;
wire [31:0] VAR14, VAR32, VAR30;
wire [31:0] VAR24, VAR33;
wire [31:0] VAR28, VAR13;
wire [32:0] VAR19;
wire VAR18;
wire VAR1;
wire [1:0] VAR11;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/diode/sky130_fd_sc_hd__diode.symbol.v | 1,245 | module MODULE1 (
input VAR5
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n.pp.symbol.v | 1,371 | module MODULE1 (
input VAR3 ,
output VAR7 ,
input VAR1,
input VAR4 ,
input VAR5 ,
input VAR2 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3/sky130_fd_sc_hd__nor3_4.v | 2,198 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR2 ,
VAR4 ,
VAR5,
VAR1,
VAR10 ,
VAR6
);
output VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR5;
input VAR1;
input VAR10 ;
input VAR6 ;
VAR9 VAR3 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_gcd_0_0/gcd_zynq_snick_gcd_0_0_stub.v | 2,724 | module MODULE1(VAR1,
VAR2, VAR9, VAR7, VAR4,
VAR6, VAR15, VAR14, VAR12,
VAR8, VAR11, VAR5,
VAR10, VAR3, VAR19, VAR13,
VAR18, VAR16, VAR17, interrupt)
;
input [5:0]VAR1;
input VAR2;
output VAR9;
input [31:0]VAR7;
input [3:0]VAR4;
input VAR6;
output VAR15;
output [1:0]VAR14;
output VAR12;
input VAR8;
input [5:0]VAR11;
in... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/shift_mux.v | 1,223 | module MODULE1
(
input wire [VAR5-1:0] VAR2,
input wire VAR12,
input wire VAR8,
output wire [VAR5-1:0] VAR4
);
genvar VAR10;
localparam integer VAR3 = 2**(VAR9);
localparam integer VAR6 = (VAR5 - 1);
generate for (VAR10=0; VAR10<=VAR5-1 ; VAR10=VAR10+1) begin : VAR1
localparam integer VAR11=(2**VAR9)+VAR10;
case ((VAR3... | gpl-3.0 |
brysonli12/CS152A-Lab4-TicTacToe | VGA/clockdiv.v | 1,731 | module MODULE1(
input wire clk, input wire rst, output wire VAR4, output wire VAR3, output wire VAR2, output wire VAR5 );
reg [17:0] VAR1;
always @(posedge clk)
begin
if (rst == 1)
VAR1 <= 0;
end
else
VAR1 <= VAR1+1;
end
assign VAR4 = VAR1[15] & ~VAR1[14] & ~VAR1[13] & ~VAR1[12] & ~VAR1[11] & ~VAR1[10] & ~VAR1[9] & ~VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.v | 2,175 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR2,
VAR4,
VAR1 ,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR8 ;
input VAR2;
input VAR4;
input VAR1 ;
input VAR7 ;
input VAR5 ;
VAR9 VAR3 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR6 ,
VAR8 ,
VAR2
);
output VAR6... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2b/sky130_fd_sc_ls__and2b.functional.pp.v | 1,934 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR6 ,
VAR5,
VAR14,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR10 ;
input VAR6 ;
input VAR5;
input VAR14;
input VAR9 ;
input VAR3 ;
wire VAR13 ;
wire VAR8 ;
wire VAR4;
not VAR15 (VAR13 , VAR10 );
and VAR12 (VAR8 , VAR13, VAR6 );
VAR2 VAR1 (VAR4, VAR8, VAR5, VAR14);
buf VAR11 (VAR7 , VAR4 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxtp/sky130_fd_sc_hvl__dfxtp.pp.blackbox.v | 1,283 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2 ,
VAR3,
VAR1,
VAR7 ,
VAR6
);
output VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR3;
input VAR1;
input VAR7 ;
input VAR6 ;
endmodule | apache-2.0 |
Willster419/ELEC3725_vivado_projects | assignment_8_p2_final/ARMS_phase1-3.v | 32,364 | module MODULE2(VAR49,clk,VAR134,VAR5,reset,VAR98);
input clk;
input reset;
output [63:0] VAR98; wire [63:0] VAR10; wire [63:0] VAR63; wire [63:0] VAR46; reg [1:0] VAR51;
wire [1:0] VAR120;
wire [1:0] VAR107;
wire VAR97; wire [63:0] VAR20; wire [63:0] VAR40;
wire [63:0] VAR101;
wire VAR86;
wire VAR95;
reg [2:0] VAR117;
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.functional.v | 1,158 | module MODULE1( VAR12, VAR6, VAR3 );
input VAR6, VAR12;
output VAR3;
wire VAR10;
and VAR11( VAR10, VAR6, VAR12 );
wire VAR7;
not VAR2( VAR7, VAR6 );
wire VAR5;
not VAR4( VAR5, VAR12 );
wire VAR9;
and VAR8( VAR9, VAR7, VAR5 );
or VAR1( VAR3, VAR10, VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211a/sky130_fd_sc_hd__o211a.pp.blackbox.v | 1,389 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR7 ,
VAR5,
VAR3,
VAR4 ,
VAR9
);
output VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR7 ;
input VAR5;
input VAR3;
input VAR4 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/decap/sky130_fd_sc_ms__decap.functional.pp.v | 1,172 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v | 144,797 | module MODULE1 #
(
parameter VAR229 = 100, parameter VAR319 = 2, parameter VAR274 = 3333, parameter VAR57 = 64, parameter VAR153 = 3, parameter VAR158 = 8, parameter VAR5 = 8, parameter VAR191 = 1, parameter VAR92 = "VAR270", parameter VAR40 = "VAR102", parameter VAR173 = "VAR168", parameter VAR389 = "VAR315", paramete... | lgpl-3.0 |
freecores/orsoc_graphics_accelerator | bench/verilog/gfx/clip_bench.v | 4,430 | module MODULE1();
parameter VAR28 = 16;
reg VAR2;
reg VAR17;
reg VAR25;
reg VAR15;
reg [31:2] VAR23;
reg [VAR28-1:0] VAR14;
reg [VAR28-1:0] VAR18;
reg [VAR28-1:0] VAR22;
reg [VAR28-1:0] VAR4;
reg [VAR28-1:0] VAR32;
reg [VAR28-1:0] VAR36;
reg [VAR28-1:0] VAR29;
reg [VAR28-1:0] VAR13;
reg [VAR28-1:0] VAR6;
reg [VAR28-1:0... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.functional.v | 1,043 | module MODULE1( VAR13, VAR10, VAR11, VAR2 );
input VAR2, VAR10, VAR11;
output VAR13;
wire VAR7;
and VAR6( VAR7, VAR2, VAR10 );
wire VAR4;
not VAR12( VAR4, VAR11 );
wire VAR8;
and VAR3( VAR8, VAR4, VAR2 );
wire VAR9;
and VAR5( VAR9, VAR10, VAR11 );
or VAR1( VAR13, VAR7, VAR8, VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf_8.v | 1,993 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR4,
VAR6,
VAR2 ,
VAR3
);
output VAR7 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR2 ;
input VAR3 ;
VAR8 VAR1 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR7,
VAR5
);
output VAR7;
input VAR5;
supply1 VAR4;
supply0 VAR6;... | apache-2.0 |
wicker/SystemVerilog-FSM | landing-gear-controller/verilog/LandingGear.v | 4,053 | module MODULE1(VAR9, VAR3,
VAR21, VAR2, VAR13, VAR4, VAR27,
VAR23, VAR18, VAR7, VAR1, VAR17);
input VAR9, VAR3, VAR21, VAR2, VAR13, VAR4, VAR27;
output VAR23, VAR18, VAR7, VAR1, VAR17;
reg VAR23, VAR18, VAR7, VAR1, VAR17;
parameter VAR24 = 1'b1;
parameter VAR8 = 1'b1;
parameter VAR16 = 1'b1;
parameter VAR26 = 1'b1;
par... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/tieh/gf180mcu_fd_sc_mcu7t5v0__tieh.behavioral.pp.v | 1,084 | module MODULE1( VAR2, VAR3, VAR5 );
inout VAR3, VAR5;
output VAR2;
VAR6 VAR1(.VAR2(VAR2),.VAR3(VAR3),.VAR5(VAR5));
VAR6 VAR4(.VAR2(VAR2),.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
kwantam/multiexp-a5gx | verilog/modmult.v | 31,681 | module MODULE1 #( parameter VAR89 = 4
, parameter VAR16 = 27
, parameter VAR102 = 1 , parameter VAR101 = 0 , parameter VAR114 = 0 , parameter VAR7 = 0
, parameter VAR97 = 0
, parameter VAR21 = VAR75(VAR89) , parameter VAR119 = 2*VAR16 + VAR21 + VAR102 + 1 , parameter VAR36 = 2*VAR16 + VAR21 , parameter VAR115 = 2*VAR89... | gpl-3.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_image_filter_1_0/synth/design_1_image_filter_1_0.v | 9,868 | module MODULE1 (
VAR30,
VAR20,
VAR10,
VAR17,
VAR29,
VAR1,
VAR6,
VAR23,
VAR35,
VAR13,
VAR3,
VAR36,
VAR22,
VAR40,
VAR33,
VAR38,
VAR5,
VAR27,
VAR37,
interrupt,
VAR41,
VAR8,
VAR14,
VAR15,
VAR18,
VAR34,
VAR11,
VAR28,
VAR24,
VAR2,
VAR31,
VAR39,
VAR21,
VAR12,
VAR19,
VAR16,
VAR4,
VAR32
);
input wire [5 : 0] VAR30;
input wire V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.v | 2,358 | module MODULE2 (
VAR1 ,
VAR8,
VAR4 ,
VAR7 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR9
);
output VAR1 ;
input VAR8;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
VAR10 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.v | 2,262 | module MODULE1 (
VAR6,
VAR5 ,
VAR10,
VAR1 ,
VAR7,
VAR8,
VAR3 ,
VAR9
);
output VAR6;
input VAR5 ;
input VAR10;
input VAR1 ;
input VAR7;
input VAR8;
input VAR3 ;
input VAR9 ;
VAR4 VAR2 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/ccx_arbdp.v | 21,809 | module MODULE1(
VAR108, VAR12, VAR84,
VAR103, VAR57, VAR92,
VAR56, VAR46, VAR96,
VAR130, VAR85, VAR133, VAR151,
VAR93,
VAR147, VAR129, VAR27,
VAR115, VAR45, VAR110,
VAR139, VAR116, VAR126, VAR120,
VAR54, VAR8, VAR114, VAR65,
VAR2, VAR149, VAR31, VAR90, VAR26,
VAR100, VAR76, VAR123, VAR150,
VAR40, VAR25, VAR88, VAR69, V... | gpl-2.0 |
benreynwar/fpga-sdrlib | verilog/channelizer/dut_channelizer.v | 1,119 | module MODULE1;
reg clk;
reg VAR5;
reg [VAR13-1:0] VAR2;
reg VAR14;
reg [VAR16-1:0] VAR4;
reg [VAR6-1:0] VAR15;
reg VAR11;
wire [VAR13-1:0] VAR1;
wire VAR9;
wire [VAR16-1:0] VAR3;
wire [VAR6-1:0] VAR10;
wire VAR8;
wire VAR7;
wire VAR12; | mit |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | lfsr_fb.v | 16,782 | module MODULE1
assign VAR1 = (VAR2==2 ) ? !(VAR3[2 ]^VAR3[1 ] ) :
(VAR2==3 ) ? !(VAR3[3 ]^VAR3[2 ] ) :
(VAR2==4 ) ? !(VAR3[4 ]^VAR3[3 ] ) :
(VAR2==5 ) ? !(VAR3[5 ]^VAR3[3 ] ) :
(VAR2==6 ) ? !(VAR3[6 ]^VAR3[5 ] ) :
(VAR2==7 ) ? !(VAR3[7 ]^VAR3[6 ] ) :
(VAR2==8 ) ? !(VAR3[8 ]^VAR3[6 ]^VAR3[5 ]^VAR3[4 ] ) :
(VAR2==9 ) ? !... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.behavioral.v | 1,108 | module MODULE1( VAR3, VAR1 );
input VAR3;
output VAR1;
VAR4 VAR5(.VAR3(VAR3),.VAR1(VAR1));
VAR4 VAR2(.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
GSejas/Karatsuba_FPU | my_sourcefiles/cordic_jorge/CORDIC_Arch3.v | 21,880 | module MODULE1 #(parameter VAR97 = 32, parameter VAR31 = 8, parameter VAR106 = 23, parameter VAR60=26, parameter VAR19 = 5)/*#(parameter VAR97 = 64, parameter VAR31 = 11, parameter VAR106 = 52, parameter VAR60 = 55, parameter VAR19 = 6) (
input wire clk, input wire rst, input wire VAR121, input wire VAR138, input wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32oi/sky130_fd_sc_hs__a32oi.behavioral.pp.v | 2,139 | module MODULE1 (
VAR7,
VAR18,
VAR1 ,
VAR3 ,
VAR13 ,
VAR11 ,
VAR12 ,
VAR6
);
input VAR7;
input VAR18;
output VAR1 ;
input VAR3 ;
input VAR13 ;
input VAR11 ;
input VAR12 ;
input VAR6 ;
wire VAR12 VAR10 ;
wire VAR12 VAR4 ;
wire VAR15 ;
wire VAR14;
nand VAR2 (VAR10 , VAR13, VAR3, VAR11 );
nand VAR8 (VAR4 , VAR6, VAR12 );
a... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.functional.pp.v | 1,867 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR12,
VAR11,
VAR4 ,
VAR6
);
output VAR8 ;
input VAR1 ;
input VAR12;
input VAR11;
input VAR4 ;
input VAR6 ;
wire VAR3 ;
wire VAR7;
not VAR5 (VAR3 , VAR1 );
VAR10 VAR2 (VAR7, VAR3, VAR12, VAR11);
buf VAR9 (VAR8 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp.pp.blackbox.v | 1,236 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3 ,
VAR2,
VAR5
);
input VAR1 ;
input VAR4 ;
output VAR3 ;
input VAR2;
input VAR5;
endmodule | apache-2.0 |
grindars/bfcore | BrainfuckCPU.v | 5,563 | module MODULE1(
VAR57, VAR2,
VAR14, VAR28, VAR20,
VAR70, VAR67, VAR21, VAR71, VAR11,
VAR51, VAR68, VAR10, VAR15, VAR69, VAR53
);
parameter VAR24 = 1;
parameter VAR56 = 11;
parameter VAR1 = 11;
parameter VAR49 = 8;
parameter VAR50 = 7;
input VAR57;
input VAR2;
output reg [VAR56 - 1:0] VAR14;
input [7:0] VAR28;
output re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha.pp.blackbox.v | 1,276 | module MODULE1 (
VAR5,
VAR2 ,
VAR7 ,
VAR8 ,
VAR1,
VAR4,
VAR3 ,
VAR6
);
output VAR5;
output VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlxtp/sky130_fd_sc_lp__srdlxtp.behavioral.pp.v | 1,958 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR16 ,
VAR10,
VAR2 ,
VAR12 ,
VAR8 ,
VAR4 ,
VAR9
);
output VAR3 ;
input VAR5 ;
input VAR16 ;
input VAR10;
input VAR2 ;
input VAR12 ;
input VAR8 ;
input VAR4 ;
input VAR9 ;
wire VAR17 ;
wire VAR13;
wire VAR6 ;
reg VAR14 ;
wire VAR1 ;
VAR7 VAR15 (VAR17 , VAR6, VAR13, VAR10, VAR14, VAR2, VAR... | apache-2.0 |
marmolejo/zet | cores/ps2/rtl/ps2_keyb_xtcodes.v | 1,330 | module MODULE1 (
input [6:0] VAR3,
output [6:0] VAR2
);
reg [7:0] VAR1[0:2**7-1];
assign VAR2 = VAR1[VAR3][6:0]; | gpl-3.0 |
nyaxt/dmix | nkmd/arch/nkmd_dai_tx_t.v | 2,229 | module MODULE1;
reg clk;
parameter VAR15 = 20;
VAR11 clk = 0;
always #(VAR15/2) clk = ~clk;
reg rst;
reg VAR14;
reg [31:0] VAR8;
wire [31:0] VAR4;
reg [31:0] VAR7;
reg VAR6;
VAR5 VAR3(
.clk(clk),
.rst(rst),
.VAR2(VAR14),
.VAR18(VAR8),
.VAR16(VAR4),
.VAR10(VAR7),
.VAR13(VAR6));
task VAR17;
input wire [23:0] VAR1;
begin
... | mit |
sh-chris110/chris | FPGA/atlas_linux_ghrd/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v | 6,176 | module MODULE1 #(
parameter VAR5 = 34,
parameter VAR2 = 0,
parameter VAR8 = 34,
parameter VAR25 = 0,
parameter VAR7 = 0,
parameter VAR9 = 0,
parameter VAR6 = 1,
parameter VAR3 = 1,
parameter VAR1 = 0,
parameter VAR21 = 34,
parameter VAR24 = 0,
parameter VAR14 = 1,
parameter VAR11 = 0,
parameter VAR4 = 1,
parameter VAR1... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/vrt/vita_tx_control.v | 6,292 | module MODULE1
parameter VAR36=32)
(input clk, input reset, input VAR43,
input VAR4, input [7:0] VAR21, input [31:0] VAR18,
input [63:0] VAR31,
output VAR56, output ack,
output reg [31:0] VAR30,
output reg VAR33,
input [5+64+16+VAR36-1:0] VAR14,
input VAR13,
output VAR29,
output [VAR36-1:0] VAR1,
output reg VAR11,
inpu... | gpl-2.0 |
myriadrf/A2300 | hdl/wca/WcaDspCounter.v | 1,153 | module MODULE1(
input VAR5,
input reset, input VAR8, input VAR1, input VAR9, output VAR7 );
parameter VAR4 = 24;
wire VAR5, reset, VAR8, VAR9;
wire [VAR4 : 0] VAR1;
wire [VAR4 : 0] VAR7;
VAR10 ( .clk(VAR5), .VAR2( VAR8), .VAR9( VAR9 | reset), .VAR3( VAR1), .VAR6( VAR7) );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_hvc_wpad/sky130_fd_io__top_ground_hvc_wpad.pp.blackbox.v | 1,866 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR15 ,
VAR16 ,
VAR13 ,
VAR1,
VAR10 ,
VAR6 ,
VAR12 ,
VAR17 ,
VAR4 ,
VAR2 ,
VAR11 ,
VAR7 ,
VAR14 ,
VAR9 ,
VAR5
);
inout VAR3 ;
inout VAR8 ;
inout VAR15 ;
inout VAR16 ;
inout VAR13 ;
inout VAR1;
inout VAR10 ;
inout VAR6 ;
inout VAR12 ;
inout VAR17 ;
inout VAR4 ;
inout VAR2 ;
inout VAR11 ;
i... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2oi/sky130_fd_sc_hd__a2bb2oi.functional.pp.v | 2,245 | module MODULE1 (
VAR18 ,
VAR19,
VAR10,
VAR16 ,
VAR14 ,
VAR15,
VAR7,
VAR12 ,
VAR11
);
output VAR18 ;
input VAR19;
input VAR10;
input VAR16 ;
input VAR14 ;
input VAR15;
input VAR7;
input VAR12 ;
input VAR11 ;
wire VAR17 ;
wire VAR6 ;
wire VAR1 ;
wire VAR4;
and VAR3 (VAR17 , VAR16, VAR14 );
nor VAR13 (VAR6 , VAR19, VAR10 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2_2.v | 2,132 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR3 ,
VAR6,
VAR8,
VAR9 ,
VAR2
);
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR6;
input VAR8;
input VAR9 ;
input VAR2 ;
VAR4 VAR5 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR7,
VAR1,
VAR3
);
output VAR7;
... | apache-2.0 |
arthurafarias/UFCG-EE-LASD-2014.1-Experiments | preparacao-2.stable/Datapath_RegisterFile.v | 1,086 | module MODULE1( output reg [VAR8-1:0] VAR6, VAR5, input [VAR8-1:0] VAR4, input [2:0] VAR1, VAR2, VAR11, input VAR7, VAR3 );
parameter VAR8 = 16;
reg [VAR8-1:0] VAR10[7:0];
always@(posedge VAR3)
if(VAR7)
case(VAR11)
3'VAR9 000 : VAR10[0] = VAR4;
3'VAR9 001 : VAR10[1] = VAR4;
3'VAR9 010 : VAR10[2] = VAR4;
3'VAR9 011 : VA... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_1.behavioral.v | 2,848 | module MODULE1( VAR15, VAR19, VAR12, VAR14 );
input VAR19, VAR15, VAR12;
output VAR14;
reg VAR21;
VAR4 VAR13(.VAR15(VAR15),.VAR19(VAR19),.VAR12(VAR12),.VAR14(VAR14),.VAR21(VAR21));
VAR4 VAR10(.VAR15(VAR15),.VAR19(VAR19),.VAR12(VAR12),.VAR14(VAR14),.VAR21(VAR21));
buf VAR16(VAR23,VAR12);
not VAR11(VAR1,VAR19);
and VAR20... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_gtp_pipe_reset.v | 19,950 | module MODULE1 #
(
parameter VAR3 = "VAR61", parameter VAR45 = 1, parameter VAR14 = 6'd63, parameter VAR33 = 1
)
(
input VAR23,
input VAR70,
input VAR41,
input VAR27,
input [VAR45-1:0] VAR55,
input [VAR45-1:0] VAR15,
input VAR10,
input [VAR45-1:0] VAR54,
input [VAR45-1:0] VAR66,
input VAR71,
input [VAR45-1:0] VAR16,
in... | gpl-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_cx4/spi.v | 3,201 | module MODULE1(
input clk,
input VAR28,
input VAR14,
inout VAR8,
input VAR5,
output VAR17,
output VAR2,
output [7:0] VAR30,
output [7:0] VAR21,
output VAR13,
output VAR20,
input [7:0] VAR22,
output [31:0] VAR29,
output [2:0] VAR26
);
reg [7:0] VAR15;
reg [7:0] VAR16;
reg [2:0] VAR7;
reg [2:0] VAR9;
always @(posedge clk... | gpl-2.0 |
ppnipuna/EDAC_ASIC_Design | rtl/edac_top.v | 1,074 | module MODULE1 (clk, VAR2,VAR14,VAR9,VAR11,VAR5,VAR18,VAR12,VAR16, VAR6,
VAR4);
parameter VAR10 = 128;
parameter VAR7 = 9;
input wire clk, VAR2,VAR14,VAR9;
input wire [VAR10:1] VAR11;
output wire [VAR10:1] VAR5;
output wire [VAR7:1] VAR18;
output wire [VAR10:1] VAR12;
output wire VAR16, VAR6;
input wire [VAR10+VAR7:1] ... | mit |
sstallion/apple-mini | cpld/addr_decode.v | 1,781 | module MODULE1(input [3:0] addr,
output VAR1, VAR3, VAR4, VAR5, VAR2, VAR6);
assign VAR5 = !(addr <= 4'b0111); assign VAR4 = !(addr == 4'b1010); assign VAR3 = !(addr == 4'b1011); assign VAR1 = !(addr == 4'b1100); assign VAR6 = !(addr == 4'b1101); assign VAR2 = !(addr >= 4'b1110); endmodule | bsd-2-clause |
ncos/Xilinx-Verilog | GYRACC/src/ACC/sel_data.v | 3,009 | module MODULE1(
VAR2,
VAR6,
VAR7,
VAR1,
VAR4,
VAR8,
VAR3,
VAR5
);
input VAR2;
input VAR6;
input [1:0] VAR7;
input [9:0] VAR1;
input [9:0] VAR4;
input [9:0] VAR8;
output [9:0] VAR3;
output [2:0] VAR5;
reg [9:0] VAR3;
reg [2:0] VAR5;
always @(posedge VAR2 or posedge VAR6)
if (VAR6 == 1'b1)
begin
VAR5 <= 3'b000;
VAR3 <= 1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4.pp.blackbox.v | 1,322 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR9 ,
VAR2 ,
VAR7 ,
VAR3,
VAR5,
VAR6 ,
VAR4
);
output VAR8 ;
input VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR3;
input VAR5;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/dependencies/ppfifo.v | 18,905 | module MODULE1
VAR56 = 4
)(
input reset,
input VAR57,
output reg [1:0] VAR55,
input [1:0] VAR1,
output [23:0] VAR20,
input VAR39,
input [VAR47 - 1: 0] VAR34,
output VAR53,
input VAR44,
input VAR9,
output reg VAR6,
input VAR33,
output reg [23:0] VAR16,
output [VAR47 - 1: 0] VAR10,
output VAR4
);
localparam VAR41 = (1 <<... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp.pp.symbol.v | 1,506 | module MODULE1 (
input VAR9 ,
output VAR7 ,
output VAR8 ,
input VAR1,
input VAR4 ,
input VAR5 ,
input VAR6 ,
input VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
hcabrera-/lancetfish | RTL/nodo_frontera/rtl/nodo_frontera.v | 11,980 | module MODULE1 #(
parameter VAR8 = 2,
parameter VAR3 = 2,
parameter VAR28 = 2,
parameter VAR44 = 2
)
(
input wire clk,
input wire reset,
input wire [VAR2-1:0] VAR29,
output wire VAR40,
output wire [VAR2-1:0] VAR1,
input wire VAR6
);
localparam VAR18 = VAR50(VAR36);
localparam VAR13 = VAR50(VAR4/5);
localparam VAR10 = 1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb_1.v | 2,334 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR7 ,
VAR3 ,
VAR6 ,
VAR10,
VAR8,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR6 ;
input VAR10;
input VAR8;
input VAR1 ;
input VAR5 ;
VAR11 VAR4 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b.functional.pp.v | 1,971 | module MODULE1 (
VAR10 ,
VAR13 ,
VAR5 ,
VAR12 ,
VAR16,
VAR7,
VAR3 ,
VAR4
);
output VAR10 ;
input VAR13 ;
input VAR5 ;
input VAR12 ;
input VAR16;
input VAR7;
input VAR3 ;
input VAR4 ;
wire VAR11 ;
wire VAR15 ;
wire VAR1;
not VAR14 (VAR11 , VAR13 );
nand VAR9 (VAR15 , VAR5, VAR11, VAR12 );
VAR6 VAR8 (VAR1, VAR15, VAR16, ... | apache-2.0 |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/soc_system_hps_hps_io.v | 10,557 | module MODULE1 (
output wire [14:0] VAR21, output wire [2:0] VAR51, output wire VAR30, output wire VAR9, output wire VAR18, output wire VAR44, output wire VAR59, output wire VAR62, output wire VAR29, output wire VAR24, inout wire [31:0] VAR32, inout wire [3:0] VAR8, inout wire [3:0] VAR52, output wire VAR28, output wir... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_processing_system7_0_0/zybo_zynq_design_processing_system7_0_0_stub.v | 5,488 | module MODULE1(VAR27, VAR50, VAR38,
VAR13, VAR6, VAR17, VAR46,
VAR3, VAR1, VAR26, VAR10,
VAR49, VAR53, VAR59, VAR60, VAR64,
VAR54, VAR9, VAR24, VAR22,
VAR65, VAR56, VAR42, VAR31, VAR63,
VAR23, VAR25, VAR19, VAR21, VAR36,
VAR18, VAR68, VAR29, VAR39, VAR16,
VAR33, VAR34, VAR47, VAR28,
VAR48, VAR44, VAR62, VAR7, VAR57,
VA... | mit |
efabless/openlane | designs/usb_cdc_core/src/usb_desc_rom.v | 7,377 | module MODULE1
(
input VAR3,
input [7:0] VAR2,
output [7:0] VAR1
);
reg [7:0] VAR4;
always @ *
begin
case (VAR2)
8'd0: VAR4 = 8'h12;
8'd1: VAR4 = 8'h01;
8'd2: VAR4 = 8'h00;
8'd3: VAR4 = 8'h02;
8'd4: VAR4 = 8'h02;
8'd5: VAR4 = 8'h00;
8'd6: VAR4 = 8'h00;
8'd7: VAR4 = VAR3 ? 8'h40 : 8'h08;
8'd8: VAR4 = 8'h50; 8'd9: VAR4 =... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_16.behavioral.pp.v | 1,251 | module MODULE1( VAR7, VAR5, VAR8, VAR1, VAR3 );
input VAR7, VAR5;
inout VAR1, VAR3;
output VAR8;
VAR2 VAR4(.VAR7(VAR7),.VAR5(VAR5),.VAR8(VAR8),.VAR1(VAR1),.VAR3(VAR3));
VAR2 VAR6(.VAR7(VAR7),.VAR5(VAR5),.VAR8(VAR8),.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_0/affine_block_ieee754_fp_multiplier_1_0_stub.v | 1,367 | module MODULE1(VAR3, VAR1, VAR2)
;
input [31:0]VAR3;
input [31:0]VAR1;
output [31:0]VAR2;
endmodule | mit |
jbelloncastro/amber_arm | hw/vlog/edc/edc_erasure.v | 9,063 | module MODULE1 (
input VAR26,
input VAR29, input VAR30, input VAR10, input VAR23, input VAR16, input [31:0] VAR35, input [31:0] VAR9, input [31:0] VAR11, input VAR28, output reg [31:0] VAR27, output reg [31:0] VAR3, output reg VAR32, output reg VAR34, output reg [7:0] VAR14, output reg VAR12, output reg VAR7 );
paramet... | lgpl-3.0 |
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