repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/Register_Shift.v | 2,263 | module MODULE1(
input [31:0] VAR15,
input [1:0] VAR14,
input [31:26] VAR2,
output [31:0] VAR16
);
wire [2:0] VAR3;
wire [31:0] VAR13,VAR17,VAR10;
assign VAR3[2] = (VAR2[31])&(!VAR2[30])&(VAR2[29])&(((!VAR2[28])&(VAR2[27])) | ((VAR2[27])&(!VAR2[26])) );
assign VAR3[1] = (VAR2[31])&(!VAR2[30])&(VAR2[29])&(((!VAR2[28])&(!... | gpl-3.0 |
freecores/altor32 | rtl/cpu_lite/altor32.v | 4,671 | module MODULE1
(
input VAR30 ,
input VAR36 ,
input VAR15 ,
input VAR20 ,
output VAR7 ,
output VAR24 ,
output [31:0] VAR18 ,
input [31:0] VAR10 ,
output [2:0] VAR27 ,
output VAR34 ,
output VAR44 ,
input VAR37,
input VAR38,
output [31:0] VAR29 ,
input [31:0] VAR26 ,
output [31:0] VAR25 ,
output [2:0] VAR28 ,
output VAR21... | lgpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat1_32.v | 6,882 | module MODULE1(
enable,
VAR14,
VAR37,
VAR26,
VAR8,
VAR9,
VAR31,
VAR35,
VAR12,
VAR20,
VAR29,
VAR17,
VAR4,
VAR30,
VAR38,
VAR5,
VAR13,
VAR21,
VAR11,
VAR7,
VAR6,
VAR33,
VAR16,
VAR36,
VAR34,
VAR32,
VAR25,
VAR19,
VAR39,
VAR23,
VAR22,
VAR10,
VAR27,
VAR24,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
VAR18,
VAR1,
o10,
o11,
o12,
o13,
o14,
o... | gpl-3.0 |
hhuang25/uwaterloo_ece224 | Lab1Good/switch_pio.v | 2,336 | module MODULE1 (
address,
VAR5,
clk,
VAR11,
VAR2,
VAR10,
VAR8,
VAR7,
VAR1
)
;
output [ 15: 0] VAR7;
output [ 15: 0] VAR1;
input [ 1: 0] address;
input VAR5;
input clk;
input [ 15: 0] VAR11;
input VAR2;
input VAR10;
input [ 15: 0] VAR8;
wire VAR3;
wire [ 15: 0] VAR6;
reg [ 15: 0] VAR4;
wire [ 15: 0] VAR7;
wire [ 15: 0] ... | mit |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_reset.v | 4,431 | module MODULE1(
VAR11,
VAR37,
VAR7,
VAR29,
VAR18,
VAR34,
VAR6,
VAR9,
VAR15,
VAR17,
VAR39,
VAR1,
VAR5,
VAR14,
VAR25,
VAR22,
VAR21,
VAR2,
VAR16,
VAR38
);
parameter VAR10 = "";
parameter VAR13 = 1;
input VAR11;
input VAR37;
input VAR7;
input VAR29;
input VAR18;
input VAR34;
input VAR6;
output VAR9;
output VAR15;
input [VA... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/hash_calculation.v | 2,880 | module MODULE1(
input VAR9,
input [31:0] VAR2,
input [13:2] VAR4,
input VAR6,
input reset,
output [3:0] VAR14,
output VAR10
);
reg [5:0] VAR11;
reg [3:0] VAR1;
wire [31:0] VAR8;
reg [31:0] VAR5;
reg VAR3;
reg [11:0] VAR13;
reg [11:0] VAR7;
reg VAR12;
always @ (posedge VAR9) begin
if(reset) begin
VAR11 = 6'b000000;
VAR1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.behavioral.v | 8,879 | module MODULE1( VAR41, VAR9, VAR57, VAR78, VAR16 );
input VAR41, VAR9, VAR78, VAR57;
output VAR16;
reg VAR4;
VAR88 VAR80(.VAR41(VAR41),.VAR9(VAR9),.VAR57(VAR57),.VAR78(VAR78),.VAR16(VAR16),.VAR4(VAR4));
VAR88 VAR84(.VAR41(VAR41),.VAR9(VAR9),.VAR57(VAR57),.VAR78(VAR78),.VAR16(VAR16),.VAR4(VAR4));
not VAR81(VAR15,VAR9);
... | apache-2.0 |
securelyfitz/44con | CPLD/conled.v | 2,059 | module MODULE1(
input clk,
output VAR3,
output VAR8,
output VAR12,
output VAR1,
output VAR2,
output VAR5
);
reg [25:0] counter;
reg [5:0] VAR6;
assign {VAR3,VAR8,VAR12,VAR1,VAR2,VAR5}=6'b111111;
assign VAR7=0;
assign VAR4=counter[15]&counter[16]&counter[17];
assign VAR10=counter[15]&counter[16];
assign VAR11=counter[15... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.v | 2,610 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR11 ,
VAR4 ,
VAR8 ,
VAR5,
VAR1 ,
VAR6 ,
VAR3 ,
VAR10
);
output VAR2 ;
input VAR9 ;
input VAR11 ;
input VAR4 ;
input VAR8 ;
input VAR5;
input VAR1 ;
input VAR6 ;
input VAR3 ;
input VAR10 ;
VAR12 VAR7 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(... | apache-2.0 |
antmicro/yosys | techlibs/nexus/brams_map.v | 2,719 | module \VAR2 (VAR4, VAR23, VAR32, VAR28, VAR27, VAR25, VAR18, VAR22);
parameter VAR15 = 9;
parameter VAR49 = 36;
parameter VAR39 = 4;
parameter VAR56 = 1;
parameter VAR52 = 1;
parameter [18431:0] VAR21 = 18432'b0;
parameter VAR50 = 8;
parameter [VAR50-1:0] VAR46 = 0;
parameter [VAR50-1:0] VAR20 = 0;
input VAR4;
input V... | isc |
jas0n1ee/THU-DSD | FB/pio_green.v | 2,090 | module MODULE1 (
address,
VAR3,
clk,
VAR7,
VAR1,
VAR5,
VAR9,
VAR6
)
;
output [ 8: 0] VAR9;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR7;
input VAR1;
input [ 31: 0] VAR5;
wire VAR2;
reg [ 8: 0] VAR8;
wire [ 8: 0] VAR9;
wire [ 8: 0] VAR4;
wire [ 31: 0] VAR6;
assign VAR2 = 1;
assign VAR4 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbn/sky130_fd_sc_hs__dlrbn.blackbox.v | 1,366 | module MODULE1 (
VAR6,
VAR5 ,
VAR4 ,
VAR1 ,
VAR2
);
input VAR6;
input VAR5 ;
input VAR4 ;
output VAR1 ;
output VAR2 ;
supply1 VAR7;
supply0 VAR3;
endmodule | apache-2.0 |
efabless/openlane | designs/151/src/RegisterFile.v | 1,094 | module MODULE1 #(
parameter VAR7 = 5,
parameter VAR1 = 1 << (VAR7)
)(
input clk,
input reset,
input [VAR7-1:0] VAR5,
input [VAR4-1:0] VAR10,
input VAR9,
input [VAR7-1:0] VAR8,
output [VAR4-1:0] VAR11,
input [VAR7-1:0] VAR2,
output [VAR4-1:0] VAR6
);
reg [VAR4-1:0] VAR3[VAR1-1:0];
assign VAR11 = VAR3[VAR8];
assign VAR6 ... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/DecWidthConverter32to16.v | 5,462 | module MODULE1
(
parameter VAR11 = 32,
parameter VAR12 = 16
)
(
VAR1 ,
VAR2 ,
VAR17 ,
VAR9 ,
VAR20 ,
VAR14 ,
VAR3 ,
VAR6
);
input VAR1 ;
input VAR2 ;
input VAR17 ;
input [VAR11 - 1:0] VAR9 ;
output VAR20 ;
output VAR14 ;
output [VAR12 - 1:0] VAR3 ;
input VAR6 ;
reg [VAR11 - 1:0] VAR7 ;
reg VAR5 ;
reg VAR15 ;
localparam... | gpl-3.0 |
klaNath/synth1 | operator.v | 2,223 | module MODULE1(
clk,
VAR13,
VAR11,
VAR3,
VAR7,
VAR9);
input wire clk, VAR13;
input wire [7:0] VAR3, VAR11;
output wire VAR9;
output wire [15:0] VAR7;
wire [15:0] VAR12;
wire [20:0] VAR15;
reg [20:0] VAR5;
reg [31:0] VAR8;
reg [23:0] VAR2;
reg [7:0] VAR6;
reg VAR14, VAR4;
VAR1 VAR2 <= 19224;
assign VAR7 = VAR8[15:0];
as... | lgpl-3.0 |
peteasa/oh | src/mio/hdl/mtx.v | 5,351 | module MODULE1 (
VAR5, VAR3, VAR21, VAR6, VAR4, VAR27,
clk, VAR8, VAR28, VAR25, VAR44, VAR22, VAR33,
VAR23, VAR9, VAR41
);
parameter VAR42 = 104; parameter VAR2 = 8; parameter VAR37 = 32; parameter VAR36 = "VAR16"; parameter VAR17 = VAR11(2*VAR42/VAR2);
input clk; input VAR8; input VAR28; input VAR25; input [7:0] VAR44... | mit |
hoglet67/CoPro6502 | src/zet/zet/zet_conv.v | 2,161 | module MODULE1 (
input [15:0] VAR14,
input [ 2:0] VAR5,
output [31:0] out,
input [ 1:0] VAR4, output [ 2:0] VAR8 );
wire VAR12, VAR19;
wire VAR17, VAR6, VAR21;
wire [15:0] VAR11, VAR3;
wire [ 7:0] VAR9, VAR13, VAR15, VAR7;
wire [15:0] VAR1, VAR22;
wire VAR10, VAR20;
wire VAR2;
VAR16 VAR18 (VAR5, VAR1, VAR11, VAR3, 16'd... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_MATLAB_Function_block.v | 1,059 | module MODULE1
(
VAR2,
VAR1
);
input [17:0] VAR2; output [8:0] VAR1;
assign VAR1 = VAR2[8:0];
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi.functional.pp.v | 2,070 | module MODULE1 (
VAR9 ,
VAR18 ,
VAR16 ,
VAR11 ,
VAR17 ,
VAR5 ,
VAR3,
VAR4,
VAR12 ,
VAR10
);
output VAR9 ;
input VAR18 ;
input VAR16 ;
input VAR11 ;
input VAR17 ;
input VAR5 ;
input VAR3;
input VAR4;
input VAR12 ;
input VAR10 ;
wire VAR15 ;
wire VAR2 ;
wire VAR1;
and VAR8 (VAR15 , VAR18, VAR16, VAR11, VAR17 );
nor VAR6 ... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/SGMII_MUX.v | 24,374 | module MODULE1(
clk,
VAR60,
VAR103,
VAR87,
VAR17,
VAR32,
reset,
VAR85,
VAR67,
VAR98,
VAR11,
VAR63,
VAR29,
VAR59,
VAR16,
VAR36,
VAR81,
VAR72,
VAR89,
VAR48,
VAR86,
VAR71,
VAR5,
VAR90,
VAR30,
VAR46,
VAR111,
VAR112,
VAR54,
VAR22,
VAR8,
VAR69,
VAR84,
VAR74,
VAR70,
VAR95,
VAR97,
VAR27,
VAR28,
VAR94,
VAR68,
VAR105,
VAR75,
VAR... | apache-2.0 |
n8thenetninja/Cloud-Car | VeriLog/QuartusProjects/ServoController/i2cslave/trunk/model/i2c_master_top.v | 10,110 | module MODULE1(
VAR5, VAR47, VAR34, VAR27, VAR12, VAR9,
VAR25, VAR13, VAR42, VAR29, VAR35,
VAR20, VAR36, VAR14, VAR19, VAR33, VAR2 );
parameter VAR16 = 1'b0;
input VAR5; input VAR47; input VAR34; input [2:0] VAR27; input [7:0] VAR12; output [7:0] VAR9; input VAR25; input VAR13; input VAR42; output VAR29; output VAR35;
... | gpl-3.0 |
asicguy/gplgpu | hdl/mc_graph/mc_mff_key.v | 5,988 | module MODULE1
(
input [(VAR3*8)-1:0] VAR2,
input [31:0] VAR7,
input [1:0] VAR5,
input [2:0] VAR4,
input [VAR3-1:0] VAR10,
output reg [VAR3-1:0] VAR9
);
reg [VAR3-1:0] VAR1;
reg [VAR3-1:0] VAR6;
always @* begin
casex(VAR5)
2'b00:
begin
VAR1[0] = (VAR2[7:0] == VAR7[7:0]);
VAR1[1] = (VAR2[15:8] == VAR7[7:0]);
VAR1[2] = (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_psa_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_s.symbol.v | 1,538 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR8,
input VAR3 ,
input VAR4 ,
input VAR7 ,
input VAR6 ,
input VAR1
);
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v | 9,348 | module MODULE1 (VAR22, VAR42, clk, reset, write, read, VAR45,
VAR39, VAR29, VAR9, VAR31, VAR35);
parameter VAR7 = 32;
parameter VAR37 = 8;
parameter VAR44 = 3;
input clk;
input reset;
input write;
input read;
input VAR45;
input [VAR7-1:0] VAR22;
output [VAR7-1:0] VAR42;
output VAR39;
output VAR29;
output VAR9;
output V... | lgpl-3.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/VGA_0.v | 2,349 | module MODULE1 (
input wire VAR17, output wire [9:0] VAR14, output wire [9:0] VAR5, output wire [9:0] VAR10, output wire VAR15, output wire VAR6, output wire VAR19, output wire VAR20, output wire VAR7, input wire VAR9, output wire [15:0] VAR1, input wire [15:0] VAR12, input wire [18:0] VAR13, input wire VAR3, input wir... | gpl-3.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/imx_umc.v | 11,078 | module MODULE1(
clk, rst,
VAR23, VAR57,
VAR34, VAR51, VAR3, VAR37, VAR17,
VAR32, VAR15, VAR5, VAR25, VAR33,
VAR45, VAR26, VAR50,
VAR27, VAR28, VAR14, VAR16,
VAR55
);
parameter VAR58 = VAR56;
input clk;
input rst;
input [31:0] VAR23;
input VAR57;
output [VAR58-1:0] VAR37;
output VAR51;
output VAR3;
output [31:0] VAR17;
... | gpl-2.0 |
fallen/milkymist-mmu | cores/pfpu/rtl/pfpu_tpram.v | 1,366 | module MODULE1(
input VAR4,
input [6:0] VAR5,
output reg [31:0] VAR8,
input [6:0] VAR1,
output reg [31:0] VAR3,
input VAR7,
input [6:0] VAR2,
input [31:0] VAR10
);
reg [31:0] VAR9[0:127];
always @(posedge VAR4) begin
if(VAR7)
VAR9[VAR2] <= VAR10;
VAR8 <= VAR9[VAR5];
end
reg [31:0] VAR6[0:127];
always @(posedge VAR4) be... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai.blackbox.v | 1,368 | module MODULE1 (
VAR8 ,
VAR6,
VAR1,
VAR4,
VAR7
);
output VAR8 ;
input VAR6;
input VAR1;
input VAR4;
input VAR7;
supply1 VAR2;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.sdram.ok/db/ip/soc_design/submodules/altera_reset_synchronizer.v | 3,479 | module MODULE1
parameter VAR4 = 1,
parameter VAR5 = 2
)
(
input VAR2 ,
input clk,
output VAR1
);
reg [VAR5-1:0] VAR6;
reg VAR3;
generate if (VAR4) begin
always @(posedge clk or posedge VAR2) begin
if (VAR2) begin
VAR6 <= {VAR5{1'b1}};
VAR3 <= 1'b1;
end
else begin
VAR6[VAR5-2:0] <= VAR6[VAR5-1:1];
VAR6[VAR5-1] <= 0;
VAR... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_2.behavioral.v | 1,180 | module MODULE1( VAR2, VAR3, VAR6 );
input VAR2, VAR6;
output VAR3;
VAR5 VAR4(.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6));
VAR5 VAR1(.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4_2.v | 2,444 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR1 ,
VAR6 ,
VAR13 ,
VAR5 ,
VAR10 ,
VAR4,
VAR11,
VAR2 ,
VAR9
);
output VAR12 ;
input VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR13 ;
input VAR5 ;
input VAR10 ;
input VAR4;
input VAR11;
input VAR2 ;
input VAR9 ;
VAR3 VAR8 (
.VAR12(VAR12),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR13(VAR1... | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/inst_rom.v | 3,299 | module MODULE1(
input [4 :0] addr, output reg [31:0] VAR1 );
wire [31:0] MODULE1[19:0]; assign MODULE1[ 0] = 32'h24010001; assign MODULE1[ 1] = 32'h00011100; assign MODULE1[ 2] = 32'h00411821; assign MODULE1[ 3] = 32'h00022082; assign MODULE1[ 4] = 32'h00642823; assign MODULE1[ 5] = 32'hAC250013; assign MODULE1[ 6] = 3... | mit |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.v | 74,329 | module MODULE1 #
(
parameter VAR189 = 100, parameter VAR180 = 135, parameter VAR397 = "0", parameter VAR130 = 3, parameter VAR392 = "8", parameter VAR94 = "VAR128", parameter VAR134 = "VAR342", parameter VAR43 = 1, parameter VAR51 = 5,
parameter VAR448 = 12, parameter VAR351 = 1, parameter VAR328 = 1, parameter VAR141 ... | mit |
audiocircuit/NCSU-Low-Power-RFID | I2C/master.v | 8,956 | module MODULE1(
input wire VAR10,
input wire clk,
input wire en,
input wire VAR5,
input wire VAR29,
input wire VAR8,
input wire [6:0] address,
input wire [7:0] VAR3,
inout reg VAR14,
inout reg VAR4,
output reg [7:0]VAR27
);
reg [3:0] VAR20;
reg [3:0] VAR26;
reg VAR13;
reg VAR17;
reg VAR15;
wire VAR16;
wire VAR23;
param... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build1/alu_current.v | 330,544 | module MODULE1 (VAR1,VAR2,VAR4,VAR5,VAR3);
output [0:127] VAR3;
input [0:127] VAR1;
input [0:127] VAR2;
input [0:1] VAR4;
input [0:4] VAR5;
reg [0:127] VAR3;
always @(VAR1 or VAR2 or VAR4 or VAR5)
begin
case(VAR5)
begin
case(VAR4)
case(VAR2[5:7])
0:
begin
VAR3[0:7]<=VAR1[0:7]>>0;
VAR3[8:15]<=VAR1[8:15]>>0;
VAR3[16:23]<... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311oi/sky130_fd_sc_ls__a311oi_2.v | 2,450 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR2 ,
VAR3 ,
VAR9 ,
VAR1 ,
VAR11,
VAR8,
VAR6 ,
VAR10
);
output VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR1 ;
input VAR11;
input VAR8;
input VAR6 ;
input VAR10 ;
VAR12 VAR4 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv.functional.pp.v | 1,883 | module MODULE1 (
VAR2,
VAR10 ,
VAR5 ,
VAR3 ,
VAR7
);
output VAR2;
input VAR10 ;
input VAR5 ;
input VAR3 ;
input VAR7 ;
wire VAR4 ;
wire VAR9;
pulldown VAR1 (VAR4 );
VAR11 VAR8 (VAR9, VAR5, VAR5, VAR4 );
bufif0 VAR6 (VAR2 , VAR9, VAR10);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/mask_mon.v | 2,136 | module MODULE1(
clk, VAR1, VAR3, VAR8, VAR4, VAR9, VAR12,
VAR11, VAR14, VAR6, VAR13, VAR2, VAR7
);
input clk;
input VAR1;
input [3:0] VAR3;
input [3:0] VAR8;
input [3:0] VAR4;
input [3:0] VAR9;
input [3:0] VAR12;
input [3:0] VAR11;
input [3:0] VAR14;
input [3:0] VAR6;
input [3:0] VAR13;
input [3:0] VAR2;
input [2:0] VA... | gpl-2.0 |
aj-michael/Digital-Systems | Lab6-Part1/ipcore_dir/Clock65MHz/example_design/Clock65MHz_exdes.v | 4,919 | module MODULE1
parameter VAR22 = 100
)
( input VAR7,
input VAR5,
output [1:1] VAR23,
output VAR1,
output VAR19
);
localparam VAR18 = 16;
wire VAR27 = !VAR19 || VAR5;
reg VAR17;
reg VAR26;
reg VAR21;
reg VAR15;
wire VAR3;
wire VAR8;
wire clk;
reg [VAR18-1:0] counter;
VAR14 VAR24
( .VAR7 (VAR7),
.VAR25 (VAR3),
.VAR19 (VA... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/mgt_null_controller_v1_02_a/hdl/verilog/mgt_null_controller.v | 2,625 | module MODULE1 (
input VAR46,
input [0:1] VAR47,
input [0:1] VAR5,
output [0:1] VAR39,
output [0:1] VAR35,
input [0:1] VAR40,
input [0:1] VAR12,
output [0:1] VAR4,
output [0:1] VAR32,
input [0:1] VAR59,
input [0:1] VAR42,
output [0:1] VAR31,
output [0:1] VAR1,
input [0:1] VAR27,
input [0:1] VAR51,
output [0:1] VAR58,
o... | bsd-2-clause |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_srl_fifo.v | 6,022 | module MODULE1 #
(
parameter VAR47 = 8,
parameter VAR18 = (VAR47>8),
parameter VAR40 = (VAR47/8),
parameter VAR33 = 1,
parameter VAR13 = 0,
parameter VAR23 = 8,
parameter VAR38 = 0,
parameter VAR49 = 8,
parameter VAR3 = 1,
parameter VAR37 = 1,
parameter VAR28 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR47-1... | mit |
nyaxt/dmix | mpemu_t.v | 1,550 | module MODULE1;
reg [31:0] VAR11 [VAR4-1:0];
reg [31:0] VAR7 [VAR4-1:0];
reg [31:0] VAR1 [VAR4-1:0];
reg clk;
reg [23:0] VAR8;
reg [23:0] VAR5;
wire [27:0] VAR9;
VAR2 VAR3(
.clk(clk),
.VAR8(VAR8), .VAR5(VAR5),
.VAR9(VAR9));
parameter VAR10 = 41.0;
integer VAR6; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf_16.v | 2,015 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR7,
VAR8,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR7;
input VAR8;
input VAR6 ;
input VAR4 ;
VAR2 VAR5 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR7;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha.blackbox.v | 1,264 | module MODULE1 (
VAR4,
VAR6 ,
VAR2 ,
VAR5
);
output VAR4;
output VAR6 ;
input VAR2 ;
input VAR5 ;
supply1 VAR3;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
LoadCode/FPGA_CODIC | rom.v | 21,202 | module MODULE1 (input clk,
input wire [8:0] addr,
output reg [31:0] VAR1);
reg [31:0] VAR2 [0:360];
always @(posedge clk) begin
VAR1 <= VAR2[addr];
end | gpl-3.0 |
liqimai/ZPC | PersonalComputer/LCD_dis.v | 10,763 | module MODULE1(
input clk,
input[127:0] VAR10,
input reset,
output reg VAR31,
output VAR62,
output reg VAR40,
output reg[3:0] VAR68,
output VAR65
);
assign VAR65 = 1;
assign VAR62 = 0;
reg [19:0] VAR59;
reg [19:0] VAR9;
wire[7:0] VAR47;
wire[3:0] VAR2;
reg[4:0] VAR61;
reg [5:0] state;
reg VAR19;
assign VAR47 = (VAR2[3]... | gpl-2.0 |
TheMadSocrates/vercpu-project | rtl/core/processor.v | 3,486 | module MODULE1(
input wire clk,
input wire VAR17,
input wire [15 : 0] VAR29,
input wire [ 7 : 0] VAR14,
output wire [ 7 : 0] VAR24,
output wire [ 7 : 0] VAR34,
output wire [ 7 : 0] VAR13,
output wire VAR27
);
wire [15 : 0] VAR16;
wire [VAR2 - 1 : 0] VAR32;
wire [ 7 : 0] VAR33,
VAR23;
wire [ 1 : 0] VAR5;
wire VAR26,
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp.symbol.v | 1,528 | module MODULE1 (
input VAR5 ,
output VAR3 ,
output VAR4 ,
input VAR11,
input VAR6 ,
input VAR7 ,
input VAR8
);
supply1 VAR2;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a.pp.symbol.v | 1,344 | module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR4 ,
output VAR3 ,
input VAR1 ,
input VAR5,
input VAR7,
input VAR2
);
endmodule | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/nios_system_alu_control.v | 2,316 | module MODULE1 (
address,
VAR4,
clk,
VAR7,
VAR9,
VAR2,
VAR6,
VAR5
)
;
output [ 2: 0] VAR6;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input VAR4;
input clk;
input VAR7;
input VAR9;
input [ 31: 0] VAR2;
wire VAR8;
reg [ 2: 0] VAR1;
wire [ 2: 0] VAR6;
wire [ 2: 0] VAR3;
wire [ 31: 0] VAR5;
assign VAR8 = 1;
assign VAR3 ... | gpl-3.0 |
jairov4/accel-oil | solution_spartan3/syn/verilog/nfa_get_finals.v | 11,263 | module MODULE1 (
VAR21,
VAR30,
VAR16,
VAR9,
VAR20,
VAR31,
VAR36,
VAR27,
VAR2,
VAR37,
VAR17,
VAR14,
VAR19,
VAR24,
VAR33,
VAR8,
VAR38,
VAR28
);
input VAR21;
input VAR30;
input VAR16;
output VAR9;
output VAR20;
output VAR31;
output VAR36;
input VAR27;
output VAR2;
input VAR37;
output VAR17;
output [31:0] VAR14;
input [31:... | lgpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_mul_u16.v | 3,812 | module MODULE1 (
clk,
VAR18,
VAR17,
VAR3,
VAR15,
VAR1);
parameter VAR19 = 16;
localparam VAR2 = VAR19 - 1;
input clk;
input [15:0] VAR18;
input [15:0] VAR17;
output [31:0] VAR3;
input [VAR2:0] VAR15;
output [VAR2:0] VAR1;
reg [VAR2:0] VAR16 = 'd0;
reg [VAR2:0] VAR4 = 'd0;
reg [VAR2:0] VAR1 = 'd0;
wire [33:0] VAR11;
alw... | lgpl-3.0 |
YosysHQ/yosys | techlibs/xilinx/brams_xc2v_map.v | 11,752 | module MODULE1 (...);
parameter VAR67 = 0;
parameter VAR73 = 0;
parameter VAR20 = 1;
parameter VAR6 = 1;
parameter VAR50 = 1;
parameter VAR52 = "VAR44";
parameter VAR75 = 0;
parameter VAR2 = 0;
parameter VAR102 = 1;
parameter VAR60 = 1;
parameter VAR14 = 0;
parameter VAR95 = "VAR44";
parameter VAR103 = 0;
parameter VAR... | isc |
ptracton/wb_soc_template | rtl/system_controller/system_controller.v | 2,456 | module MODULE1 (
VAR4, VAR1, VAR5,
VAR2, VAR3
) ;
input wire VAR2;
input wire VAR3;
output wire VAR4;
output wire VAR1;
output wire VAR5; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp.behavioral.pp.v | 1,764 | module MODULE1 (
VAR4,
VAR7,
VAR1 ,
VAR11 ,
VAR6
);
input VAR4;
input VAR7;
output VAR1 ;
input VAR11 ;
input VAR6 ;
wire VAR10 ;
wire VAR8;
VAR2 VAR9 (VAR10 , VAR11, VAR4, VAR7 );
VAR2 VAR3 (VAR8, VAR6, VAR4, VAR7 );
notif1 VAR5 (VAR1 , VAR10, VAR8);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp.blackbox.v | 1,365 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR1;
supply1 VAR6;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai.behavioral.v | 1,577 | module MODULE1 (
VAR10 ,
VAR13,
VAR7,
VAR6,
VAR3,
VAR2
);
output VAR10 ;
input VAR13;
input VAR7;
input VAR6;
input VAR3;
input VAR2;
supply1 VAR8;
supply0 VAR1;
supply1 VAR11 ;
supply0 VAR5 ;
wire VAR9 ;
wire VAR14;
or VAR12 (VAR9 , VAR7, VAR13, VAR6 );
nand VAR4 (VAR14, VAR2, VAR9, VAR3);
buf VAR15 (VAR10 , VAR14 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32o/sky130_fd_sc_ms__a32o.functional.pp.v | 2,224 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR12 ,
VAR13 ,
VAR5 ,
VAR4 ,
VAR10,
VAR8,
VAR3 ,
VAR19
);
output VAR6 ;
input VAR2 ;
input VAR12 ;
input VAR13 ;
input VAR5 ;
input VAR4 ;
input VAR10;
input VAR8;
input VAR3 ;
input VAR19 ;
wire VAR20 ;
wire VAR11 ;
wire VAR16 ;
wire VAR15;
and VAR18 (VAR20 , VAR13, VAR2, VAR12 );
and V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1.behavioral.pp.v | 1,850 | module MODULE1 (
VAR12 ,
VAR10 ,
VAR1,
VAR9,
VAR7 ,
VAR4
);
output VAR12 ;
input VAR10 ;
input VAR1;
input VAR9;
input VAR7 ;
input VAR4 ;
wire VAR8 ;
wire VAR2;
buf VAR11 (VAR8 , VAR10 );
VAR3 VAR6 (VAR2, VAR8, VAR1, VAR9);
buf VAR5 (VAR12 , VAR2 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_axi_basic_rx.v | 8,258 | module MODULE1 #(
parameter VAR21 = 128, parameter VAR3 = "VAR9", parameter VAR20 = "VAR16", parameter VAR4 = "VAR16", parameter VAR37 = 1,
parameter VAR18 = (VAR21 == 128) ? 2 : 1, parameter VAR35 = VAR21 / 8 ) (
output [VAR21-1:0] VAR34, output VAR33, input VAR12, output [VAR35-1:0] VAR19, output VAR31, output [21:0]... | lgpl-3.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v | 2,314 | module MODULE1(
VAR4,
VAR26,
VAR17,
VAR23,
VAR15
);
parameter VAR12 = 1;
localparam VAR6 = 4 * VAR12;
localparam VAR24 = VAR12;
input [VAR6-1:0] VAR4;
input VAR26;
input [VAR12-1:0] VAR23;
input [VAR12-1:0] VAR15;
output [VAR24-1:0] VAR17;
generate
genvar VAR3;
for (VAR3 = 0; VAR3 < VAR12; VAR3 = VAR3 + 1)
begin:VAR9
w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrbp/sky130_fd_sc_lp__dfrbp.functional.v | 1,759 | module MODULE1 (
VAR9 ,
VAR13 ,
VAR8 ,
VAR5 ,
VAR6
);
output VAR9 ;
output VAR13 ;
input VAR8 ;
input VAR5 ;
input VAR6;
wire VAR12;
wire VAR3;
not VAR11 (VAR3 , VAR6 );
VAR10 VAR1 VAR7 (VAR12 , VAR5, VAR8, VAR3 );
buf VAR2 (VAR9 , VAR12 );
not VAR4 (VAR13 , VAR12 );
endmodule | apache-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/CLS_LED_Output_Fader.v | 2,798 | module MODULE1
(
input VAR6,
input [6:0] VAR3,
input VAR4,
input VAR7,
output reg VAR1,
input VAR2
);
reg [2:0] VAR8;
reg [2:0] VAR5;
begin
begin
end
begin
begin | mit |
gbraad/minimig-de1 | rtl/or1200/or1200_spram_2048x32_bw.v | 13,836 | module MODULE1(
VAR71, VAR56, VAR18,
clk, rst, VAR62, VAR31, VAR10, addr, VAR26, VAR63
);
input VAR71;
input [VAR17 - 1:0] VAR18; output VAR56;
input clk; input rst; input VAR62; input [3:0] VAR31; input VAR10; input [10:0] addr; input [31:0] VAR26; output [31:0] VAR63;
assign VAR56 = VAR71;
VAR32 VAR36(
VAR65 VAR36(
V... | gpl-3.0 |
rkrajnc/minimig-de1 | rtl/minimig/Sprites.v | 11,262 | module MODULE2
(
input clk, input reset, input [8:1] VAR4, input [8:0] VAR49, input [15:0] VAR10, input VAR41, output [7:0] VAR33, output reg [3:0] VAR43 );
parameter VAR15 = 9'h140;
wire VAR24; wire VAR11; wire VAR48; wire VAR40; wire VAR44; wire VAR39; wire VAR46; wire VAR34;
wire [1:0] VAR47; wire [1:0] VAR2; wire [... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/stage3.v | 13,615 | module MODULE1(
clk,rst,
VAR109,VAR111,
VAR45,
VAR35 ,VAR52 ,VAR124 ,VAR129 ,
VAR120 ,VAR90 ,VAR73 ,VAR7 ,
VAR14 ,VAR104 ,VAR85,VAR79,
VAR78,VAR49,VAR103,VAR69,
VAR38,VAR132,VAR99,VAR6,
VAR47,VAR108,VAR135,VAR70,
VAR92,VAR24,VAR137,VAR18,
VAR59,VAR3,VAR134,VAR121,
VAR117,
o0 ,o1 ,o2 ,o3 ,
o4 ,o5 ,o6 ,o7 ,
VAR41 ,VAR107... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.behavioral.pp.v | 2,030 | module MODULE1( VAR4, VAR9, VAR7, VAR3, VAR10, VAR8, VAR2 );
input VAR10, VAR3, VAR7, VAR4;
inout VAR8, VAR2;
output VAR9;
VAR5 VAR6(.VAR4(VAR4),.VAR9(VAR9),.VAR7(VAR7),.VAR3(VAR3),.VAR10(VAR10),.VAR8(VAR8),.VAR2(VAR2));
VAR5 VAR1(.VAR4(VAR4),.VAR9(VAR9),.VAR7(VAR7),.VAR3(VAR3),.VAR10(VAR10),.VAR8(VAR8),.VAR2(VAR2)); | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/ip/Master_Clock_Divider/Master_Clock_Divider_clk_wiz.v | 7,774 | module MODULE1
( output VAR41,
output VAR17,
output VAR22,
input reset,
output VAR51,
input VAR66,
input VAR96
);
wire VAR99;
wire VAR20;
VAR32 VAR25
(.VAR27 (VAR99),
.VAR28 (VAR66),
.VAR8 (VAR96));
wire VAR10;
wire VAR45;
wire VAR54;
wire VAR12;
wire VAR73;
wire VAR91;
wire VAR97;
wire [15:0] VAR79;
wire VAR52;
wire V... | lgpl-3.0 |
GustavoOS/ARMAria | src/ControlUnit/controlcore.v | 12,244 | module MODULE1(
input VAR12, VAR13, VAR11,
input [6 : 0] VAR7,
output reg enable, VAR15, VAR2,
output reg VAR14, VAR9,
output reg [2 : 0] VAR3, VAR5,
output reg [2 : 0] VAR4, VAR8,
output reg [3 : 0] VAR1, VAR6, VAR10
);
always @ ( * ) begin
VAR1 = 12;
VAR6 = 0;
VAR4 = 1;
VAR3 = 0;
VAR5 = 0;
VAR8 = 0;
VAR15 = 0;
VAR2 =... | mit |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/models/fifo.v | 1,619 | module MODULE1( VAR19, VAR6, VAR13, VAR4, VAR12, VAR2, VAR10,
VAR9, VAR14, VAR1, VAR16, VAR17, VAR3);
parameter VAR11 = 16;
parameter VAR15 = 1024;
parameter VAR20 = 10;
input [VAR11-1:0] VAR19;
input VAR6;
input VAR13;
input VAR4;
input VAR12;
input VAR2;
output [VAR11-1:0] VAR10;
output VAR9;
output VAR14;
output reg... | gpl-3.0 |
Rmin1995/NoC | router.v | 3,803 | module MODULE1(VAR18, VAR2, VAR40, VAR46, VAR41, VAR35, write,
VAR3, VAR24, reset);
parameter VAR1 = 16;
parameter VAR9 = 4;
output [1:VAR20*VAR47] VAR18;
output [0:VAR9*VAR20-1] VAR2;
input [1:VAR20*VAR47] VAR40;
input [1:VAR16] VAR46;
input [0:VAR9*VAR20-1] VAR41;
input [1:VAR5] VAR35;
input write;
input VAR3;
input ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.behavioral.pp.v | 1,182 | module MODULE1( VAR7, VAR2, VAR6, VAR4 );
input VAR7;
inout VAR6, VAR4;
output VAR2;
VAR3 VAR1(.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6),.VAR4(VAR4));
VAR3 VAR5(.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6),.VAR4(VAR4)); | apache-2.0 |
versaloon/vsf | vsf/old/example/vsfusbh/proj/Keil_v5_CMEM7/fpga/src/armcm3_v1.v | 5,080 | module MODULE1(
VAR24,
VAR98,
VAR42,
VAR100,
VAR60,
VAR106,
VAR72
);
input VAR24;
input VAR98;
input VAR42;
input VAR100;
output [31:0] VAR60;
output [31:0] VAR106;
input [31:0] VAR72;
VAR51 #(
.VAR19 (1'b1),
.VAR43 (1'b1),
.VAR15 (1'b0),
.VAR66 (1'b0),
.VAR74 (1'b0),
.VAR34 (1'b1),
.VAR28 (1'b0),
.VAR16 (12'b000000000... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai_2.v | 2,424 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR5 ,
VAR10 ,
VAR6 ,
VAR7 ,
VAR8,
VAR11,
VAR9 ,
VAR4
);
output VAR3 ;
input VAR12 ;
input VAR5 ;
input VAR10 ;
input VAR6 ;
input VAR7 ;
input VAR8;
input VAR11;
input VAR9 ;
input VAR4 ;
VAR1 VAR2 (
.VAR3(VAR3),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd/sky130_fd_sc_lp__tapvgnd.blackbox.v | 1,249 | module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/tracking_camera_system_nios2_qsys_0_mult_cell.v | 6,468 | module MODULE1 (
VAR47,
VAR45,
clk,
VAR8,
VAR38
)
;
output [ 31: 0] VAR38;
input [ 31: 0] VAR47;
input [ 31: 0] VAR45;
input clk;
input VAR8;
wire [ 31: 0] VAR38;
wire [ 31: 0] VAR44;
wire [ 15: 0] VAR53;
wire VAR6;
assign VAR6 = ~VAR8;
VAR31 VAR29
(
.VAR37 (VAR6),
.VAR17 (clk),
.VAR33 (VAR47[15 : 0]),
.VAR14 (VAR45[15... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/Booth_Multipliers-master/Src/Booth_Multiplier_4xA.v | 27,525 | module MODULE1 #(
parameter VAR12 = 16 )(
input VAR27, input VAR14,
input VAR4, input [(VAR12 - 1):0] VAR16, input [(VAR12 - 1):0] VAR13, output reg VAR29, output reg [((2*VAR12) - 1):0] VAR31 );
localparam VAR20 = ((VAR12 + 1)/4);
reg [4:0] VAR2; reg [4:0] VAR11; reg VAR18; reg [(VAR12 + 3):0] VAR23; wire [(VAR12 + 3)... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_dp_macb_l.v | 4,712 | module MODULE1(
VAR19, VAR11, VAR26,
VAR25, VAR22, VAR2,
VAR28, VAR17, VAR10,
VAR1, VAR21, VAR16, VAR9
);
output [149:0] VAR19; output VAR11;
output VAR26;
input VAR25; input VAR22; input VAR2; input VAR28; input VAR17; input [149:0] VAR10; input [149:0] VAR1;
input VAR21;
input VAR16;
input VAR9;
wire VAR27;
wire [149... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.behavioral.v | 2,716 | module MODULE1( VAR10, VAR11, VAR6, VAR14 );
input VAR6, VAR11, VAR10;
output VAR14;
reg VAR2;
VAR3 VAR13(.VAR10(VAR10),.VAR11(VAR11),.VAR6(VAR6),.VAR14(VAR14),.VAR2(VAR2));
VAR3 VAR15(.VAR10(VAR10),.VAR11(VAR11),.VAR6(VAR6),.VAR14(VAR14),.VAR2(VAR2));
not VAR19(VAR18,VAR11);
not VAR8(VAR24,VAR10);
and VAR1(VAR20,VAR24... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3.behavioral.v | 1,387 | module MODULE1 (
VAR9,
VAR11,
VAR8,
VAR6
);
output VAR9;
input VAR11;
input VAR8;
input VAR6;
supply1 VAR7;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR3 ;
wire VAR5;
nand VAR10 (VAR5, VAR8, VAR11, VAR6 );
buf VAR4 (VAR9 , VAR5 );
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/top.v | 13,853 | module MODULE1 #
(
parameter VAR141 = 1,
parameter VAR220 = 3,
parameter VAR86 = 1,
parameter VAR138 = 1,
parameter VAR242 = 10,
parameter VAR238 = 1,
parameter VAR218 = 8,
parameter VAR101 = 64,
parameter VAR135 = 8,
parameter VAR233 = 14,
parameter VAR85 = 4,
parameter VAR215 = 4,
parameter VAR175 = 1,
parameter VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.blackbox.v | 1,327 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR8 ,
VAR1
);
output VAR6 ;
output VAR2 ;
input VAR8 ;
input VAR1;
supply1 VAR7;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
mlarouche/sd2snes | verilog/sd2snes/msu.v | 5,243 | module MODULE1(
input VAR43,
input enable,
input [13:0] VAR15,
input [7:0] VAR14,
input VAR24,
input [2:0] VAR20,
input [7:0] VAR12,
output [7:0] VAR10,
input VAR26,
input VAR37,
input VAR35,
output [6:0] VAR13,
output [7:0] VAR2,
output VAR31,
output [31:0] VAR22,
output [15:0] VAR32,
input [5:0] VAR33,
input [5:0] VA... | gpl-2.0 |
m-labs/milkymist | cores/uart/rtl/uart.v | 3,042 | module MODULE1 #(
parameter VAR22 = 4'h0,
parameter VAR27 = 100000000,
parameter VAR21 = 115200,
parameter VAR28 = 1'b0
) (
input VAR2,
input VAR11,
input [13:0] VAR8,
input VAR6,
input [31:0] VAR29,
output reg [31:0] VAR3,
output irq,
input VAR14,
output VAR24,
output break
);
reg [15:0] VAR4;
wire [7:0] VAR9;
wire [7... | lgpl-3.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/topPos_module_tst.v | 3,137 | module MODULE1;
reg clk;
reg rst;
reg en;
wire VAR36;
wire [15:0] VAR19;
wire VAR31;
reg VAR14;
reg VAR10;
reg [7:0] VAR11;
reg [31:0] VAR23;
reg VAR1;
wire VAR5;
wire [31:0] VAR22;
wire [31:0] VAR32;
wire [31:0] VAR24;
wire [31:0] VAR29;
wire [31:0] VAR41;
wire [31:0] VAR27;
wire VAR18;
wire VAR6;
wire VAR8;
wire [31:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba.functional.v | 1,958 | module MODULE1 (
VAR4,
VAR5,
VAR9 ,
VAR6 ,
VAR3 ,
VAR10
);
input VAR4;
input VAR5;
output VAR9 ;
input VAR6 ;
input VAR3 ;
input VAR10;
wire VAR14 ;
wire VAR1 ;
wire VAR13;
nor VAR11 (VAR14 , VAR6, VAR3 );
nor VAR8 (VAR1 , VAR10, VAR14 );
VAR12 VAR7 (VAR13, VAR1, VAR4, VAR5);
buf VAR2 (VAR9 , VAR13 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/cmm_errman_ftl.v | 9,345 | module MODULE1 (
VAR9, VAR10,
VAR13, VAR12,
VAR11,
VAR2,
VAR4,
VAR1,
rst,
clk
);
output [2:0] VAR9;
output VAR10;
input VAR13;
input VAR12;
input VAR11;
input VAR2;
input VAR4;
input VAR1;
input rst;
input clk;
parameter VAR8 = 1;
reg [2:0] VAR5;
reg VAR7;
always @(VAR4 or
VAR13 or
VAR12 or
VAR11 or VAR2 or
VAR1) begin... | lgpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/win/win_stub.v | 1,254 | module MODULE1(VAR5, VAR2, VAR3, VAR4, VAR1)
;
input VAR5;
input [0:0]VAR2;
input [13:0]VAR3;
input [11:0]VAR4;
output [11:0]VAR1;
endmodule | gpl-3.0 |
jacgoudsmit/P8X32A_Emulation | P8X32A_Nexys4/src/cog_ram.v | 1,346 | module MODULE1
(
input clk,
input VAR1,
input VAR3,
input [8:0] VAR5,
input [31:0] VAR4,
output reg [31:0] VAR6
);
reg [31:0] VAR2 [511:0];
always @(posedge clk)
begin
if (VAR1 && VAR3)
VAR2[VAR5] <= VAR4;
if (VAR1)
VAR6 <= VAR2[VAR5];
end
endmodule | gpl-3.0 |
cpulabs/mist1032sa | src/core/execute/execute_port0.v | 4,000 | module MODULE1(
input wire VAR26,
input wire VAR29,
input wire VAR8,
input wire VAR9,
input wire [5:0] VAR52,
input wire [4:0] VAR31,
input wire [3:0] VAR41,
input wire [4:0] VAR39,
input wire [31:0] VAR18,
input wire [31:0] VAR1,
output wire VAR49,
output wire VAR38,
output wire [31:0] VAR34,
output wire VAR22,
output... | bsd-2-clause |
chebykinn/university | circuitry/lab1/src/controller.v | 1,182 | module MODULE1(
clk,
reset,
VAR13,
VAR9,
VAR10
);
input clk;
input reset;
output VAR13;
output VAR9;
output VAR10;
wire clk;
wire reset;
wire VAR13;
wire VAR9;
wire VAR10;
reg [31:0] VAR2 = 0;
reg [31:0] VAR7 = 0;
reg signed [31:0] VAR4 = 0;
VAR12 VAR6 (
.clk(clk),
.reset(reset),
.VAR4(VAR4),
.out(VAR13)
);
VAR12 VAR5 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbp/sky130_fd_sc_lp__sdfbbp.behavioral.v | 3,323 | module MODULE1 (
VAR1 ,
VAR17 ,
VAR31 ,
VAR26 ,
VAR14 ,
VAR3 ,
VAR12 ,
VAR6
);
output VAR1 ;
output VAR17 ;
input VAR31 ;
input VAR26 ;
input VAR14 ;
input VAR3 ;
input VAR12 ;
input VAR6;
supply1 VAR35;
supply0 VAR25;
supply1 VAR4 ;
supply0 VAR34 ;
wire VAR10 ;
wire VAR22 ;
wire VAR15 ;
reg VAR8 ;
wire VAR28 ;
wire VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4_4.v | 2,242 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR8 ,
VAR5 ,
VAR4 ,
VAR10,
VAR11,
VAR3 ,
VAR6
);
output VAR2 ;
input VAR9 ;
input VAR8 ;
input VAR5 ;
input VAR4 ;
input VAR10;
input VAR11;
input VAR3 ;
input VAR6 ;
VAR7 VAR1 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(VAR3),
.... | apache-2.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/SyncFIFO.v | 12,535 | module MODULE1(
VAR25,
VAR27,
VAR39,
VAR20,
VAR29,
VAR13,
VAR37,
VAR41,
VAR15
) ;
parameter VAR30 = 1 ;
parameter VAR22 = 2 ; parameter VAR38 = 1 ; parameter VAR12 = 1;
parameter VAR19 = 1;
input VAR25 ;
input VAR27 ;
input VAR20 ;
input [VAR30 -1 : 0] VAR29 ;
output VAR13 ;
input VAR39 ;
input VAR37 ;
output VAR15 ;
o... | gpl-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0_stub.v | 4,578 | module MODULE1(VAR23, VAR5, VAR41, VAR17,
VAR38, VAR30, VAR26, VAR60, VAR18, VAR57, VAR61, VAR29,
VAR48, VAR44, VAR40, VAR43, VAR52, VAR4, VAR58, VAR7,
VAR27, VAR19, VAR10, VAR56, VAR47, VAR53, VAR6,
VAR46, VAR12, VAR45, VAR13, VAR31, VAR50,
VAR24, VAR51, VAR63, VAR3, VAR28, VAR22,
VAR14, VAR25, VAR2, VAR16, VAR32, VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.behavioral.pp.v | 1,236 | module MODULE1( VAR1, VAR6, VAR7, VAR4, VAR5 );
input VAR1, VAR6;
inout VAR4, VAR5;
output VAR7;
VAR2 VAR3(.VAR1(VAR1),.VAR6(VAR6),.VAR7(VAR7),.VAR4(VAR4),.VAR5(VAR5));
VAR2 VAR8(.VAR1(VAR1),.VAR6(VAR6),.VAR7(VAR7),.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9234/axi_ad9234.v | 9,583 | module MODULE1 (
VAR10,
VAR51,
VAR104,
VAR99,
VAR65,
VAR5,
VAR9,
VAR14,
VAR95,
VAR55,
VAR124,
VAR26,
VAR119,
VAR112,
VAR96,
VAR2,
VAR117,
VAR42,
VAR108,
VAR56,
VAR91,
VAR59,
VAR105,
VAR78,
VAR37,
VAR1,
VAR50,
VAR85,
VAR118,
VAR106);
parameter VAR45 = 0;
parameter VAR24 = 0;
parameter VAR97 = "VAR8";
input VAR10;
input ... | gpl-3.0 |
cr88192/bgbtech_bjx1core | srvcore/FpuFp64.v | 3,788 | module MODULE1(
clk,
VAR20,
VAR11,
VAR29,
VAR39,
VAR49,
VAR14,
VAR48
);
input clk;
input VAR20; input[3:0] VAR11;
input[63:0] VAR29;
input[63:0] VAR39;
output[63:0] VAR49;
input[3:0] VAR14;
output[3:0] VAR48;
parameter[3:0] VAR22 = 4'h00;
parameter[3:0] VAR13 = 4'h01;
parameter[3:0] VAR32 = 4'h02;
parameter[3:0] VAR9 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxtp/sky130_fd_sc_hd__dfxtp_2.v | 2,128 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR1 ,
VAR3,
VAR9,
VAR2 ,
VAR8
);
output VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR3;
input VAR9;
input VAR2 ;
input VAR8 ;
VAR4 VAR6 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR5 ,
VAR7,
VAR1
);
output VAR5 ... | apache-2.0 |
ServerTech/neptune | code/user_interface_core.v | 7,474 | module MODULE1(clk, rst, VAR32, VAR12, wr, VAR3, VAR37, VAR18, VAR16, VAR20, VAR5, VAR33, VAR23, VAR27, VAR2, VAR35, VAR31, VAR14, VAR10, VAR13, VAR6, VAR24, VAR34, dout, VAR28, VAR7);
parameter VAR8 = 'd16; parameter VAR21 = 'd13; parameter VAR4 = 'd20;
input wire clk , rst , VAR32 ; input wire VAR12 ; input wire wr ,... | mit |
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