repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
GSejas/Karatsuba_FPU | FPGA_FLOW/Proyectos Funcionales Francis Jeffrey/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/fpuuart/Coun_Baud.v | 1,164 | module MODULE1 #(
parameter VAR4=10, VAR2=656 ) (
input wire clk, reset,
output wire VAR1
);
reg [VAR4-1:0] VAR3=0;
wire [VAR4-1:0] VAR5;
always @ (posedge clk , posedge reset)
if (reset)
VAR3 <= 0 ;
else
VAR3 <= VAR5;
assign VAR5 = (VAR3==(VAR2-1)) ? 0 : VAR3 + 1;
assign VAR1 = (VAR3==(VAR2-1)) ? 1'b1 : 1'b0;
endmodul... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4.behavioral.pp.v | 1,828 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR9 ,
VAR5 ,
VAR12 ,
VAR15,
VAR2,
VAR7 ,
VAR11
);
output VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR12 ;
input VAR15;
input VAR2;
input VAR7 ;
input VAR11 ;
wire VAR14 ;
wire VAR13;
or VAR10 (VAR14 , VAR12, VAR5, VAR9, VAR8 );
VAR3 VAR4 (VAR13, VAR14, VAR15, VAR2);
buf VAR1 (... | apache-2.0 |
ultraembedded/altor32 | rtl/cpu/altor32.v | 13,895 | module MODULE1
(
input VAR78 ,
input VAR160 ,
input VAR149 ,
input VAR107 ,
output VAR48 ,
output VAR104 ,
output [31:0] VAR39 ,
input [31:0] VAR25 ,
output [2:0] VAR163 ,
output VAR150 ,
output VAR31 ,
input VAR94,
input VAR130,
output [31:0] VAR62 ,
output [31:0] VAR88 ,
input [31:0] VAR89 ,
output [3:0] VAR47 ,
outp... | lgpl-3.0 |
Raimmaster/Breakout-FPGA | Main.v | 3,098 | module MODULE1(
input VAR47,
output [5:0] VAR20,
output VAR16,
output VAR4,
input VAR18,
input VAR21,
input VAR9,
input VAR36,
input VAR1,
output [3:0] VAR14
);
wire VAR35;
wire VAR49;
wire VAR6;
wire [5:0] VAR24;
wire VAR30;
wire VAR42;
wire [9:0] VAR40;
wire [9:0] VAR52;
wire [9:0] VAR37;
wire [9:0] VAR17;
wire [9:0]... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.behavioral.pp.v | 2,820 | module MODULE1( VAR26, VAR18, VAR22, VAR23, VAR10, VAR24 );
input VAR22, VAR18, VAR26;
inout VAR10, VAR24;
output VAR23;
reg VAR3;
VAR11 VAR1(.VAR26(VAR26),.VAR18(VAR18),.VAR22(VAR22),.VAR23(VAR23),.VAR10(VAR10),.VAR24(VAR24),.VAR3(VAR3));
VAR11 VAR9(.VAR26(VAR26),.VAR18(VAR18),.VAR22(VAR22),.VAR23(VAR23),.VAR10(VAR10)... | apache-2.0 |
mcgodfrey/kinetic_sculpture | servo_controller.v | 1,330 | module MODULE1 (
input clk,
input rst,
input [7:0] VAR3,
output VAR6
);
reg VAR2, VAR1;
reg [19:0] VAR4, VAR5;
assign VAR6 = VAR2;
always @(*) begin
VAR5 = VAR4 + 1'b1;
if (VAR3 + 9'd165 > VAR4[19:8]) begin
VAR1 = 1'b1;
end else begin
VAR1 = 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
VAR4 <= 1'b0;
end els... | mit |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v | 3,930 | module MODULE1
(
input clk,
input rst,
output VAR6,
input VAR4, input VAR8, input VAR12, input VAR11, input VAR3, input VAR9,
input VAR14, input VAR5 );
localparam [1:0]
VAR7 = 2'b00,
VAR13 = 2'b01,
VAR2 = 2'b10,
VAR10 = 2'b11;
reg [1:0] state = VAR2;
assign VAR6 = (state[1] && VAR12) || (!state[1] && VAR11);
wire VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ba/sky130_fd_sc_lp__o21ba.functional.pp.v | 2,037 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR11 ,
VAR5,
VAR12,
VAR2,
VAR7 ,
VAR3
);
output VAR10 ;
input VAR15 ;
input VAR11 ;
input VAR5;
input VAR12;
input VAR2;
input VAR7 ;
input VAR3 ;
wire VAR8 ;
wire VAR9 ;
wire VAR6;
nor VAR4 (VAR8 , VAR15, VAR11 );
nor VAR13 (VAR9 , VAR5, VAR8 );
VAR1 VAR16 (VAR6, VAR9, VAR12, VAR2);
b... | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/clk_gen_top/clk_switch_module.v | 6,455 | module MODULE1(
VAR1 , VAR15 , sel , VAR14 );
input VAR1 ; input VAR15 ; input sel ; output VAR14 ;
wire VAR9 ; wire VAR5 ; reg VAR2 ; reg VAR10 ;
wire VAR13 ; wire VAR8 ; reg VAR12 ; reg VAR4 ; assign VAR9 = (~sel) & (~VAR4);
assign VAR13 = sel & (~VAR10);
always @(posedge VAR1) begin : VAR3
VAR2 <= VAR9;
end
always @... | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/Loop_loop_height_hbi.v | 1,187 | module MODULE1 (
VAR5, VAR1, VAR6, clk);
parameter VAR2 = 8;
parameter VAR3 = 8;
parameter VAR4 = 256;
input[VAR3-1:0] VAR5;
input VAR1;
output reg[VAR2-1:0] VAR6;
input clk;
reg [VAR2-1:0] VAR7[0:VAR4-1];
begin
begin | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_4.behavioral.pp.v | 1,164 | module MODULE1( VAR7, VAR2, VAR4, VAR6 );
input VAR7;
inout VAR4, VAR6;
output VAR2;
VAR3 VAR1(.VAR7(VAR7),.VAR2(VAR2),.VAR4(VAR4),.VAR6(VAR6));
VAR3 VAR5(.VAR7(VAR7),.VAR2(VAR2),.VAR4(VAR4),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcon/sky130_fd_sc_ls__fahcon.behavioral.v | 1,829 | module MODULE1 (
VAR21,
VAR15 ,
VAR16 ,
VAR8 ,
VAR13
);
output VAR21;
output VAR15 ;
input VAR16 ;
input VAR8 ;
input VAR13 ;
supply1 VAR20;
supply0 VAR10;
supply1 VAR14 ;
supply0 VAR1 ;
wire VAR2 ;
wire VAR17 ;
wire VAR7 ;
wire VAR9 ;
wire VAR11;
xor VAR3 (VAR2 , VAR16, VAR8, VAR13 );
buf VAR5 (VAR15 , VAR2 );
nor VAR... | apache-2.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/synth/daala_zynq_auto_pc_120.v | 14,278 | module MODULE1 (
VAR75,
VAR11,
VAR68,
VAR111,
VAR39,
VAR61,
VAR48,
VAR104,
VAR77,
VAR13,
VAR82,
VAR102,
VAR56,
VAR76,
VAR78,
VAR112,
VAR35,
VAR8,
VAR110,
VAR10,
VAR25,
VAR103,
VAR83,
VAR6,
VAR88,
VAR45,
VAR52,
VAR27,
VAR19,
VAR66,
VAR46,
VAR57,
VAR49,
VAR43,
VAR41,
VAR1,
VAR99,
VAR101,
VAR62,
VAR100,
VAR69,
VAR64,
VAR3... | bsd-2-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodRTCC_v1_0/src/PmodRTCC.v | 9,441 | module MODULE1
(VAR137,
VAR72,
VAR114,
VAR156,
VAR130,
VAR89,
VAR113,
VAR155,
VAR37,
VAR123,
VAR15,
VAR5,
VAR43,
VAR69,
VAR47,
VAR79,
VAR90,
VAR133,
VAR55,
VAR115,
VAR73,
VAR27,
VAR143,
VAR83,
VAR1,
VAR128,
VAR66,
VAR30,
VAR116,
VAR91,
VAR74,
VAR158,
VAR135,
VAR70,
VAR54,
VAR13,
VAR29,
VAR9,
VAR86,
VAR8,
VAR17,
VAR65,
... | bsd-3-clause |
eda-globetrotter/MarcheProcessor | final/src/shift.v | 99,439 | module MODULE1 (VAR25,VAR5,VAR19,VAR32,VAR30);
output [0:127] VAR30;
input [0:127] VAR25;
input [0:127] VAR5;
input [0:1] VAR19;
input [0:4] VAR32;
parameter VAR28 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR30;
reg [0:127] VAR8;
reg [0:15] VAR24;
reg [0:15] VAR23;
reg [0:15] VAR10;
reg [0:15] VAR3;
reg [0:... | mit |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_timer.v | 6,898 | module MODULE1 (
address,
VAR12,
clk,
VAR8,
VAR33,
VAR3,
irq,
VAR24
)
;
output irq;
output [ 15: 0] VAR24;
input [ 2: 0] address;
input VAR12;
input clk;
input VAR8;
input VAR33;
input [ 15: 0] VAR3;
wire VAR17;
wire VAR14;
wire VAR9;
reg [ 3: 0] VAR27;
wire VAR25;
reg VAR11;
wire VAR18;
wire [ 31: 0] VAR26;
reg [ 31: ... | mit |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_OA_RVT_TT_201020.v | 197,600 | module MODULE1 (VAR9, VAR7, VAR3, VAR4, VAR8);
output VAR9;
input VAR7, VAR3, VAR4, VAR8;
wire VAR11, VAR6, VAR1;
wire VAR10, VAR5, VAR2;
not (VAR10, VAR8);
not (VAR1, VAR4);
and (VAR5, VAR1, VAR10);
not (VAR6, VAR3);
not (VAR11, VAR7);
and (VAR2, VAR11, VAR6, VAR10);
or (VAR9, VAR2, VAR5); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi.behavioral.pp.v | 2,238 | module MODULE1 (
VAR16 ,
VAR13 ,
VAR9 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR7,
VAR15,
VAR19 ,
VAR20
);
output VAR16 ;
input VAR13 ;
input VAR9 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR7;
input VAR15;
input VAR19 ;
input VAR20 ;
wire VAR17 ;
wire VAR14 ;
wire VAR6 ;
wire VAR11;
nand VAR2 (VAR17 , VAR9, VAR13, VAR5 );
nand ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4.behavioral.v | 1,688 | module MODULE1 (
VAR2 ,
VAR8,
VAR5,
VAR3,
VAR10,
VAR15,
VAR9
);
output VAR2 ;
input VAR8;
input VAR5;
input VAR3;
input VAR10;
input VAR15;
input VAR9;
supply1 VAR7;
supply0 VAR13;
supply1 VAR6 ;
supply0 VAR1 ;
wire VAR4;
VAR14 VAR12 (VAR4, VAR8, VAR5, VAR3, VAR10, VAR15, VAR9);
buf VAR11 (VAR2 , VAR4 );
endmodule | apache-2.0 |
neale/CS-program | 474-VLSI/UART/db/Display_PLL_altpll.v | 4,554 | module MODULE1
(
VAR6,
clk,
VAR2,
VAR1) ;
input VAR6;
output [4:0] clk;
input [1:0] VAR2;
output VAR1;
tri0 VAR6;
tri0 [1:0] VAR2;
reg VAR4;
wire [4:0] VAR7;
wire VAR3;
wire VAR5; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_pr_pp_pkg_sn/sky130_fd_sc_hs__udp_dlatch_pr_pp_pkg_sn.symbol.v | 1,559 | module MODULE1 (
input VAR3 ,
output VAR7 ,
input VAR6 ,
input VAR8 ,
input VAR5 ,
input VAR4 ,
input VAR9,
input VAR1 ,
input VAR2
);
endmodule | apache-2.0 |
YosysHQ/yosys | techlibs/ecp5/brams_map.v | 11,917 | module MODULE2 (...);
parameter VAR13 = 0;
parameter VAR243 = "VAR49";
parameter VAR192 = 18;
parameter VAR34 = 2;
parameter VAR176 = 1;
parameter VAR107 = "VAR12";
input VAR123;
input VAR99;
input VAR52;
input VAR223;
input VAR84;
input [13:0] VAR213;
input [VAR34-1:0] VAR39;
input [VAR192-1:0] VAR31;
output [VAR192-1... | isc |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen_stub.v | 1,133 | module MODULE1(VAR2, VAR1, reset)
;
input VAR2;
output VAR1;
input reset;
endmodule | gpl-3.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_ACAIN8Q5_syn.v | 8,025 | module MODULE1 ( VAR153, VAR269, VAR270, VAR243 );
input [15:0] VAR269;
input [15:0] VAR270;
output [16:0] VAR243;
input VAR153;
wire VAR321, VAR232, VAR142, VAR3, VAR242, VAR255, VAR118, VAR76, VAR133, VAR190, VAR6, VAR279, VAR172, VAR51,
VAR302, VAR167, VAR33, VAR69, VAR126, VAR171, VAR84, VAR203, VAR9, VAR186, VAR60... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/demux.v | 2,690 | module MODULE1
parameter VAR7 = 12,
parameter VAR5 = 1
)
(
input [VAR5-1:0] VAR4, input [VAR3(VAR7)-1:0] VAR6, output [VAR7*VAR5-1:0] VAR2 );
genvar VAR8;
reg [VAR7*VAR5-1:0] VAR1;
assign VAR2 = VAR1;
always @(*) begin
VAR1 = 0;
VAR1[VAR5*VAR6 +: VAR5] = VAR4;
end
endmodule | gpl-3.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_MENU.v | 2,986 | module MODULE1 (
address,
VAR12,
clk,
VAR13,
VAR1,
VAR9,
VAR2,
VAR4
)
;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR12;
input clk;
input VAR13;
input VAR1;
input VAR9;
input [ 31: 0] VAR2;
wire VAR5;
reg VAR11;
reg VAR3;
wire VAR14;
reg VAR8;
wire VAR10;
wire VAR6;
wire VAR7;
reg [ 31: 0] VAR4;
assign VAR5 = ... | gpl-2.0 |
aj-michael/Digital-Systems | Pong/Phase4/vsyncModule.v | 1,262 | module MODULE1(VAR5, VAR6, VAR10, VAR12, VAR1, VAR3, VAR9, reset, VAR13);
parameter VAR16=10;
input [VAR16-1:0] VAR6, VAR10, VAR12, VAR1;
input reset, VAR13, VAR5;
output VAR3;
output reg [VAR16-1:0] VAR9;
wire [VAR16-1:0] VAR17;
VAR8 VAR2(VAR5, VAR15, reset, VAR13);
assign VAR3 = ~((VAR17 > VAR12+VAR10) && (VAR17 <= V... | mit |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_pipe_drp.v | 25,404 | module MODULE1 #
(
parameter VAR44 = "3.0", parameter VAR87 = "VAR123", parameter VAR56 = "VAR18", parameter VAR2 = "VAR25", parameter VAR97 = 0, parameter VAR38 = 0, parameter VAR45 = 4'd11
)
(
input VAR66,
input VAR78,
input VAR104,
input [ 1:0] VAR62,
input VAR121,
input [15:0] VAR32,
input VAR111,
output [ 8:0] VAR... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/Latch_Index_Pulse.v | 1,338 | module MODULE1
(
VAR6,
reset,
VAR5,
VAR7,
VAR4
);
input VAR6;
input reset;
input VAR5;
input VAR7;
output VAR4;
wire VAR8;
wire VAR1;
reg VAR3;
assign VAR8 = 1'b1;
always @(posedge VAR6)
begin : VAR2
if (reset == 1'b1) begin
VAR3 <= 1'b0;
end
else if (VAR5) begin
VAR3 <= VAR1;
end
end
assign VAR1 = (VAR3 == 1'b0 ? VAR7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.blackbox.v | 1,395 | module MODULE1 (
VAR8 ,
VAR4,
VAR6,
VAR2,
VAR3,
VAR10
);
output VAR8 ;
input VAR4;
input VAR6;
input VAR2;
input VAR3;
input VAR10;
supply1 VAR7;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41a/sky130_fd_sc_ms__o41a.behavioral.pp.v | 2,047 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR15 ,
VAR13 ,
VAR9 ,
VAR1 ,
VAR16,
VAR3,
VAR17 ,
VAR8
);
output VAR4 ;
input VAR5 ;
input VAR15 ;
input VAR13 ;
input VAR9 ;
input VAR1 ;
input VAR16;
input VAR3;
input VAR17 ;
input VAR8 ;
wire VAR6 ;
wire VAR7 ;
wire VAR11;
or VAR2 (VAR6 , VAR9, VAR13, VAR15, VAR5 );
and VAR12 (VAR7 ,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor3/sky130_fd_sc_lp__xnor3.behavioral.v | 1,396 | module MODULE1 (
VAR7,
VAR4,
VAR8,
VAR3
);
output VAR7;
input VAR4;
input VAR8;
input VAR3;
supply1 VAR2;
supply0 VAR10;
supply1 VAR1 ;
supply0 VAR11 ;
wire VAR5;
xnor VAR6 (VAR5, VAR4, VAR8, VAR3 );
buf VAR9 (VAR7 , VAR5 );
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_mem_if_top.v | 16,134 | module MODULE1 #
(
parameter VAR87 = 2,
parameter VAR81 = 1,
parameter VAR107 = 1,
parameter VAR22 = 10,
parameter VAR83 = 0,
parameter VAR82 = 1,
parameter VAR93 = 1,
parameter VAR108 = 1,
parameter VAR56 = 9,
parameter VAR20 = 72,
parameter VAR91 = 7,
parameter VAR12 = 8,
parameter VAR120 = 4,
parameter VAR78 = 9,
pa... | mit |
alexforencich/xfcp | lib/eth/rtl/axis_xgmii_rx_64.v | 16,503 | module MODULE1 #
(
parameter VAR5 = 64,
parameter VAR19 = (VAR5/8),
parameter VAR11 = (VAR5/8),
parameter VAR17 = 4'h6,
parameter VAR7 = 16'h6666,
parameter VAR3 = 0,
parameter VAR15 = 96,
parameter VAR13 = (VAR3 ? VAR15 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR8,
input wire [VAR11-1:0] VAR... | mit |
borti4938/sd2snes | verilog/sd2snes_cx4/cx4.v | 28,382 | module MODULE1(
input [7:0] VAR31,
output [7:0] VAR24,
input [12:0] VAR51,
input VAR49,
input VAR9,
input VAR22,
input VAR12,
input [7:0] VAR8,
output [23:0] VAR29,
output VAR52,
input VAR5,
output VAR53,
output [2:0] VAR38,
input VAR50
);
reg [2:0] VAR11;
parameter VAR35 = 2'b00;
parameter VAR48 = 2'b01;
parameter VAR... | gpl-2.0 |
neale/CS-program | 474-VLSI/Lab3/tes_pll_bb.v | 15,711 | module MODULE1 (
VAR5,
VAR7,
VAR4,
VAR6,
VAR2,
VAR1,
VAR3);
input VAR5;
input VAR7;
output VAR4;
output VAR6;
output VAR2;
output VAR1;
output VAR3;
tri0 VAR5;
endmodule | unlicense |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_convert_to_ieee.v | 1,548 | module MODULE1(VAR8, VAR1, VAR3, VAR9, VAR6, VAR11, VAR10, VAR4, VAR2, VAR5, enable);
input VAR8, VAR1;
input [26:0] VAR3;
input [8:0] VAR9;
input VAR6;
output [31:0] VAR11;
input VAR10, VAR2, enable;
output VAR4, VAR5;
parameter VAR7 = 1;
assign VAR4 = VAR10;
assign VAR5 = VAR2;
generate
if (VAR7 == 0)
assign VAR11 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtp/sky130_fd_sc_ls__dlxtp.functional.v | 1,488 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR7
);
output VAR6 ;
input VAR5 ;
input VAR7;
wire VAR3;
VAR4 VAR1 (VAR3 , VAR5, VAR7 );
buf VAR2 (VAR6 , VAR3 );
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/AXIvideo2Mat.v | 43,829 | module MODULE1 (
VAR80,
VAR132,
VAR151,
VAR90,
VAR67,
VAR30,
VAR158,
VAR165,
VAR50,
VAR81,
VAR93,
VAR31,
VAR74,
VAR129,
VAR29,
VAR23,
VAR45,
VAR134,
VAR149,
VAR78,
VAR125,
VAR94,
VAR100,
VAR128,
VAR83,
VAR21,
VAR10,
VAR53,
VAR27,
VAR75,
VAR110,
VAR170,
VAR156,
VAR88,
VAR7,
VAR39,
VAR68,
VAR118,
VAR99,
VAR133
);
paramet... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.pp.symbol.v | 1,413 | module MODULE1 (
input VAR7 ,
output VAR2 ,
input VAR3,
input VAR1 ,
input VAR4 ,
input VAR5 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2.symbol.v | 1,260 | module MODULE1 (
input VAR7,
input VAR3,
output VAR4
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_demux.v | 9,560 | module MODULE1 #
(
parameter VAR41 = 4,
parameter VAR13 = 8,
parameter VAR44 = (VAR13>8),
parameter VAR38 = (VAR13/8),
parameter VAR17 = 0,
parameter VAR28 = 8,
parameter VAR39 = 0,
parameter VAR46 = 8,
parameter VAR11 = 1,
parameter VAR63 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR13-1:0] VAR14,
input wire... | mit |
VishalRohra/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/nandc.v | 19,180 | module MODULE1 #(
parameter VAR8 = VAR8,
parameter VAR21 = VAR21,
parameter VAR63 = VAR63,
parameter VAR41 = VAR41,
parameter VAR6 = 2, parameter VAR66 = 4, parameter VAR51 = 5, parameter VAR10 = 3, parameter VAR42 = 4 ) (
input wire VAR37, input wire VAR36,
input wire [2:0] VAR19, input wire [1:0] VAR61, input wire [3... | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_2/part_1/ip/clk_video/clk_video_stub.v | 1,210 | module MODULE1(VAR2, VAR1, VAR3)
;
input VAR2;
output VAR1;
output VAR3;
endmodule | gpl-2.0 |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_usb2_platform/rtl/wb_artemis_usb2_platform.v | 15,064 | module MODULE1 #(
parameter VAR29 = 2'h3,
parameter VAR80 = 4'h6
)(
input clk,
input rst,
input VAR39,
input VAR97,
input [3:0] VAR52,
input [31:0] VAR58,
input VAR88,
output reg VAR66,
output reg [31:0] VAR109,
input [31:0] VAR49,
output reg VAR106,
output VAR6,
output VAR11,
output VAR99,
output [3:0] VAR13,
output [... | gpl-2.0 |
merckhung/zet | cores/serial/rtl/serial_atx.v | 2,819 | module MODULE1 (
input clk,
input VAR2,
input VAR4, input [7:0] VAR3,
output reg VAR1, output VAR10
);
parameter VAR9 = 1; reg [3:0] state;
wire VAR5 = VAR10 ? VAR4 : 1'b0;
wire VAR11;
reg [7:0] VAR8;
assign VAR11 = (state==0);
assign VAR10 = ~VAR11;
always @(posedge clk) if(VAR11 & VAR2) VAR8 <= VAR3;
wire [7:0] VAR7 ... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_hdmi_rx/axi_hdmi_rx_core.v | 11,998 | module MODULE1 (
VAR10,
VAR18,
VAR31,
VAR27,
VAR38,
VAR64,
VAR43,
VAR25,
VAR4,
VAR30,
VAR71,
VAR77,
VAR8,
VAR15,
VAR49,
VAR7,
VAR82,
VAR19,
VAR2);
input VAR10;
input VAR18;
input [15:0] VAR31;
input VAR27;
input VAR38;
input VAR64;
input VAR43;
input [15:0] VAR25;
input [15:0] VAR4;
output VAR30;
output VAR71;
output V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxbp/sky130_fd_sc_hd__sdfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR14 ,
VAR8 ,
VAR9 ,
VAR19 ,
VAR2 ,
VAR15 ,
VAR12,
VAR13,
VAR7 ,
VAR17
);
output VAR14 ;
output VAR8 ;
input VAR9 ;
input VAR19 ;
input VAR2 ;
input VAR15 ;
input VAR12;
input VAR13;
input VAR7 ;
input VAR17 ;
wire VAR11 ;
wire VAR1;
VAR4 VAR16 (VAR1, VAR19, VAR2, VAR15 );
VAR6 VAR3 VAR5 (VAR11 , VAR1... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/image_filter_PaintMask_32_0_1080_1920_s.v | 20,760 | module MODULE1 (
VAR58,
VAR8,
VAR62,
VAR79,
VAR66,
VAR26,
VAR68,
VAR92,
VAR1,
VAR82,
VAR64,
VAR24,
VAR12,
VAR20,
VAR48,
VAR59,
VAR61,
VAR80,
VAR10,
VAR77,
VAR19,
VAR4,
VAR43,
VAR3,
VAR91,
VAR52,
VAR32,
VAR78,
VAR7,
VAR55,
VAR25,
VAR71,
VAR46,
VAR21
);
parameter VAR49 = 1'b1;
parameter VAR88 = 1'b0;
parameter VAR41 = 4'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi.behavioral.pp.v | 2,058 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR16 ,
VAR5 ,
VAR8 ,
VAR9,
VAR3,
VAR14 ,
VAR2
);
output VAR10 ;
input VAR1 ;
input VAR16 ;
input VAR5 ;
input VAR8 ;
input VAR9;
input VAR3;
input VAR14 ;
input VAR2 ;
wire VAR13 ;
wire VAR15 ;
wire VAR6;
and VAR17 (VAR13 , VAR5, VAR1, VAR16 );
nor VAR4 (VAR15 , VAR8, VAR13 );
VAR12 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp.blackbox.v | 1,344 | module MODULE1 (
VAR6 ,
VAR4,
VAR8 ,
VAR7,
VAR9
);
output VAR6 ;
input VAR4;
input VAR8 ;
input VAR7;
input VAR9;
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b.pp.blackbox.v | 1,341 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR7 ,
VAR4 ,
VAR6 ,
VAR2,
VAR5,
VAR9 ,
VAR1
);
output VAR8 ;
input VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR2;
input VAR5;
input VAR9 ;
input VAR1 ;
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_custom_add_core.v | 8,428 | module MODULE1(VAR34, VAR63, VAR61, VAR2, VAR42, VAR41, VAR37, VAR71, VAR69, enable);
input VAR34, VAR63;
input VAR41, VAR71;
output VAR37, VAR69;
input enable;
input [31:0] VAR61;
input [31:0] VAR2;
output [31:0] VAR42;
parameter VAR49 = 1;
parameter VAR19 = 0;
parameter VAR76 = 1;
parameter VAR21 = 0;
parameter VAR55... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbp/sky130_fd_sc_lp__sdfbbp.pp.blackbox.v | 1,562 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR2 ,
VAR5 ,
VAR3 ,
VAR7 ,
VAR10 ,
VAR8,
VAR1 ,
VAR4 ,
VAR6 ,
VAR12
);
output VAR9 ;
output VAR11 ;
input VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR10 ;
input VAR8;
input VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR12 ;
endmodule | apache-2.0 |
davidkoltak/tawas-core | ip/debug_ip/rtl/avalon2rcn.v | 2,444 | module MODULE1
(
input VAR8,
input VAR14,
output VAR17,
input [21:0] VAR22,
input VAR21,
input VAR16,
input [3:0] VAR6,
input [31:0] VAR19,
output [31:0] VAR2,
output VAR12,
input [68:0] VAR13,
output [68:0] VAR11
);
parameter VAR3 = 6'h3F;
reg [68:0] VAR5;
reg [68:0] VAR10;
reg [2:0] VAR7;
reg [2:0] VAR15;
reg [2:0] V... | mit |
TWW12/lzw | ip_repo/axi_compression_1.0/src/input_fifo/input_fifo_stub.v | 1,384 | module MODULE1(clk, VAR4, din, VAR2, VAR3, dout, VAR5, VAR1)
;
input clk;
input VAR4;
input [7:0]din;
input VAR2;
input VAR3;
output [7:0]dout;
output VAR5;
output VAR1;
endmodule | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2.functional.v | 1,508 | module MODULE1 (
VAR1 ,
VAR8,
VAR2,
VAR3
);
output VAR1 ;
input VAR8;
input VAR2;
input VAR3 ;
wire VAR4;
VAR5 VAR7 (VAR4, VAR8, VAR2, VAR3 );
buf VAR6 (VAR1 , VAR4);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21o/sky130_fd_sc_hs__a21o.behavioral.pp.v | 1,922 | module MODULE1 (
VAR7,
VAR10,
VAR9 ,
VAR13 ,
VAR1 ,
VAR8
);
input VAR7;
input VAR10;
output VAR9 ;
input VAR13 ;
input VAR1 ;
input VAR8 ;
wire VAR14 ;
wire VAR11 ;
wire VAR4;
and VAR12 (VAR14 , VAR13, VAR1 );
or VAR5 (VAR11 , VAR14, VAR8 );
VAR6 VAR2 (VAR4, VAR11, VAR7, VAR10);
buf VAR3 (VAR9 , VAR4 );
endmodule | apache-2.0 |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_auto_pc_1/synth/base_zynq_design_auto_pc_1.v | 15,760 | module MODULE1 (
VAR84,
VAR53,
VAR93,
VAR75,
VAR28,
VAR88,
VAR6,
VAR13,
VAR69,
VAR82,
VAR108,
VAR67,
VAR83,
VAR30,
VAR41,
VAR60,
VAR16,
VAR92,
VAR5,
VAR12,
VAR50,
VAR97,
VAR32,
VAR49,
VAR90,
VAR106,
VAR54,
VAR66,
VAR48,
VAR86,
VAR37,
VAR44,
VAR14,
VAR104,
VAR70,
VAR4,
VAR85,
VAR10,
VAR35,
VAR39,
VAR15,
VAR101,
VAR107,
... | gpl-3.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_tx/Ramdon_gen.v | 5,537 | module MODULE1(
VAR9 ,
VAR7 ,
VAR2 ,
VAR4 ,
VAR1
);
input VAR9 ;
input VAR7 ;
input VAR2 ;
input [3:0] VAR4 ;
output VAR1;
reg [9:0] VAR5 ;
reg [9:0] VAR3 ;
reg [9:0] VAR6 ;
reg [7:0] VAR8; reg VAR1;
always @ (posedge VAR7 or posedge VAR9)
if (VAR9)
VAR5 <=0;
else
VAR5 <={VAR5[8:0],~(VAR5[2]^VAR5[9])};
always @ (VAR4 o... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.functional.pp.v | 1,681 | module MODULE1( VAR7, VAR9, VAR20, VAR19, VAR5, VAR6, VAR1, VAR10 );
input VAR19, VAR20, VAR7, VAR9, VAR6, VAR1, VAR10;
output VAR5;
wire VAR4;
not VAR12( VAR4, VAR20 );
wire VAR25;
not VAR18( VAR25, VAR7 );
wire VAR24;
and VAR3( VAR24, VAR4, VAR25 );
wire VAR23;
not VAR11( VAR23, VAR9 );
wire VAR16;
and VAR22( VAR16, ... | apache-2.0 |
SymbiFlow/yosys | techlibs/gowin/brams_map.v | 4,036 | module \VAR8 (VAR12, VAR30, VAR24, VAR26, VAR35, VAR14, VAR17, VAR38);
parameter VAR19 = 10;
parameter VAR16 = 16;
parameter VAR31 = 1;
parameter [16383:0] VAR39 = 16384'VAR2;
parameter VAR15 = 1;
parameter VAR13 = 1;
input VAR12;
input VAR30;
input [VAR19-1:0] VAR24;
input [VAR16-1:0] VAR26;
input [VAR31-1:0] VAR35;
i... | isc |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/eth_outputcontrol.v | 6,078 | module MODULE1(VAR6, VAR5, VAR15, VAR12, VAR14, VAR3, VAR2, VAR1, VAR9, VAR7);
input VAR6; input VAR5; input VAR3; input VAR2; input VAR15; input VAR12; input [6:0] VAR14; input VAR1;
output VAR9; output VAR7;
wire VAR10;
reg VAR11;
reg VAR4;
reg VAR7;
reg VAR8;
reg VAR13;
reg VAR9;
assign VAR10 = VAR3 & VAR15 & ( VAR1... | gpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/utils/cdc_pulse_sync.v | 1,384 | module MODULE1 (
input wire VAR7,
input wire VAR10,
input wire VAR11,
output wire VAR12
);
wire VAR9;
reg [1:0] VAR6;
always @(posedge VAR7) begin
VAR6[0] <= VAR10;
VAR6[1] <= VAR6[0];
end
wire VAR2;
assign VAR2 = !VAR6[1] && VAR6[0];
reg VAR3;
VAR8 VAR3 = 0; always @(posedge VAR7) begin
if (VAR9)
VAR3 <= 0;
end
else i... | bsd-3-clause |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_edge_detection_gaussian_smoothing_filter.v | 9,519 | module MODULE1 (
clk,
reset,
VAR20,
VAR26,
VAR22
);
parameter VAR21 = 640;
input clk;
input reset;
input [ 7: 0] VAR20;
input VAR26;
output [ 8: 0] VAR22;
wire [ 7: 0] VAR24[ 3: 0];
reg [ 7: 0] VAR17[ 4: 0];
reg [ 7: 0] VAR10[ 4: 0];
reg [ 7: 0] VAR4[ 4: 0];
reg [ 7: 0] VAR12[ 4: 0];
reg [ 7: 0] VAR29[ 4: 0];
reg [15: ... | mit |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/83dd42eed290f363/design_1_xbar_0_stub.v | 3,579 | module MODULE1(VAR31, VAR29, VAR2, VAR37,
VAR21, VAR34, VAR20, VAR9, VAR15, VAR8,
VAR26, VAR24, VAR13, VAR25, VAR32, VAR40,
VAR23, VAR1, VAR17, VAR22, VAR35, VAR12,
VAR28, VAR38, VAR16, VAR27, VAR5, VAR36,
VAR3, VAR4, VAR7, VAR39, VAR18, VAR30,
VAR6, VAR19, VAR33, VAR14, VAR11, VAR10)
;
input VAR31;
input VAR29;
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111a/sky130_fd_sc_hd__o2111a.symbol.v | 1,393 | module MODULE1 (
input VAR2,
input VAR4,
input VAR3,
input VAR10,
input VAR5,
output VAR6
);
supply1 VAR8;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3/sky130_fd_sc_hs__nand3.pp.symbol.v | 1,253 | module MODULE1 (
input VAR3 ,
input VAR2 ,
input VAR6 ,
output VAR1 ,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_out.v | 6,774 | module MODULE1 (
VAR13,
VAR30,
VAR36,
VAR24,
VAR17,
VAR11,
VAR14,
VAR3,
VAR8,
VAR38,
VAR29,
VAR42,
VAR35,
VAR19,
VAR25,
VAR27,
VAR12,
VAR45,
VAR2,
VAR22,
VAR18,
VAR20,
VAR26,
VAR9,
VAR1,
VAR4,
VAR10,
VAR6,
VAR15,
VAR39,
VAR21,
VAR40,
VAR44,
VAR32,
VAR5,
VAR28,
VAR43,
VAR34,
VAR23,
VAR37
);
input VAR13; input VAR30; inp... | gpl-2.0 |
KestrelComputer/polaris | wb-bridge/rtl/verilog/bridge.v | 4,195 | module MODULE1(
input VAR55,
input [1:0] VAR52,
input [2:0] VAR36,
input [63:0] VAR3,
output [63:0] VAR19,
output [7:0] VAR38,
output [63:0] VAR24,
input [63:0] VAR5
);
wire VAR27 = (VAR52 == 2'b00);
wire VAR2 = (VAR52 == 2'b01);
wire VAR14 = (VAR52 == 2'b10);
wire VAR4 = (VAR52 == 2'b11);
wire VAR62 = VAR36[2:0] == 3'... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn.pp.blackbox.v | 1,289 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4,
VAR3,
VAR7,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR4;
input VAR3;
input VAR7;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21boi/sky130_fd_sc_ms__a21boi.behavioral.v | 1,639 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR15 ,
VAR11
);
output VAR8 ;
input VAR10 ;
input VAR15 ;
input VAR11;
supply1 VAR3;
supply0 VAR4;
supply1 VAR14 ;
supply0 VAR6 ;
wire VAR7 ;
wire VAR12 ;
wire VAR1;
not VAR2 (VAR7 , VAR11 );
and VAR13 (VAR12 , VAR10, VAR15 );
nor VAR9 (VAR1, VAR7, VAR12 );
buf VAR5 (VAR8 , VAR1 );
endm... | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOS_Sys/synthesis/submodules/Ultrasound_interface.v | 4,992 | module MODULE1(clk,VAR11,VAR19,address,write,VAR14,read,VAR16,VAR8,VAR6,VAR20);
parameter VAR18=4'b0001, VAR21=4'b0010, VAR2=4'b0100, VAR4=4'b1000;
input clk;
input VAR11;
input VAR19;
input [1:0]address;
input write;
input [31:0] VAR14;
input read;
input [3:0] VAR16;
output reg [31:0] VAR8;
input VAR20;
output reg VAR... | gpl-2.0 |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_hdmi.v | 14,055 | module MODULE1 (
VAR75,
VAR105,
VAR87,
VAR69,
VAR119,
VAR34,
VAR43,
VAR45,
VAR80,
VAR78,
VAR32,
VAR14,
VAR33,
VAR82,
VAR83,
VAR20,
VAR59,
VAR47,
VAR124,
VAR106,
VAR22,
VAR86,
VAR120,
VAR131,
VAR1,
VAR35,
VAR19,
VAR41,
VAR108);
input VAR75;
output VAR105;
output VAR87;
output VAR69;
output [15:0] VAR119;
output VAR34;
o... | mit |
bluespec/Flute | src_bsc_lib_RTL/MakeResetA.v | 1,638 | module MODULE1 (
VAR1,
VAR14,
VAR10,
VAR12,
VAR7,
VAR13
);
parameter VAR8 = 2 ; parameter VAR2 = 1 ;
input VAR1 ;
input VAR14 ;
input VAR10 ;
output VAR12 ;
input VAR7 ;
output VAR13 ;
reg rst ;
wire VAR13 ;
assign VAR12 = rst == VAR4 ;
VAR11 #(VAR8) VAR9 (.VAR1(VAR7),
.VAR3(rst),
.VAR13(VAR13));
always@(posedge VAR1 o... | apache-2.0 |
Rod2693rm/netfpga-firewal-ddos | src/header_e.v | 9,632 | module MODULE1
parameter VAR77 = 64,
parameter VAR79 = VAR77/8,
parameter VAR4 = 2
)
(
input [VAR77-1:0] VAR45,
input [VAR79-1:0] VAR73,
input VAR9,
output VAR58,
output [31:0] VAR26,
output [31:0] VAR11,
output [15:0] VAR15,
output [15:0] VAR3,
output [7:0] VAR54,
input VAR30,
input VAR65,
input VAR43,
input [VAR10-1:... | gpl-3.0 |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/X5000_ztexmerge/hdl/comm.v | 2,173 | module MODULE1 (
input VAR10,
input VAR17,
input [31:0] VAR5,
output [255:0] VAR18,
output [95:0] VAR6
);
reg [351:0] VAR9 = 352'd0;
reg [255:0] VAR23 = 256'd0;
reg [95:0] VAR3 = 96'd0;
assign VAR18 = VAR23;
assign VAR6 = VAR3;
reg [31:0] VAR19 = 32'd0;
reg [3:0] VAR11 = 3'd0;
reg read = 1'b0;
wire [8:0] VAR7;
wire VAR... | gpl-3.0 |
ineganov/bare_system | hard/mcpu.v | 5,505 | module MODULE1( input VAR27,
input VAR7,
input VAR11,
input VAR29,
output [29:0] VAR9,
input [31:0] VAR36,
output VAR25,
output [3:0] VAR14,
output [29:0] VAR35,
output [31:0] VAR43,
input [31:0] VAR4 );
wire VAR33, VAR13, VAR38, VAR17,
VAR34, VAR28, VAR32, VAR31, VAR16,
VAR5, VAR1, VAR21, VAR26,
VAR44;
wire [1:0] VAR1... | gpl-2.0 |
DeadWitcher/amber-de0-nano | hw/vlog/system/boot_mem32.v | 6,670 | module MODULE1 #(
parameter VAR13 = 32,
parameter VAR3 = 4,
parameter VAR29 = 12
)(
input VAR30,
input [31:0] VAR11,
input [VAR3-1:0] VAR16,
input VAR8,
output [VAR13-1:0] VAR12,
input [VAR13-1:0] VAR31,
input VAR20,
input VAR9,
output VAR17,
output VAR10
);
wire VAR14;
wire VAR24;
reg [7:0] VAR18 = 8'h0f;
reg [1:0] VA... | lgpl-2.1 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_fpga_only_master.v | 21,649 | module MODULE1 #(
parameter VAR36 = 0,
parameter VAR28 = 50000,
parameter VAR47 = 2
) (
input wire VAR9, input wire VAR24, output wire [31:0] VAR4, input wire [31:0] VAR27, output wire VAR48, output wire VAR17, output wire [31:0] VAR11, input wire VAR39, input wire VAR12, output wire [3:0] VAR3, output wire VAR21 );
wi... | gpl-3.0 |
ruishihan/R7-with-notes | src/rtl/S2A_controller.v | 3,236 | module MODULE1(
rst,
VAR19,
sync,
VAR22,
VAR3,
VAR17,
VAR4,
VAR1,
VAR28,
VAR10,
VAR29,
VAR20,
VAR6,
VAR7,
VAR25,
VAR9,
VAR16,
VAR27,
VAR30
);
parameter VAR18 = 3'd0;
parameter VAR11 = 3'd1;
parameter VAR21 = 3'd2;
parameter VAR5 = 3'd3;
input VAR19,rst,sync,VAR22;
output VAR30;
output reg[4:0] VAR27;
output[4:0] VAR3;
... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_38.v | 25,468 | module MODULE2 (
clk,
reset,
VAR121,
VAR76,
VAR69,
VAR23,
VAR227
);
parameter VAR214 = 18;
parameter VAR27 = 38;
parameter VAR10 = 19;
localparam VAR102 = 39;
input clk;
input reset;
input VAR121;
input VAR76;
input [VAR214-1:0] VAR69; output VAR23;
output [VAR214-1:0] VAR227;
localparam VAR75 = 18; localparam VAR142 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b.functional.v | 1,393 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR6;
wire VAR2 ;
wire VAR4;
not VAR8 (VAR2 , VAR5 );
and VAR1 (VAR4, VAR2, VAR6 );
buf VAR7 (VAR3 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapmet1/sky130_fd_sc_hs__tapmet1.blackbox.v | 1,187 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/clk_gen.v | 2,722 | module MODULE1 (
input wire VAR7,
input wire VAR3,
output wire clk,
output wire VAR4,
output wire VAR2
);
wire VAR5;
wire VAR9;
assign VAR5 = 1'b1;
assign VAR9 = (VAR3 == VAR8) ? VAR6 : VAR1;
assign VAR2 = ((VAR3 == VAR8) || (VAR5 == VAR1)) ?
assign clk = VAR7;
assign VAR4 = ~VAR7;
endmodule | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/I2C/I2C_Top.v | 10,314 | module MODULE1(
input clk,
input VAR30,
input rst,
input en,
input VAR32,
input VAR3,
input VAR25,
input VAR11,
input [7:0] VAR28,
output reg VAR26,
output reg VAR35,
output reg [7:0] VAR10,
output VAR40,
inout VAR31
);
reg VAR2, VAR29, VAR13, VAR37, VAR17; wire VAR4, VAR14; VAR36 VAR24 ( .clk(clk), .VAR30(VAR30), .rst... | mit |
seyedmaysamlavasani/GorillaPP | chisel/Gorilla++/verilogOrig/Top-harness-augmented-npu.v | 3,088 | module MODULE1;
reg clk = 0;
reg reset = 1;
wire [31:0] VAR3;
wire [7:0] VAR2;
wire [7:0] VAR4;
wire [7:0] VAR1; | bsd-3-clause |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_dipsw_pio.v | 6,182 | module MODULE1 (
address,
VAR9,
clk,
VAR13,
VAR4,
VAR5,
VAR14,
irq,
VAR8
)
;
output irq;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR9;
input clk;
input [ 9: 0] VAR13;
input VAR4;
input VAR5;
input [ 31: 0] VAR14;
wire VAR11;
reg [ 9: 0] VAR12;
reg [ 9: 0] VAR15;
wire [ 9: 0] VAR6;
reg [ 9: 0] VAR10;
wire VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2/sky130_fd_sc_hd__or2.blackbox.v | 1,227 | module MODULE1 (
VAR5,
VAR7,
VAR4
);
output VAR5;
input VAR7;
input VAR4;
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
jotego/jt12 | hdl/jt12_eg.v | 6,025 | module MODULE1 (
input rst,
input clk,
input VAR9 ,
input VAR1,
input VAR54,
input [4:0] VAR83,
input [4:0] VAR53, input [4:0] VAR17, input [4:0] VAR36, input [3:0] VAR46, input [3:0] VAR100, input [1:0] VAR57, input VAR91,
input [2:0] VAR101,
input VAR102,
input [6:0] VAR43,
input VAR98,
input [1:0] VAR40,
input [6:0]... | gpl-3.0 |
GLADICOS/AES128 | rtl/mix_columns.v | 4,384 | module MODULE1
(
output [31:0] VAR9,
output [31:0] VAR7,
input [31:0] VAR10
);
localparam integer VAR2 = 32;
localparam integer VAR15 = 8;
localparam integer VAR8 = 4;
wire [VAR15 - 1 : 0] VAR11 [0 : VAR8 - 1];
wire [VAR15 - 1 : 0] VAR6[0 : VAR8 - 1];
wire [VAR15 - 1 : 0] VAR14 [0 : VAR8 - 2];
function [7:0] VAR4;
inpu... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/diode/sky130_fd_sc_hd__diode.blackbox.v | 1,214 | module MODULE1 (
VAR4
);
input VAR4;
supply1 VAR3;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/homework_bb.v | 5,006 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/tri_mode_eth_mac_v5_2_fifo_block.v | 14,206 | module MODULE1 #(
parameter VAR82 = 32'h00
) (
input VAR11,
input VAR28,
input VAR1,
input VAR61,
input VAR87,
output VAR33,
output VAR37,
output [27:0] VAR43,
output VAR34,
input VAR14,
input VAR3,
output [7:0] VAR73,
output VAR62,
input VAR24,
output VAR19,
output VAR58,
input [7:0] VAR32,
output [31:0] VAR76,
output... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/ppu.v | 33,262 | module MODULE1(
input clk,
input VAR199,
input reset,
output [239:0] VAR80,
output [239:0] VAR97,
input [63:0] VAR187,
input [23:0] VAR88,
input VAR25,
input VAR29,
output VAR51,
input VAR228,
input [63:0] VAR274,
input [23:0] VAR20,
input VAR215,
input VAR39,
output VAR301,
input VAR2,
input VAR53,
input [63:0] VAR59,... | mit |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_5/synth/design_1_auto_pc_5.v | 15,745 | module MODULE1 (
VAR44,
VAR80,
VAR23,
VAR88,
VAR35,
VAR54,
VAR63,
VAR65,
VAR22,
VAR45,
VAR55,
VAR39,
VAR109,
VAR111,
VAR2,
VAR19,
VAR42,
VAR1,
VAR86,
VAR84,
VAR47,
VAR26,
VAR10,
VAR73,
VAR85,
VAR81,
VAR72,
VAR17,
VAR67,
VAR106,
VAR40,
VAR56,
VAR59,
VAR50,
VAR112,
VAR41,
VAR64,
VAR43,
VAR11,
VAR32,
VAR101,
VAR13,
VAR14,... | gpl-3.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_iir_block.v | 15,834 | module MODULE1
parameter VAR85 = 1,
parameter VAR17 = 3,
parameter VAR7 = 1000
)
(
input VAR12 , input VAR16 , input [ 14-1: 0] VAR37 , output reg [ 14-1: 0] VAR24 ,
input [ 16-1: 0] addr,
input VAR80,
input VAR10,
output reg ack,
output reg [ 32-1: 0] VAR55,
input [ 32-1: 0] VAR69
);
reg [VAR6-1:0] VAR71;
reg VAR42;
r... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.functional.pp.v | 1,066 | module MODULE1( VAR9, VAR2, VAR4, VAR7, VAR1 );
input VAR4, VAR9;
inout VAR7, VAR1;
output VAR2;
wire VAR10;
not VAR6( VAR10, VAR4 );
wire VAR8;
not VAR3( VAR8, VAR9 );
and VAR5( VAR2, VAR10, VAR8 );
endmodule | apache-2.0 |
jeremyherbert/real_time_stdev | sqrt/hdl/sqrt.v | 3,230 | module MODULE1 #(parameter VAR19 = 28) (
input wire [VAR19-1:0] VAR4,
output wire [(VAR19/2+1):0] VAR13,
output wire [(VAR19/2-1):0] VAR16,
input wire reset,
input wire clk
);
localparam VAR9 = VAR19/2;
genvar VAR2;
generate
for (VAR2=VAR9-1; VAR2 >= 0; VAR2=VAR2-1) begin : VAR21
wire [VAR19-1 - VAR20:0] VAR5;
wire [VA... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/source/pcie_blk_ll_arb.v | 34,095 | module MODULE1
parameter VAR74 = 0,
parameter VAR4 = 0
)
(
input wire clk,
input wire VAR99,
output reg VAR60,
output reg [2:0] VAR75 = 0,
output wire [1:0] VAR42,
output wire VAR64,
output wire VAR92,
input wire VAR28,
input wire VAR93,
input wire VAR70,
input wire VAR36,
input wire [7:0] VAR57,
input wire [7:0] VAR76... | lgpl-3.0 |
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