repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
JakeMercer/mac | MAC_components/state_machines/rx.v | 4,899 | module MODULE1 #(
parameter VAR37 = 3'h0,
parameter VAR6 = 3'h1,
parameter VAR26 = 3'h2,
parameter VAR12 = 3'h3,
parameter VAR35 = 3'h4,
parameter VAR7 = 3'h5
)(
input reset,
input VAR20,
input VAR23,
input [7:0] VAR9,
input VAR15,
output reg [7:0] VAR16,
output reg VAR34,
output reg VAR5,
output reg VAR14,
input wire ... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_lvc_wpad/sky130_fd_io__top_ground_lvc_wpad.blackbox.v | 1,686 | module MODULE1 (
VAR18 ,
VAR10,
VAR14
);
inout VAR18 ;
inout VAR10;
inout VAR14;
supply0 VAR20;
supply0 VAR6;
supply1 VAR12 ;
supply1 VAR8 ;
supply1 VAR3 ;
supply0 VAR5 ;
supply0 VAR7 ;
supply1 VAR4 ;
supply1 VAR11 ;
supply1 VAR1 ;
supply1 VAR13 ;
supply1 VAR17 ;
supply1 VAR15 ;
supply0 VAR19 ;
supply0 VAR16 ;
supply0 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3/sky130_fd_sc_ms__or3_2.v | 2,153 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR7,
VAR1,
VAR2 ,
VAR3
);
output VAR5 ;
input VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR7;
input VAR1;
input VAR2 ;
input VAR3 ;
VAR10 VAR4 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE1 (... | apache-2.0 |
hakehuang/pycpld | quartus-II/top_twrkv58/data_deal.v | 1,536 | module MODULE1(
clk,
VAR4,
VAR2,
VAR1,
VAR5,
VAR7,
VAR6,
VAR9
);
input clk;
input VAR4;
input [6:0] VAR2;
input VAR1;
output [6:0] VAR5;
output VAR7;
input VAR6;
output VAR9;
reg [6:0] VAR3;
reg VAR9;
reg [6:0] VAR5;
reg VAR7;
reg VAR8;
always @(posedge clk or negedge VAR4)begin
if(!VAR4)begin
VAR3 <= 7'h0;
VAR9 <= 1'h... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_intp2_2.v | 3,583 | module MODULE1 (
clk,
VAR12,
VAR6,
VAR13);
input clk;
input [15:0] VAR12;
output [15:0] VAR6;
output [15:0] VAR13;
reg [15:0] VAR7 = 'd0;
reg [15:0] VAR1 = 'd0;
reg [15:0] VAR5 = 'd0;
reg [15:0] VAR8 = 'd0;
reg [15:0] VAR11 = 'd0;
reg [15:0] VAR10 = 'd0;
always @(posedge clk) begin
VAR7 <= VAR1;
VAR1 <= VAR5;
VAR5 <= V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.functional.pp.v | 1,803 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR10,
VAR6 ,
VAR5 ,
VAR3 ,
VAR7
);
output VAR9 ;
input VAR8 ;
input VAR10;
input VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR7 ;
wire VAR1;
and VAR4 (VAR1, VAR8, VAR10 );
VAR2 VAR11 (VAR9 , VAR1, VAR6, VAR5);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi.functional.v | 1,476 | module MODULE1 (
VAR2 ,
VAR4,
VAR5,
VAR10,
VAR3,
VAR11
);
output VAR2 ;
input VAR4;
input VAR5;
input VAR10;
input VAR3;
input VAR11;
wire VAR7 ;
wire VAR6;
and VAR9 (VAR7 , VAR4, VAR5, VAR10, VAR3 );
nor VAR1 (VAR6, VAR11, VAR7 );
buf VAR8 (VAR2 , VAR6 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | src/alu.v | 174,945 | module MODULE1 (VAR29,VAR2,VAR33,VAR22,VAR1);
output [0:127] VAR1;
input [0:127] VAR29;
input [0:127] VAR2;
input [0:1] VAR33;
input [0:4] VAR22;
parameter VAR27 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR1;
reg [0:127] VAR11;
reg [0:15] VAR30;
reg [0:15] VAR21;
reg [0:15] VAR19;
reg [0:15] VAR17;
reg [0:1... | mit |
mathiashelsen/WolfCoreOne | logic/quartus_prj/mainPLL.v | 17,092 | module MODULE1 (
input wire VAR4, input wire rst, output wire VAR2, output wire VAR5 );
VAR3 VAR1 (
.VAR4 (VAR4), .rst (rst), .VAR2 (VAR2), .VAR5 (VAR5) );
endmodule | mit |
joaocarlos/udlx-verilog | rtl/pipeline/registers/if_id_reg.v | 2,489 | module MODULE1
parameter VAR3 = 20,
parameter VAR4 = 32
)(
input clk, input VAR5, input en,
input VAR6, input VAR8, input [VAR4-1:0] VAR9, input [VAR3-1:0] VAR1,
output reg [VAR3-1:0] VAR2, output reg [VAR4-1:0] VAR7 );
always@(posedge clk or negedge VAR5)begin
if(!VAR5) begin
VAR2 <= 0;
VAR7 <= 0;
end else if((!VAR6)&... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_wseldp.v | 7,137 | module MODULE1 (
VAR5, VAR7, VAR11,
VAR9,
VAR21, VAR30, VAR32, VAR22, VAR8,
VAR24, VAR1
);
input VAR21,
VAR30,
VAR32;
input [135:0] VAR22,
VAR8;
input [3:0] VAR24;
input [1:0] VAR1;
output [33:0] VAR5;
output [33:0] VAR7;
output [67:0] VAR11;
output VAR9;
wire [3:0] VAR12,
VAR3;
wire [1:0] VAR28;
wire [33:0] VAR29,
VAR... | gpl-2.0 |
openlogic/ol-github-linguist | samples/Verilog/pipeline_registers.v | 3,369 | module MODULE1
(
input clk,
input VAR7,
input [VAR4-1:0] VAR5,
output reg [VAR4-1:0] VAR6
);
parameter
VAR4 = 10,
VAR2 = 5;
generate
genvar VAR3;
if (VAR2 == 0) begin
always @ *
VAR6 = VAR5;
end
else if (VAR2 == 1) begin
always @ (posedge clk or negedge VAR7)
VAR6 <= (!VAR7) ? 0 : VAR5;
end
else begin
reg [VAR4*(VAR2-1... | mit |
richard42/CoCo3FPGA | FFF0_bb.v | 5,901 | module MODULE1 (
address,
VAR4,
VAR2,
VAR3,
VAR1);
input [10:0] address;
input VAR4;
input [7:0] VAR2;
input VAR3;
output [7:0] VAR1;
tri1 VAR4;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp_1.v | 2,128 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR4 ,
VAR1,
VAR8,
VAR5 ,
VAR7
);
output VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR1;
input VAR8;
input VAR5 ;
input VAR7 ;
VAR9 VAR6 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3 ,
VAR2,
VAR4
);
output VAR3 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai.blackbox.v | 1,400 | module MODULE1 (
VAR1 ,
VAR8,
VAR2,
VAR7,
VAR4,
VAR10
);
output VAR1 ;
input VAR8;
input VAR2;
input VAR7;
input VAR4;
input VAR10;
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.symbol.v | 1,413 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR6 ,
input VAR1,
input VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3b/sky130_fd_sc_ms__or3b_1.v | 2,209 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR10 ,
VAR5 ,
VAR4,
VAR6,
VAR7 ,
VAR2
);
output VAR1 ;
input VAR9 ;
input VAR10 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR7 ;
input VAR2 ;
VAR8 VAR3 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
ammelto/FPGAdventure | Adventure/BlackInner.v | 1,166 | module MODULE1(VAR1, VAR5, VAR3, VAR2, VAR6);
input VAR1;
input [9:0]VAR5;
input [8:0]VAR3;
input [7:0]VAR6;
output [7:0]VAR2;
reg [7:0]VAR4;
always @(posedge VAR1) begin
if(((VAR3 < 40) && (VAR5 < 260)) || ((VAR3 < 40) && ~(VAR5 < 380))) begin
VAR4[7:0] <= VAR6;
end
else if(VAR5 < 40) begin
VAR4[7:0] <= VAR6;
end
else... | mit |
CospanDesign/nysa-sdio-device | rtl/cia/sdio_cia.v | 14,090 | module MODULE1 #(
parameter VAR86 = 8,
parameter VAR61 = 1'b0
)(
input clk, input rst,
input VAR23,
input VAR117,
output VAR49,
output VAR85,
input VAR79,
input VAR108,
input [17:0] VAR33,
input VAR83,
input [17:0] VAR47,
input [7:0] VAR28,
output [7:0] VAR4,
output VAR51,
output [7:0] VAR113,
output VAR105,
output VAR... | mit |
bargei/NoC264 | NoC264_2x2/hps_fpga/hps_fpga_bb.v | 6,827 | module MODULE1 (
VAR13,
VAR30,
VAR84,
VAR10,
VAR65,
VAR3,
VAR67,
VAR43,
VAR75,
VAR83,
VAR2,
VAR44,
VAR87,
VAR74,
VAR24,
VAR31,
VAR11,
VAR9,
VAR59,
VAR52,
VAR26,
VAR93,
VAR25,
VAR14,
VAR85,
VAR66,
VAR45,
VAR55,
VAR34,
VAR42,
VAR64,
VAR77,
VAR21,
VAR89,
VAR68,
VAR57,
VAR1,
VAR32,
VAR71,
VAR72,
VAR62,
VAR46,
VAR70,
VAR81,... | mit |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/credit_manager.v | 5,959 | module MODULE1 #(
parameter VAR19 = 0
)(
input clk,
input rst,
output [2:0] VAR15, input VAR14,
input [7:0] VAR12, input [11:0] VAR8,
output VAR13, input [9:0] VAR21,
input VAR20,
input [9:0] VAR6,
input VAR9
);
reg [7:0] VAR4;
reg [11:0] VAR17;
wire VAR10;
wire VAR1;
reg [7:0] VAR22;
wire [7:0] VAR2;
wire [11:0] VAR23... | mit |
petrmikheev/miksys | verilog/RAM4096x64_2RW.v | 11,253 | module MODULE1 (
VAR12,
VAR13,
VAR23,
VAR18,
VAR52,
VAR64,
VAR6,
VAR37,
VAR8,
VAR48,
VAR4);
input [11:0] VAR12;
input [11:0] VAR13;
input [7:0] VAR23;
input [7:0] VAR18;
input VAR52;
input [63:0] VAR64;
input [63:0] VAR6;
input VAR37;
input VAR8;
output [63:0] VAR48;
output [63:0] VAR4;
tri1 [7:0] VAR23;
tri1 [7:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf.behavioral.pp.v | 1,755 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR1,
VAR5,
VAR6 ,
VAR9
);
output VAR8 ;
input VAR11 ;
input VAR1;
input VAR5;
input VAR6 ;
input VAR9 ;
wire VAR4 ;
wire VAR2;
buf VAR7 (VAR4 , VAR11 );
VAR10 VAR12 (VAR2, VAR4, VAR1, VAR5);
buf VAR3 (VAR8 , VAR2 );
endmodule | apache-2.0 |
pdaxrom/p601zero | uart_rx.v | 4,073 | module MODULE1 #
(
parameter VAR10 = 8
)
(
input wire clk,
input wire rst,
output wire [VAR10-1:0] VAR17,
output wire VAR7,
input wire VAR12,
input wire VAR18,
output wire VAR9,
output wire VAR3,
output wire VAR4,
input wire [15:0] VAR11
);
reg [VAR10-1:0] VAR16 = 0;
reg VAR2 = 0;
reg VAR5 = 1;
reg VAR13 = 0;
reg VAR6 ... | gpl-3.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/arria2gx_pmem.v | 7,637 | module MODULE1 (
address,
VAR25,
VAR30,
VAR28,
VAR42,
VAR18,
VAR20);
input [11:0] address;
input [1:0] VAR25;
input VAR30;
input VAR28;
input [15:0] VAR42;
input VAR18;
output [15:0] VAR20;
tri1 [1:0] VAR25;
tri1 VAR30;
tri1 VAR28;
wire [15:0] VAR39;
wire [15:0] VAR20 = VAR39[15:0];
VAR57 VAR34 (
.VAR43 (VAR30),
.VAR36... | bsd-3-clause |
DoctorWkt/CSCv2 | Verilog/TinyFPGA_B.v | 2,520 | module MODULE1 (
input VAR6,
output VAR19,
);
reg [15:0] counter=0;
always @(posedge VAR6) counter <= counter + 1;
wire VAR16;
assign VAR16= counter[11];
wire VAR21;
wire [3:0] VAR18;
wire [3:0] VAR24;
wire [7:0] VAR5;
wire VAR1;
wire [7:0] address;
wire [3:0] VAR20;
wire [2:0] VAR12;
wire [3:0] VAR15;
wire [3:0] VAR13... | gpl-3.0 |
CospanDesign/nysa-sata | rtl/link/sata_link_layer_read.v | 9,832 | module MODULE1 (
input rst, input clk,
input VAR15,
input en,
output VAR3,
input VAR26,
input VAR8,
input VAR48,
input VAR33,
input VAR11,
input VAR22,
input VAR29,
input VAR13,
input VAR21,
input VAR7,
input VAR31,
input VAR44,
output [31:0] VAR45,
output VAR32,
input [31:0] VAR30,
input [3:0] VAR19,
output reg VAR27,... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_122.v | 1,616 | module MODULE1 (
VAR5,
VAR15
);
input [31:0] VAR5;
output [31:0]
VAR15;
wire [31:0]
VAR16,
VAR8,
VAR14,
VAR6,
VAR9,
VAR3,
VAR12,
VAR13,
VAR2,
VAR7,
VAR10;
assign VAR16 = VAR5;
assign VAR6 = VAR16 << 7;
assign VAR13 = VAR16 << 4;
assign VAR3 = VAR9 << 2;
assign VAR10 = VAR2 - VAR7;
assign VAR2 = VAR12 - VAR13;
assign VA... | mit |
scalable-networks/ext | uhd/fpga/usrp2/models/serdes_model.v | 1,551 | module MODULE1
(input VAR14,
input VAR8,
input VAR15,
input [15:0] VAR9,
output VAR1,
output VAR10,
output VAR11,
output [15:0] VAR4,
input VAR7,
input VAR2);
wire [15:0] VAR6;
wire VAR5, VAR3;
reg [7:0] VAR13;
reg VAR12;
always @(posedge VAR14) VAR12 <= VAR15;
always @(posedge VAR14) VAR13 <= VAR9[15:8];
assign VAR5 =... | gpl-2.0 |
cospan/prometheus_fpga | rtl/slave_fifo/prometheus_fx3_zlp.v | 2,995 | module MODULE1(
input VAR3,
input VAR11,
input VAR4,
input VAR12,
input VAR18,
output VAR5,
output VAR2,
output [31:0] VAR19
);
reg [2:0]VAR14;
reg [2:0]VAR1;
parameter [2:0] VAR15 = 3'd0;
parameter [2:0] VAR16 = 3'd1;
parameter [2:0] VAR13 = 3'd2;
parameter [2:0] VAR6 = 3'd3;
parameter [2:0] VAR10 = 3'd4;
reg [3:0]VAR... | gpl-3.0 |
valptek/v586 | board_specific_files/esa11/TOP_SYS.v | 18,191 | module MODULE1(
VAR415,
VAR166,
VAR157,
VAR144,VAR111,
VAR335,
VAR67,
VAR436,
VAR185,
VAR258,
VAR384,
VAR442,
VAR420,
VAR168,
VAR164,
VAR446,
VAR382,
VAR96,
VAR37,
VAR123,VAR290,VAR419,
VAR435,
VAR26,
VAR287,
VAR195,
VAR395
);
wire [2:0] VAR358;
input VAR415,VAR166;
input VAR157;
output VAR144;
wire [6:0] VAR344;
outpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222o/sky130_fd_sc_ls__a222o.behavioral.v | 1,786 | module MODULE1 (
VAR14 ,
VAR5,
VAR18,
VAR2,
VAR10,
VAR16,
VAR9
);
output VAR14 ;
input VAR5;
input VAR18;
input VAR2;
input VAR10;
input VAR16;
input VAR9;
supply1 VAR13;
supply0 VAR4;
supply1 VAR17 ;
supply0 VAR1 ;
wire VAR7 ;
wire VAR19 ;
wire VAR8 ;
wire VAR20;
and VAR12 (VAR7 , VAR2, VAR10 );
and VAR6 (VAR19 , VAR5... | apache-2.0 |
zaqwes8811/ip-cores | ip-cores/rtl_vlog/controlers_ifaces_lib.v | 2,324 | module MODULE1(
clk, rst, VAR12,
VAR15, VAR19, VAR17 );
parameter VAR4 = 8;
parameter VAR9 = 14;
input clk, rst, VAR12;
input VAR15;
output VAR19;
output VAR17;
wire VAR7; wire VAR18; wire [VAR4-1:0] VAR3;
wire VAR6;
wire VAR2; wire VAR14;
VAR20 #(.VAR9(VAR9))
VAR5(
.clk(clk), .rst(rst), .VAR12(VAR19),
.VAR18(VAR15), .... | mit |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_auto_pc_2/synth/dma_loopback_auto_pc_2.v | 16,267 | module MODULE1 (
VAR30,
VAR102,
VAR57,
VAR68,
VAR64,
VAR66,
VAR75,
VAR13,
VAR98,
VAR41,
VAR95,
VAR108,
VAR56,
VAR89,
VAR90,
VAR21,
VAR47,
VAR18,
VAR103,
VAR32,
VAR39,
VAR54,
VAR42,
VAR22,
VAR53,
VAR79,
VAR94,
VAR48,
VAR2,
VAR1,
VAR73,
VAR74,
VAR50,
VAR35,
VAR11,
VAR46,
VAR6,
VAR82,
VAR110,
VAR3,
VAR92,
VAR20,
VAR109,
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busreceiver/sky130_fd_sc_lp__busreceiver.blackbox.v | 1,255 | module MODULE1 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR2;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_reg_file.v | 9,437 | module MODULE1(
clk,
VAR1,
VAR28,
VAR80,
VAR35,
VAR77,
rd,
VAR13
);
input wire clk;
input wire VAR1;
input wire [VAR97-1:0] VAR28;
output reg [VAR81-1:0] VAR80;
input wire [VAR97-1:0] VAR35;
output reg [VAR81-1:0] VAR77;
input wire [VAR97-1:0] rd;
input wire [VAR81-1:0] VAR13;
reg [VAR81-1:0] VAR101;
reg [VAR81-1:0] VA... | bsd-2-clause |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ps2_dual_ref_v1_00_a/hdl/verilog/opb_ps2_dual_ref.v | 10,435 | module MODULE1 (
VAR56, VAR58, VAR16, VAR53, VAR29, VAR18, VAR51, VAR10, VAR59, VAR20, VAR2, VAR7, VAR64, VAR13, VAR38, VAR41, VAR49, VAR26, VAR39, VAR42, VAR44, VAR9, VAR11, VAR50 );
input [0:3] VAR56; input VAR58; input VAR16; input [0:31] VAR53; input VAR29; input [0:31] VAR18; input VAR51; input VAR10;
output VAR59... | gpl-3.0 |
alexforencich/xfcp | lib/eth/example/KC705/fpga_gmii/rtl/fpga.v | 5,408 | module MODULE1 (
input wire VAR58,
input wire VAR21,
input wire reset,
input wire VAR14,
input wire VAR73,
input wire VAR68,
input wire VAR10,
input wire VAR19,
input wire [3:0] VAR78,
output wire [7:0] VAR94,
input wire VAR6,
input wire [7:0] VAR77,
input wire VAR64,
input wire VAR45,
output wire VAR31,
input wire VAR... | mit |
eecsninja/duinocube-core | common/spi_memory.v | 5,047 | module MODULE1(select, VAR13, VAR4, VAR16,
addr, VAR10, VAR3, rd, wr,
);
input select, VAR13, VAR4;
output VAR16;
output [VAR6-1:0] addr;
input [VAR9-1:0] VAR3;
output [VAR9-1:0] VAR10;
output rd, wr;
reg [VAR12-1:0] VAR21;
reg [VAR8-1:0] VAR19;
reg [VAR8-1:0] VAR20;
reg [VAR8-1:0] VAR14;
always @ (posedge VAR13)
if (~... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/conb/sky130_fd_sc_hvl__conb.symbol.v | 1,274 | module MODULE1 (
output VAR6,
output VAR2
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapmet1/sky130_fd_sc_ls__tapmet1.blackbox.v | 1,223 | module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
tinkercnc/spi-fpga-driver | pluto_spi_stepper_firmware/spi_main.v | 6,971 | module MODULE1(clk, VAR49, VAR18, VAR17, VAR48, VAR38, VAR27, VAR34, VAR12, dout, din, VAR25, VAR30);
parameter VAR50=10;
parameter VAR39=11;
parameter VAR46=4;
input clk;
input VAR49, VAR48, VAR18, VAR38;
output VAR17, VAR12 = 1'VAR51, VAR27;
output VAR34;
input [15:0] din;
assign VAR12 = VAR38;
assign VAR27 = 1'b1;
r... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/altera_up_av_config_auto_init_lcm.v | 7,818 | module MODULE1 (
VAR9,
VAR23
);
parameter VAR12 = 8'h00;
parameter VAR15 = 8'h01;
parameter VAR8 = 8'h3F;
parameter VAR17 = 8'h17;
parameter VAR3 = 8'h18;
parameter VAR11 = 8'h08;
parameter VAR19 = 8'h00;
parameter VAR16 = 8'h20;
parameter VAR20 = 8'h20;
parameter VAR10 = 8'h20;
parameter VAR7 = 8'h10;
parameter VAR1 =... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv.symbol.v | 1,292 | module MODULE1 (
input VAR1 ,
output VAR3
);
supply1 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/mast_new.v | 6,409 | module MODULE1 (
address,
VAR34,
VAR5);
input [11:0] address;
input VAR34;
output [11:0] VAR5;
tri1 VAR34;
wire [11:0] VAR42;
wire [11:0] VAR5 = VAR42[11:0];
VAR11 VAR6 (
.VAR37 (address),
.VAR41 (VAR34),
.VAR24 (VAR42),
.VAR51 (1'b0),
.VAR40 (1'b0),
.VAR47 (1'b1),
.VAR32 (1'b0),
.VAR17 (1'b0),
.VAR18 (1'b1),
.VAR44 (1... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_csr.v | 23,960 | module MODULE1(
VAR103, VAR119, VAR78, VAR70,
VAR20, VAR86, VAR72,
VAR73, VAR66, VAR99, VAR132,
VAR37, VAR21, VAR24, VAR53,
VAR137, VAR7, VAR8, VAR16,
VAR39, VAR100, VAR145, VAR142, VAR83, VAR105,
VAR62, VAR107, VAR28, VAR50,
VAR115, VAR64, VAR139,
VAR102, VAR15, VAR45,
VAR138, VAR146, VAR18, VAR67,
VAR98, VAR94, VAR49... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.behavioral.pp.v | 1,868 | module MODULE1 (
VAR2,
VAR12,
VAR9 ,
VAR4 ,
VAR3
);
input VAR2;
input VAR12;
output VAR9 ;
input VAR4 ;
input VAR3 ;
wire VAR9 VAR11 ;
wire VAR10 ;
wire VAR1;
not VAR7 (VAR11 , VAR4 );
and VAR6 (VAR10 , VAR11, VAR3 );
VAR8 VAR13 (VAR1, VAR10, VAR2, VAR12);
buf VAR5 (VAR9 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrbp/sky130_fd_sc_ms__sdfrbp.symbol.v | 1,538 | module MODULE1 (
input VAR4 ,
output VAR3 ,
output VAR11 ,
input VAR5,
input VAR2 ,
input VAR6 ,
input VAR7
);
supply1 VAR9;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
ptracton/wb_dsp | rtl/wb_daq_top.v | 13,974 | module MODULE1 (
VAR146, VAR142, VAR8, VAR65,
VAR57, VAR35, VAR37, VAR63,
VAR114, VAR82, VAR152, VAR64,
interrupt, VAR138, VAR118,
VAR151, VAR90, VAR70,
VAR137, VAR45, VAR150, VAR149, VAR100, VAR83,
VAR43, VAR135, VAR1, VAR34,
VAR20, VAR94, VAR78, VAR95,
VAR51, VAR19, VAR71, VAR31
) ;
parameter VAR50 = 32;
parameter VA... | mit |
efabless/openlane | designs/PPU/src/PPU.v | 32,341 | module MODULE1(input clk, input VAR4,
input VAR3,
input [2:0] VAR10, input [7:0] din, input read, input write, input VAR12, input [8:0] VAR7,
output [14:0] VAR8,
output [2:0] VAR9); reg VAR1; reg [14:0] VAR5;
reg [14:0] VAR6;
reg [2:0] VAR11;
reg VAR2; | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/mmu.v | 11,114 | module MODULE1(
input wire clk,
input wire rst,
input wire[2:0] VAR54,
input wire[31:0] VAR71,
input wire[31:0] VAR58,
input wire[31:0] VAR50,
input wire[31:0] VAR48,
input wire[31:0] VAR37,
input wire[31:0] VAR7,
input wire[31:0] VAR13,
input wire[31:0] VAR67,
input wire[31:0] VAR56,
input wire[31:0] VAR8,
input wire[... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.blackbox.v | 1,437 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR6,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR6;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/PLL_BASE.v | 4,340 | module MODULE1 (
VAR26,
VAR55,
VAR38,
VAR2,
VAR58,
VAR49,
VAR23,
VAR52,
VAR8,
VAR59,
VAR11
);
parameter VAR51 = "VAR12";
parameter integer VAR71 = 1;
parameter real VAR25 = 0.0;
parameter real VAR60 = 0.000;
parameter integer VAR43 = 1;
parameter real VAR32 = 0.5;
parameter real VAR45 = 0.0;
parameter integer VAR39 = 1... | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_SLVT_TT_210930.v | 73,208 | module MODULE1 (VAR12, VAR2, VAR5, VAR3);
output VAR12;
input VAR2, VAR5, VAR3;
reg VAR16;
wire VAR11, VAR13;
wire VAR7, VAR9, VAR6;
wire VAR14;
not (VAR7, VAR11);
not (VAR6, VAR5);
VAR10 (VAR14, VAR13, VAR7, VAR6);
VAR15 (VAR9, VAR16, VAR13, VAR7, VAR6, VAR14);
buf (VAR12, VAR9);
wire VAR8, VAR4, VAR1;
and (VAR8, VAR2... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr_6.v | 2,112 | module MODULE1 (
VAR1 ,
VAR2,
VAR3 ,
VAR4 ,
VAR7
);
input VAR1 ;
input VAR2;
input VAR3 ;
input VAR4 ;
input VAR7 ;
VAR5 VAR6 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 ();
supply1 VAR1 ;
supply1 VAR2;
supply0 VAR3 ;
supply1 VAR4 ;
supply0 VAR7 ;
VAR5 VAR6 ();
endmodul... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_acl_iface_acl_kernel_clk_pll_rom.v | 3,407 | module MODULE1 (
address,
VAR20,
VAR35,
clk,
VAR34,
VAR16,
reset,
VAR23,
write,
VAR7,
VAR5
)
;
parameter VAR14 = "VAR12.VAR33";
output [ 31: 0] VAR5;
input [ 7: 0] address;
input [ 3: 0] VAR20;
input VAR35;
input clk;
input VAR34;
input VAR16;
input reset;
input VAR23;
input write;
input [ 31: 0] VAR7;
wire VAR9;
reg [... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/pcie_blk_ll_oqbqfifo.v | 22,082 | module MODULE1
(
input wire clk,
input wire VAR90,
output reg VAR89 = 0,
output reg [63:0] VAR52 = 0,
output reg [7:0] VAR22 = 0,
output reg VAR28 = 0,
output reg VAR95 = 0,
output reg VAR70 = 0,
output reg [6:0] VAR88 = 0,
output reg VAR58 = 1,
output reg VAR50 = 1,
input VAR128,
input VAR7,
input VAR9,
input [63:0] V... | lgpl-3.0 |
jcrono/sd-host | src/buffer/sram.v | 2,961 | module MODULE1 (
VAR9, VAR11, VAR10, VAR4, VAR8, VAR2, VAR6, VAR5 );
input [VAR7:0] VAR4;
input VAR11,
VAR2,
VAR9,
VAR8;
input [VAR3:0] VAR10,
VAR6;
output [VAR7:0] VAR5;
reg [VAR7:0] VAR1 [0:128];
reg [VAR7:0] VAR5;
wire [VAR7:0] VAR4;
always @(posedge VAR11) begin
if (VAR9) VAR1[VAR10] <= VAR4;
end
always @(posedge V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.v | 2,241 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR1 ,
VAR8 ,
VAR10,
VAR9,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR10;
input VAR9;
input VAR3 ;
input VAR2 ;
VAR6 VAR7 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcon/sky130_fd_sc_ms__fahcon.behavioral.pp.v | 2,730 | module MODULE1 (
VAR12,
VAR23 ,
VAR18 ,
VAR14 ,
VAR17 ,
VAR4 ,
VAR7 ,
VAR5 ,
VAR9
);
output VAR12;
output VAR23 ;
input VAR18 ;
input VAR14 ;
input VAR17 ;
input VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR9 ;
wire VAR15 ;
wire VAR1 ;
wire VAR19 ;
wire VAR13 ;
wire VAR21 ;
wire VAR6 ;
wire VAR11;
xor VAR8 (VAR15 , VAR18,... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/8b10b/decode_8b10b.v | 5,788 | module MODULE1 (VAR9, VAR40, VAR59, VAR46, VAR29, VAR34) ;
input [9:0] VAR9 ;
input VAR40 ;
output [8:0] VAR59 ;
output VAR46 ;
output VAR29 ;
output VAR34 ;
wire VAR49 = VAR9[0] ;
wire VAR47 = VAR9[1] ;
wire VAR5 = VAR9[2] ;
wire VAR23 = VAR9[3] ;
wire VAR2 = VAR9[4] ;
wire VAR55 = VAR9[5] ;
wire VAR7 = VAR9[6] ;
wire... | gpl-2.0 |
hoglet67/CoPro6502 | src/amber23/a23_fetch.v | 8,303 | module MODULE1
(
input VAR8,
input [31:0] VAR7,
input VAR22,
input [31:0] VAR43, input [31:0] VAR31,
input VAR18,
output [31:0] VAR16,
input VAR1,
input VAR17, input [3:0] VAR36,
input VAR35, input VAR26, input VAR40, input [31:0] VAR5, input VAR27,
output VAR33,
output [31:0] VAR4,
output [3:0] VAR19,
output VAR13,
in... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o_4.v | 2,463 | module MODULE2 (
VAR9 ,
VAR6,
VAR7,
VAR8 ,
VAR5 ,
VAR3,
VAR2,
VAR1 ,
VAR10
);
output VAR9 ;
input VAR6;
input VAR7;
input VAR8 ;
input VAR5 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR10 ;
VAR11 VAR4 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR3 ,
input VAR9 ,
input VAR6 ,
input VAR4 ,
output VAR1 ,
input VAR7 ,
input VAR2,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
jeremysalwen/combinatorial_aes | rtl/round.v | 2,514 | module MODULE1 (VAR33, VAR12, VAR22);
input [127:0] VAR33, VAR12;
output reg [127:0] VAR22;
wire [31:0] VAR27, VAR28, VAR25, VAR21,
VAR8, VAR31, VAR24, VAR3,
VAR36, VAR1, VAR35, VAR15,
VAR5, VAR13, VAR2, VAR9,
VAR6, VAR20, VAR10, VAR7,
VAR34, VAR17, VAR16, VAR19,
VAR32, VAR26, VAR18, VAR11;
assign {VAR32, VAR26, VAR18,... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/phy_read.v | 10,010 | module MODULE1 #
(
parameter VAR22 = 100, parameter VAR27 = 2, parameter VAR44 = 3333, parameter VAR6 = 300.0, parameter VAR28 = 8, parameter VAR9 = 64, parameter VAR3 = 8, parameter VAR33 = "VAR21", parameter VAR1 = 4, parameter VAR32 = 4, parameter VAR15 = 0, parameter VAR19 = 0, parameter VAR39 = 32'h03020100, param... | mit |
cpulabs/mist1032isa | src/dps/utim64/dps_utim64_module.v | 7,990 | module MODULE1(
input wire VAR50, input wire VAR35,
input wire VAR91,
input wire VAR1,
output wire VAR74,
input wire VAR65,
input wire [3:0] VAR10,
input wire [31:0] VAR4,
output wire VAR89,
output wire [31:0] VAR78,
output wire [3:0] VAR96
);
wire VAR45;
wire VAR12;
wire VAR23;
wire [31:0] VAR16;
wire [3:0] VAR3;
wire... | bsd-2-clause |
sabertazimi/hust-lab | architecture/design/fpga/src/ID_EX.v | 7,052 | module MODULE1
(
input clk,
input rst,
input en,
input [VAR37-1:0] VAR43,
input [VAR37-1:0] VAR33,
input VAR64,
input VAR51,
input VAR65,
input VAR63,
input VAR22,
input VAR11,
input VAR56,
input VAR15,
input [3:0] VAR17,
input VAR36,
input VAR46,
input VAR5,
input VAR19,
input [4:0] VAR25,
input [4:0] VAR66,
input [4:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a.behavioral.pp.v | 2,156 | module MODULE1 (
VAR16 ,
VAR2 ,
VAR3 ,
VAR6 ,
VAR14 ,
VAR9,
VAR13,
VAR19 ,
VAR12
);
output VAR16 ;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR14 ;
input VAR9;
input VAR13;
input VAR19 ;
input VAR12 ;
wire VAR4 ;
wire VAR15 ;
wire VAR7 ;
wire VAR18;
or VAR10 (VAR4 , VAR3, VAR2 );
or VAR5 (VAR15 , VAR14, VAR6 );
and... | apache-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/fpga/reg_256x32b_3r_1w_fpga.v | 2,014 | module MODULE1
(
VAR27, VAR21, VAR10,
clk, VAR1, VAR8, VAR4, VAR15, VAR19, VAR9
);
input clk;
output [31:0] VAR27;
output [31:0] VAR21;
output [31:0] VAR10;
input [9:0] VAR1;
input [9:0] VAR8;
input [9:0] VAR4;
input [9:0] VAR15;
input VAR19;
input [31:0] VAR9;
wire [31:0] VAR22;
wire [31:0] VAR14;
wire [31:0] VAR11;
r... | bsd-3-clause |
scalable-networks/ext | uhd/fpga/usrp2/timing/time_64bit.v | 4,638 | module MODULE1
parameter VAR34 = 0)
(input clk, input rst,
input VAR9, input [7:0] VAR27, input [31:0] VAR39,
input VAR6,
output reg [63:0] VAR30,
output reg [63:0] VAR12,
output VAR1,
input VAR3, output VAR32,
output reg VAR14,
output [31:0] VAR22
);
localparam VAR10 = 0;
localparam VAR4 = 1;
localparam VAR11 = 2;
loc... | gpl-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_measure_pulse_v1_0/axis_measure_pulse.v | 11,326 | module MODULE1 #
(
parameter integer VAR26 = 16,
parameter integer VAR41 = 16,
parameter integer VAR45 = 16,
parameter integer VAR19 = 16,
parameter integer VAR46 = 16
)
(
input wire VAR1,
input wire VAR39,
input wire [VAR45*4+95:0] VAR7,
output wire VAR52,
output wire [2:0] VAR22,
output wire [31:0] VAR32,
output wire... | mit |
alexforencich/verilog-dsp | rtl/phase_accumulator.v | 2,683 | module MODULE1 #
(
parameter VAR10 = 32,
parameter VAR4 = 0,
parameter VAR14 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR10-1:0] VAR3,
input wire VAR12,
output wire VAR13,
input wire [VAR10-1:0] VAR2,
input wire VAR6,
output wire VAR11,
output wire [VAR10-1:0] VAR1,
output wire VAR5,
input wire VAR7
);
reg [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp_2.v | 2,378 | module MODULE2 (
VAR9 ,
VAR6,
VAR7 ,
VAR8 ,
VAR5 ,
VAR1 ,
VAR2 ,
VAR4
);
output VAR9 ;
input VAR6;
input VAR7 ;
input VAR8 ;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR4 ;
VAR3 VAR10 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill.blackbox.v | 1,166 | module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3b/sky130_fd_sc_ms__or3b.symbol.v | 1,301 | module MODULE1 (
input VAR7 ,
input VAR8 ,
input VAR3,
output VAR6
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
HarmonInstruments/hififo | hdl/gt_drp.v | 1,890 | module MODULE1
(
input VAR1,
input VAR3,
input write,
input [63:0] din,
output reg [16:0] dout = 0,
output reg [8:0] VAR12,
output VAR11,
output reg [15:0] VAR10,
input [15:0] VAR2,
input VAR4,
output reg VAR9
);
reg [3:0] state = 0;
reg VAR5 = 0;
wire VAR7;
sync VAR13 (.VAR1(VAR1), .in(VAR4), .out(VAR7));
VAR8 VAR6 (.... | gpl-3.0 |
cornell-zhang/datuner | designs/quartus/processor/lab5dram.v | 4,129 | module MODULE1(VAR9, VAR16, VAR20, VAR13, VAR1, VAR7, VAR4, VAR2, VAR8, VAR18, VAR19, VAR15, VAR12);
input VAR9;
input VAR16;
input [7:0] VAR20;
input [7:0] VAR13;
input VAR1;
output [7:0] VAR7;
input [7:0] VAR4;
input [7:0] VAR2;
input [7:0] VAR8;
output [7:0] VAR18;
output [7:0] VAR19;
output [7:0] VAR15;
output [7:0... | bsd-3-clause |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/c2c/src/c2cTop.v | 9,184 | module MODULE1 (
input [31:00] VAR48,
input [31:00] VAR62,
output [31:00] VAR88,
output [31:00] VAR56,
input VAR13,
output VAR127,
input VAR69,
output VAR8,
input VAR124,
output VAR60,
input VAR16,
output VAR81,
input VAR110,
input VAR113,
input VAR49,
input VAR7,
input [63:00] VAR99,
output [63:00] VAR59,
input [63:00... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/ecc/ecc_gen.v | 7,899 | module MODULE1
parameter VAR10 = 72,
parameter VAR22 = 8,
parameter VAR9 = 64
)
(
VAR21
);
function integer VAR6 (input integer VAR13);
integer VAR19;
if (VAR13 == 1) VAR6 = 1;
else begin
VAR6 = 1;
for (VAR19=2; VAR19<=VAR13; VAR19=VAR19+1)
VAR6 = VAR6 * VAR19;
end
endfunction
function integer VAR4 (input integer VAR12... | lgpl-3.0 |
8l/connectal | verilog/PositiveReset.v | 2,734 | module MODULE1 (
VAR4,
VAR3,
VAR1
);
parameter VAR8 = 1 ;
input VAR3 ;
input VAR4 ;
output VAR1 ;
reg [VAR8:0] VAR6 ;
wire [VAR8+1:0] VAR2 = {VAR6, 1'b0} ;
assign VAR1 = VAR6[VAR8] ;
always @( posedge VAR3 ) begin
if (VAR4 == VAR7)
begin
VAR6 <= VAR5 -1 ;
end
else
begin
VAR6 <= VAR5 VAR2[VAR8:0];
end
end
begin
VAR6 = 0... | mit |
DougFirErickson/parallella-hw | fpga/old/hdl/elink-gold/ewrapper_link_rxi.v | 22,648 | module MODULE1 (
VAR89, VAR31, VAR58, VAR38,
VAR105, VAR46, VAR28,
VAR8,
reset, VAR47, VAR125, VAR88, VAR83, VAR67
);
input reset;
input [63:0] VAR47; input VAR125; input [7:0] VAR88;
input VAR83;
input VAR67;
output VAR89;
output VAR31;
output VAR58;
output [1:0] VAR38;
output [3:0] VAR105;
output [31:0] VAR46;
output... | gpl-3.0 |
vvk/sysrek | rgb2hsv/src/rx/decode.v | 7,603 | module MODULE1 (
input wire reset, input wire VAR44, input wire VAR41, input wire VAR23, input wire VAR4, input wire VAR22, input wire VAR3, input wire VAR2, input wire VAR14, input wire VAR24, input wire VAR12,
output wire VAR6, output wire VAR1, output wire VAR49, output reg VAR20,
output reg VAR33,
output reg VAR8,
... | gpl-2.0 |
zYeoman/32BIT-MIPS-CPU | Single/CPU.v | 4,487 | module MODULE1 (
input clk, VAR5,
input [7:0] VAR21,
input VAR2,
output VAR60,
output [7:0] VAR56,
output [6:0] VAR49,
output [6:0] VAR45,
output [6:0] VAR61,
output [6:0] VAR66
);
wire rst;
reg [31:0] VAR39;
wire [31:0] VAR1,
VAR19,
VAR42;
wire VAR38; wire [25:0] VAR53; wire [15:0] VAR27;
wire [4:0] VAR33,
VAR57,
VAR6... | gpl-2.0 |
mammenx/pegasus | wxp/dgn/rtl/common/pkt_ff_async/pkt_ff_async_mem.v | 9,544 | module MODULE1 #(VAR9=32, VAR48=128) (
VAR49,
VAR60,
VAR54,
VAR55,
VAR4,
VAR61,
VAR7);
localparam VAR6 = VAR28(VAR48);
input [VAR9-1:0] VAR49;
input [VAR6-1:0] VAR60;
input VAR54;
input [VAR6-1:0] VAR55;
input VAR4;
input VAR61;
output [VAR9-1:0] VAR7;
tri1 VAR4;
tri0 VAR61;
wire [VAR9-1:0] VAR10;
wire [VAR9-1:0] VAR7 ... | gpl-3.0 |
trun/fpgaboy | src/io/input/joypad_snes_adapter.v | 2,584 | module MODULE1(
input wire VAR11,
input wire reset,
input wire [1:0] VAR7,
output wire [3:0] VAR8,
output reg [15:0] VAR6,
input wire VAR4,
output wire VAR5,
output wire VAR10
);
parameter VAR1 = 0;
parameter VAR2 = 1;
parameter VAR3 = 2;
reg [1:0] state;
reg [3:0] VAR9;
always @(posedge VAR11) begin
if (reset)
state <... | mit |
chimeh/stopwatch_verilog | src/state_matchin.v | 2,408 | module MODULE1( input VAR4, input VAR11, input VAR3, output reg VAR5, output reg VAR10, output reg VAR8);
localparam [1:0] reset =2'b00, VAR6 =2'b01, VAR1=2'b10, VAR2=2'b11;
reg [1:0] VAR9; reg [1:0] VAR7 = reset;
always @ ( VAR11 or VAR3 or VAR9 ) begin case(VAR9)
reset:
case({VAR11,VAR3})
2'b10:VAR7 <= VAR1;
default:... | unlicense |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/mmio_if/synthesis/submodules/mmio_if_pio_1.v | 1,830 | module MODULE1 (
address,
clk,
VAR5,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR5;
input VAR1;
wire VAR4;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR6;
reg [ 31: 0] VAR3;
assign VAR4 = 1;
assign VAR6 = {8 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR1)
begin
if (VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv_2.v | 2,036 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR6,
VAR2,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR6;
input VAR2;
input VAR5 ;
input VAR4 ;
VAR1 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR6;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b.blackbox.v | 1,276 | module MODULE1 (
VAR6 ,
VAR7,
VAR2
);
output VAR6 ;
input VAR7;
input VAR2 ;
supply1 VAR3;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_125.v | 1,435 | module MODULE2 (
VAR12,
VAR4
);
input [31:0] VAR12;
output [31:0]
VAR4;
wire [31:0]
VAR10,
VAR3,
VAR5,
VAR9,
VAR2,
VAR6,
VAR11;
assign VAR10 = VAR12;
assign VAR9 = VAR10 << 1;
assign VAR3 = VAR10 << 8;
assign VAR5 = VAR10 + VAR3;
assign VAR2 = VAR5 + VAR9;
assign VAR11 = VAR6 - VAR2;
assign VAR6 = VAR5 << 4;
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221a/sky130_fd_sc_hd__o221a.symbol.v | 1,394 | module MODULE1 (
input VAR3,
input VAR10,
input VAR1,
input VAR5,
input VAR9,
output VAR2
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2.functional.pp.v | 1,832 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR3,
VAR1,
VAR9 ,
VAR6
);
output VAR5 ;
input VAR4 ;
input VAR3;
input VAR1;
input VAR9 ;
input VAR6 ;
wire VAR10 ;
wire VAR7;
buf VAR2 (VAR10 , VAR4 );
VAR11 VAR12 (VAR7, VAR10, VAR3, VAR1);
buf VAR8 (VAR5 , VAR7 );
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/ST_to_MM_Adapter.v | 5,149 | module MODULE1 (
clk,
reset,
enable,
address,
VAR13,
VAR7,
VAR20,
VAR4,
VAR9,
VAR16,
VAR5
);
parameter VAR22 = 32;
parameter VAR6 = 2;
parameter VAR23 = 32;
parameter VAR19 = 0; localparam VAR12 = VAR6 + 1;
input clk;
input reset;
input enable; input [VAR23-1:0] address;
input VAR13; input VAR7;
input VAR20;
output wir... | gpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/ex_reg.v | 4,731 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR33] VAR35, input wire VAR18,
input wire VAR12, input wire VAR11, input wire VAR9,
input wire [VAR41] VAR30, input wire VAR31, input wire VAR40, input wire [VAR10] VAR17, input wire [VAR33] VAR13, input wire [VAR23] VAR26, input wire [VAR39] VAR38, input ... | apache-2.0 |
jairov4/accel-oil | solution_spartan3/syn/verilog/sample_iterator_get_offset.v | 41,689 | module MODULE1 (
VAR115,
VAR86,
VAR35,
VAR46,
VAR53,
VAR104,
VAR105,
VAR39,
VAR26,
VAR11,
VAR51,
VAR68,
VAR114,
VAR25,
VAR100,
VAR116,
VAR9,
VAR2,
VAR31,
VAR4,
VAR40,
VAR72,
VAR45,
VAR23,
VAR123,
VAR78,
VAR43,
VAR28,
VAR70,
VAR83,
VAR52,
VAR3,
VAR41,
VAR57,
VAR93,
VAR76,
VAR122,
VAR50,
VAR81
);
input VAR115;
input VAR8... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41o/sky130_fd_sc_lp__a41o.functional.pp.v | 2,058 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR12 ,
VAR9 ,
VAR17 ,
VAR14 ,
VAR10,
VAR18,
VAR15 ,
VAR6
);
output VAR1 ;
input VAR8 ;
input VAR12 ;
input VAR9 ;
input VAR17 ;
input VAR14 ;
input VAR10;
input VAR18;
input VAR15 ;
input VAR6 ;
wire VAR4 ;
wire VAR2 ;
wire VAR16;
and VAR5 (VAR4 , VAR8, VAR12, VAR9, VAR17 );
or VAR3 (VAR... | apache-2.0 |
Kumikomi/openreroc_gyrosensor | hardware/src/SPI_IF.v | 4,590 | module MODULE1(
input clk,
input rst,
input [6:0] VAR19, input [7:0] VAR5, input VAR6, input VAR18, output VAR4, output VAR7, output VAR13, output VAR1, input VAR10, output [7:0] VAR21 );
reg [7:0] VAR12; reg [7:0] VAR2;
reg [11:0] counter; reg VAR22; reg VAR15; reg VAR9; reg VAR20; reg VAR16; reg [4:0] VAR8; reg [4:0]... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/axi_ipif/pselect_f.v | 6,789 | module MODULE1 (VAR12, VAR3, VAR4);
parameter VAR11 = 9;
parameter VAR7 = 32;
parameter [0:VAR7 - 1] VAR5 = 'VAR10;
parameter VAR6 = "VAR2";
input[0:VAR7-1] VAR12;
input VAR3;
output VAR4;
wire VAR4;
parameter [0:VAR11-1]VAR8 = VAR5[0:VAR11-1];
generate
if (VAR11 > 0) begin : VAR9
assign VAR4 = (VAR12[0:VAR11 - 1] == V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai.pp.symbol.v | 1,398 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR4 ,
input VAR1 ,
input VAR10 ,
output VAR3 ,
input VAR5 ,
input VAR8,
input VAR2,
input VAR9
);
endmodule | apache-2.0 |
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