repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/BloquePruebaManual/conmutacion.v | 1,079 | module MODULE1
(
input [3:0] VAR1,
input [3:0] VAR10,
input [3:0] VAR3,
input VAR2,
input VAR4,
input VAR8,
input VAR9,
output reg [1:0] VAR6,
output reg [3:0] VAR11
);
reg VAR5;
reg [1:0] VAR7;
begin
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin | gpl-3.0 |
migajv/mips_pipeline | verilog/iq.v | 4,579 | module MODULE1(
input clk,
input rst,
input VAR31,
input [31:0] VAR15,
input VAR12,
input [31:0] VAR5,
input [31:0] VAR4,
input [31:0] VAR30,
input VAR27,
input [31:0] VAR21,
input VAR35,
input VAR18,
input VAR29,
input VAR26,
output logic VAR6,
output logic VAR28,
output logic VAR36,
output logic [31:0] VAR11,
output ... | gpl-3.0 |
alexforencich/xfcp | lib/eth/rtl/ptp_ts_extract.v | 1,985 | module MODULE1 #
(
parameter VAR8 = 96,
parameter VAR5 = 1,
parameter VAR9 = VAR8+VAR5
)
(
input wire clk,
input wire rst,
input wire VAR3,
input wire VAR7,
input wire [VAR9-1:0] VAR1,
output wire [VAR8-1:0] VAR2,
output wire VAR6
);
reg VAR4 = 1'b0;
assign VAR2 = VAR1 >> VAR5;
assign VAR6 = VAR3 && !VAR4;
always @(pos... | mit |
tec499-20142/t02-warmup | rtl/ula_k.v | 1,122 | module MODULE1(
input [7:0] VAR3,
input [7:0] VAR2,
input [7:0] VAR1,
output reg [7:0] VAR4,
output reg VAR5
);
always @(VAR3 or VAR2)
begin
case(VAR1)
8'b00000000: VAR4 = VAR3 + VAR2;
8'b00000001: VAR4 = VAR3 - VAR2;
8'b00000010: VAR4 = VAR3 & VAR2;
8'b00000011: VAR4 = VAR3 | VAR2;
8'b00000100: VAR4 = VAR3 * VAR2;
8'b... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3_lp.v | 2,207 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR9,
VAR2,
VAR8 ,
VAR1
);
output VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR9;
input VAR2;
input VAR8 ;
input VAR1 ;
VAR10 VAR4 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp.behavioral.v | 3,020 | module MODULE1 (
VAR9 ,
VAR25 ,
VAR12 ,
VAR8 ,
VAR5 ,
VAR15 ,
VAR23
);
output VAR9 ;
output VAR25 ;
input VAR12 ;
input VAR8 ;
input VAR5 ;
input VAR15 ;
input VAR23;
supply1 VAR28;
supply0 VAR29;
supply1 VAR11 ;
supply0 VAR21 ;
wire VAR30 ;
wire VAR2 ;
wire VAR20 ;
reg VAR31 ;
wire VAR16 ;
wire VAR33 ;
wire VAR10 ;
wi... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3/sky130_fd_sc_ms__or3.symbol.v | 1,268 | module MODULE1 (
input VAR6,
input VAR7,
input VAR1,
output VAR5
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
r2apu/Labo_Digitales | MIniAlu_g2/actual/MiniAlu.v | 9,626 | module MODULE1
(
input wire VAR3,
input wire VAR13,
output wire [7:0] VAR64,
output wire VAR21,
output wire VAR12,
output wire [2:0] VAR51
);
wire [15:0] VAR57,VAR77;
reg VAR60,VAR8,VAR46;
wire [27:0] VAR94;
wire [7:0] VAR68;
reg VAR59;
wire [3:0] VAR43, VAR96;
reg signed [15:0] VAR32;
wire [15:0] VAR74;
wire [7:0] VAR... | gpl-3.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/imx_cbu_burst.v | 9,347 | module MODULE1(
clk, rst, VAR21,
VAR40, VAR26, VAR1, VAR28, VAR51, VAR46,
VAR7, VAR29, VAR16, VAR20, VAR25, VAR41,
VAR17, VAR24,
VAR23, VAR4, VAR47, VAR10, VAR42,
VAR45, VAR30, VAR35
);
parameter VAR5 = 32;
parameter VAR52 = 5;
input clk; input rst; input [1:0] VAR21;
input [VAR5-1:0] VAR23; input [VAR52-1:0] VAR4; inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b.symbol.v | 1,341 | module MODULE1 (
input VAR6 ,
input VAR7 ,
input VAR5,
output VAR8
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Elphel/x393_sata | device/sata_device.v | 59,979 | module MODULE1(
input wire rst,
input wire VAR36,
input wire VAR22,
output wire VAR35,
output wire VAR2,
input wire VAR7,
input wire VAR45
);
reg [639:0] VAR32 = 'VAR9; integer VAR37;
wire VAR10;
wire [31:0] VAR42;
wire [3:0] VAR29;
wire [3:0] VAR28;
wire clk;
wire VAR15;
reg [31:0] VAR6 = 32'hB5B5957C; reg [3:0] VAR30... | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | contador_AD_MES_2dig.v | 2,218 | module MODULE1
(
input wire clk,
input wire reset,
input wire [3:0] VAR10,
input wire VAR9,
input wire VAR8,
output wire [7:0] VAR7
);
localparam VAR3 = 4; reg [VAR3-1:0] VAR5, VAR2;
wire [VAR3-1:0] VAR1;
reg [3:0] VAR4, VAR6;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR5 <= 4'b0;
end
else
begin
VAR5 <... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a_1.v | 2,221 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR3 ,
VAR7 ,
VAR8 ,
VAR4,
VAR9
);
output VAR1 ;
input VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR4;
input VAR9;
VAR5 VAR2 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR1 ,
VAR6,
VAR3,
VAR7,
VAR8
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.pp.blackbox.v | 1,314 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR8 ,
VAR2 ,
VAR6,
VAR5,
VAR1 ,
VAR7
);
output VAR4 ;
output VAR3 ;
input VAR8 ;
input VAR2 ;
input VAR6;
input VAR5;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/clk_182/clk_182_stub.v | 1,159 | module MODULE1(VAR3, VAR1, VAR2)
;
input VAR3;
output VAR1;
output VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.v | 2,242 | module MODULE1 (
VAR6 ,
VAR8,
VAR3 ,
VAR5 ,
VAR7 ,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR8;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR2 ;
VAR9 VAR4 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR6 ,
VAR8,
VAR3
);
output VAR... | apache-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_BeMicroCV/hub_mem.v | 2,955 | module MODULE1
(
input VAR4,
input VAR20,
input VAR16,
input [3:0] VAR13,
input [13:0] VAR15,
input [31:0] VAR17,
output [31:0] VAR7
);
reg [7:0] VAR6 [8191:0];
reg [7:0] VAR8 [8191:0];
reg [7:0] VAR18 [8191:0];
reg [7:0] VAR9 [8191:0];
reg [7:0] VAR11;
reg [7:0] VAR3;
reg [7:0] VAR2;
reg [7:0] VAR12;
always @(posedge ... | gpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v | 12,678 | module MODULE1(
VAR43, VAR59, VAR22,
clk, rst, VAR39, VAR72, VAR36, addr, VAR65, VAR30
);
parameter VAR38 = 11;
parameter VAR17 = 32;
input VAR43;
input [VAR49 - 1:0] VAR22;
output VAR59;
input clk; input rst; input VAR39; input VAR72; input VAR36; input [VAR38-1:0] addr; input [VAR17-1:0] VAR65; output [VAR17-1:0] VAR... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/jtag_cores.v | 4,026 | module MODULE1 (VAR19, VAR17, VAR27, VAR16, VAR9, VAR31, VAR13, VAR8) ;
input VAR19 ;
output VAR17 ;
output VAR27 ;
output VAR16 ;
output VAR9 ;
output VAR31 ;
output VAR13 ;
output VAR8 ;
endmodule
module MODULE2 (
VAR15,
VAR2,
VAR20,
VAR6,
VAR10,
VAR17,
VAR31
);
input [7:0] VAR15;
input [2:0] VAR2;
output VAR20;
wire... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4.functional.pp.v | 1,870 | module MODULE1 (
VAR14 ,
VAR13 ,
VAR15 ,
VAR12 ,
VAR3 ,
VAR7,
VAR11,
VAR1 ,
VAR2
);
output VAR14 ;
input VAR13 ;
input VAR15 ;
input VAR12 ;
input VAR3 ;
input VAR7;
input VAR11;
input VAR1 ;
input VAR2 ;
wire VAR4 ;
wire VAR10;
nor VAR9 (VAR4 , VAR13, VAR15, VAR12, VAR3 );
VAR8 VAR5 (VAR10, VAR4, VAR7, VAR11);
buf VAR... | apache-2.0 |
ptracton/pmodacl2 | soc/xilinx/SRL16E.v | 3,726 | module MODULE1 #(
parameter VAR27 = "VAR12",
parameter [15:0] VAR6 = 16'h0000,
parameter [0:0] VAR13 = 1'b0
)(
output VAR15,
input VAR20,
input VAR16,
input VAR22,
input VAR7,
input VAR24,
input VAR23,
input VAR10
);
wire VAR25;
wire [3:0] VAR1;
wire VAR11;
wire VAR8;
wire VAR9;
wire VAR3;
wire VAR2;
wire VAR18;
assign... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_nsr/sky130_fd_sc_hdll__udp_dff_nsr.symbol.v | 1,416 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR5,
input VAR1 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufkapwr/sky130_fd_sc_lp__bufkapwr.pp.symbol.v | 1,309 | module MODULE1 (
input VAR4 ,
output VAR7 ,
input VAR2,
input VAR3 ,
input VAR6 ,
input VAR1 ,
input VAR5
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.functional.pp.v | 1,469 | module MODULE1( VAR4, VAR2, VAR8, VAR1, VAR12, VAR7, VAR11 );
input VAR8, VAR4, VAR1, VAR12;
inout VAR7, VAR11;
output VAR2;
wire VAR18;
not VAR9( VAR18, VAR8 );
wire VAR17;
not VAR3( VAR17, VAR4 );
wire VAR5;
and VAR13( VAR5, VAR18, VAR17 );
wire VAR16;
not VAR10( VAR16, VAR1 );
wire VAR6;
not VAR14( VAR6, VAR12 );
or... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o.symbol.v | 1,367 | module MODULE1 (
input VAR2,
input VAR1,
input VAR4,
input VAR9,
output VAR5
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_dpram.v | 5,497 | module MODULE1
(
VAR4, VAR18, VAR17, VAR3,
VAR16, VAR9, VAR2, VAR13, VAR12
);
parameter VAR11 = 5;
parameter VAR6 = 32;
input VAR4; input VAR18; input [VAR11-1:0] VAR17; output [VAR6-1:0] VAR3; input VAR16; input VAR9; input VAR2; input [VAR11-1:0] VAR13; input [VAR6-1:0] VAR12;
reg [VAR6-1:0] VAR10 [(1<<VAR11)-1:0] ; ... | mit |
gbraad/minimig-de1 | rtl/minimig/Userio.v | 46,835 | module MODULE2
(
input clk, input reset, input VAR154,
input VAR81,
input VAR14,
input VAR123, input VAR58, input [8:1] VAR17, input [15:0] VAR4, output reg [15:0] VAR78, inout VAR15, inout VAR48, output VAR115, output VAR181, input [5:0] VAR188, input [5:0] VAR129, input VAR24, input [2:0] VAR130,
input VAR69,
input V... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/ddr2/ddr2_mem_if_top.v | 16,055 | module MODULE1 #
(
parameter VAR84 = 2,
parameter VAR27 = 1,
parameter VAR90 = 1,
parameter VAR122 = 10,
parameter VAR53 = 0,
parameter VAR96 = 1,
parameter VAR33 = 1,
parameter VAR73 = 1,
parameter VAR127 = 9,
parameter VAR24 = 72,
parameter VAR87 = 7,
parameter VAR66 = 8,
parameter VAR17 = 4,
parameter VAR74 = 9,
par... | mit |
iceman1001/proxmark3 | fpga/hi_read_tx.v | 1,904 | module MODULE1(
VAR12, VAR4, VAR7,
VAR16, VAR5, VAR15, VAR20, VAR9, VAR6,
VAR2, VAR19,
VAR10, VAR14, VAR17, VAR21,
VAR8, VAR18,
VAR13,
VAR1
);
input VAR12, VAR4, VAR7;
output VAR16, VAR5, VAR15, VAR20, VAR9, VAR6;
input [7:0] VAR2;
output VAR19;
input VAR17;
output VAR10, VAR14, VAR21;
input VAR8, VAR18;
output VAR13;
... | gpl-2.0 |
Jbag/edge_detect | design/edge_detect.v | 2,504 | module MODULE1(
input VAR8, input VAR1, input VAR10, output VAR3, output VAR11, output VAR4 );
reg VAR6=1'b0;
reg [21:0] VAR5;
always @(posedge VAR8 or negedge VAR1) if(!VAR1)
VAR5 <= 22'b0;
else
if(VAR5 == 22'd4194303)
VAR5 <= 22'b0;
else
VAR5 <= VAR5 +1'b1;
always @(posedge VAR8 or negedge VAR1)
if(!VAR1)
VAR6 <= 1'b... | gpl-3.0 |
Jside/pdp1 | pdp1_iot.v | 2,286 | module MODULE1(VAR18, VAR4,
VAR8, VAR6, VAR12, VAR13,
VAR19, VAR16, VAR17, VAR20, VAR11, VAR7);
input VAR18;
input VAR4;
input [0:17] VAR8;
output VAR6;
input [0:17] VAR12;
output [0:17] VAR13;
output reg VAR19;
output [0:10] VAR16;
output VAR17;
input VAR20;
output [0:17] VAR11;
input [0:17] VAR7;
wire [0:4] VAR15;
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4/sky130_fd_sc_hdll__nand4.behavioral.pp.v | 1,864 | module MODULE1 (
VAR12 ,
VAR13 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR4,
VAR8,
VAR15 ,
VAR9
);
output VAR12 ;
input VAR13 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR4;
input VAR8;
input VAR15 ;
input VAR9 ;
wire VAR5 ;
wire VAR2;
nand VAR11 (VAR5 , VAR3, VAR6, VAR7, VAR13 );
VAR14 VAR1 (VAR2, VAR5, VAR4, VAR8);
buf VAR10 (VA... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_rgmii_in4.v | 4,986 | module MODULE1 (
VAR14,
VAR1,
VAR6,
VAR12,
VAR3);
input VAR14;
input [3:0] VAR1;
input VAR6;
output [3:0] VAR12;
output [3:0] VAR3;
wire [3:0] VAR8;
wire [3:0] VAR10;
wire [3:0] VAR12 = VAR8[3:0];
wire [3:0] VAR3 = VAR10[3:0];
VAR4 VAR16 (
.VAR1 (VAR1),
.VAR6 (VAR6),
.VAR14 (VAR14),
.VAR12 (VAR8),
.VAR3 (VAR10),
.VAR15... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpu/integracion_fisica/front_end/source/KOA_2c.v | 5,601 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR1,
input wire [VAR8-1:0] VAR21,
input wire [VAR8-1:0] VAR27,
output wire [2*VAR8-1:0] VAR15
);
wire [1:0] VAR14;
wire [3:0] VAR13;
assign VAR14 = 2'b00;
assign VAR13 = 4'b0000;
wire [VAR8/2-1:0] VAR19;
wire [VAR8/2:0] VAR23;
wire [VAR8/2-3:0] VAR3;
wire [VA... | gpl-3.0 |
bluespec/Flute | builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkBranch_Predictor.v | 25,694 | module MODULE1(VAR38,
VAR59,
VAR60,
VAR41,
VAR2,
VAR19,
VAR27,
VAR62,
VAR79,
VAR14,
VAR48,
VAR106,
VAR73,
VAR10,
VAR116,
VAR85);
input VAR38;
input VAR59;
input VAR60;
output VAR41;
input [31 : 0] VAR2;
input VAR19;
output VAR27;
input VAR62;
input [31 : 0] VAR79;
output [31 : 0] VAR14;
input [31 : 0] VAR48;
input VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/diode/sky130_fd_sc_hd__diode.pp.symbol.v | 1,213 | module MODULE1 (
input VAR4,
input VAR5 ,
input VAR2 ,
input VAR1 ,
input VAR3
);
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/old/hdl/parallella-I/fpgacfg.v | 21,846 | module MODULE1 (
VAR45, VAR51, VAR13, VAR2,
VAR110, VAR71, VAR127,
VAR73, VAR1, VAR102,
VAR55, VAR47, VAR53, VAR119,
VAR106, VAR132, VAR109, VAR126,
VAR67, VAR44, VAR6, VAR93,
VAR64,
VAR49, VAR10, reset, VAR17, VAR33,
VAR19, VAR104, VAR101,
VAR92, VAR14, VAR131,
VAR68, VAR3, VAR80, VAR136,
VAR87, VAR123, VAR105, VAR56,... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram2_ddr2_rptr.v | 4,414 | module MODULE1(
VAR26, VAR23, VAR9,
VAR33, VAR24, VAR4,
VAR15, VAR27,
VAR32, VAR13,
VAR7, VAR36, VAR18,
VAR35, VAR19, VAR30,
VAR12, VAR22,
VAR21, VAR14, VAR20,
VAR16, VAR31, VAR28,
VAR6, VAR10, VAR25,
VAR3, VAR29, VAR1,
VAR34, VAR8, VAR2, VAR11,
VAR17, VAR5
);
output VAR26;
output [31:0] VAR23;
output [255:0] VAR9;
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi_1.v | 2,377 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR10 ,
VAR1 ,
VAR4 ,
VAR6,
VAR2,
VAR7 ,
VAR8
);
output VAR3 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR4 ;
input VAR6;
input VAR2;
input VAR7 ;
input VAR8 ;
VAR9 VAR11 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR... | apache-2.0 |
trevortheblack/NewLondo16 | Verilog/register_bank.v | 2,182 | module MODULE1(
input wire [31:0] VAR7,
input wire [31:0] VAR46,
input wire [31:0] VAR50,
input wire [31:0] VAR27,
input wire [31:0] VAR4,
input wire [31:0] VAR41,
input wire [31:0] VAR9,
input wire [31:0] VAR18,
input wire [31:0] VAR53,
input wire [31:0] VAR42,
input wire [31:0] VAR30,
input wire [31:0] VAR23,
input w... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/fill/sky130_fd_sc_hdll__fill.functional.v | 1,118 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf.behavioral.v | 1,319 | module MODULE1 (
VAR7,
VAR6
);
output VAR7;
input VAR6;
supply1 VAR9;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR1 ;
wire VAR8;
buf VAR3 (VAR8, VAR6 );
buf VAR2 (VAR7 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b.functional.pp.v | 1,924 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR12 ,
VAR8,
VAR14,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR12 ;
input VAR8;
input VAR14;
input VAR2 ;
input VAR1 ;
wire VAR15 ;
wire VAR11 ;
wire VAR10;
not VAR3 (VAR15 , VAR12 );
or VAR13 (VAR11 , VAR15, VAR6 );
VAR4 VAR9 (VAR10, VAR11, VAR8, VAR14);
buf VAR7 (VAR5 , VAR10 )... | apache-2.0 |
racerxdl/SuperINT | Slave Codes/FPGA/SuperINT.v | 19,148 | module MODULE1(
input clk,
input VAR61,
input VAR70,
output VAR81,
output VAR7
);
parameter VAR10 = 6; parameter VAR5 = 12; parameter VAR3 = 07;
reg [3:0] VAR77 = 0; wire VAR60 = (VAR77 > 7);
always @(posedge clk)
VAR77 <= VAR77 +1;
wire [23:0] VAR36;
wire VAR71;
reg [7:0] VAR18 = 0;
reg [7:0] VAR52 = 0;
reg [7:0] VAR9... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o.behavioral.pp.v | 2,052 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR16 ,
VAR10 ,
VAR11 ,
VAR9,
VAR3,
VAR6 ,
VAR17
);
output VAR1 ;
input VAR7 ;
input VAR16 ;
input VAR10 ;
input VAR11 ;
input VAR9;
input VAR3;
input VAR6 ;
input VAR17 ;
wire VAR15 ;
wire VAR5 ;
wire VAR4;
and VAR8 (VAR15 , VAR7, VAR16 );
or VAR14 (VAR5 , VAR15, VAR11, VAR10 );
VAR12 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b.behavioral.pp.v | 1,981 | module MODULE1 (
VAR3 ,
VAR13 ,
VAR5 ,
VAR12 ,
VAR16,
VAR14,
VAR8 ,
VAR9
);
output VAR3 ;
input VAR13 ;
input VAR5 ;
input VAR12 ;
input VAR16;
input VAR14;
input VAR8 ;
input VAR9 ;
wire VAR15 ;
wire VAR1 ;
wire VAR11;
not VAR10 (VAR15 , VAR13 );
and VAR6 (VAR1 , VAR12, VAR15, VAR5 );
VAR4 VAR2 (VAR11, VAR1, VAR16, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha.symbol.v | 1,274 | module MODULE1 (
input VAR4 ,
input VAR3 ,
output VAR7,
output VAR8
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
richard42/CoCo3FPGA | 6850TX.v | 4,600 | module MODULE1(
VAR10,
VAR13,
VAR12,
VAR1,
VAR9,
VAR6,
VAR7,
VAR5,
VAR11,
VAR15
);
input VAR10;
input VAR13;
output VAR12;
reg VAR12;
input VAR1;
output VAR9;
reg VAR9;
input VAR6;
input VAR7;
input VAR5;
input VAR11;
input [7:0] VAR15;
reg [6:0] VAR3;
reg [2:0] VAR14;
wire VAR4;
reg VAR2;
reg VAR8;
assign VAR4 = ((VAR... | bsd-3-clause |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_phy_alt_mem_phy_pll.v | 24,102 | module MODULE1 (
VAR46,
VAR10,
VAR101,
VAR93,
VAR69,
VAR41,
VAR77,
VAR25,
VAR70,
VAR28,
VAR29,
VAR108,
VAR54,
VAR1);
input VAR46;
input VAR10;
input [3:0] VAR101;
input VAR93;
input VAR69;
input VAR41;
output VAR77;
output VAR25;
output VAR70;
output VAR28;
output VAR29;
output VAR108;
output VAR54;
output VAR1;
tri0 V... | gpl-3.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_fetch_cappuccino.v | 20,711 | module MODULE1
parameter VAR8 = 32,
parameter VAR72 = {{(VAR8-13){1'b0}},
parameter VAR54 = 5,
parameter VAR81 = "VAR32",
parameter VAR63 = 5,
parameter VAR114 = 9,
parameter VAR49 = 2,
parameter VAR60 = 32,
parameter VAR82 = "VAR32",
parameter VAR87 = "VAR32",
parameter VAR21 = 6,
parameter VAR10 = 1
)
(
input clk,
in... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp_2.v | 2,362 | module MODULE1 (
VAR2 ,
VAR8,
VAR5 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR7 ,
VAR1
);
output VAR2 ;
input VAR8;
input VAR5 ;
input VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
VAR9 VAR10 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_binari_get_sig_ctx.v | 10,481 | module MODULE1(
VAR5 ,
VAR1 ,
VAR4 ,
VAR7 ,
VAR17 ,
VAR8 ,
VAR12
);
input [ 1:0 ] VAR5 ;
input [ 1:0 ] VAR1 ;
input [ 4:0 ] VAR4 ;
input [ 4:0 ] VAR7 ;
input [ 1:0 ] VAR17 ;
input [ 1:0 ] VAR8 ;
output [ 7:0 ] VAR12 ;
reg [ 3:0 ] VAR18 ;
wire [ 3:0 ] VAR3 ;
assign VAR3 = (VAR7[1:0]<<2) + VAR4[1:0] ;
always @* begin
cas... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/4-way/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_mc_phy_wrapper.v | 66,993 | module MODULE1 #
(
parameter VAR46 = 100, parameter VAR76 = 2500, parameter VAR437 = "VAR441", parameter VAR417 = "VAR395", parameter VAR110 = "VAR225", parameter VAR38 = "VAR311",
parameter VAR97 = 4, parameter VAR157 = 1, parameter VAR343 = 3, parameter VAR415 = 1, parameter VAR215 = 1, parameter VAR89 = 1, parameter... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mesosync_io/src/bsg_mesosync_link.v | 6,444 | module MODULE1
, parameter VAR46 = VAR41 + VAR13
)
( input clk
, input reset
, input VAR43 VAR5
, input [VAR46-1:0] VAR42
, output logic [VAR46-1:0] VAR55
, input [VAR46-3:0] VAR32
, input VAR16
, output logic VAR53
, output VAR6
, output [VAR46-3:0] VAR4
, input VAR29
);
logic VAR48;
logic VAR37;
logic ready, valid;
l... | bsd-3-clause |
myriadrf/A2300 | hdl/wca/WcaReadWordReg.v | 2,016 | module MODULE1
(
input wire reset, input wire VAR8, input wire VAR11, input wire [15:0] in,
input wire [11:0] VAR4, inout wire [7:0] VAR12 );
parameter VAR2 = 0;
wire [7:0] VAR5;
wire [7:0] VAR3;
wire VAR16 = (VAR2 == VAR4[11:4]);
wire read = VAR16 & VAR4[3];
wire enable = VAR11 & ~VAR16;
reg select;
always @(posedge V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai.pp.symbol.v | 1,408 | module MODULE1 (
input VAR4 ,
input VAR7 ,
input VAR9 ,
input VAR1 ,
input VAR3 ,
output VAR2 ,
input VAR6 ,
input VAR5,
input VAR10,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3.behavioral.pp.v | 1,867 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR8,
VAR7,
VAR6 ,
VAR3
);
output VAR10 ;
input VAR5 ;
input VAR8;
input VAR7;
input VAR6 ;
input VAR3 ;
wire VAR2 ;
wire VAR1;
not VAR12 (VAR2 , VAR5 );
VAR11 VAR4 (VAR1, VAR2, VAR8, VAR7);
buf VAR9 (VAR10 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.pp.blackbox.v | 1,392 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR3 ,
VAR4,
VAR6,
VAR1,
VAR8 ,
VAR7
);
output VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR6;
input VAR1;
input VAR8 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbp/sky130_fd_sc_hd__dfbbp.behavioral.v | 2,671 | module MODULE1 (
VAR10 ,
VAR25 ,
VAR18 ,
VAR11 ,
VAR9 ,
VAR15
);
output VAR10 ;
output VAR25 ;
input VAR18 ;
input VAR11 ;
input VAR9 ;
input VAR15;
supply1 VAR14;
supply0 VAR24;
supply1 VAR8 ;
supply0 VAR7 ;
wire VAR28 ;
wire VAR1 ;
wire VAR16 ;
wire VAR4 ;
wire VAR20;
wire VAR17 ;
reg VAR5 ;
wire VAR21 ;
wire VAR13 ;... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/dbg_if/dbg_register.v | 4,057 | module MODULE1 (
VAR2,
VAR3,
write,
clk,
reset
);
parameter VAR1 = 8; parameter VAR4 = 0;
input [VAR1-1:0] VAR2;
input write;
input clk;
input reset;
output [VAR1-1:0] VAR3;
reg [VAR1-1:0] VAR3;
always @ (posedge clk or posedge reset)
begin
if(reset)
VAR3[VAR1-1:0] <= VAR4;
end
else if(write)
VAR3[VAR1-1:0] <= VAR2[VAR... | mit |
vvk/sysrek | pipeline_summator/summator.v | 1,262 | module MODULE1(
input [12:0] VAR7,
input clk,
input VAR10,
input rst,
output [20:0] VAR5
);
reg [20:0] sum = 21'b0;
wire [20:0] VAR2;
reg [20:0 ] VAR6 = 21'b0;
always @(posedge clk)
begin
if(rst) sum = 21'b0;
end
else
begin
sum = VAR2;
if(VAR10) VAR6 = {{VAR7[12]}, {8{VAR7[12]}}, {VAR7[11:0]}};
end
else VAR6 = 0;
end
e... | gpl-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_hps_only_master_b2p_adapter.v | 1,501 | module MODULE1 (
input clk,
input VAR6,
output reg VAR1,
input VAR12,
input [ 7: 0] VAR11,
input [ 7: 0] VAR13,
input VAR10,
input VAR5,
input VAR4,
output reg VAR7,
output reg [ 7: 0] VAR2,
output reg VAR8,
output reg VAR3
);
reg VAR9;
always @* begin
VAR1 = VAR4;
VAR7 = VAR12;
VAR2 = VAR11;
VAR8 = VAR10;
VAR3 = VAR5;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp.functional.v | 2,061 | module MODULE1 (
VAR16 ,
VAR6 ,
VAR12 ,
VAR7 ,
VAR17 ,
VAR4 ,
VAR10
);
output VAR16 ;
output VAR6 ;
input VAR12 ;
input VAR7 ;
input VAR17 ;
input VAR4 ;
input VAR10;
wire VAR8 ;
wire VAR13 ;
wire VAR1;
not VAR14 (VAR13 , VAR10 );
VAR18 VAR5 (VAR1, VAR7, VAR17, VAR4 );
VAR15 VAR9 VAR3 (VAR8 , VAR1, VAR12, VAR13);
buf V... | apache-2.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_external_sdram_controller.v | 24,345 | module MODULE2 (
clk,
rd,
VAR70,
wr,
VAR72,
VAR59,
VAR34,
VAR65,
VAR52,
VAR40
)
;
output VAR59;
output VAR34;
output VAR65;
output VAR52;
output [ 42: 0] VAR40;
input clk;
input rd;
input VAR70;
input wr;
input [ 42: 0] VAR72;
wire VAR59;
wire VAR34;
wire VAR65;
reg [ 1: 0] VAR80;
reg [ 42: 0] VAR17;
reg [ 42: 0] VAR77... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtn/sky130_fd_sc_hd__dfrtn.pp.blackbox.v | 1,401 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR6 ,
VAR7,
VAR4 ,
VAR8 ,
VAR5 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR7;
input VAR4 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_1g_fifo.v | 10,046 | module MODULE1 #
(
parameter VAR105 = 8,
parameter VAR91 = (VAR105>8),
parameter VAR104 = (VAR105/8),
parameter VAR87 = 1,
parameter VAR86 = 64,
parameter VAR80 = 4096,
parameter VAR122 = 1,
parameter VAR64 = 1,
parameter VAR76 = VAR64,
parameter VAR38 = VAR76,
parameter VAR9 = 0,
parameter VAR8 = 4096,
parameter VAR31... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_mul_exp_dp.v | 12,318 | module MODULE1 (
VAR41,
VAR14,
VAR67,
VAR68,
VAR4,
VAR84,
VAR74,
VAR51,
VAR31,
VAR11,
VAR62,
VAR45,
VAR40,
VAR27,
VAR72,
VAR26,
VAR75,
VAR46,
VAR58,
VAR47,
VAR55,
VAR5,
VAR24,
VAR70,
VAR44,
VAR65,
VAR61,
VAR13,
VAR20,
VAR77,
VAR80,
VAR85,
VAR9,
VAR73,
VAR32,
VAR1,
VAR25
);
input [62:52] VAR41; input [62:52] VAR14; inpu... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/packet_queue.v | 18,396 | module MODULE1(
input clk,
input VAR162,
input reset,
output [239:0] VAR66,
output [239:0] VAR126,
output reg VAR187,
input [10:2] VAR104,
input [31:0] VAR213,
output [31:0] VAR224,
input VAR71,
input VAR105,
input VAR27,
input [7:0] VAR19,
input [63:0] VAR205,
input [23:0] VAR145,
input VAR137,
input VAR203,
output VA... | mit |
chcbaram/Altera_DE0_nano_Exam | prj_niosii/db/ip/niosii/niosii.v | 25,232 | module MODULE1 (
input wire VAR57, output wire [7:0] VAR19, input wire VAR146 );
wire [31:0] VAR159; wire VAR45; wire VAR113; wire [17:0] VAR32; wire [3:0] VAR178; wire VAR151; wire VAR174; wire VAR191; wire [31:0] VAR149; wire [31:0] VAR143; wire VAR64; wire [17:0] VAR54; wire VAR129; wire VAR91; wire VAR46; wire [31:... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/ui/ui_wr_data.v | 20,862 | module MODULE1 #
(
parameter VAR72 = 100,
parameter VAR18 = 256,
parameter VAR34 = 32,
parameter VAR20 = "VAR41",
parameter VAR15 = "VAR41",
parameter VAR38 = 5
)
(
VAR84, VAR68, VAR26, VAR45, VAR101,
VAR74,
rst, clk, VAR7, VAR36, VAR85, VAR109,
VAR94, VAR8, VAR12, VAR5, VAR3,
VAR43, VAR71
);
input rst;
input clk;
inpu... | lgpl-3.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/PreFabALU+RF+BS/RegisterFile.v | 2,257 | module MODULE1(input [31:0] in,VAR5,input [19:0] VAR13,input VAR31, VAR42, VAR1, VAR30,VAR14, output [31:0] VAR21,VAR15,VAR26,VAR20);
wire [31:0] VAR9[15:0];
wire [15:0] VAR25; VAR29 VAR18(.VAR27(VAR13[15:12]),.VAR34(VAR25));
wire [3:0] VAR32;
VAR41 mux(VAR13[19:16],VAR13[3:0],VAR14,VAR32);
wire [15:0] VAR33; VAR29 VAR... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_aon_lclkgen_regs.v | 2,835 | module MODULE1(
input clk,
input VAR9,
output VAR17,
input VAR16,
output VAR2,
input [8 -1:0] VAR18,
input VAR8,
input [32-1:0] VAR12,
output VAR3,
input VAR11,
output [32-1:0] VAR13
);
assign VAR3 = VAR16;
assign VAR2 = VAR11;
wire VAR1 = VAR16 & VAR2 & (~VAR8);
wire [32-1:0] VAR14 = VAR12;
wire [32-1:0] VAR5;
wire VA... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/spree/ifetch_pipe.v | 4,554 | module MODULE1(clk,VAR29,
en,
VAR6,
VAR5,
VAR10,
VAR22,
VAR25,
VAR4,
VAR1,
VAR14,
VAR24,
VAR3,
VAR20,
VAR8,
VAR18,
rd,
VAR12,
VAR26,
VAR13,
VAR2,
VAR9);
parameter VAR23=30;
parameter VAR15=32;
parameter VAR28=14;
parameter VAR21=16384;
input [31:0] VAR14;
input [31:0] VAR24;
input VAR3;
input clk;
input VAR29;
input en... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_021bits.v | 1,917 | module MODULE1 (
clk,
VAR28, VAR19, VAR3, VAR20, VAR12, VAR24, VAR14, VAR16,
sum,
);
input clk;
input [VAR6+0-1:0] VAR28, VAR19, VAR3, VAR20, VAR12, VAR24, VAR14, VAR16;
output [VAR6 :0] sum;
reg [VAR6 :0] sum;
wire [VAR6+3-1:0] VAR5;
wire [VAR6+2-1:0] VAR30, VAR33;
wire [VAR6+1-1:0] VAR32, VAR17, VAR22, VAR34;
reg [VA... | mit |
sh-chris110/chris | FPGA/HPS/Qsys/hps_design/synthesis/submodules/hps_design_SMP_HPS_hps_io.v | 1,931 | module MODULE1 (
output wire [14:0] VAR1, output wire [2:0] VAR18, output wire VAR10, output wire VAR2, output wire VAR8, output wire VAR5, output wire VAR9, output wire VAR6, output wire VAR3, output wire VAR4, inout wire [15:0] VAR11, inout wire [1:0] VAR15, inout wire [1:0] VAR14, output wire VAR13, output wire [1:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill_diode/sky130_fd_sc_hs__fill_diode.functional.pp.v | 1,178 | module MODULE1 (
VAR4,
VAR1,
VAR3 ,
VAR2
);
input VAR4;
input VAR1;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/MemControl.v | 11,424 | module MODULE1(
input VAR32,
input reset,
input [31:0] VAR22, input [31:0] VAR37, input [31:0] VAR2, input VAR12, input VAR5, input VAR45, input VAR19, input VAR11, input VAR9, input VAR3, input VAR44, input VAR1, input VAR31, input VAR15, input VAR34, input VAR43,
input VAR30, output reg [31:0] VAR41, output [31:0] VA... | lgpl-3.0 |
iceman1001/proxmark3 | fpga/fpga_hf.v | 7,039 | module MODULE1(
input VAR80, output VAR108, input VAR15, input VAR71,
input VAR91, input VAR102, input VAR65,
output VAR20, output VAR33,
output VAR58, output VAR90, output VAR45, output VAR89,
input [7:0] VAR120, output VAR68, output VAR87,
output VAR43, output VAR72, input VAR75, output VAR39,
input VAR48, input VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2.pp.blackbox.v | 1,263 | module MODULE1 (
VAR1,
VAR4,
VAR2 ,
VAR3
);
input VAR1;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
tanelikaivola/blinkenlichten | fpga/main.v | 1,833 | module MODULE1(
input VAR21,
output [7:0] VAR2,
output [7:0] VAR12,
output reg VAR30,
output VAR15,
input [2:0] VAR5,
inout [3:0] VAR14,
input [3:0] VAR31
);
localparam VAR9 = 20;
wire [7:0] VAR8;
wire VAR11;
reg VAR26 = 1;
wire [255:0] VAR20;
reg [255:0] VAR13 = 256'b0;
wire VAR1;
wire VAR28;
reg [8:0] VAR16 = 0;
reg ... | mit |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/sequencer_scc_siii_phase_decode.v | 11,473 | module MODULE1
VAR6 = 32,
VAR1 = 6
)
(
VAR2,
VAR4,
VAR5,
VAR7,
VAR3
);
input [VAR6 - 1:0] VAR2;
output [2:0] VAR4;
output [6:0] VAR5;
output [6:0] VAR7;
output [5:0] VAR3;
reg [2:0] VAR4;
reg [6:0] VAR5;
reg [6:0] VAR7;
reg [5:0] VAR3;
always @ (*) begin
VAR4 = 0;
VAR5 = 0;
VAR7 = 0;
VAR3 = 0;
case (VAR1)
6: begin
VAR4... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/keyboard.v | 3,313 | module MODULE1 (
output reg [79:0] VAR2,
input VAR3, input VAR1,
input [3:0] VAR5, input [7:0] VAR8,
output reg [7:0] VAR6,
input VAR4,
input VAR7
);
reg [79:0] MODULE1;
always @(posedge VAR3)
begin
if( !VAR1 ) begin
MODULE1 <= 80'd0;
VAR2 <= ~(80'd0);
end
else begin
if( !VAR7 ) begin
VAR6 <= (VAR5 == 4'd0) ? MODULE1[7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.pp.symbol.v | 1,394 | module MODULE1 (
input VAR2 ,
input VAR6 ,
input VAR7 ,
input VAR10 ,
input VAR9 ,
output VAR1 ,
input VAR5 ,
input VAR8,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v | 3,359 | module MODULE1(
VAR67,
VAR13,
VAR12,
VAR38,
VAR21,
VAR63,
VAR43,
VAR31,
VAR47,
VAR41,
VAR49,
VAR48,
VAR53,
VAR56,
VAR65,
VAR42,
VAR51,
VAR2,
VAR50,
VAR23,
VAR61,
VAR1,
VAR15,
VAR45,
VAR44,
VAR39,
VAR52,
VAR8,
VAR60,
VAR57,
VAR14,
VAR27,
VAR62,
VAR54,
VAR46,
VAR25,
VAR16,
VAR30
);
input VAR67;
input VAR13;
input [VAR19-... | gpl-3.0 |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/Exponential/LUT_SHIFT.v | 2,039 | module MODULE1 #(parameter VAR2 = 5) (
input wire VAR3,
input wire VAR4,
input wire [4:0] VAR1,
output reg [VAR2-1:0] VAR5
);
always @(posedge VAR3)
if (VAR4)
case (VAR1)
5'b00000: VAR5 <= 5'b00000;
5'b00001: VAR5 <= 5'b00000;
5'b00010: VAR5 <= 5'b00001;
5'b00011: VAR5 <= 5'b00010;
5'b00100: VAR5 <= 5'b00011;
5'b00101:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4.functional.pp.v | 1,870 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR14 ,
VAR8 ,
VAR10 ,
VAR9,
VAR15,
VAR1 ,
VAR11
);
output VAR3 ;
input VAR7 ;
input VAR14 ;
input VAR8 ;
input VAR10 ;
input VAR9;
input VAR15;
input VAR1 ;
input VAR11 ;
wire VAR6 ;
wire VAR5;
nor VAR2 (VAR6 , VAR7, VAR14, VAR8, VAR10 );
VAR13 VAR12 (VAR5, VAR6, VAR9, VAR15);
buf VAR4 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha.functional.v | 1,415 | module MODULE1 (
VAR3,
VAR10 ,
VAR5 ,
VAR9
);
output VAR3;
output VAR10 ;
input VAR5 ;
input VAR9 ;
wire VAR2;
wire VAR4 ;
and VAR1 (VAR2, VAR5, VAR9 );
buf VAR7 (VAR3 , VAR2 );
xor VAR8 (VAR4 , VAR9, VAR5 );
buf VAR6 (VAR10 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2.blackbox.v | 1,269 | module MODULE1 (
VAR8 ,
VAR1,
VAR3,
VAR2
);
output VAR8 ;
input VAR1;
input VAR3;
input VAR2 ;
supply1 VAR7;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbn/sky130_fd_sc_ls__dlrbn.pp.symbol.v | 1,458 | module MODULE1 (
input VAR6 ,
output VAR4 ,
output VAR8 ,
input VAR3,
input VAR7 ,
input VAR5 ,
input VAR2 ,
input VAR9 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai.functional.v | 1,592 | module MODULE1 (
VAR13 ,
VAR4,
VAR7,
VAR3,
VAR12,
VAR1
);
output VAR13 ;
input VAR4;
input VAR7;
input VAR3;
input VAR12;
input VAR1;
wire VAR8 ;
wire VAR6 ;
wire VAR10;
or VAR11 (VAR8 , VAR12, VAR3 );
or VAR9 (VAR6 , VAR7, VAR4 );
nand VAR2 (VAR10, VAR6, VAR8, VAR1);
buf VAR5 (VAR13 , VAR10 );
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/project_1.xpr/project_1/project_1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Add-Subt/FPU_Add_Subtract_Function.v | 12,630 | module MODULE1
wire [VAR23-1:0] VAR27;
assign VAR27 = ~VAR31;
VAR12 #(.VAR23(VAR23),.VAR16(VAR16)) VAR14 (
.clk(clk),
.rst(VAR8),
.VAR38(VAR21),
.VAR3(VAR27),
.VAR5(VAR11)
);
VAR26 VAR33(
.VAR15(VAR1[1:0]),
.VAR34(VAR6),
.VAR28(VAR22),
.VAR17(VAR25)
);
VAR13 #(.VAR36(VAR36),.VAR7(VAR7),.VAR37(VAR37)) VAR10(
.clk(clk),
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4.blackbox.v | 1,269 | module MODULE1 (
VAR2,
VAR9,
VAR3,
VAR4,
VAR1
);
output VAR2;
input VAR9;
input VAR3;
input VAR4;
input VAR1;
supply1 VAR6;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_bleeder/sky130_fd_sc_hd__lpflow_bleeder.pp.blackbox.v | 1,290 | module MODULE1 (
VAR1,
VAR2 ,
VAR4 ,
VAR5 ,
VAR3
);
input VAR1;
inout VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2/sky130_fd_sc_ms__nor2.pp.symbol.v | 1,263 | module MODULE1 (
input VAR3 ,
input VAR1 ,
output VAR5 ,
input VAR7 ,
input VAR2,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p.functional.v | 1,260 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR3 ;
input VAR1;
wire VAR5;
not VAR4 (VAR5, VAR1 );
and VAR2 (VAR6 , VAR3, VAR5 );
endmodule | apache-2.0 |
somethingnew2-0/CS552-CPU | RoadRunner/off_by_one.tar.gz_extracted/MemoryHierarchy.v | 3,152 | module MODULE1(clk, VAR17, VAR23, VAR16, VAR27, VAR41, VAR47, VAR50, VAR11, VAR49, VAR42);
input clk, VAR17, VAR23, VAR16, VAR27; input [15:0] VAR41, VAR47, VAR50;
output VAR11;
output [15:0] VAR49, VAR42;
wire rd, wr;
wire [15:0] addr;
wire VAR32, VAR15, VAR14, VAR2, VAR5, VAR18, VAR26;
wire [7:0] VAR39, VAR46;
wire [... | mit |
GSejas/Karatsuba_FPU | ASIC_FLOW/global_sources/KOA_c_ASIC.v | 9,599 | module MODULE1
(
input wire [VAR5-1:0] VAR8,
input wire [VAR5-1:0] VAR22,
output wire [2*VAR5-1:0] VAR20
);
wire [VAR5/2+1:0] VAR37;
wire [VAR5/2+1:0] VAR10;
wire [2*(VAR5/2)-1:0] VAR35;
wire [2*(VAR5/2+1)-1:0] VAR16;
wire [2*(VAR5/2+2)-1:0] VAR23;
wire [2*(VAR5/2+2)-1:0] VAR36;
wire [2*(VAR5/2+2)-1:0] VAR27;
wire [4*(... | gpl-3.0 |
shaform/ArkanoidOnVerilog | stage_rom.v | 8,702 | module MODULE1(
input VAR1, enable,
input [4:0] addr,
input [1:0] VAR2,
output reg [29:0] VAR3
);
always @(posedge VAR1)
begin
if (enable)
case (VAR2)
2'b00: case (addr)
5'b00000: VAR3 <= 30'b111111111111111111111111111111;
5'b00001: VAR3 <= 30'b000000000000000000000100000000;
5'b00010: VAR3 <= 30'b00000000000000000000... | gpl-3.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_sync_h.v | 5,014 | module MODULE1(
input wire clk,
input wire VAR9,
input wire VAR16, input wire VAR4,
input wire VAR7,
input wire VAR23,
output reg VAR24,
output reg VAR27,
output reg VAR22, output reg VAR14,
output reg VAR5,
output reg VAR11,
output reg VAR25,
output reg VAR13, output reg VAR15
);
localparam VAR1 = 9'd00;
localparam VA... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | src/pipe2.v | 2,352 | module MODULE1(VAR22, VAR24,
VAR26, VAR15,
VAR6, VAR11,
VAR8, VAR2,
VAR3, VAR27,
VAR4, VAR21,
VAR14, VAR18,
VAR10, VAR19,
VAR13, VAR5,
VAR12, VAR7,
VAR17, VAR9,
VAR1, VAR23,
VAR20, VAR25,
clk,
reset);
input [0:4] VAR22;
input [0:1] VAR26;
input VAR6, VAR8;
input [0:20] VAR3;
input [0:15] VAR4;
input VAR14;
input [0:4] ... | mit |
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