repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.v | 9,058 | module MODULE1
parameter [3:0] VAR24 = 4'h1, parameter [5:0] VAR23 = 6'h08, parameter VAR15 = "VAR17",
parameter VAR21 = 0,
parameter VAR19 = 1,
parameter VAR9 = 1,
parameter VAR7 = 1
)
(
input VAR1,
input VAR22,
input VAR6,
input [12:0] VAR11,
input [71:0] VAR4,
input VAR14,
input VAR26,
input [12:0] VAR20,
output [71... | lgpl-3.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/ereset.v | 1,724 | module MODULE1 (
reset, VAR3,
VAR1, VAR2
);
input VAR1; input VAR2;
output reset; output VAR3;
assign reset = VAR1 | VAR2;
assign VAR3 = ~(VAR1 | VAR2);
endmodule | gpl-3.0 |
shahid313/MSCourseWork | Adv ASIC Design and FPGA/8bitRISCProcessor/8bitRISCProcessor/RISC/Control.v | 1,510 | module MODULE1(input [3:0] VAR8,output [2:0]VAR5,output VAR4,VAR9,VAR2,VAR1,
VAR7,VAR3
);
reg [8:0] VAR6;
assign {VAR4,VAR9,VAR2,VAR5,VAR1,VAR7,VAR3} = VAR6 ;
always @(VAR8)
case(VAR8)
4'b0000: VAR6=9'b000000000; 4'b0001: VAR6=9'b110001000; 4'b0010: VAR6=9'b110010000; 4'b0011: VAR6=9'b110011000; 4'b0100: VAR6=9'b110010... | gpl-2.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,553 | module MODULE1
parameter VAR29 = 8,
VAR20 = 8,
VAR1 = 0,
VAR16 = 0,
VAR38 = 1,
VAR19 = 0,
VAR37 = 1,
VAR35 = 2,
VAR34 = 2,
VAR10 = 1,
VAR36 = VAR29 / VAR20,
VAR14 = VAR6(VAR36)
)
(
input VAR22,
input VAR8,
input VAR42,
input VAR12,
output VAR4,
input VAR25,
input [VAR29 - 1 : 0] VAR39,
input [VAR38 - 1 : 0] VAR9,
input... | gpl-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/MULT_sumXsq/MULT_sumXsq_bb.v | 3,785 | module MODULE1 (
VAR3,
VAR2,
VAR1);
input [25:0] VAR3;
input [23:0] VAR2;
output [49:0] VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o.blackbox.v | 1,395 | module MODULE1 (
VAR8 ,
VAR3,
VAR7,
VAR1,
VAR2,
VAR10
);
output VAR8 ;
input VAR3;
input VAR7;
input VAR1;
input VAR2;
input VAR10;
supply1 VAR5;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v | 51,690 | module MODULE1 #
(
parameter VAR24 = 100, parameter VAR90 = 2, parameter VAR40 = 5, parameter VAR31 = "0",
parameter VAR92 = 5, parameter VAR109 = "VAR140", parameter VAR41 = 1, parameter VAR20 = 3, parameter VAR113 = 8, parameter VAR46 = 8, parameter VAR94 = "VAR6", parameter VAR58 = "VAR81", parameter VAR123 = 3, par... | mit |
kevintownsend/inara-hdl-libraries | multistage_interconnect_network/multistage_interconnect_network.v | 2,532 | module MODULE1(clk, VAR12, din, valid, dout, VAR8);
parameter VAR15 = 64;
parameter VAR14 = 16;
parameter VAR11 = 5;
parameter VAR18 = VAR14;
parameter VAR21 = VAR7(VAR18-1); input clk;
input [0:VAR14-1] VAR12;
input [VAR14*VAR15-1:0] din;
output [0:VAR18-1] valid;
output [VAR18*VAR15-1:0] dout;
input [VAR21-1:0] VAR8;... | apache-2.0 |
jhennessy/parallella-hw-old | fpga/projects/vivado_parallella_7010_headless/parallella_7010_headless.srcs/sources_1/ip/processing_system7_0/processing_system7_0_stub.v | 9,503 | module MODULE1(VAR12, VAR85, VAR14, VAR92, VAR108, VAR21, VAR5, VAR103, VAR50, VAR110, VAR48, VAR7, VAR77, VAR124, VAR121, VAR25, VAR78, VAR80, VAR47, VAR98, VAR75, VAR105, VAR115, VAR53, VAR37, VAR11, VAR112, VAR100, VAR39, VAR57, VAR113, VAR120, VAR45, VAR9, VAR93, VAR79, VAR27, VAR22, VAR123, VAR30, VAR28, VAR62, VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1_2.v | 2,219 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR6 ,
VAR7,
VAR5,
VAR8 ,
VAR9
);
output VAR3 ;
input [3:0] VAR4 ;
input [3:0] VAR6 ;
input VAR7;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR1 VAR2 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR3,
VAR4,
VAR6
);
o... | apache-2.0 |
valkwarble/finalProject | BWIMAGE/zbt_6111_sample.v | 29,359 | module MODULE4(VAR186, VAR121,
VAR30, VAR140, VAR119,
VAR12,
VAR15, VAR195, VAR241, VAR76,
VAR75, VAR225, VAR96,
VAR91,
VAR87, VAR85, VAR164, VAR7,
VAR179, VAR176, VAR221,
VAR161, VAR203, VAR110,
VAR183, VAR83, VAR17,
VAR27, VAR9, VAR41, VAR33,
VAR120, VAR224, VAR8,
VAR158, VAR226, VAR139, VAR239,
VAR184, VAR98, VAR202... | gpl-2.0 |
SymbiFlow/yosys | techlibs/intel/cycloneiv/cells_map.v | 2,300 | module \VAR15 (input VAR3, output VAR8);
VAR20 VAR24 (.VAR12(VAR8), .VAR10(VAR3), .VAR19(1'b0));
endmodule
module \VAR7 (input VAR3, output VAR8);
VAR23 VAR24 (.VAR12(VAR8), .VAR10(VAR3), .VAR14(1'b1));
endmodule
module MODULE2 (VAR11, VAR6);
parameter VAR21 = 0;
parameter VAR2 = 0;
input [VAR21-1:0] VAR11;
output VAR6... | isc |
vvk/sysrek | arithm/ipcore_dir/mul1.v | 37,890 | module MODULE2 (
clk, VAR7, VAR229, VAR10
);
input clk;
output [30 : 0] VAR7;
input [18 : 0] VAR229;
input [11 : 0] VAR10;
wire \VAR161/VAR44 ;
wire \VAR161/VAR228 ;
wire \VAR161/VAR266 ;
wire \VAR161/VAR280 ;
wire \VAR161/VAR283 ;
wire \VAR161/VAR68 ;
wire \VAR161/VAR328 ;
wire \VAR161/VAR327 ;
wire \VAR161/VAR268 ;
w... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/top.v | 23,660 | module MODULE1 #(parameter VAR217 = 1, parameter VAR210 = 8,
parameter VAR38 = 128,
parameter VAR55 = 256,
parameter VAR151 = 6)
(output [(VAR210 - 1) : 0] VAR24,
output [(VAR210 - 1) : 0] VAR64,
input [(VAR210 - 1) : 0] VAR131,
input [(VAR210 - 1) : 0] VAR225,
output [3:0] VAR223,
input VAR80,
input VAR150,
input VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32oi/sky130_fd_sc_hs__a32oi.symbol.v | 1,397 | module MODULE1 (
input VAR3,
input VAR4,
input VAR8,
input VAR6,
input VAR2,
output VAR1
);
supply1 VAR5;
supply0 VAR7;
endmodule | apache-2.0 |
cyrozap/blake2 | src/rtl/blake2_m_select.v | 14,380 | module MODULE1(
input wire clk,
input wire VAR39,
input wire VAR44,
input wire [1023 : 0] VAR37,
input wire [3 : 0] VAR46,
input wire state,
output wire [63 : 0] VAR36,
output wire [63 : 0] VAR24,
output wire [63 : 0] VAR20,
output wire [63 : 0] VAR35,
output wire [63 : 0] VAR31,
output wire [63 : 0] VAR27,
output wire... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi.functional.v | 1,465 | module MODULE1 (
VAR5 ,
VAR3,
VAR2,
VAR6,
VAR7
);
output VAR5 ;
input VAR3;
input VAR2;
input VAR6;
input VAR7;
wire VAR1 ;
wire VAR9;
and VAR10 (VAR1 , VAR3, VAR2 );
nor VAR8 (VAR9, VAR1, VAR6, VAR7);
buf VAR4 (VAR5 , VAR9 );
endmodule | apache-2.0 |
mshaklunov/mips_onemore | rtl/mips_cpucore.v | 12,362 | module MODULE1 (
input VAR142,
input VAR110,
input[5:0] VAR46,
input VAR90,
input VAR137,
input[31:0] VAR26,
output[31:2] VAR103,
output VAR126,
output VAR29,
input VAR124,
input VAR33,
input[31:0] VAR74,
output[31:2] VAR21,
output[31:0] VAR4,
output VAR111,
output VAR94,
output VAR77,
output[3:0] VAR2
);
localparam VA... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/synth/ghrd_10as066n2_pr_region_controller_0.v | 3,420 | module MODULE1 (
input wire VAR11, input wire VAR16, input wire [1:0] VAR9, input wire [31:0] VAR10, output wire [31:0] VAR15, output wire VAR18, input wire VAR6, output wire VAR12, input wire VAR4, input wire VAR3, output wire VAR1, input wire VAR17, output wire VAR8, input wire VAR14, input wire VAR5, output wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a.behavioral.v | 1,635 | module MODULE1 (
VAR10 ,
VAR14,
VAR1,
VAR17,
VAR9,
VAR5
);
output VAR10 ;
input VAR14;
input VAR1;
input VAR17;
input VAR9;
input VAR5;
supply1 VAR13;
supply0 VAR16;
supply1 VAR12 ;
supply0 VAR7 ;
wire VAR2 ;
wire VAR15 ;
wire VAR3;
or VAR6 (VAR2 , VAR1, VAR14, VAR17 );
or VAR4 (VAR15 , VAR5, VAR9 );
and VAR11 (VAR3, V... | apache-2.0 |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/top.v | 7,447 | module MODULE1(reset, clk, VAR29, VAR58, VAR73, VAR25, VAR80, VAR12, VAR24, VAR28, VAR27, VAR95, VAR77,
VAR59, VAR90,
VAR33, VAR30, VAR20,
VAR48, VAR84);
input reset, clk, VAR29;
output VAR58;
input VAR33, VAR30, VAR20;
input [7:0] VAR27;
output [3:0] VAR95;
output VAR77;
input VAR80;
output VAR25, VAR73;
input VAR28;
... | gpl-3.0 |
eclay42/cs220-galois-aig-rewriting | mult4_strash.v | 3,918 | module MODULE1 (
VAR90, VAR102, VAR95, VAR76, b0, b1, VAR104, VAR34,
VAR7, VAR114, VAR81, VAR79, VAR74, VAR14, VAR38, VAR13 );
input VAR90, VAR102, VAR95, VAR76, b0, b1, VAR104, VAR34;
output VAR7, VAR114, VAR81, VAR79, VAR74, VAR14, VAR38, VAR13;
wire VAR118, VAR50, VAR56, VAR119, VAR19, VAR98, VAR91, VAR32, VAR43, VA... | mit |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx_cpu.v | 25,949 | module MODULE1
parameter VAR18 = 32,
parameter VAR11 = "VAR58",
parameter VAR46 = "VAR131",
parameter VAR54 = 5,
parameter VAR29 = 9,
parameter VAR75 = 2,
parameter VAR2 = 32,
parameter VAR164 = "VAR131",
parameter VAR93 = "VAR131",
parameter VAR139 = "VAR131",
parameter VAR158 = 6,
parameter VAR149 = 1,
parameter VAR7... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/MySource/ad9777_spi.v | 1,574 | module MODULE1(
output reg VAR6,
output reg VAR2,
input rst,
input clk,
output reg VAR7
);
wire [6:0] VAR4=7'd5;
function [15:0] VAR3;
input [5:0] addr;
begin
case(addr) 6'd0 :VAR3=16'b0000000000000100; 6'd1 :VAR3=16'b0000000100000000; 6'd2 :VAR3=16'b0000010100000001; 6'd3 :VAR3=16'b0000011000001111; 6'd4 :VAR3=16'b000... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode.functional.v | 1,141 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.functional.v | 1,446 | module MODULE1 (
VAR1 ,
VAR4,
VAR2,
VAR7,
VAR6
);
output VAR1 ;
input VAR4;
input VAR2;
input VAR7;
input VAR6;
wire VAR5 ;
wire VAR8;
or VAR10 (VAR5 , VAR2, VAR4 );
and VAR3 (VAR8, VAR5, VAR7, VAR6);
buf VAR9 (VAR1 , VAR8 );
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/opt_harder2_multi.v | 2,603 | module MODULE1(VAR4, VAR3, VAR5, VAR7, VAR1, VAR2, valid);
wire 00;
wire 01;
wire 02;
wire 03;
wire 04;
wire 05;
wire 06;
wire 07;
wire 08;
wire 09;
wire 10;
wire 11;
wire 12;
wire 13;
wire 14;
wire 15;
wire 16;
wire 17;
wire 18;
wire 19;
wire 20;
wire 21;
wire 22;
wire 23;
wire 24;
wire 25;
wire 26;
wire 27;
wire 28;
... | mit |
lkesteloot/alice | alice4/fpga/Alice4-DE0/VGA_FIFO_bb.v | 6,074 | module MODULE1 (
VAR9,
VAR3,
VAR7,
VAR4,
VAR1,
VAR2,
VAR10,
VAR6,
VAR8,
VAR5);
input VAR9;
input [11:0] VAR3;
input VAR7;
input VAR4;
input VAR1;
input VAR2;
output [11:0] VAR10;
output VAR6;
output VAR8;
output [7:0] VAR5;
tri0 VAR9;
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_axis_broadcaster_0_0/hdl/tuser_design_1_axis_broadcaster_0_0.v | 3,320 | module MODULE1 #
(
parameter VAR1 = 8,
parameter VAR2 = 8
)
(
input wire [VAR1-1:0] VAR4,
output wire [VAR2-1:0] VAR3
);
assign VAR3 = {1'b0,1'b0};
endmodule | gpl-3.0 |
GSejas/Aproximate-Arithmetic-Operators | src_lib/multlib/ETM_Multi.v | 2,494 | module MODULE1
input wire [VAR10-1:0] VAR4,
input wire [VAR10-1:0] VAR17,
output wire [2*VAR10-1:0] VAR14
);
generate
genvar VAR13;
if (VAR10%2==0) begin
wire [(VAR10>>1)-1:0] VAR15;
wire [(VAR10>>1)-1:0] VAR3;
wire [(VAR10>>1)-1:0] VAR2;
wire [(VAR10>>1)-1:0] VAR18;
assign VAR15 = VAR4[VAR10-1:(VAR10>>1)];
assign VAR3... | apache-2.0 |
ptracton/pmodacl2 | soc/system_controller/system_controller.v | 2,079 | module MODULE1(
VAR10, VAR2, VAR13,
VAR11, VAR12
);
input wire VAR11;
output wire VAR10;
input wire VAR12;
output wire VAR2;
output wire VAR13;
wire VAR16;
VAR1 VAR3(.VAR17(VAR11), .VAR9(VAR16));
wire VAR13;
assign VAR13 = 1;
reg [5:0] VAR5 = 6'h0;
assign VAR2 = VAR12 | ~VAR13 | (|VAR5);
always @(posedge VAR11)
if (VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2.functional.pp.v | 1,927 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR13 ,
VAR14 ,
VAR2,
VAR11,
VAR4 ,
VAR3
);
output VAR8 ;
input VAR5 ;
input VAR13 ;
input VAR14 ;
input VAR2;
input VAR11;
input VAR4 ;
input VAR3 ;
wire VAR9 ;
wire VAR6;
VAR7 VAR15 (VAR9 , VAR5, VAR13, VAR14 );
VAR10 VAR12 (VAR6, VAR9, VAR2, VAR11);
buf VAR1 (VAR8 , VAR6 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_082.v | 1,581 | module MODULE1 (
VAR2,
VAR9
);
input [31:0] VAR2;
output [31:0]
VAR9;
wire [31:0]
VAR6,
VAR13,
VAR11,
VAR7,
VAR14,
VAR1,
VAR8,
VAR10,
VAR4,
VAR3;
assign VAR6 = VAR2;
assign VAR1 = VAR11 << 2;
assign VAR4 = VAR8 - VAR10;
assign VAR8 = VAR14 - VAR1;
assign VAR14 = VAR7 - VAR11;
assign VAR7 = VAR6 << 14;
assign VAR13 = VA... | mit |
Siliciumer/DOS-Mario-FPGA | sources/clouds.v | 4,506 | module MODULE1 (
input wire clk,
input wire rst,
input wire [9:0] VAR9,
input wire [9:0] VAR20,
input wire VAR8,
input wire [9:0] VAR18,
input wire VAR2,
input wire [23:0] VAR12,
input wire VAR17,
output reg [9:0] VAR14,
output reg VAR7,
output reg [9:0] VAR19,
output reg VAR10,
output reg [23:0] VAR23,
output reg VAR2... | mit |
alankarkotwal/lca-processor | pipeline/pipeline_regs.v | 12,271 | module MODULE5(clk, reset, VAR35, VAR57, VAR80, VAR63, VAR59, VAR61,VAR97,VAR117,VAR23);
output VAR117
output [15:0] VAR63, VAR59, VAR61;
input [15:0] VAR35, VAR57, VAR80;
input reset, clk;
input VAR97,VAR23;
wire [15:0]VAR12;
wire VAR113;
assign VAR113 = (VAR23==1'b1?1'b0:VAR97); assign VAR12 = (VAR23==1'b1?{16'b11110... | gpl-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/Comparador.v | 3,597 | module MODULE1 #(parameter VAR29 = 24, VAR53= -32'VAR22, VAR5= -32'VAR20,
VAR59 = -32'VAR19, VAR33 = -32'VAR57, VAR42 = -32'VAR35, VAR40 = -32'VAR3, VAR50 = -32'VAR26, VAR30 = -32'VAR34, VAR58 = -32'VAR2, VAR24 = -32'VAR62,
VAR36= -32'VAR44, VAR46= -32'VAR37, VAR17 = -32'VAR10, VAR43 = -32'VAR47, VAR4 = -32'VAR54, VAR3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb_2.v | 2,314 | module MODULE2 (
VAR11 ,
VAR1 ,
VAR2 ,
VAR10 ,
VAR3 ,
VAR4,
VAR8,
VAR6 ,
VAR9
);
output VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR10 ;
input VAR3 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR9 ;
VAR7 VAR5 (
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/conbus/rtl/conbus.v | 7,272 | module MODULE1 #(
parameter VAR67 = 4,
parameter VAR36 = 4'h0,
parameter VAR90 = 4'h1,
parameter VAR76 = 4'h2,
parameter VAR77 = 4'h3,
parameter VAR58 = 4'h4
) (
input VAR93,
input VAR40,
input [31:0] VAR10,
output [31:0] VAR110,
input [31:0] VAR18,
input [2:0] VAR69,
input [3:0] VAR47,
input VAR65,
input VAR119,
input... | lgpl-3.0 |
JakeMercer/mac | MAC/rtl/mac/tx/tx_sm.v | 9,355 | module MODULE1 #(
parameter VAR43 = 4'h0,
parameter VAR31 = 4'h1,
parameter VAR35 = 4'h2,
parameter VAR1 = 4'h3,
parameter VAR16 = 4'h4,
parameter VAR20 = 4'h5,
parameter VAR45 = 4'h6,
parameter VAR3 = 4'h7,
parameter VAR10 = 4'h8,
parameter VAR26 = 4'h9,
parameter VAR25 = 4'hA,
parameter VAR2 = 4'hB
)(
input wire rese... | mit |
iAklis/teoca | EXP2/MAIN.v | 1,474 | module MODULE4(VAR20, VAR21, VAR1, VAR15, VAR23
);
parameter VAR4 = 4;
input [VAR4-1: 0] VAR20, VAR21;
input VAR1;
output [VAR4-1: 0] VAR15;
output VAR23;
wire VAR17, VAR3, VAR5;
wire VAR7, VAR8, VAR9, VAR10;
wire VAR24, VAR19, VAR14, VAR2;
MODULE2 VAR7(VAR20[0], VAR21[0], VAR7);
MODULE2 VAR8(VAR20[1], VAR21[1], VAR8);... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi.functional.v | 1,623 | module MODULE1 (
VAR7 ,
VAR8,
VAR1,
VAR3,
VAR6,
VAR2
);
output VAR7 ;
input VAR8;
input VAR1;
input VAR3;
input VAR6;
input VAR2;
wire VAR11 ;
wire VAR13 ;
wire VAR12;
nand VAR9 (VAR11 , VAR1, VAR8, VAR3 );
nand VAR10 (VAR13 , VAR2, VAR6 );
and VAR4 (VAR12, VAR11, VAR13);
buf VAR5 (VAR7 , VAR12 );
endmodule | apache-2.0 |
silent-observer/RCPU | CPU/source/UART_Controller/RS232RX.v | 1,567 | module MODULE1 (
input wire clk,
input wire rst,
input wire VAR7,
output reg[7:0] VAR6,
output reg ready,
input wire VAR8,
output reg VAR1
);
reg VAR2, VAR4, VAR10, VAR3;
always @(posedge clk) begin
if (rst) begin
VAR2 <= 1'b0;
VAR4 <= 1'b0;
VAR10 <= 1'b0;
VAR3 <= 1'b0;
end else begin
VAR2 <= VAR7;
VAR4 <= VAR2;
VAR10 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrbp/sky130_fd_sc_hd__dfrbp.pp.blackbox.v | 1,408 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR4 ,
VAR8 ,
VAR3,
VAR7 ,
VAR2 ,
VAR1 ,
VAR6
);
output VAR5 ;
output VAR9 ;
input VAR4 ;
input VAR8 ;
input VAR3;
input VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_clk_wiz_1_0/system_clk_wiz_1_0_clk_wiz.v | 7,973 | module MODULE1
( output VAR78,
output VAR56,
output VAR42,
output VAR86,
input VAR10,
output VAR75,
input VAR76
);
wire VAR27;
wire VAR47;
VAR67 VAR26
(.VAR25 (VAR27),
.VAR21 (VAR76));
wire VAR45;
wire VAR72;
wire VAR91;
wire VAR95;
wire VAR11;
wire VAR30;
wire VAR36;
wire [15:0] VAR58;
wire VAR22;
wire VAR71;
wire VAR... | apache-2.0 |
LorhanSohaky/UFSCar | 2017/lab_cd/aula7/Verilog/projeto.v | 2,205 | module MODULE5 ( VAR23, VAR12, MODULE3, VAR41);
input VAR23, VAR12;
output MODULE3, VAR41;
assign MODULE3 = VAR23 ^ VAR12;
assign VAR41 = VAR23 * VAR12;
endmodule
module MODULE4 ( VAR23, VAR12, VAR3, MODULE3, VAR41);
input VAR23, VAR12, VAR3;
output MODULE3, VAR41;
wire VAR19, VAR10, VAR15;
MODULE5 MODULE10 ( VAR23, VA... | mit |
DeadWitcher/amber-de0-nano | hw/vlog/amber25/a25_wishbone_buf.v | 6,831 | module MODULE1 (
input VAR12,
input VAR19,
input VAR11,
input [127:0] VAR10,
input [15:0] VAR24,
input [31:0] VAR29,
output [127:0] VAR14,
output VAR7,
output VAR21,
input VAR16,
output VAR5,
output [127:0] VAR8,
output [15:0] VAR20,
output [31:0] VAR25,
input [127:0] VAR13,
input VAR22
);
reg [1:0] VAR4 = 'd0;
reg [12... | lgpl-2.1 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_add_hc.v | 1,729 | module MODULE1(VAR6, VAR5, VAR8, VAR15, VAR1, VAR17, VAR9, VAR4, VAR11);
input VAR6, VAR5;
input VAR17, VAR4;
output VAR9, VAR11;
input [31:0] VAR8;
input [31:0] VAR15;
output [31:0] VAR1;
VAR13 VAR10(
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR15(VAR15),
.VAR1(VAR1),
.VAR17(VAR17),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtn/sky130_fd_sc_hs__dlrtn.pp.symbol.v | 1,381 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR6,
input VAR1 ,
input VAR5 ,
input VAR2
);
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/var15_multi.v | 1,261 | module MODULE1 (VAR21, VAR10, VAR1, VAR5, VAR14, VAR9, VAR13, VAR8, VAR12, VAR19, VAR15, VAR17, VAR2, VAR4, VAR6, valid);
input VAR21, VAR10, VAR1, VAR5, VAR14, VAR9, VAR13, VAR8, VAR12, VAR19, VAR15, VAR17, VAR2, VAR4, VAR6;
output valid;
wire [7:0] VAR16 = 8'd120;
wire [7:0] VAR20 = 8'd60;
wire [7:0] VAR18 = 8'd60;
w... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.behavioral.pp.v | 1,476 | module MODULE1( VAR3, VAR2, VAR5, VAR8, VAR7 );
input VAR2, VAR3;
inout VAR8, VAR7;
output VAR5;
VAR4 VAR6(.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7));
VAR4 VAR1(.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/lp_FIR_stub.v | 1,552 | module MODULE1(VAR6, VAR1, VAR4, VAR5, VAR2, VAR3)
;
input VAR6;
input VAR1;
output VAR4;
input [23:0]VAR5;
output VAR2;
output [23:0]VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai.blackbox.v | 1,403 | module MODULE1 (
VAR9 ,
VAR8,
VAR2,
VAR5,
VAR1,
VAR7
);
output VAR9 ;
input VAR8;
input VAR2;
input VAR5;
input VAR1;
input VAR7;
supply1 VAR3;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
jaechoon2/FPGA-Imaging-Library | LocalFilter/MeanFilter/HDL/MeanFilter.srcs/sources_1/new/MeanFilter.v | 5,712 | module MODULE1(
clk,
VAR15,
VAR2,
VAR16,
VAR14,
VAR1);
parameter[0 : 0] VAR5 = 0;
parameter[3 : 0] VAR17 = 3;
parameter[3: 0] VAR11 = 8;
parameter VAR10 = 3;
input clk;
input VAR15;
input VAR2;
input [VAR11 * VAR17 * VAR17 - 1 : 0] VAR16;
output VAR14;
output[VAR11 - 1 : 0] VAR1;
reg[VAR11 - 1 : 0] VAR4[0 : VAR6 - 1];
... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b_2.v | 2,300 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR9 ,
VAR11,
VAR3,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR11;
input VAR3;
input VAR4 ;
input VAR6 ;
VAR2 VAR10 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4.pp.blackbox.v | 1,347 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR6 ,
VAR1 ,
VAR4 ,
VAR7,
VAR2,
VAR9 ,
VAR5
);
output VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR9 ;
input VAR5 ;
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | smalltst/compdec/ModTxtMemW.v | 3,771 | module MODULE1(VAR19, reset,
VAR17, VAR27,
VAR5, VAR33,
VAR15, VAR3, VAR30, VAR22, VAR20);
input VAR19;
input reset;
input[13:0] VAR17;
output[127:0] VAR27;
input[15:0] VAR5;
output[63:0] VAR33;
input[31:0] VAR15;
inout[31:0] VAR3;
input VAR30;
input VAR22;
output VAR20;
reg VAR28; reg[31:0] VAR25; wire VAR2;
assign VA... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/st_top.v | 10,036 | module MODULE3
(
clk, reset, VAR32, VAR13, VAR9, VAR43, VAR18, VAR38, VAR36
);
parameter VAR24 = 32;
parameter VAR47 = 0;
parameter VAR4 = 32'h0000000000000000;
input clk;
input reset;
input VAR32;
input [VAR24-1:0] VAR13;
input VAR9;
output VAR43;
output [VAR24-1:0] VAR18;
output VAR38;
input VAR36;
reg [VAR24-1:0] VA... | mit |
spesialstyrker/boula | gen/PCIe/example_design/pcie_app_v6.v | 9,599 | module MODULE1#(
parameter VAR78 = 64,
parameter VAR77 = VAR78 / 8 )(
input VAR49,
input VAR55,
input VAR1,
input [5:0] VAR5,
input VAR26,
input VAR6,
output VAR63,
input VAR84,
output [VAR78-1:0] VAR31,
output [VAR77-1:0] VAR58,
output [3:0] VAR37,
output VAR18,
output VAR20,
output VAR62,
input [VAR78-1:0] VAR4,
inpu... | gpl-2.0 |
samyk/proxmark3 | fpga/fpga_hf.v | 9,471 | module MODULE1(
input VAR97, output VAR103, input VAR101, input VAR18,
input VAR69, input VAR53, input VAR19,
output VAR63, output VAR96,
output VAR60, output VAR58, output VAR25, output VAR4,
input [7:0] VAR29, output VAR86, output VAR47,
output VAR82, output VAR70, input VAR77, output VAR13,
input VAR45, input VAR22,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.blackbox.v | 1,208 | module MODULE1 (
VAR4 ,
VAR2,
VAR1,
VAR3
);
output VAR4 ;
input VAR2;
input VAR1;
input VAR3 ;
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_0_mem_intfc.v | 43,927 | module MODULE1 #
(
parameter VAR85 = 100,
parameter VAR156 = "135", parameter VAR246 = 64,
parameter VAR321 = "1T",
parameter VAR96 = "0", parameter VAR165 = 3, parameter VAR216 = 2, parameter VAR31 = "8", parameter VAR315 = "VAR25", parameter VAR258 = "VAR29", parameter VAR188 = 1, parameter VAR243 = 4'hc,
parameter V... | mit |
c4puter/bridge-hdl | modules/wb_conmax/wb_conmax_arb.v | 7,662 | module MODULE1(clk, rst, req, VAR2, VAR3);
input clk;
input rst;
input [7:0] req; output [2:0] VAR2; input VAR3;
parameter [2:0]
VAR9 = 3'h0,
VAR1 = 3'h1,
VAR10 = 3'h2,
VAR7 = 3'h3,
VAR8 = 3'h4,
VAR11 = 3'h5,
VAR6 = 3'h6,
VAR4 = 3'h7;
reg [2:0] state, VAR5;
assign VAR2 = state;
always@(posedge clk or posedge rst)
if(rs... | gpl-2.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/wasca_spi_0.v | 11,810 | module MODULE1 (
VAR28,
clk,
VAR47,
VAR55,
VAR48,
VAR1,
VAR19,
VAR56,
VAR10,
VAR61,
VAR45,
VAR30,
VAR63,
VAR22,
irq,
VAR13
)
;
output VAR10;
output VAR61;
output VAR45;
output [ 15: 0] VAR30;
output VAR63;
output VAR22;
output irq;
output VAR13;
input VAR28;
input clk;
input [ 15: 0] VAR47;
input [ 2: 0] VAR55;
input V... | gpl-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/new/SP32B1024.v | 3,202 | module MODULE1 #(
parameter VAR5 = 32, parameter VAR4 = 1024, parameter VAR13 = "" ) (
input [VAR12(VAR4-1)-1:0] VAR3, input [VAR5-1:0] VAR9, input VAR11, input VAR1, input VAR6, output [VAR5-1:0] VAR8 );
reg [VAR5-1:0] VAR2 [VAR4-1:0];
reg [VAR5-1:0] VAR10 = {VAR5{1'b0}};
generate
if (VAR13 != "") begin: VAR7 | mit |
everskar2013/PentiumX | Hardware/Code/vga_core.v | 2,758 | module MODULE1(
VAR3,
rst,
addr,
VAR7,
VAR1,
VAR8
);
input VAR3; input rst;
output [18: 0] addr; output VAR7; output VAR1, VAR8;
reg [9:0] VAR5 = 0; always @ (posedge VAR3 or posedge rst) begin
if (rst) begin
VAR5 <= 10'h0;
end else if (VAR5 == 10'd799) begin
VAR5 <= 10'h0;
end else begin
VAR5 <= VAR5 + 10'h1;
end
end
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4b/sky130_fd_sc_hdll__and4b.behavioral.pp.v | 2,008 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR16 ,
VAR11 ,
VAR12 ,
VAR10,
VAR1,
VAR9 ,
VAR17
);
output VAR6 ;
input VAR3 ;
input VAR16 ;
input VAR11 ;
input VAR12 ;
input VAR10;
input VAR1;
input VAR9 ;
input VAR17 ;
wire VAR7 ;
wire VAR4 ;
wire VAR13;
not VAR15 (VAR7 , VAR3 );
and VAR2 (VAR4 , VAR7, VAR16, VAR11, VAR12 );
VAR8 VA... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_SEQ_SRAM_TT_220101.v | 81,267 | module MODULE1 (VAR28, VAR24, VAR26, VAR13, VAR14);
output VAR28;
input VAR24, VAR26, VAR13, VAR14;
reg VAR18;
wire VAR20, VAR4, VAR9, VAR17;
wire VAR21, VAR2, VAR7;
wire VAR27, VAR11;
not (VAR21, VAR20);
not (VAR27, VAR4);
not (VAR7, VAR9);
VAR10 (VAR11, VAR17, VAR21, VAR27, VAR7);
VAR19 (VAR2, VAR18, VAR17, VAR21, VA... | bsd-3-clause |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_pl_status.v | 1,646 | module MODULE1 (VAR18,
VAR9,
VAR8,
VAR15,
VAR7);
parameter VAR12=5;
parameter VAR5=4;
parameter VAR19 = 0;
input VAR1 VAR18 [VAR12-1:0][VAR5-1:0];
input [VAR5-1:0] VAR9 [VAR12-1:0][VAR5-1:0]; input [VAR12-1:0][VAR5-1:0] VAR8; input [VAR12-1:0][VAR5-1:0] VAR15; output [VAR12-1:0][VAR5-1:0] VAR7;
logic [VAR12-1:0][VAR5-1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr.blackbox.v | 1,376 | module MODULE1 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR5 ;
supply0 VAR7 ;
supply1 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3/sky130_fd_sc_hs__nand3.behavioral.v | 1,711 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR4 ,
VAR2 ,
VAR1,
VAR8
);
output VAR6 ;
input VAR10 ;
input VAR4 ;
input VAR2 ;
input VAR1;
input VAR8;
wire VAR5 ;
wire VAR11;
nand VAR12 (VAR5 , VAR4, VAR10, VAR2 );
VAR7 VAR9 (VAR11, VAR5, VAR1, VAR8);
buf VAR3 (VAR6 , VAR11 );
endmodule | apache-2.0 |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/ethernet_parser_32bit.v | 3,763 | module MODULE1
parameter VAR3=VAR23/8,
parameter VAR21 = 3,
parameter VAR16 = 2
)
( input [VAR23-1:0] VAR2,
input [VAR3-1:0] VAR9,
input VAR10,
output reg [47:0] VAR8,
output reg [47:0] VAR12,
output reg [15:0] VAR7,
output reg VAR1,
output reg [VAR21-1:0] VAR18,
input reset,
input clk
);
parameter VAR22 = 5;
parameter... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfstp/sky130_fd_sc_hvl__dfstp.symbol.v | 1,391 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR8,
input VAR5
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3.behavioral.pp.v | 1,742 | module MODULE1 (
VAR5,
VAR9,
VAR8 ,
VAR1 ,
VAR2 ,
VAR3
);
input VAR5;
input VAR9;
output VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
wire VAR11 ;
wire VAR7;
nor VAR4 (VAR11 , VAR3, VAR1, VAR2 );
VAR10 VAR6 (VAR7, VAR11, VAR5, VAR9);
buf VAR12 (VAR8 , VAR7 );
endmodule | apache-2.0 |
zYeoman/32BIT-MIPS-CPU | pipeline/InstructionMem.v | 5,624 | module MODULE1 (
input [31:0] addr,
output reg [31:0] VAR1
);
parameter VAR2 = 128;
parameter VAR3 = 7;
always @ (*)
case (addr[VAR3+1:2])
7'd0: VAR1 = 32'h08000003;
7'd1: VAR1 = 32'h0800004b;
7'd2: VAR1 = 32'h08000002;
7'd3: VAR1 = 32'h20080014;
7'd4: VAR1 = 32'h01000008;
7'd5: VAR1 = 32'h3c104000;
7'd6: VAR1 = 32'h20... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/example_design/rtl/traffic_gen/data_prbs_gen.v | 4,708 | module MODULE1 #
(
parameter VAR7 = 100,
parameter VAR2 = "VAR9",
parameter VAR4 = 32, parameter VAR6 = 32
)
(
input VAR13,
input VAR3,
input VAR11,
input VAR5, input [VAR4 - 1:0] VAR1,
output [VAR4 - 1:0] VAR10 );
reg [VAR4 - 1 :0] VAR12;
reg [VAR4 :1] VAR14;
integer VAR8;
always @ (posedge VAR13)
begin
if (VAR5 && VA... | lgpl-3.0 |
anderson1008/NOCulator | hring/hw/buffered/src/c_rr_arbiter.v | 4,019 | module MODULE1
(clk, reset, VAR15, req, VAR8);
parameter VAR2 = 32;
parameter VAR17 = VAR4;
input clk;
input reset;
input VAR15;
input [0:VAR2-1] req;
output [0:VAR2-1] VAR8;
wire [0:VAR2-1] VAR8;
generate
if(VAR2 > 1)
begin
wire [0:VAR2-1] VAR19;
VAR7
VAR11
(.VAR3(req),
.VAR14(VAR19));
wire [0:VAR2-2] VAR9;
wire [0:VA... | mit |
SiLab-Bonn/basil | basil/firmware/modules/timestamp/timestamp_core.v | 5,310 | module MODULE1 #(
parameter VAR14 = 16,
parameter VAR33 = 4'b0001
) (
input wire VAR55,
input wire VAR17,
input wire VAR39,
input wire [63:0] VAR59,
output wire [63:0] VAR72,
input wire VAR57,
output wire VAR75,
output wire [31:0] VAR2,
input wire VAR66,
input wire [VAR14-1:0] VAR20,
input wire [7:0] VAR13,
output reg ... | bsd-3-clause |
alexforencich/verilog-dsp | rtl/cic_decimator.v | 4,819 | module MODULE1 #(
parameter VAR12 = 16,
parameter VAR20 = 2,
parameter VAR1 = 1,
parameter VAR7 = 2,
parameter VAR15 = VAR12+VAR5((VAR20*VAR1)**VAR7)
)
(
input wire clk,
input wire rst,
input wire [VAR12-1:0] VAR11,
input wire VAR6,
output wire VAR22,
output wire [VAR15-1:0] VAR21,
output wire VAR16,
input wire VAR3,
i... | mit |
toomij/DE2Labs | Lab3/lab3_part2.v | 1,346 | module MODULE1 (VAR8,VAR4);
input [17:0] VAR8;
output [17:0] VAR4;
MODULE2(VAR8[1],VAR8[0],VAR4[0]);
endmodule
module MODULE2 (VAR7, VAR1, VAR5);
input VAR7, VAR1;
output VAR5;
wire VAR3, VAR6, VAR9, VAR2 ;
assign VAR6 = ((~VAR1 & ~VAR7) | (~VAR1 & VAR7) | (VAR1 & ~VAR7));
assign VAR3 = ((~VAR1 & ~VAR7) | (VAR1 & ~VAR7... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai.behavioral.pp.v | 2,065 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR13 ,
VAR6 ,
VAR5 ,
VAR11 ,
VAR17,
VAR18,
VAR7 ,
VAR9
);
output VAR10 ;
input VAR2 ;
input VAR13 ;
input VAR6 ;
input VAR5 ;
input VAR11 ;
input VAR17;
input VAR18;
input VAR7 ;
input VAR9 ;
wire VAR15 ;
wire VAR16 ;
wire VAR12;
or VAR1 (VAR15 , VAR13, VAR2, VAR6 );
nand VAR8 (VAR16 , ... | apache-2.0 |
manili/Pipelined_6502 | Core.v | 7,469 | module MODULE1(
VAR13,
VAR50,
VAR133,
VAR73,
VAR116,
VAR120,
VAR122,
VAR124,
VAR38,
VAR125,
VAR118,
VAR8,
VAR36,
VAR9,
VAR86,
VAR89,
VAR49,
VAR15,
VAR83
,VAR115,
VAR44,
VAR74,
VAR12,
VAR130,
VAR3,
VAR10,
VAR48,
VAR106
);
input wire VAR13;
input wire VAR50;
input wire VAR133;
input wire VAR73;
input wire VAR116;
input w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a.behavioral.pp.v | 2,199 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR5 ,
VAR3 ,
VAR12 ,
VAR1 ,
VAR17,
VAR13,
VAR19 ,
VAR2
);
output VAR9 ;
input VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR12 ;
input VAR1 ;
input VAR17;
input VAR13;
input VAR19 ;
input VAR2 ;
wire VAR7 ;
wire VAR20 ;
wire VAR14 ;
wire VAR6;
or VAR16 (VAR7 , VAR12, VAR3 );
or VAR8 (VAR20... | apache-2.0 |
bgelb/digilite_zl | rtl/zl_sync_invert_randomizer.v | 4,178 | module MODULE1
(
input clk,
input VAR1,
input VAR27,
output reg VAR20,
input [7:0] VAR6,
output reg VAR23,
input VAR15,
output reg [7:0] VAR17
);
localparam VAR25 = 0;
localparam VAR2 = 1;
localparam VAR5 = 2;
localparam VAR26 = 8'h47;
localparam VAR28 = 188;
localparam VAR4 = 8;
localparam VAR14 = 8;
localparam VAR30 ... | bsd-2-clause |
cr88192/bgbtech_bjx1core | srvcore/FpuFp64B.v | 4,890 | module MODULE1(
clk,
VAR15,
VAR13,
VAR49,
VAR12,
VAR5,
VAR47,
VAR54,
VAR32
);
input clk;
input VAR15; input[3:0] VAR13;
input[63:0] VAR49;
input[63:0] VAR12;
input[63:0] VAR5;
output[63:0] VAR47;
input[3:0] VAR54;
output[3:0] VAR32;
parameter[3:0] VAR22 = 4'h00;
parameter[3:0] VAR1 = 4'h01; parameter[3:0] VAR60 = 4'h02... | mit |
alexforencich/verilog-ethernet | rtl/axis_baser_tx_64.v | 27,354 | module MODULE1 #
(
parameter VAR14 = 64,
parameter VAR5 = (VAR14/8),
parameter VAR18 = 2,
parameter VAR1 = 1,
parameter VAR10 = 1,
parameter VAR29 = 64,
parameter VAR4 = 4'h6,
parameter VAR23 = 16'h6666,
parameter VAR22 = 0,
parameter VAR3 = 96,
parameter VAR13 = VAR22,
parameter VAR28 = 16,
parameter VAR31 = (VAR13 ? ... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/image_filter_Mat2AXIvideo.v | 18,854 | module MODULE1 (
VAR47,
VAR56,
VAR34,
VAR55,
VAR15,
VAR9,
VAR61,
VAR17,
VAR29,
VAR13,
VAR79,
VAR28,
VAR8,
VAR84,
VAR83,
VAR6,
VAR7,
VAR37,
VAR4,
VAR80,
VAR39,
VAR20,
VAR75,
VAR2,
VAR76,
VAR30,
VAR68
);
parameter VAR14 = 1'b1;
parameter VAR51 = 1'b0;
parameter VAR35 = 4'b1;
parameter VAR57 = 4'b10;
parameter VAR63 = 4'b... | gpl-3.0 |
jayrandez/Processor | method_finder.v | 3,583 | module MODULE1(
input wire VAR24,
input wire VAR26,
input wire reset,
output reg[31:0] VAR27 = 0,
output reg[31:0] VAR17 = 0,
input wire[31:0] VAR22,
output reg VAR10 = 0,
output reg VAR25 = 0,
output reg[4:0] VAR6 = 0,
input wire[31:0] VAR28,
output reg VAR15 = 0,
output reg[31:0] VAR5 = 0,
output reg VAR7 = 0,
output... | apache-2.0 |
Koheron/zynq-sdk | fpga/cores/tlast_gen_v1_0/tlast_gen.v | 2,057 | module MODULE1
parameter VAR10 = 8,
parameter VAR2 = 1024*1024
)
(
input VAR12,
input VAR9,
input VAR8,
output VAR11,
input [VAR10-1:0] VAR13,
output VAR14,
input VAR5,
output VAR1,
output [VAR10-1:0] VAR6
);
wire VAR4;
reg [VAR7(VAR2):0] VAR3 = 0;
assign VAR11 = VAR5;
assign VAR14 = VAR8;
assign VAR6 = VAR13;
assign V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fill/sky130_fd_sc_hd__fill.symbol.v | 1,186 | module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ncos/Xilinx-Verilog | INTERFACES/src/SPI/spi.v | 3,005 | module MODULE1#
(
parameter integer VAR26 = 15, parameter integer VAR37 = 100 )
(
output reg [127:0] VAR56 = " ",
output reg [127:0] VAR42 = " ",
output reg [127:0] VAR41 = " ",
output reg [127:0] VAR50 = " ",
input wire VAR19,
input wire VAR59,
input wire [7:0] VAR33,
input wire VAR1,
input wire VAR38,
output wire VAR... | mit |
drom/elastic | rtl/eb_fifo_ctrl.v | 1,599 | module MODULE1 #(
parameter VAR6 = 4'd15,
parameter VAR12 = 3
) (
input VAR3,
output VAR1,
output reg VAR7,
input VAR10,
output reg [VAR12 : 0] VAR8,
output wire [VAR12 : 0] VAR2,
output VAR9, VAR5,
input clk, VAR4
);
reg [VAR12 : 0] VAR11;
reg [VAR12 : 0] VAR13;
assign VAR1 = !(VAR11 == VAR6);
assign VAR5 = 1;
assign ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp.symbol.v | 1,502 | module MODULE1 (
input VAR3 ,
output VAR9 ,
output VAR5 ,
input VAR6,
input VAR4 ,
input VAR1 ,
input VAR8
);
supply1 VAR7;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4/sky130_fd_sc_hs__nand4.behavioral.pp.v | 1,744 | module MODULE1 (
VAR7,
VAR13,
VAR10 ,
VAR4 ,
VAR11 ,
VAR6 ,
VAR9
);
input VAR7;
input VAR13;
output VAR10 ;
input VAR4 ;
input VAR11 ;
input VAR6 ;
input VAR9 ;
wire VAR3 ;
wire VAR5;
nand VAR12 (VAR3 , VAR9, VAR6, VAR11, VAR4 );
VAR1 VAR2 (VAR5, VAR3, VAR7, VAR13);
buf VAR8 (VAR10 , VAR5 );
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/io/uart/rtl/uart_ctrl.v | 3,786 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR33, input wire VAR2, input wire VAR17, input wire [VAR31] addr, input wire [VAR19] VAR28, output reg [VAR19] VAR5, output reg VAR12,
output reg VAR26, output reg VAR27,
input wire VAR16, input wire VAR23, input wire [VAR22] VAR13, input wire VAR32, input ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv.pp.blackbox.v | 1,342 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR5,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR5;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/Oper_Start_In_syn.v | 41,643 | module MODULE9 ( clk, rst, VAR148, VAR14, VAR52 );
input [31:0] VAR14;
output [31:0] VAR52;
input clk, rst, VAR148;
wire VAR348, VAR181, VAR143, VAR73, VAR183, VAR7, VAR259, VAR227, VAR91, VAR172, VAR333, VAR158, VAR104, VAR248, VAR364, VAR313,
VAR84, VAR284, VAR162, VAR319, VAR44, VAR185, VAR95, VAR328, VAR356, VAR265... | gpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/uart16550/uart_debug_if.v | 6,190 | module MODULE1 (
VAR6,
VAR9, VAR11, VAR5, VAR2, VAR4, VAR3, VAR15,
VAR1, VAR8, VAR13, VAR10, VAR7
) ;
input [VAR12-1:0] VAR9;
output [31:0] VAR6;
input [3:0] VAR11;
input [3:0] VAR5;
input [1:0] VAR2; input [4:0] VAR4;
input [7:0] VAR3;
input [7:0] VAR15;
input [7:0] VAR1;
input [VAR14-1:0] VAR8;
input [VAR14-1:0] VAR1... | apache-2.0 |
jotego/jt12 | hdl/mixer/jt12_genmix.v | 5,408 | module MODULE1(
input rst,
input clk,
input signed [15:0] VAR8,
input signed [15:0] VAR24,
input signed [10:0] VAR35,
input VAR27, input VAR39, output signed [15:0] VAR6,
output signed [15:0] VAR43
);
reg [5:0] VAR19;
reg [2:0] VAR12, VAR22;
reg [1:0] VAR1;
always @(posedge clk)
if( rst ) begin
VAR19 <= 6'd0;
VAR12 <= ... | gpl-3.0 |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/new/Snake.v | 4,508 | module MODULE1
(
input clk,
input rst,
input[15:0] VAR37,
input VAR1,
input VAR20,
input VAR35,
input VAR31,
output reg [1:0]VAR19,
input [9:0]VAR3,
input [9:0]VAR14,
output [5:0]VAR25,
output [5:0]VAR4,
input VAR8,
input [1:0]VAR13,
output reg [6:0]VAR34,
output reg VAR18, output reg VAR2, input VAR24 );
localparam VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai.pp.symbol.v | 1,399 | module MODULE1 (
input VAR3 ,
input VAR2 ,
input VAR6,
output VAR8 ,
input VAR5 ,
input VAR1,
input VAR4,
input VAR7
);
endmodule | apache-2.0 |
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