repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.symbol.v | 1,269 | module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/io_mux.v | 3,132 | module MODULE1 (
VAR2,
VAR4,
VAR11,
VAR3,
VAR7,
VAR8,
VAR14,
VAR13,
VAR10,
sel
);
parameter VAR6 = 8;
output [VAR6-1:0] VAR2;
input [VAR6-1:0] VAR4;
input [VAR6-1:0] VAR11;
output [VAR6-1:0] VAR3;
input [VAR6-1:0] VAR7;
input [VAR6-1:0] VAR8;
input [VAR6-1:0] VAR14;
output [VAR6-1:0] VAR13;
output [VAR6-1:0] VAR10;
inp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapmet1/sky130_fd_sc_hs__tapmet1.functional.v | 1,144 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/UART/peripheral_uart_2.v | 2,137 | module MODULE1 (
input clk,
input rst,
input [15:0] din, input VAR14, input [3:0] addr, input rd, input wr,
output reg [15:0] dout,
input VAR5,
output VAR11, output VAR4, output VAR10 );
reg [3:0] VAR13;
reg [10:0] VAR7 = 11'b1000000011 ; wire [10:0] VAR9;
localparam VAR12 = 28'd100000000; localparam VAR8 = 28'd115200;... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/example_design/rtl/traffic_gen/tg_prbs_gen.v | 6,577 | module MODULE1 #
(
parameter VAR21 = 64, parameter VAR3 = 32'h00000000,
parameter VAR17 = "VAR2",
parameter VAR5 = 0,
parameter [VAR21-1:0] VAR7= 32'h80200003
)
(
input VAR18,
input VAR4,
input rst,
input [VAR21-1:0] VAR26,
output VAR13,
output [VAR21-1:0] VAR19, output reg [3:0] VAR25,
output [31:0] VAR22
);
wire VAR6... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregrbp/sky130_fd_sc_lp__sregrbp.blackbox.v | 1,381 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR10 ,
VAR3 ,
VAR4
);
output VAR11 ;
output VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR10 ;
input VAR3 ;
input VAR4;
supply1 VAR5;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch.functional.v | 1,576 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR9
);
output VAR7 ;
input VAR3 ;
input VAR9;
wire VAR8 ;
wire VAR4;
wire VAR10 ;
VAR2 VAR1 VAR5 (VAR8 , VAR3, VAR9 );
buf VAR6 (VAR7 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2_2.v | 2,091 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3 ,
VAR9,
VAR7,
VAR4 ,
VAR5
);
output VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR9;
input VAR7;
input VAR4 ;
input VAR5 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR2,
VAR1,
VAR3
);
output VAR2;
... | apache-2.0 |
liqimai/Assignment1-Calculator | Floating-Number-Division/divider.v | 1,861 | module MODULE1(VAR4,VAR5,VAR7);
input wire [31:0] VAR4;
input wire [31:0] VAR5;
output reg [31:0] VAR7;
reg [47:0]VAR8;
reg [23:0]VAR10;
reg [47:0]VAR11;
reg [47:0] VAR1;
reg [8:0]VAR9;
reg [8:0]VAR3;
reg VAR2;
integer VAR6; always @(VAR4 or VAR5) begin
VAR7=0;
VAR1=0;
VAR8={1,VAR4[22:0],24'b0};
VAR10={1,VAR5[22:0]};
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi.symbol.v | 1,410 | module MODULE1 (
input VAR3,
input VAR5,
input VAR4,
input VAR7,
input VAR9,
output VAR1
);
supply1 VAR10;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/freedm_bus_slave/fb_slave_counters.v | 6,963 | module MODULE1 (VAR14, VAR21, VAR15, VAR40, VAR33, VAR19, VAR12,
VAR46, VAR10, VAR24, VAR51, VAR5, VAR22, VAR7,
VAR45, VAR50, VAR36, VAR31, VAR8,
VAR25, VAR4, VAR42, VAR47, VAR48, VAR44, VAR2
);
input VAR14; input VAR21;
input VAR15; input VAR40;
input VAR33;
input VAR19;
input VAR12;
input VAR46; input VAR10; input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.v | 2,474 | module MODULE2 (
VAR11 ,
VAR4,
VAR10,
VAR9 ,
VAR2 ,
VAR7,
VAR8,
VAR3 ,
VAR6
);
output VAR11 ;
input VAR4;
input VAR10;
input VAR9 ;
input VAR2 ;
input VAR7;
input VAR8;
input VAR3 ;
input VAR6 ;
VAR5 VAR1 (
.VAR11(VAR11),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6... | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/ddr_axi.v | 11,058 | module MODULE1 (
inout [15:0] VAR22,
inout [1:0] VAR4,
inout [1:0] VAR59,
output [12:0] VAR62,
output [2:0] VAR52,
output VAR27,
output VAR30,
output VAR8,
output [0:0] VAR29,
output [0:0] VAR42,
output [0:0] VAR6,
output [0:0] VAR21,
output [1:0] VAR12,
output [0:0] VAR49,
input VAR58,
output VAR36,
output VAR3,
outpu... | mit |
ptracton/UART_ECHO | behavioral/wb_master/wb_mast_model.v | 11,862 | module MODULE1(clk, rst, VAR1, din, dout, VAR5, VAR4, sel, VAR2, ack, VAR3, VAR8);
input clk, rst;
output [31:0] VAR1;
input [31:0] din;
output [31:0] dout;
output VAR5, VAR4;
output [3:0] sel;
output VAR2;
input ack, VAR3, VAR8;
parameter VAR6 = 4096;
reg [31:0] VAR1;
reg [31:0] dout;
reg VAR5, VAR4;
reg [3:0] sel;
re... | mit |
andres-erbsen/sha3-verilog-mirror | low_throughput_core/rtl/keccak.v | 3,140 | module MODULE1(clk, reset, in, VAR8, VAR12, VAR25, VAR5, out, VAR15);
input clk, reset;
input [31:0] in;
input VAR8, VAR12;
input [1:0] VAR25;
output VAR5;
output [511:0] out;
output reg VAR15;
reg state;
wire [575:0] VAR7,
VAR22;
wire VAR10;
wire VAR21;
wire [1599:0] VAR1;
wire VAR2;
wire [511:0] VAR17;
reg [22:0] VAR... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/fake_uart.v | 2,679 | module MODULE1 (
input VAR16,
input VAR28,
input [5:0] VAR23, input VAR1,
input VAR25,
input [31:0] VAR26,
output [31:0] VAR17,
input VAR15,
output VAR3,
input VAR18,
output VAR6 );
reg [5:0] VAR14;
reg [7:0] VAR8;
reg rd, wr;
reg reset = 0;
assign VAR6 = reset;
VAR21 VAR24(
.VAR9(VAR15),
.VAR19(VAR3),
.VAR4(VAR18),
.V... | gpl-3.0 |
calee0219/Course | DLAB/Lab05/01_RTL/SORT.v | 6,386 | module MODULE1(
clk,
VAR2,
VAR17,
VAR4,
in,
VAR14,
VAR19,
VAR5,
out
);
input clk;
input VAR2;
input VAR14;
input VAR17, VAR4;
input [4:0] in;
input [1:0] VAR19;
output reg VAR5;
output reg [4:0] out;
parameter VAR11=0;
parameter VAR13=1;
parameter VAR22=2;
integer VAR6;
reg VAR16;
reg [1:0] VAR23, VAR15;
reg [3:0] VAR2... | mit |
ShepardSiegel/ocpi | libsrc/hdl/bsv/SyncPulse.v | 3,747 | module MODULE1(
VAR10,
VAR5,
VAR3,
VAR13,
VAR1
);
input VAR10 ;
input VAR5 ;
input VAR13 ;
input VAR3 ;
output VAR1 ;
reg VAR6;
reg VAR2, VAR9;
reg VAR8;
assign VAR1 = VAR9 != VAR8 ;
always @(posedge VAR10 or VAR4 VAR5)
begin
if (VAR5 == VAR7)
VAR6 <= VAR11 1'b0 ;
end
else
begin
if ( VAR13 )
begin
VAR6 <= VAR11 ! VAR6 ... | lgpl-3.0 |
kyzhai/NUNY | src/hardware/bomb.v | 6,356 | module MODULE1 (
address,
VAR35,
VAR2);
input [11:0] address;
input VAR35;
output [11:0] VAR2;
tri1 VAR35;
wire [11:0] VAR11;
wire [11:0] VAR2 = VAR11[11:0];
VAR37 VAR33 (
.VAR38 (address),
.VAR45 (VAR35),
.VAR30 (VAR11),
.VAR26 (1'b0),
.VAR17 (1'b0),
.VAR32 (1'b1),
.VAR6 (1'b0),
.VAR39 (1'b0),
.VAR50 (1'b1),
.VAR52 (1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1.behavioral.v | 1,413 | module MODULE1 (
VAR7,
VAR8
);
output VAR7;
input VAR8;
supply1 VAR6;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR9 ;
wire VAR3;
buf VAR5 (VAR3, VAR8 );
buf VAR2 (VAR7 , VAR3 );
endmodule | apache-2.0 |
chadharrington/all_spark_cube | fpga/rom.v | 3,414 | module MODULE1
(
input clk,
input VAR1,
input [5:0] addr,
output VAR3,
output VAR2,
output VAR4,
output VAR5,
output VAR7
);
reg [4:0] VAR8, VAR6;
always @(posedge clk, negedge VAR1)
begin
if (!VAR1)
begin
VAR6 <= 5'b00010;
end
else
begin
VAR6 <= VAR8;
end
end
always @*
begin
case (addr)
6'd00: VAR8 = 5'b10000;
6'd01: ... | mit |
colinww/spi-core-generator | example/results_verilog/spi_map.v | 42,006 | module MODULE1(
VAR21, VAR138, VAR84, VAR113, VAR116,
VAR65, VAR82, VAR64, VAR72,
VAR27, VAR112, VAR25, VAR199,
VAR184, VAR105,
VAR119, VAR189,
VAR179, VAR104, VAR223,
VAR196, VAR83, VAR226,
VAR239, VAR186,
VAR90, VAR128, VAR212,
VAR68, VAR267,
VAR273, VAR263, VAR136, VAR10,
VAR264, VAR8, VAR126,
VAR227, VAR29, VAR269,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o.symbol.v | 1,424 | module MODULE1 (
input VAR4,
input VAR2,
input VAR10,
input VAR1,
input VAR7,
output VAR5
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_project/ram_32_128x8_dp_be/ram_32_128x8_dp_be.v | 10,639 | module MODULE1 (
VAR27,
VAR8,
VAR31,
VAR21,
VAR29,
VAR30,
VAR38,
VAR19,
VAR18,
VAR17,
VAR37);
input [2:0] VAR27;
input [4:0] VAR8;
input [3:0] VAR31;
input VAR21;
input VAR29;
input [127:0] VAR30;
input [31:0] VAR38;
input VAR19;
input VAR18;
output [127:0] VAR17;
output [31:0] VAR37;
wire [127:0] VAR15;
wire [31:0] VA... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/cache/Cache_DataRAM.v | 10,686 | module MODULE1 (
VAR62,
VAR38,
VAR13,
VAR4,
VAR31,
VAR17,
VAR57,
VAR55,
VAR40);
input [10:0] VAR62;
input [10:0] VAR38;
input VAR13;
input [17:0] VAR4;
input [17:0] VAR31;
input VAR17;
input VAR57;
output [17:0] VAR55;
output [17:0] VAR40;
tri1 VAR13;
tri0 VAR17;
tri0 VAR57;
wire [17:0] VAR51;
wire [17:0] VAR14;
wire [... | gpl-3.0 |
subailong/miaow | src/verilog/rtl/vgpr/reg_1024x32b_3r_1w.v | 10,810 | module MODULE1 (
VAR50, VAR13, VAR8,
VAR21, VAR25, VAR26, VAR28, VAR24, VAR54, clk
);
output [127:0] VAR50;
output [31:0] VAR13;
output [31:0] VAR8;
input [9:0] VAR21;
input [9:0] VAR25;
input [9:0] VAR26;
input [9:0] VAR28;
input [3:0] VAR24;
input [127:0] VAR54;
input clk;
reg [127:0] VAR50;
reg [31:0] VAR13;
reg [31... | bsd-3-clause |
alexforencich/xfcp | lib/eth/rtl/oddr.v | 3,858 | module MODULE1 #
(
parameter VAR26 = "VAR12",
parameter VAR5 = "VAR33",
parameter VAR27 = 1
)
(
input wire clk,
input wire [VAR27-1:0] VAR41,
input wire [VAR27-1:0] VAR36,
output wire [VAR27-1:0] VAR30
);
genvar VAR28;
generate
if (VAR26 == "VAR45") begin
for (VAR28 = 0; VAR28 < VAR27; VAR28 = VAR28 + 1) begin : MODULE... | mit |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,861 | module MODULE1 (
clk,
reset,
VAR1,
VAR2,
VAR7,
VAR15,
VAR16,
VAR4
);
parameter VAR6 = 1;
parameter VAR11 = 8;
parameter VAR12 = 1;
localparam VAR9 = VAR6 * VAR11;
input clk;
input reset;
output VAR1;
input VAR2;
input [VAR9-1:0] VAR7;
input VAR15;
output VAR16;
output [VAR9-1:0] VAR4;
reg VAR10;
reg VAR3;
reg [VAR9-1:0... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_sync.v | 27,176 | module MODULE1 #
(
parameter VAR56 = "VAR87", parameter VAR104 = "VAR13", parameter VAR84 = "VAR26", parameter VAR43 = 0, parameter VAR39 = 0, parameter VAR88 = 1, parameter VAR57 = 3, parameter VAR107 = 0, parameter VAR20 = 0
)
(
input VAR80,
input VAR97,
input VAR62,
input VAR6,
input VAR105,
input VAR85,
input VAR66... | gpl-3.0 |
nyaxt/dmix | ise/tepla/ipcore_dir/nkmd_ddr3/example_design/rtl/mcb_controller/iodrp_controller.v | 11,430 | module MODULE1(
input wire [7:0] VAR13,
input wire [7:0] VAR8,
output reg [7:0] VAR11,
input wire VAR33,
input wire VAR41,
output wire VAR25,
input wire VAR46,
input wire VAR29,
input wire VAR20,
output reg VAR35,
output wire VAR49, output reg VAR22,
output reg VAR19,
input wire VAR12 );
reg [7:0] VAR18; reg [7:0] VAR4... | mit |
prernaa/CPUVerilog | control_exe.v | 8,209 | module MODULE1(
clk,
rst,
VAR14, VAR22, flag, VAR13, VAR5, VAR20, VAR21, VAR1, VAR25, VAR19, VAR29, VAR11, VAR8, VAR16, );
input clk;
input rst;
input [15:0] VAR14;
input [15:0] VAR22;
input VAR5;
input VAR20;
input VAR21;
input VAR1;
input [2:0] flag;
input [3:0] VAR13;
output VAR25;
reg VAR10;
reg VAR27;
output VAR19... | mit |
SymbiFlow/fpga-tool-perf | src/blinky/blinky.v | 1,165 | module MODULE1 (input VAR6, output [11:0] VAR1);
wire clk;
VAR4 VAR7 (
.VAR3(VAR6),
.VAR9(clk)
);
reg VAR8;
reg [22:0] VAR2;
always @(posedge clk) {VAR8, VAR2} <= VAR2 + 1'b1;
reg [5:0] VAR5 = 4'b0000;
always @(posedge clk) begin
if (VAR8)
VAR5 <= VAR5 + 1'b1;
end
wire [11:0] VAR10 = VAR5[3:0] << (4 * VAR5[5:4]);
assig... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf.behavioral.v | 1,327 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
supply1 VAR3;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR5;
buf VAR2 (VAR5, VAR1 );
buf VAR9 (VAR4 , VAR5 );
endmodule | apache-2.0 |
kylemsguy/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-B/salsaengine.v | 21,171 | module MODULE1 (VAR22, reset, din, dout, VAR9, VAR78, VAR97, VAR58 );
input VAR22;
input reset; input din;
input VAR9;
input VAR78; output VAR97;
output reg VAR58 = 1'b0;
output dout;
parameter VAR21 = 12;
parameter VAR105 = 8;
function integer VAR91; input integer VAR82;
begin
VAR82 = VAR82-1;
for (VAR91=0; VAR82>0; V... | gpl-3.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_top.v | 66,308 | module MODULE1 #
(
parameter VAR341 = 100, parameter VAR241 = 135, parameter VAR388 = "0", parameter VAR9 = 3, parameter VAR272 = "8", parameter VAR312 = "VAR239", parameter VAR159 = "VAR105", parameter VAR400 = 1, parameter VAR316 = 5,
parameter VAR25 = 12, parameter VAR324 = 1, parameter VAR357 = 1, parameter VAR65 =... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o.pp.symbol.v | 1,368 | module MODULE1 (
input VAR5 ,
input VAR6 ,
input VAR1 ,
input VAR7 ,
input VAR2 ,
output VAR4 ,
input VAR3,
input VAR8
);
endmodule | apache-2.0 |
theapi/de1-soc | vga/ip/pll/vga_pll.v | 17,278 | module MODULE1 (
input wire VAR6, input wire rst, output wire VAR2, output wire VAR7, output wire VAR8, output wire VAR1 );
VAR3 VAR5 (
.VAR6 (VAR6), .rst (rst), .VAR2 (VAR2), .VAR7 (VAR7), .VAR8 (VAR8), .VAR1 (VAR1), .VAR4 () );
endmodule | mit |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_ddr_phy_init.v | 195,065 | module MODULE1 #
(
parameter VAR165 = 100,
parameter VAR312 = 4, parameter VAR132 = 3000, parameter VAR267 = 0, parameter VAR48 = 8, parameter VAR224 = 2,
parameter VAR254 = "VAR157", parameter VAR257 = 10,
parameter VAR242 = 1, parameter VAR280 = 64,
parameter VAR220 = 8,
parameter VAR335 = 3, parameter VAR130 = 14,
p... | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_ic_local_mem_router_terminator.v | 2,568 | module MODULE1 #(
parameter integer VAR21 = 256
)
(
input logic VAR9,
input logic VAR15,
input logic VAR2,
input logic VAR19,
input logic VAR16,
output logic VAR10,
output logic VAR20,
output logic VAR23,
output logic [VAR21-1:0] VAR3,
output logic VAR5
);
reg VAR18;
reg VAR6;
assign VAR10 = 1'b0;
assign VAR20 = 1'b0;
... | mit |
yyang29/MIPS | design/mips_core.v | 9,545 | module MODULE1(
VAR46, VAR40, VAR60, VAR25, VAR33,
clk, VAR18, VAR57, VAR68, VAR61, VAR55
);
parameter VAR59 = 32'h00400000;
input clk, VAR18, VAR57;
output [29:0] VAR46;
output [29:0] VAR40;
input [31:0] VAR68, VAR61;
output [31:0] VAR60;
output [3:0] VAR25;
output VAR33;
input VAR55;
assign VAR40 = 0;
assign VAR60 = ... | gpl-2.0 |
dailypips/miaow | src/verilog/rtl/common/encoder.v | 1,210 | module MODULE1(in,out);
input [39:0] in;
output [5:0] out;
assign out = (in[0]==1'b1)?6'd0:
(in[1]==1'b1)?6'd1:
(in[2]==1'b1)?6'd2:
(in[3]==1'b1)?6'd3:
(in[4]==1'b1)?6'd4:
(in[5]==1'b1)?6'd5:
(in[6]==1'b1)?6'd6:
(in[7]==1'b1)?6'd7:
(in[8]==1'b1)?6'd8:
(in[9]==1'b1)?6'd9:
(in[10]==1'b1)?6'd10:
(in[11]==1'b1)?6'd11:
(in[... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn.behavioral.v | 1,314 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR4;
supply1 VAR7;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
notif0 VAR8 (VAR3 , VAR2, VAR4 );
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPhy_Toggle_Physical_Input_DDR100.v | 11,387 | module MODULE1
(
parameter VAR90 = 13,
parameter VAR78 = 0
)
(
VAR83 ,
VAR101 ,
VAR4 ,
VAR37 ,
VAR38 ,
VAR53 ,
VAR40 ,
VAR13 ,
VAR14 ,
VAR22 ,
VAR104,
VAR39 ,
VAR86 ,
VAR15 ,
VAR49
);
input VAR83 ;
input VAR101 ;
input VAR4 ;
input VAR37 ;
input VAR38 ;
input VAR53 ;
input [2:0] VAR40 ; output VAR13 ;
output [31:0] VAR... | gpl-3.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/l2warm.v | 50,651 | module MODULE1();
begin | gpl-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_nand_nto1.v | 2,273 | module MODULE1
(VAR7, VAR1);
parameter VAR9 = 2;
parameter VAR6 = 1;
input [0:VAR6*VAR9-1] VAR7;
output [0:VAR6-1] VAR1;
wire [0:VAR6-1] VAR1;
generate
genvar VAR5;
for(VAR5 = 0; VAR5 < VAR6; VAR5 = VAR5 + 1)
begin:VAR2
wire [0:VAR9-1] VAR8;
genvar VAR4;
for(VAR4 = 0; VAR4 < VAR9; VAR4 = VAR4 + 1)
begin:VAR3
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31oi/sky130_fd_sc_ms__a31oi.blackbox.v | 1,362 | module MODULE1 (
VAR9 ,
VAR8,
VAR1,
VAR5,
VAR4
);
output VAR9 ;
input VAR8;
input VAR1;
input VAR5;
input VAR4;
supply1 VAR2;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probec_p/sky130_fd_sc_hvl__probec_p.behavioral.pp.v | 1,801 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR11,
VAR6,
VAR2 ,
VAR9
);
output VAR7 ;
input VAR10 ;
input VAR11;
input VAR6;
input VAR2 ;
input VAR9 ;
wire VAR3 ;
wire VAR4;
buf VAR12 (VAR3 , VAR10 );
VAR8 VAR5 (VAR4, VAR3, VAR11, VAR6);
buf VAR1 (VAR7 , VAR4 );
endmodule | apache-2.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_lfo.v | 6,254 | module MODULE1(
input rst,
input clk,
input VAR24,
input VAR26,
input [7:0] VAR1,
input [6:0] VAR5,
input [6:0] VAR3,
input [1:0] VAR2,
output reg [6:0] VAR16,
output reg [7:0] VAR37
);
reg signed [7:0] VAR23;
always @ begin : VAR30
VAR13 = VAR1[7:4]
+ ( VAR2==2'd2 ? 1'b1 : 1'b0 );
case( VAR13 )
5'h10: VAR7 = VAR6[b0-1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi.functional.v | 1,590 | module MODULE1 (
VAR3 ,
VAR2,
VAR4,
VAR12,
VAR10,
VAR8
);
output VAR3 ;
input VAR2;
input VAR4;
input VAR12;
input VAR10;
input VAR8;
wire VAR9 ;
wire VAR5 ;
wire VAR6;
and VAR7 (VAR9 , VAR12, VAR10 );
and VAR13 (VAR5 , VAR2, VAR4 );
nor VAR1 (VAR6, VAR9, VAR8, VAR5);
buf VAR11 (VAR3 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbp/sky130_fd_sc_lp__dlrbp.behavioral.pp.v | 2,490 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR2,
VAR19 ,
VAR22 ,
VAR5 ,
VAR21 ,
VAR7 ,
VAR15
);
output VAR9 ;
output VAR3 ;
input VAR2;
input VAR19 ;
input VAR22 ;
input VAR5 ;
input VAR21 ;
input VAR7 ;
input VAR15 ;
wire VAR23 ;
reg VAR14 ;
wire VAR18 ;
wire VAR6 ;
wire VAR4 ;
wire VAR24;
wire VAR10 ;
wire VAR8 ;
wire VAR20 ;
wi... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.behavioral.v | 1,121 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1));
VAR4 VAR3(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/33befe9f7af11a93/ip_design_led_controller_0_0_stub.v | 2,544 | module MODULE1(VAR8, VAR11, VAR10,
VAR21, VAR20, VAR13, VAR17, VAR7,
VAR4, VAR6, VAR3, VAR12, VAR5,
VAR19, VAR16, VAR15, VAR9, VAR2,
VAR22, VAR1, VAR14, VAR18)
;
output [7:0]VAR8;
input [3:0]VAR11;
input [2:0]VAR10;
input VAR21;
output VAR20;
input [31:0]VAR13;
input [3:0]VAR17;
input VAR7;
output VAR4;
output [1:0]VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o_1.v | 2,310 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR1 ,
VAR2 ,
VAR8 ,
VAR9 ,
VAR6,
VAR5
);
output VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR6;
input VAR5;
VAR10 VAR4 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3.symbol.v | 1,274 | module MODULE1 (
input VAR3,
input VAR6,
input VAR2,
output VAR7
);
supply1 VAR5;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4_lp.v | 2,283 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR8 ,
VAR3 ,
VAR4 ,
VAR9,
VAR2,
VAR1 ,
VAR5
);
output VAR7 ;
input VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR4 ;
input VAR9;
input VAR2;
input VAR1 ;
input VAR5 ;
VAR11 VAR6 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp.blackbox.v | 1,327 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR8 ,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR6;
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
wgml/sysrek | arithm/ipcore_dir/mul2.v | 41,757 | module MODULE1 (
clk, VAR271, VAR34, VAR368
);
input clk;
output [34 : 0] VAR271;
input [14 : 0] VAR34;
input [19 : 0] VAR368;
wire \VAR243/VAR73 ;
wire \VAR243/VAR345 ;
wire \VAR243/VAR246 ;
wire \VAR243/VAR56 ;
wire \VAR243/VAR218 ;
wire \VAR243/VAR228 ;
wire \VAR243/VAR355 ;
wire \VAR243/VAR91 ;
wire \VAR243/VAR132 ... | gpl-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/acl_push.v | 5,792 | module MODULE1 (
VAR22,
VAR50,
VAR36,
VAR23,
VAR37,
VAR44,
VAR12,
VAR21,
VAR46,
VAR18,
VAR43,
VAR14,
VAR2
);
parameter VAR40 = 32;
parameter VAR31 = 1;
parameter VAR24 = 0;
parameter string VAR28 = "VAR25"; parameter VAR33 = 0;
input VAR22, VAR50, VAR46, VAR37, VAR2;
output VAR44, VAR21, VAR14;
input [VAR40-1:0] VAR23;... | mit |
asicguy/gplgpu | hdl/altera_rams/dpram_32x256.v | 9,645 | module MODULE1 (
VAR27,
VAR53,
VAR51,
VAR59,
VAR42,
VAR3,
VAR28,
VAR48);
input [31:0] VAR27;
input [7:0] VAR53;
input VAR51;
input VAR59;
input [7:0] VAR42;
input VAR3;
input VAR28;
output [31:0] VAR48;
wire [31:0] VAR38;
wire [31:0] VAR48 = VAR38[31:0];
VAR31 VAR5 (
.VAR21 (VAR28),
.VAR41 (VAR3),
.VAR50 (VAR51),
.VAR5... | gpl-3.0 |
Gurint/EPC-Gen2-RFID-Tag-Baseband-Processor | crg.v | 7,888 | module MODULE1
(
output VAR60,
output VAR6,
output VAR56,
output VAR28,
output VAR17,
output reg VAR19,
output VAR18,
output reg VAR33,
output VAR24,
output VAR7,
output reg VAR54,
output VAR8,
output reg VAR20,
input VAR1, input VAR13, input VAR15,
input rst,
input VAR16,
input [1:0]VAR55,
input VAR3,
input VAR61,
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0p/sky130_fd_sc_hd__lpflow_inputiso0p.pp.blackbox.v | 1,410 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1,
VAR2 ,
VAR5 ,
VAR4 ,
VAR7
);
output VAR6 ;
input VAR3 ;
input VAR1;
input VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/HPS/Qsys/hps_design/synthesis/submodules/hps_design_pll_0.v | 2,078 | module MODULE1(
input wire VAR13,
input wire rst,
output wire VAR6,
output wire VAR31
);
VAR72 #(
.VAR43("false"),
.VAR35("50.0 VAR34"),
.VAR16("VAR47"),
.VAR4(1),
.VAR66("100.000000 VAR34"),
.VAR37("0 VAR5"),
.VAR27(50),
.VAR48("0 VAR34"),
.VAR7("0 VAR5"),
.VAR32(50),
.VAR14("0 VAR34"),
.VAR59("0 VAR5"),
.VAR52(50),
.... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3.pp.symbol.v | 1,357 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR3 ,
input VAR2,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp.behavioral.pp.v | 2,768 | module MODULE1 (
VAR28 ,
VAR27 ,
VAR21 ,
VAR14 ,
VAR25 ,
VAR13 ,
VAR16 ,
VAR15,
VAR7,
VAR6 ,
VAR22
);
output VAR28 ;
output VAR27 ;
input VAR21 ;
input VAR14 ;
input VAR25 ;
input VAR13 ;
input VAR16 ;
input VAR15;
input VAR7;
input VAR6 ;
input VAR22 ;
wire VAR24 ;
reg VAR9 ;
wire VAR26 ;
wire VAR17 ;
wire VAR31;
wire... | apache-2.0 |
luccas641/Processador-ICMC | Processor_FPGA/Processor_Template_VHDL_DE70/SeletorClock.v | 2,898 | module MODULE1(
input wire VAR13,
input wire reset,
input wire VAR6,
input wire VAR19,
input wire VAR17,
input wire VAR16,
input wire VAR5,
input wire VAR18,
input wire VAR11,
input wire VAR15,
input wire VAR2,
input wire VAR3,
input wire VAR10,
input wire VAR8,
input wire VAR7,
input wire VAR12,
input wire VAR4,
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb.blackbox.v | 1,332 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR9 ,
VAR6,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR9 ;
input VAR6;
input VAR5;
supply1 VAR3;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211oi/sky130_fd_sc_lp__a211oi_4.v | 2,361 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR9,
VAR1,
VAR7 ,
VAR11
);
output VAR5 ;
input VAR2 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR9;
input VAR1;
input VAR7 ;
input VAR11 ;
VAR4 VAR10 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.v | 2,695 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR12 ,
VAR8 ,
VAR5 ,
VAR11 ,
VAR3,
VAR6 ,
VAR2 ,
VAR1 ,
VAR7
);
output VAR13 ;
output VAR4 ;
input VAR12 ;
input VAR8 ;
input VAR5 ;
input VAR11 ;
input VAR3;
input VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR7 ;
VAR9 VAR10 (
.VAR13(VAR13),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR5(V... | apache-2.0 |
monotone-RK/FACE | CQ/src/riffa/offset_flag_to_one_hot.v | 2,660 | module MODULE1
parameter VAR2 = 4
)
(
input [VAR3(VAR2)-1:0] VAR5,
input VAR1,
output [VAR2-1:0] VAR4
);
assign VAR4 = {{(VAR2-1){1'b0}},VAR1} << VAR5;
endmodule | mit |
AntonovAlexander/activecore | designs/rtl/udm/hw/uart_rx.v | 3,621 | module MODULE1
parameter VAR10 = "VAR4"
)
(
input VAR6, VAR3,
input VAR21,
output reg VAR9,
output reg [7:0] VAR16,
output reg VAR14,
output reg [28:0] VAR7
);
localparam VAR22 = 4'h0;
localparam VAR8 = 4'h1;
localparam VAR1 = 4'h2;
localparam VAR26 = 4'h3;
localparam VAR23 = 4'h4;
localparam VAR24 = 4'h5;
localparam V... | apache-2.0 |
P3Stor/P3Stor | ftl/arbitrator.v | 3,087 | module MODULE1(
reset,
clk,
VAR8,
VAR15,
VAR2,
VAR13,
VAR9,
VAR21,
VAR12,
VAR18,
VAR25,
VAR6,
VAR28,
VAR26,
VAR22,
VAR14,
VAR29,
VAR20,
VAR4,
VAR11
);
input reset;
input clk;
input VAR8;
input VAR15;
input VAR2;
input VAR13;
input VAR9;
input VAR21;
input VAR12;
input VAR18;
input VAR25;
input VAR6;
input VAR28;
input ... | gpl-2.0 |
hoglet67/opc | copro/src/copro.v | 7,868 | module MODULE1 (
input VAR61,
output reg [8:2] VAR68,
output VAR82,
input VAR42, input [2:0] VAR74,
inout [7:0] VAR2,
input VAR60,
input VAR39,
input VAR16,
inout VAR5,
output VAR13,
output VAR78,
output VAR30,
inout [7:0] VAR4,
output [18:0] VAR53
);
parameter VAR55 = 32;
parameter VAR19 = 20;
parameter VAR34 = 12;
p... | gpl-3.0 |
danbone/core | riscv/src/main/riscv_mem.v | 3,233 | module MODULE1 (
input clk,
input VAR21,
input VAR10,
output VAR7,
input VAR23,
input [31:0] VAR3,
input [VAR2-1:0] VAR16,
input [VAR12-1:0] VAR4,
input [31:0] VAR18,
output [31:0] VAR17,
output VAR15,
output VAR8,
input VAR6,
input [31:0] VAR20,
output [31:0] VAR5,
output [3:0] VAR19,
output VAR14,
output [31:0] VAR1
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i.behavioral.v | 1,851 | module MODULE1 (
VAR13 ,
VAR3 ,
VAR10 ,
VAR6 ,
VAR2,
VAR7
);
output VAR13 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR2;
input VAR7;
wire VAR11;
wire VAR12 ;
VAR9 VAR5 (VAR11, VAR3, VAR10, VAR6 );
VAR4 VAR8 (VAR12 , VAR11, VAR2, VAR7);
buf VAR1 (VAR13 , VAR12 );
endmodule | apache-2.0 |
brianbennett/fpga_nes | hw/src/cpu/cpu.v | 85,457 | module MODULE1
(
input wire VAR229, input wire VAR251, input wire VAR8,
input wire VAR7, input wire VAR97, input wire VAR57,
input wire [ 7:0] din, output wire [ 7:0] dout, output wire [15:0] VAR40, output reg VAR90,
input wire [ 3:0] VAR68, input wire [ 7:0] VAR83, input wire VAR36, output reg [ 7:0] VAR261, output re... | bsd-2-clause |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/atlys/rtl/verilog/dvi_gen/dcmspi.v | 3,193 | module MODULE1 (
input VAR19, input VAR29, input VAR12, input VAR5,
input [7:0] VAR23, input [7:0] VAR34, input VAR22, output reg VAR16,
output reg VAR32, output reg VAR35 );
parameter VAR27 = 1;
wire [9:0] VAR26 = {VAR23, 1'b1, 1'b1}; wire [9:0] VAR4 = {VAR34, 1'b0, 1'b1};
reg VAR31;
reg VAR33;
always @ (posedge VAR29... | gpl-2.0 |
BoolLi/Pollard-s-p-1-algorithm | e_finder.v | 5,107 | module MODULE1(
input clk,
input [63:0] VAR3,
output reg [63:0] VAR18,
output reg VAR12
);
reg VAR8;
reg VAR19;
reg VAR6;
reg [12:0] VAR14;
reg [12:0] VAR13;
reg [63:0] VAR21;
reg VAR17;
reg VAR1;
reg VAR16;
reg VAR5;
reg VAR10;
reg VAR11;
wire VAR9;
wire [8:0] VAR7;
wire VAR15;
wire [7:0] VAR2;
wire [99:0] VAR20;
wire... | mit |
trivoldus28/pulsarch-verilog | verif/env/cmp/playback_dump.v | 2,011 | module MODULE1();
integer VAR2;
reg VAR1;
reg clk; | gpl-2.0 |
donnaware/TabX1 | rtl/tabx1/tabx1.v | 13,776 | module MODULE1 (
input VAR7, input reset, output VAR120,
input VAR124, input VAR111, output VAR54, input VAR8, input VAR131, inout VAR74, inout VAR70,
inout [ 7:0] VAR2, input [20:0] VAR84, input VAR59, input VAR14, input VAR53, input VAR94, output VAR28,
inout [ 7:0] VAR32, output [11:0] VAR100, output VAR9, output VA... | gpl-3.0 |
darekb74/WSIZ_SW_Projekt1 | Maszyna_do_kawy.srcs/sources_1/new/mdk.v | 16,102 | module MODULE1(
input wire VAR12, input wire [2:0]VAR62, input wire VAR5, input wire VAR59, input wire [6:0] VAR34, output reg [3:0] VAR51, input wire[1:0]VAR22, input wire[4:0]VAR24, output reg [2:0]VAR31, output reg [4:0] VAR7, output reg [4:0] VAR27, output reg [4:0] VAR36, output reg [4:0] VAR2, output reg [2:0]VAR... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mesosync_io/src/bsg_mesosync_core.v | 4,664 | module MODULE1 #( parameter VAR30(VAR46 )
, parameter VAR30(VAR28 )
, parameter VAR30(VAR10 )
, parameter VAR30(VAR21 )
, parameter VAR30(VAR3 )
)
( input VAR49
, input VAR27
, input VAR14
, input VAR2
, input [VAR46-1:0] VAR31
, input VAR34
, output logic VAR25
, output VAR16
, output [VAR46-1:0] VAR33
, input VAR7
, ... | bsd-3-clause |
chriz2600/DreamcastHDMI | Core/source/osc/synthesis/submodules/altera_int_osc.v | 2,121 | module MODULE1
(
VAR4,
VAR5) ;
output VAR4;
input VAR5;
wire VAR1;
VAR3 VAR2
(
.VAR4(VAR1),
.VAR5(VAR5));
assign
VAR4 = VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tap/sky130_fd_sc_lp__tap.pp.symbol.v | 1,217 | module MODULE1 (
input VAR4 ,
input VAR1,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_2.behavioral.v | 3,689 | module MODULE1( VAR14, VAR27, VAR7, VAR8 );
input VAR14, VAR27, VAR7;
output VAR8;
reg VAR4;
VAR24 VAR32(.VAR14(VAR14),.VAR27(VAR27),.VAR7(VAR7),.VAR8(VAR8),.VAR4(VAR4));
VAR24 VAR22(.VAR14(VAR14),.VAR27(VAR27),.VAR7(VAR7),.VAR8(VAR8),.VAR4(VAR4));
not VAR2(VAR9,VAR27);
and VAR18(VAR13,VAR7,VAR9);
and VAR25(VAR16,VAR7,... | apache-2.0 |
Dennis-Chhun/Pong-Game | src/VGAController.v | 3,163 | module MODULE1 (VAR10,
VAR5,
VAR16,
VAR7,
VAR13,
VAR17,
VAR8,
VAR6,
VAR1,
VAR18,
VAR9);
parameter VAR12 = 1688;
parameter VAR23 = 1280;
parameter VAR22 = 112;
parameter VAR11 = 248;
parameter VAR2 = 1066;
parameter VAR14 = 1024;
parameter VAR21 = 3;
parameter VAR4 = 38;
input VAR10;
input [7:0] VAR5;
input [7:0] VAR16;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4b/sky130_fd_sc_hs__nor4b.functional.v | 1,881 | module MODULE1 (
VAR2,
VAR1,
VAR5 ,
VAR15 ,
VAR10 ,
VAR14 ,
VAR6
);
input VAR2;
input VAR1;
output VAR5 ;
input VAR15 ;
input VAR10 ;
input VAR14 ;
input VAR6 ;
wire VAR6 VAR12 ;
wire VAR3 ;
wire VAR4;
not VAR13 (VAR12 , VAR6 );
nor VAR11 (VAR3 , VAR15, VAR10, VAR14, VAR12 );
VAR9 VAR8 (VAR4, VAR3, VAR2, VAR1);
buf VAR... | apache-2.0 |
SeanZarzycki/openSPARC-FPU | dc_compiler/src/idec.v | 3,351 | module MODULE1(VAR11,VAR9,VAR4, VAR19,VAR14,VAR22,VAR6,
VAR21, VAR15, VAR10, VAR8, VAR18, VAR3,
VAR2,VAR16,VAR24,reset);
output [3:0] VAR11,VAR9,VAR4, VAR19;
output [1:0] VAR14,VAR22;
output VAR6, VAR21, VAR15, VAR10, VAR8, VAR18,VAR3 ;
input [15:0] VAR2,VAR16;
input [3:0] VAR24;
input reset;
wire VAR17 = VAR2[3],
VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3.behavioral.pp.v | 1,742 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR8 ,
VAR2 ,
VAR9,
VAR10
);
output VAR7 ;
input VAR11 ;
input VAR8 ;
input VAR2 ;
input VAR9;
input VAR10;
wire VAR12 ;
wire VAR1;
xor VAR5 (VAR12 , VAR11, VAR8, VAR2 );
VAR6 VAR3 (VAR1, VAR12, VAR9, VAR10);
buf VAR4 (VAR7 , VAR1 );
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_089.v | 1,436 | module MODULE1 (
VAR1,
VAR10
);
input [31:0] VAR1;
output [31:0]
VAR10;
wire [31:0]
VAR4,
VAR5,
VAR3,
VAR7,
VAR11,
VAR6,
VAR8;
assign VAR4 = VAR1;
assign VAR11 = VAR3 - VAR7;
assign VAR3 = VAR5 - VAR4;
assign VAR5 = VAR4 << 8;
assign VAR7 = VAR4 << 5;
assign VAR6 = VAR11 << 5;
assign VAR8 = VAR4 + VAR6;
assign VAR10 = ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_3.behavioral.v | 1,093 | module MODULE1( VAR5, VAR2 );
input VAR5;
output VAR2;
VAR4 VAR3(.VAR5(VAR5),.VAR2(VAR2));
VAR4 VAR1(.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v | 57,111 | module MODULE1 # (
parameter VAR243 = 10'd512, parameter VAR161 = "VAR154", parameter VAR178 = "VAR214", parameter VAR176 = 1'b0, parameter VAR71 = 1'b0, parameter VAR187 = 1'b1, parameter VAR138 = "VAR59"
)
(
input wire VAR22, input wire VAR207, output reg VAR194,
input wire VAR224, input wire VAR172,
input wire VAR4,... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_3.behavioral.v | 1,101 | module MODULE1( VAR3, VAR5 );
input VAR3;
output VAR5;
VAR1 VAR2(.VAR3(VAR3),.VAR5(VAR5));
VAR1 VAR4(.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
bargei/NoC264 | NoC264_3x3/mkRouterOutputArbitersRoundRobin.v | 37,365 | module MODULE1(VAR1,
VAR132,
VAR129,
VAR209,
VAR219,
VAR185,
VAR62,
VAR170,
VAR106,
VAR215,
VAR16,
VAR58,
VAR196,
VAR181,
VAR90,
VAR26,
VAR189);
input VAR1;
input VAR132;
input [4 : 0] VAR129;
output [4 : 0] VAR209;
input VAR219;
input [4 : 0] VAR185;
output [4 : 0] VAR62;
input VAR170;
input [4 : 0] VAR106;
output [4 ... | mit |
zhaishaomin/ring_network-based-multicore- | communication_assist/m_rep_upload.v | 3,251 | module MODULE1( clk,
rst,
VAR14,
VAR19,
VAR7,
VAR12,
VAR13,
VAR17,
VAR18,
VAR9,
VAR6
);
input clk;
input rst;
input [175:0] VAR14;
input VAR19;
input [3:0] VAR7;
input VAR12;
input VAR13;
output [15:0] VAR17;
output VAR18;
output [1:0] VAR9;
output VAR6;
parameter VAR3=1'b0;
parameter VAR2=1'b1;
reg VAR5;
reg [143:0] V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfstp/sky130_fd_sc_lp__srsdfstp.pp.symbol.v | 1,577 | module MODULE1 (
input VAR7 ,
output VAR10 ,
input VAR1 ,
input VAR9 ,
input VAR12 ,
input VAR3 ,
input VAR5,
input VAR2 ,
input VAR4 ,
input VAR6 ,
input VAR11 ,
input VAR8
);
endmodule | apache-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_CPU_mult_cell.v | 6,292 | module MODULE1 (
VAR50,
VAR53,
clk,
VAR37,
VAR35
)
;
output [ 31: 0] VAR35;
input [ 31: 0] VAR50;
input [ 31: 0] VAR53;
input clk;
input VAR37;
wire [ 31: 0] VAR35;
wire [ 31: 0] VAR55;
wire [ 15: 0] VAR46;
wire VAR7;
assign VAR7 = ~VAR37;
VAR30 VAR11
(
.VAR1 (VAR7),
.VAR8 (clk),
.VAR5 (VAR50[15 : 0]),
.VAR51 (VAR53[15... | mit |
HashRatio/mm-hashratio | verilog/superkdf9/components/lm32_top/er1.v | 7,897 | module MODULE1 (input VAR20,
input VAR8,
output VAR37,
output reg VAR27,
input VAR13,
input VAR5,
input VAR9,
input VAR31,
input [14:0] VAR4,
output reg [14:0] VAR18,
input VAR2,
output VAR1,
output VAR3);
wire VAR28;
wire VAR24;
wire [3:0] VAR25;
wire [9:0] VAR23;
wire VAR17;
assign VAR37 = VAR23[0];
VAR32 VAR6 (.VAR3... | unlicense |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_cmos2_term_dn.v | 1,120 | module MODULE1 (
VAR1, out
);
inout out;
input VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapmet1/sky130_fd_sc_ls__tapmet1.pp.blackbox.v | 1,230 | module MODULE1 (
VAR2,
VAR1,
VAR4 ,
VAR3
);
input VAR2;
input VAR1;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
ptracton/pmodacl2 | soc/soc.v | 7,468 | module MODULE1 (
VAR42, VAR27, VAR12, VAR5, VAR29, VAR17,
VAR22, VAR19, VAR1,
VAR15, VAR41, VAR24, VAR13, VAR25, VAR44
) ;
input VAR15;
input VAR41;
inout [15:0] VAR22;
inout [15:0] VAR19;
inout [3:0] VAR1;
input VAR24;
output VAR42;
output [3:0] VAR27;
output [7:0] VAR12;
output wire VAR5;
output wire VAR29;
output wi... | mit |
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