repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a.behavioral.v | 1,542 | module MODULE1 (
VAR5 ,
VAR14,
VAR9,
VAR3,
VAR6
);
output VAR5 ;
input VAR14;
input VAR9;
input VAR3;
input VAR6;
supply1 VAR4;
supply0 VAR13;
supply1 VAR8 ;
supply0 VAR7 ;
wire VAR11 ;
wire VAR1;
or VAR12 (VAR11 , VAR9, VAR14 );
and VAR2 (VAR1, VAR11, VAR3, VAR6);
buf VAR10 (VAR5 , VAR1 );
endmodule | apache-2.0 |
uzlonewolf/proxmark3 | fpga/hi_reader.v | 9,467 | module MODULE1(
VAR29,
VAR7, VAR9, VAR20, VAR23, VAR3, VAR17,
VAR10, VAR13,
VAR41, VAR44, VAR38, VAR14,
VAR37,
VAR24, VAR33
);
input VAR29;
output VAR7, VAR9, VAR20, VAR23, VAR3, VAR17;
input [7:0] VAR10;
output VAR13;
input VAR38;
output VAR41, VAR44, VAR14;
output VAR37;
input [1:0] VAR24;
input [3:0] VAR33;
assign V... | gpl-2.0 |
m-labs/milkymist | cores/softusb/rtl/softusb.v | 3,334 | module MODULE1 #(
parameter VAR33 = 4'h0,
parameter VAR21 = 12,
parameter VAR23 = 13,
parameter VAR32 = ""
) (
input VAR40,
input VAR8,
input VAR13,
input [13:0] VAR54,
input VAR10,
input [31:0] VAR45,
output [31:0] VAR20,
output irq,
input [31:0] VAR48,
output [31:0] VAR55,
input [31:0] VAR26,
input [3:0] VAR41,
input... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/example/ML605/fpga_sgmii/rtl/fpga.v | 10,610 | module MODULE1 (
input wire VAR35,
input wire VAR28,
input wire reset,
input wire VAR53,
input wire VAR138,
input wire VAR190,
input wire VAR164,
input wire VAR161,
input wire [7:0] VAR58,
output wire VAR141,
output wire VAR140,
output wire VAR10,
output wire VAR5,
output wire VAR55,
output wire [7:0] VAR151,
input wir... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_altmemddr_0.v | 29,534 | module MODULE1 (
VAR92,
VAR22,
VAR67,
VAR48,
VAR83,
VAR54,
VAR35,
VAR74,
VAR3,
VAR53,
VAR34,
VAR9,
VAR95,
VAR89,
VAR105,
VAR107,
VAR79,
VAR85,
VAR84,
VAR4,
VAR2,
VAR77,
VAR20,
VAR12,
VAR7,
VAR60,
VAR102,
VAR90,
VAR86,
VAR61,
VAR103,
VAR68,
VAR106);
input [23:0] VAR92;
input VAR22;
input VAR67;
input VAR48;
input [31:0]... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/src/v/bsg_cache_dma_to_wormhole.v | 8,726 | module MODULE1
import VAR67::*;
import VAR79::*;
, parameter VAR82(VAR63)
, parameter VAR82(VAR92)
, parameter VAR82(VAR90)
, parameter VAR82(VAR93)
, parameter VAR115=VAR83(VAR21)
, parameter VAR46=VAR60(VAR63)
, parameter VAR9=VAR63
, parameter VAR34 = 1
)
(
input VAR98
, input VAR49
, input [VAR115-1:0] VAR105
, inp... | bsd-3-clause |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_rxmac.v | 9,210 | module MODULE1 (VAR46, VAR18, VAR25, VAR44, VAR8,
VAR4, VAR27, VAR2, VAR11, VAR29,
VAR1, VAR51, VAR17, VAR58, VAR67,
VAR10, VAR59, VAR47, VAR60, VAR6, VAR43, VAR16, VAR28,VAR54
);
input VAR46;
input VAR18;
input [3:0] VAR25;
input VAR44;
input [7:0] VAR8;
output [7:0] VAR4;
output VAR27;
output [7:0] VAR2;
output [7:0]... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/05MicroSD/Version_02/02 verilog/spi.v | 1,127 | module MODULE1
parameter VAR11=50000)
(
input [VAR2-1:0] VAR1,
input en,
input reset,
input clk,
input VAR8,
output reg [VAR2-1:0] VAR4,
output reg VAR13,
output reg VAR6,
output reg VAR3,
output reg VAR10
);
integer VAR9=0;
integer VAR12=0;
reg [VAR2-1:0] VAR7=0;
reg [VAR2-1:0] VAR5=0;
reg VAR14=0;
always @(posedge cl... | gpl-3.0 |
marqs85/ossc | rtl/linebuf.v | 9,202 | module MODULE1 (
VAR8,
VAR5,
VAR32,
VAR53,
VAR7,
VAR15,
VAR47);
input [23:0] VAR8;
input [11:0] VAR5;
input VAR32;
input [11:0] VAR53;
input VAR7;
input VAR15;
output [23:0] VAR47;
tri1 VAR7;
tri0 VAR15;
wire [23:0] VAR55;
wire [23:0] VAR47 = VAR55[23:0];
VAR26 VAR40 (
.VAR58 (VAR53),
.VAR1 (VAR5),
.VAR48 (VAR7),
.VAR5... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/controller/arb_select.v | 20,255 | module MODULE1 #
(
parameter VAR22 = 100,
parameter VAR11 = "1T",
parameter VAR60 = 11,
parameter VAR110 = 3,
parameter VAR103 = "8",
parameter VAR134 = 4,
parameter VAR25 = 5,
parameter VAR84 = 31,
parameter VAR83 = 8,
parameter VAR20 = "VAR52",
parameter VAR30 = "VAR100",
parameter VAR115 = "VAR100",
parameter VAR112... | lgpl-3.0 |
rurume/openrisc_vision_hardware | ISE/or1200_ic_fsm.v | 9,561 | module MODULE1(
clk, rst,
VAR8, VAR12, VAR10,
VAR15, VAR14, VAR23, VAR24, VAR21,
VAR5, VAR3, VAR16, VAR11, VAR2,
VAR18, VAR17
);
input clk;
input rst;
input VAR8;
input VAR12;
input VAR10;
input VAR15;
input VAR14;
input VAR23;
input [31:0] VAR24;
output [31:0] VAR21;
output [3:0] VAR5;
output VAR3;
output VAR16;
outpu... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/EncWidthConverter32to16.v | 5,980 | module MODULE1
(
parameter VAR13 = 32,
parameter VAR2 = 16
)
(
VAR12 ,
VAR16 ,
VAR20 ,
VAR9 ,
VAR6 ,
VAR1 ,
VAR8 ,
VAR11 ,
VAR3 ,
VAR7
);
input VAR12 ;
input VAR16 ;
input VAR20 ;
input VAR9 ;
input [VAR13 - 1:0] VAR6 ;
output VAR1 ;
output VAR8 ;
output VAR11 ;
output [VAR2 - 1:0] VAR3 ;
input VAR7 ;
reg [VAR13 - 1:0]... | gpl-3.0 |
rbarzic/async_logic | async_lib/memories/async_mem.v | 2,013 | module MODULE1 (
ack, dout,
req, addr, din, VAR9
);
parameter VAR15 = 10;
parameter VAR6 = 1024;
parameter VAR2 = 12;
parameter VAR8 = "VAR1.VAR3";
localparam VAR14 = 8;
localparam VAR12 = 4;
localparam VAR11 = 5;
input req;
output ack;
input [VAR2-1:0] addr; input [VAR12*VAR14-1:0] din; input [VAR12-1:0] VAR9;
output ... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/quad_uart.v | 3,076 | module MODULE1
parameter VAR41 = 1)
(input VAR29, input VAR44,
input VAR20, input VAR4, input VAR26, output reg VAR25,
input [4:0] VAR19, input [31:0] VAR9, output reg [31:0] VAR42,
output [3:0] VAR10, output [3:0] VAR30,
output [3:0] VAR32, input [3:0] VAR31, output [3:0] VAR35
);
localparam VAR17 = 0;
localparam VAR1... | gpl-2.0 |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part6/DE1_displ.v | 2,475 | module MODULE1 (
output reg [3:0] VAR14,
output reg [6:0] VAR6,
input wire [6:0] VAR1,
input wire [6:0] VAR4,
input wire [6:0] VAR2,
input wire [6:0] VAR12,
input wire clk
);
parameter
VAR5 = 3'b000,
VAR8 = 3'b001,
VAR15 = 3'b010,
VAR7 = 3'b011,
VAR3 = 3'b100,
VAR10 = 3'b101,
VAR9 = 3'b110,
VAR13 = 3'b111;
reg [2:0] st... | unlicense |
DreamSourceLab/DSLogic-hdl | src/uart/uart_tx.v | 2,618 | module MODULE1
(
VAR5, reset,
VAR9, VAR2, VAR3,
VAR4, VAR7
);
input VAR5; input reset; input VAR9; input [7:0] VAR2; input VAR3; output VAR4; output VAR7;
wire VAR6;
reg VAR4;
reg VAR7;
reg [3:0] VAR8;
reg [3:0] VAR10;
reg [8:0] VAR1;
always @ (posedge VAR5 or posedge reset)
begin
if (reset)
VAR8 <= 4'b0;
end
else if (... | gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/DMA_READ_QUEUE.v | 13,377 | module MODULE1(
clk,
VAR360,
din,
VAR180,
VAR22,
dout,
VAR261,
VAR269
);
input clk;
input VAR360;
input [63 : 0] din;
input VAR180;
input VAR22;
output [63 : 0] dout;
output VAR261;
output VAR269;
VAR80 #(
.VAR342(0),
.VAR238(0),
.VAR189(0),
.VAR237(0),
.VAR398(0),
.VAR267(0),
.VAR137(0),
.VAR388(32),
.VAR373(1),
.VAR2... | gpl-2.0 |
cpulabs/gci-std-display | rtl/lib/gci_std_display_sync_fifo.v | 2,610 | module MODULE1 #(
parameter VAR15 = 16,
parameter VAR9 = 4,
parameter VAR3 = 2
)(
input VAR1,
input VAR20,
input VAR7,
output [VAR3:0] VAR25,
input VAR24,
input [VAR15-1:0] VAR14,
output VAR10,
output VAR12,
input VAR5,
output [VAR15-1:0] VAR19,
output VAR18,
output VAR13
);
reg [VAR3:0] VAR4;
reg [VAR3:0] VAR2;
reg [V... | bsd-2-clause |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/bench/verilog/eth_memory.v | 5,836 | module MODULE1
(
VAR9, VAR6, VAR1, VAR7, VAR13, VAR10,
VAR5, VAR15, VAR14, VAR4, VAR2
);
parameter VAR3=1;
input VAR9, VAR6;
input [31:0] VAR1, VAR2;
input [3:0] VAR7;
input VAR13, VAR10, VAR5;
output VAR15, VAR14;
output [31:0] VAR4;
reg VAR15, VAR14;
reg [31:0] VAR4;
reg [7:0] VAR11 [0:65535];
reg [7:0] VAR17 [0:6553... | gpl-2.0 |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/arith_map.v | 2,635 | module MODULE1(
module 80quicklogicalu (VAR34, VAR16, VAR28, VAR17, VAR26, VAR23, VAR12);
parameter VAR31 = 0;
parameter VAR19 = 0;
parameter VAR25 = 2;
parameter VAR29 = 2;
parameter VAR14 = 2;
parameter VAR1 = 0;
parameter VAR15 = 0;
input [VAR25-1:0] VAR34;
input [VAR29-1:0] VAR16;
output [VAR14-1:0] VAR26, VAR23;
i... | apache-2.0 |
hydai/Verilog-Practice | DigitalDesign/hw3/datapath.v | 4,579 | module MODULE1 (
output reg [291:0] VAR20,
input [25:0] VAR25,
input [15:0] VAR11,
input [15:0] VAR7,
input clk,
input VAR18
);
reg [15:0] VAR23 [0:15];
reg [15:0] VAR14, VAR16, VAR6;
reg [3:0] VAR12, VAR1, VAR5, VAR22, VAR10;
reg [2:0] VAR19;
reg VAR2, VAR3, VAR9, VAR21, VAR15, VAR26, VAR8;
reg [15:0] VAR27, VAR13;
re... | mit |
keith-epidev/VHDL-lib | top/mono_radio/ip/clk_193MHz/clk_193MHz_stub.v | 1,171 | module MODULE1(VAR2, MODULE1, VAR1)
;
input VAR2;
output MODULE1;
output VAR1;
endmodule | gpl-2.0 |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/ice_bus.v | 5,727 | module MODULE1 (
input reset,
input clk,
input [4:1] VAR12,
input VAR40,
output VAR53,
output VAR36,
output VAR19,
output VAR32,
output VAR25,
output VAR47,
input VAR23,
input VAR16,
input VAR54,
output VAR38,
output VAR61,
output VAR42,
input VAR58,
output VAR66,
output VAR67,
output VAR63,
input VAR30,
input VAR52,
o... | apache-2.0 |
prernaa/CPUVerilog | hdUnit.v | 4,400 | module MODULE1(
VAR10, VAR13, VAR5, VAR3, VAR4, VAR2, VAR1, VAR8,
VAR7, VAR12, VAR6, VAR11,
VAR9
);
input [3:0] VAR10;
input [3:0] VAR13;
input VAR5;
input VAR3;
input VAR4;
input [3:0] VAR2;
input VAR1;
input [3:0] VAR8;
input VAR9;
output VAR7;
output VAR12;
output VAR6;
output VAR11;
assign VAR7 = (VAR9 === 1'b1)? 1... | mit |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/About/About_stub.v | 1,250 | module MODULE1(VAR3, VAR1, VAR2)
;
input VAR3;
input [9:0]VAR1;
output [799:0]VAR2;
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.behavioral.v | 1,341 | module MODULE1( VAR4, VAR3, VAR6, VAR5, VAR1 );
input VAR1, VAR5, VAR6, VAR4;
output VAR3;
VAR2 VAR8(.VAR4(VAR4),.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1));
VAR2 VAR7(.VAR4(VAR4),.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
silent-observer/RCPU | CPU/source/PS2_Controller/Altera_UP_PS2_Command_Out.v | 10,795 | module MODULE1 (
clk,
reset,
VAR7,
VAR26,
VAR19,
VAR20,
VAR6,
VAR31,
VAR17,
VAR18
);
parameter VAR16 = 5050;
parameter VAR8 = 13;
parameter VAR15 = 13'h0001;
parameter VAR22 = 750000;
parameter VAR12 = 20;
parameter VAR10 = 20'h00001;
parameter VAR1 = 100000;
parameter VAR24 = 17;
parameter VAR25 = 17'h00001;
input clk... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_mm_interconnect_0.v | 20,294 | module MODULE1 (
input wire VAR12, input wire VAR85, input wire [29:0] VAR90, output wire VAR44, input wire [4:0] VAR38, input wire [31:0] VAR7, input wire VAR15, output wire [255:0] VAR59, output wire VAR9, input wire VAR68, input wire [255:0] VAR67, output wire [29:0] VAR16, output wire VAR34, output wire VAR76, inpu... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat_4.v | 1,063 | module MODULE1(
VAR4,
VAR3,
VAR1,
VAR2,
o0,
o1,
o2,
o3
);
input signed [27:0] VAR4;
input signed [27:0] VAR3;
input signed [27:0] VAR1;
input signed [27:0] VAR2;
output signed [27:0] o0;
output signed [27:0] o1;
output signed [27:0] o2;
output signed [27:0] o3;
assign o0=VAR4;
assign o1=VAR1;
assign o2=VAR3;
assign o3=... | gpl-3.0 |
sh-chris110/chris | FPGA/atlas_linux_ghrd/soc_system/synthesis/submodules/soc_system_sysid_qsys.v | 1,419 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1441816799 : 2899645186;
endmodule | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_xbar_0/synth/OpenSSD2_xbar_0.v | 13,313 | module MODULE1 (
VAR84,
VAR17,
VAR25,
VAR104,
VAR54,
VAR83,
VAR26,
VAR70,
VAR8,
VAR36,
VAR71,
VAR110,
VAR131,
VAR86,
VAR55,
VAR38,
VAR56,
VAR7,
VAR101,
VAR99,
VAR64,
VAR80,
VAR16,
VAR93,
VAR39,
VAR63,
VAR107,
VAR94,
VAR14,
VAR61,
VAR87,
VAR113,
VAR77,
VAR105,
VAR130,
VAR51,
VAR2,
VAR60,
VAR72,
VAR88
);
input wire VAR84... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_cfgr.v | 12,329 | module MODULE1(
VAR91, VAR71
);
input [31:0] VAR91; output [31:0] VAR71;
reg [31:0] VAR71;
always @(VAR91)
if (~|VAR91[31:4])
case(VAR91[3:0]) VAR72: begin
VAR71[VAR108] = VAR135;
VAR71[VAR103] = VAR111;
VAR71[VAR52] = VAR44;
VAR71[VAR64] = VAR51;
end
VAR71[VAR116] = VAR25;
VAR71[VAR7] = VAR67;
VAR71[VAR3] = VAR11;
VAR... | gpl-2.0 |
vvk/sysrek | arithm/ipcore_dir/add.v | 22,064 | module MODULE1 (
clk, VAR248, VAR112, VAR76, VAR211
);
input clk;
input VAR248;
output [14 : 0] VAR112;
input [13 : 0] VAR76;
input [13 : 0] VAR211;
wire \VAR106/VAR150 ;
wire \VAR106/VAR84 ;
wire \VAR106/VAR60 ;
wire \VAR106/VAR140 ;
wire \VAR106/VAR156 ;
wire \VAR106/VAR129 ;
wire \VAR106/VAR202 ;
wire \VAR106/VAR67 ... | gpl-2.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axis_register_slice_0_0/axis_infrastructure_v1_1/hdl/verilog/axis_infrastructure_v1_1_util_aclken_converter.v | 8,412 | module MODULE1 # (
parameter integer VAR4 = 32,
parameter integer VAR24 = 1,
parameter integer VAR19 = 1
)
(
input wire VAR8,
input wire VAR15,
input wire VAR14,
input wire [VAR4-1:0] VAR17,
input wire VAR13,
output wire VAR16,
input wire VAR9,
output wire [VAR4-1:0] VAR27,
output wire VAR10,
input wire VAR6
);
localpa... | bsd-2-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/iobdg_ctrl/rtl/iobdg_ctrl.v | 65,477 | module MODULE1 (
VAR253, VAR33, VAR387,
VAR309, VAR279, VAR54,
VAR220, VAR257, VAR336,
VAR401, VAR333, VAR76,
VAR353, VAR26, VAR337,
VAR326, VAR296, VAR421, VAR434,
VAR43, VAR203, VAR144,
VAR431, VAR318, VAR395, VAR23,
VAR187, VAR300, VAR417, VAR107,
VAR57, VAR288,
VAR18, VAR341,
VAR182, VAR35,
VAR223, VAR184, VAR208,
... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9649_v1_00_a/hdl/verilog/cf_pnmon.v | 9,872 | module MODULE1 (
VAR16,
VAR12,
VAR13,
VAR24,
VAR1);
input VAR16;
input [13:0] VAR12;
output VAR13;
output VAR24;
input VAR1;
reg VAR23 = 'd0;
reg VAR3 = 'd0;
reg VAR8 = 'd0;
reg VAR9 = 'd0;
reg [13:0] VAR20 = 'd0;
reg [27:0] VAR11 = 'd0;
reg VAR21 = 'd0;
reg VAR4 = 'd0;
reg [ 6:0] VAR22 = 'd0;
reg VAR13 = 'd0;
reg [ 4:... | mit |
takeshineshiro/fpga_linear_128 | SPI_AD.v | 1,531 | module MODULE1(
input VAR5,
input VAR4,
input [12:0] VAR2,
input [7:0] VAR10,
output reg [7:0] VAR12,
input VAR6, output reg VAR3,
inout reg VAR7,
output reg VAR11
);
reg [15:0] VAR13;
reg [7:0] VAR8;
reg [7:0] VAR9;
always @(negedge VAR5 or posedge VAR4 ) begin
if(VAR4) begin
VAR13 <={VAR6,1'b0,1'b0,VAR2[12:0]};
VAR8 ... | mit |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_SEQ_RVT_TT_220101.v | 81,234 | module MODULE1 (VAR24, VAR4, VAR1, VAR11, VAR3);
output VAR24;
input VAR4, VAR1, VAR11, VAR3;
reg VAR21;
wire VAR2, VAR6, VAR15, VAR18;
wire VAR22, VAR7, VAR27;
wire VAR5, VAR23;
not (VAR22, VAR2);
not (VAR5, VAR6);
not (VAR27, VAR15);
VAR28 (VAR23, VAR18, VAR22, VAR5, VAR27);
VAR9 (VAR7, VAR21, VAR18, VAR22, VAR5, VAR... | bsd-3-clause |
freecores/zet86 | soc/keyb/rtl/ps2_keyb.v | 15,999 | module MODULE1 (
input VAR9,
input VAR6,
output reg [7:0] VAR22, output reg VAR2, input VAR43,
inout VAR47,
inout VAR29
);
parameter VAR21 = 1920; parameter VAR39 = 11; parameter VAR24 = 186; parameter VAR57 = 8; parameter VAR42 = 0;
parameter VAR10 = 1;
parameter VAR44 = 0;
parameter VAR17 = 13;
parameter VAR40 = 14;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill/sky130_fd_sc_hs__fill_2.v | 1,840 | module MODULE2 (
VAR1,
VAR4,
VAR2 ,
VAR6
);
input VAR1;
input VAR4;
input VAR2 ;
input VAR6 ;
VAR5 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR6 ;
VAR5 VAR3 ();
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/riffa/fifo_packer_32.v | 3,906 | module MODULE1 (
input VAR3,
input VAR18,
input [31:0] VAR2, input VAR6, input VAR4, input VAR15, input VAR13, output [31:0] VAR1, output VAR12, output VAR10, output VAR11, output VAR8 );
reg VAR5=0, VAR5=0;
reg VAR17=0, VAR17=0;
reg VAR9=0, VAR9=0;
reg VAR7=0, VAR7=0;
reg [31:0] VAR16=64'd0, VAR16=64'd0;
reg VAR14=0, ... | mit |
sam-falvo/kestrel | cores/KCP53K/processor/rtl/verilog/alu.v | 2,545 | module MODULE1(
input [63:0] VAR33,
input [63:0] VAR4,
input VAR25,
input VAR6,
input VAR19,
input VAR29,
input VAR32,
input VAR34,
input VAR13,
input VAR9, input VAR5, output [63:0] VAR3,
output VAR14,
output VAR38,
output VAR22
);
wire [63:0] VAR36 = VAR4 ^ ({64{VAR32}});
wire [63:0] VAR23 = VAR33[62:0] + VAR36[62:0]... | mpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.behavioral.v | 7,158 | module MODULE1( VAR2, VAR10, VAR4, VAR9, VAR7, VAR5, VAR3 );
input VAR5, VAR3, VAR9, VAR7, VAR2, VAR4;
output VAR10;
VAR8 VAR1(.VAR2(VAR2),.VAR10(VAR10),.VAR4(VAR4),.VAR9(VAR9),.VAR7(VAR7),.VAR5(VAR5),.VAR3(VAR3));
VAR8 VAR6(.VAR2(VAR2),.VAR10(VAR10),.VAR4(VAR4),.VAR9(VAR9),.VAR7(VAR7),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n.behavioral.pp.v | 1,899 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR13,
VAR10 ,
VAR6 ,
VAR5 ,
VAR4
);
output VAR1 ;
input VAR7 ;
input VAR13;
input VAR10 ;
input VAR6 ;
input VAR5 ;
input VAR4 ;
wire VAR8 ;
wire VAR2;
not VAR11 (VAR8 , VAR13 );
or VAR3 (VAR2, VAR7, VAR8 );
VAR9 VAR12 (VAR1 , VAR2, VAR10, VAR6);
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/memory/hdl/fifo_full_block.v | 3,483 | module MODULE1 (
VAR2, VAR5, VAR13, VAR9,
reset, VAR7, VAR12, VAR6
);
parameter VAR3 = 2;
input reset;
input VAR7;
input [VAR3:0] VAR12; input VAR6;
output VAR2;
output VAR5;
output [VAR3-1:0] VAR13;
output [VAR3:0] VAR9;
reg [VAR3:0] VAR9;
reg [VAR3:0] VAR11;
reg VAR2;
wire VAR10;
wire [VAR3:0] VAR1;
wire [VAR3:0] VAR... | gpl-3.0 |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkDM_Run_Control.v | 34,437 | module MODULE1(VAR102,
VAR56,
VAR76,
VAR9,
VAR23,
VAR25,
VAR46,
VAR110,
VAR199,
VAR173,
VAR57,
VAR19,
VAR164,
VAR15,
VAR51,
VAR153,
VAR65,
VAR144,
VAR145,
VAR161,
VAR197,
VAR60,
VAR198,
VAR35,
VAR113,
VAR179,
VAR208,
VAR32,
VAR73,
VAR97,
VAR96,
VAR37,
VAR118,
VAR43,
VAR79);
input VAR102;
input VAR56;
output VAR76;
outp... | apache-2.0 |
ptracton/vscale_soc | rtl/uart16550-1.5.4/rtl/verilog-backup/uart_transmitter.v | 9,777 | module MODULE1 (clk, VAR4, VAR1, VAR19, VAR13, enable, VAR32, state, VAR18, VAR21);
input clk;
input VAR4;
input [7:0] VAR1;
input VAR19;
input [7:0] VAR13;
input enable;
input VAR21;
output VAR32;
output [2:0] state;
output [VAR25-1:0] VAR18;
reg [2:0] state;
reg [4:0] counter;
reg [2:0] VAR20; reg [6:0] VAR26; reg VA... | mit |
benreynwar/fpga-sdrlib | verilog/uhd/u1plus_core_loop.v | 14,961 | module MODULE1
parameter VAR120 = 2,
parameter VAR81 = 20,
parameter VAR1 = 10, parameter VAR126 = 10,
parameter VAR3 = 11,
parameter VAR30 = 11,
parameter VAR47 = 0
)
(input clk, input reset,
output [31:0] VAR122, output [1:0] VAR52,
input [35:0] VAR165, input VAR12, output VAR66,
output [35:0] VAR94, output VAR139, i... | mit |
jobisoft/jTDC | modules/counter/loadable_downcounter8.v | 2,129 | module MODULE1 ( VAR1, VAR4, VAR3, VAR5, VAR2);
input wire VAR1;
input wire VAR4;
input wire [7:0] VAR3;
input wire VAR5;
output reg [7:0] VAR2;
always@(posedge VAR1)
begin
if (VAR5 == 1'b1) VAR2 <= VAR3;
end
else VAR2 <= VAR2 - VAR4;
end
endmodule | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/FIFO_OPENFLOW/ram_128_134.v | 9,624 | module MODULE1 (
VAR25,
VAR50,
VAR34,
VAR48,
VAR37,
VAR26,
VAR18,
VAR12);
input VAR25;
input VAR50;
input [133:0] VAR34;
input [6:0] VAR48;
input VAR37;
input [6:0] VAR26;
input VAR18;
output [133:0] VAR12;
tri0 VAR25;
tri1 VAR50;
tri1 VAR37;
tri0 VAR18;
wire [133:0] VAR59;
wire [133:0] VAR12 = VAR59[133:0];
VAR14 VAR7... | apache-2.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/imx_uocm.v | 1,351 | module MODULE1(
clk,
VAR4, VAR10, VAR9,
addr, VAR8, VAR1
);
parameter VAR2 = VAR3; parameter VAR5 = 32;
input clk;
input VAR4;
input VAR9;
input VAR10;
input [VAR2-1:0] addr;
input [VAR5-1:0] VAR8;
output [VAR5-1:0] VAR1;
reg [VAR5-1:0] VAR6 [(1<<VAR2)-1:0] ;
reg [VAR2-1:0] VAR7; | gpl-2.0 |
jameshegarty/rigel | platform/camera1x/vsrc/top.v | 22,216 | module MODULE1
(
inout [53:0] VAR6,
inout VAR330,
inout VAR129,
inout VAR103,
inout VAR93,
inout VAR379,
inout VAR201,
inout VAR86,
inout VAR303,
inout VAR396,
output VAR5,
inout [2:0] VAR199,
inout [14:0] VAR318,
inout VAR322,
inout VAR78,
inout [31:0] VAR299,
inout [3:0] VAR100,
inout [3:0] VAR58,
inout [3:0] VAR133,... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/cpu_dma_queue.v | 4,612 | module MODULE1
parameter VAR9=VAR31/8,
parameter VAR26 = VAR3,
parameter VAR8 = VAR26/8,
parameter VAR21 = 125000
)
(output [VAR31-1:0] VAR18,
output [VAR9-1:0] VAR29,
output VAR28,
input VAR15,
input [VAR31-1:0] VAR27,
input [VAR9-1:0] VAR10,
input VAR17,
output VAR4,
output VAR13,
input VAR19,
output [VAR26-1:0] VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3/sky130_fd_sc_hd__nand3.behavioral.pp.v | 1,819 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR8 ,
VAR6 ,
VAR13,
VAR14,
VAR12 ,
VAR10
);
output VAR9 ;
input VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR13;
input VAR14;
input VAR12 ;
input VAR10 ;
wire VAR7 ;
wire VAR11;
nand VAR2 (VAR7 , VAR8, VAR4, VAR6 );
VAR3 VAR1 (VAR11, VAR7, VAR13, VAR14);
buf VAR5 (VAR9 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111a/sky130_fd_sc_hd__o2111a.behavioral.v | 1,588 | module MODULE1 (
VAR12 ,
VAR10,
VAR8,
VAR5,
VAR1,
VAR6
);
output VAR12 ;
input VAR10;
input VAR8;
input VAR5;
input VAR1;
input VAR6;
supply1 VAR3;
supply0 VAR9;
supply1 VAR14 ;
supply0 VAR4 ;
wire VAR7 ;
wire VAR13;
or VAR15 (VAR7 , VAR8, VAR10 );
and VAR2 (VAR13, VAR5, VAR1, VAR7, VAR6);
buf VAR11 (VAR12 , VAR13 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcon/sky130_fd_sc_ls__fahcon.pp.symbol.v | 1,361 | module MODULE1 (
input VAR1 ,
input VAR9 ,
input VAR8 ,
output VAR3,
output VAR6 ,
input VAR7 ,
input VAR4 ,
input VAR5 ,
input VAR2
);
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_hps_0_hps_io.v | 1,922 | module MODULE1 (
output wire [12:0] VAR9, output wire [2:0] VAR14, output wire VAR1, output wire VAR15, output wire VAR2, output wire VAR3, output wire VAR7, output wire VAR16, output wire VAR13, output wire VAR18, inout wire [7:0] VAR5, inout wire VAR4, inout wire VAR17, output wire VAR8, output wire VAR12, input wire... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi_4.v | 2,483 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR1 ,
VAR2 ,
VAR4,
VAR3,
VAR11 ,
VAR9
);
output VAR8 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR3;
input VAR11 ;
input VAR9 ;
VAR12 VAR7 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VA... | apache-2.0 |
betontalpfa2/AXI2SPI-bridge | hdl/spi_clock_generator.v | 3,690 | module MODULE1(
input VAR8,
input VAR7,
input VAR19,
input VAR18,
input VAR2,
input VAR22,
input VAR9,
output VAR1,
output VAR13,
output VAR5,
output VAR4,
output VAR3
);
reg [6:0] VAR20;
wire VAR23;
wire [1:0]VAR12;
reg VAR21; wire VAR10;
wire VAR6;
wire VAR16;
wire VAR14;
wire [1:0] VAR17;
always @(posedge VAR8) begi... | gpl-3.0 |
ElegantLin/My-CPU | project_4/project_4.srcs/sources_1/imports/Chapter11/ex.v | 18,115 | module MODULE1(
input wire rst,
input wire[VAR7] VAR83,
input wire[VAR101] VAR86,
input wire[VAR100] VAR1,
input wire[VAR100] VAR56,
input wire[VAR57] VAR71,
input wire VAR3,
input wire[VAR100] VAR102,
input wire[31:0] VAR79,
input wire[VAR100] VAR63,
input wire[VAR100] VAR44,
input wire[VAR100] VAR93,
input wire[VAR10... | gpl-3.0 |
ByronPhung/hardware-accelerated-dna-matching-and-variation-detection | Hardware/Verilog/Search_4Comparators_tf.v | 2,439 | module MODULE1;
reg VAR1;
reg reset;
reg [1023:0] VAR2;
reg [63:0] VAR6;
wire VAR4;
VAR3 VAR5 (
.VAR1(VAR1),
.reset(reset),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4)
); | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pr_region_controller_0/ghrd_10as066n2_pr_region_controller_0_bb.v | 1,336 | module MODULE1 (
input wire VAR13, input wire VAR11, input wire [1:0] VAR12, input wire [31:0] VAR15, output wire [31:0] VAR2, output wire VAR14, input wire VAR6, output wire VAR1, input wire VAR3, input wire VAR4, output wire VAR7, input wire VAR8, output wire VAR16, input wire VAR5, input wire VAR9, output wire VAR10... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_rf32x108.v | 13,874 | module MODULE1(
dout, VAR29,
din, VAR4, VAR10, VAR8, VAR30, VAR6, VAR31,
VAR24, VAR32, VAR37, VAR34, VAR28, VAR39, VAR7
);
input [107:0] din; input [4:0] VAR4; input [4:0] VAR10; input VAR8; input [4:0] VAR30; input VAR6;
input VAR31 ; input [3:0] VAR24; input VAR32 ; input VAR37;
input VAR34, VAR28 ;
input VAR39;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp.symbol.v | 1,488 | module MODULE1 (
input VAR9 ,
output VAR4 ,
output VAR2 ,
input VAR1,
input VAR6 ,
input VAR8 ,
input VAR3
);
supply1 VAR5;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtp/sky130_fd_sc_hs__dlxtp.functional.pp.v | 1,600 | module MODULE1 (
VAR1,
VAR4,
VAR3 ,
VAR9 ,
VAR5
);
input VAR1;
input VAR4;
output VAR3 ;
input VAR9 ;
input VAR5;
wire VAR6 VAR2;
wire VAR6 VAR8 ;
wire VAR6 ;
VAR11 VAR10 (VAR6 , VAR9, VAR5, VAR1, VAR4);
buf VAR7 (VAR3 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3.functional.pp.v | 2,186 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR11 ,
VAR12 ,
VAR7,
VAR18,
VAR15 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR11 ;
input VAR12 ;
input VAR7;
input VAR18;
input VAR15 ;
input VAR8 ;
wire VAR4 ;
wire VAR13 ;
wire VAR16 ;
wire VAR20 ;
wire VAR6;
or VAR14 (VAR4 , VAR11, VAR9 );
and VAR17 (VAR13 , VAR4, VAR12 );
and VAR10... | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_FIFO.v | 13,459 | module MODULE1(
rst,
VAR187,
VAR288,
din,
VAR302,
VAR51,
dout,
VAR223,
VAR35,
VAR219
);
input rst;
input VAR187;
input VAR288;
input [255 : 0] din;
input VAR302;
input VAR51;
output [31 : 0] dout;
output VAR223;
output VAR35;
output VAR219;
VAR331 #(
.VAR120(0),
.VAR234(0),
.VAR405(0),
.VAR21(0),
.VAR300(0),
.VAR69(0),... | gpl-2.0 |
Murailab-arch/magukara | boards/ecp3versa/rtl/ipexpress/ecp3/biosrom/biosrom.v | 11,912 | module MODULE1 (VAR9, VAR182, VAR41, VAR90, VAR141);
input wire [9:0] VAR9;
input wire VAR182;
input wire VAR41;
input wire VAR90;
output wire [15:0] VAR141;
wire VAR168;
wire VAR88;
VAR81 VAR187 (.VAR20(VAR168));
VAR136 VAR78 (.VAR20(VAR88));
VAR... | gpl-3.0 |
SymbiFlow/prjxray-experiments-archive-2017 | picorv32-v/top.v | 2,191 | module MODULE2(input clk, VAR37, VAR31, output do);
localparam integer VAR18 = 42;
localparam integer VAR29 = 79;
reg [VAR18-1:0] din;
wire [VAR29-1:0] dout;
reg [VAR18-1:0] VAR21;
reg [VAR29-1:0] VAR26;
always @(posedge clk) begin
VAR21 <= {VAR21, VAR31};
VAR26 <= {VAR26, VAR21[VAR18-1]};
if (VAR37) begin
din <= VAR21... | isc |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_xbar_0/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_wdata_router.v | 6,675 | module MODULE1 #
(
parameter VAR11 = "none", parameter integer VAR19 = 1, parameter integer VAR13 = 1, parameter integer VAR10 = 1, parameter integer VAR22 = 0 )
(
input wire VAR31,
input wire VAR3,
input wire [VAR19-1:0] VAR18,
input wire VAR21,
input wire VAR6,
output wire VAR28,
output wire [VAR19-1:0] VAR25, output... | bsd-2-clause |
hydai/Verilog-Practice | DigitalDesign/SYN/hw5/fifo_ctr_syn.v | 6,240 | module MODULE1 ( clk, VAR121, VAR23, VAR59, VAR61, VAR98, VAR163,
VAR87, VAR72, VAR82, VAR148, VAR153, addr );
output [4:0] addr;
input clk, VAR121, VAR23, VAR59;
output VAR61, VAR98, VAR163, VAR87, VAR72, VAR82, VAR148, VAR153;
wire \VAR30[0] , VAR106, VAR85, VAR144, VAR84, VAR45, VAR92, VAR184, VAR111, VAR132, VAR177... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.pp.symbol.v | 1,291 | module MODULE1 (
input VAR3 ,
input VAR4 ,
input VAR5 ,
output VAR9,
output VAR6 ,
input VAR8 ,
input VAR7,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3.behavioral.v | 1,371 | module MODULE1 (
VAR6,
VAR3,
VAR7,
VAR10
);
output VAR6;
input VAR3;
input VAR7;
input VAR10;
supply1 VAR2;
supply0 VAR8;
supply1 VAR11 ;
supply0 VAR9 ;
wire VAR5;
and VAR4 (VAR5, VAR10, VAR3, VAR7 );
buf VAR1 (VAR6 , VAR5 );
endmodule | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GDAN8M8P2_syn.v | 8,421 | module MODULE1 ( VAR257, VAR50, VAR31, VAR185 );
input [15:0] VAR50;
input [15:0] VAR31;
output [16:0] VAR185;
input VAR257;
wire VAR259, VAR102, VAR65, VAR27, VAR80, VAR246, VAR314, VAR307, VAR2, VAR150, VAR41, VAR164, VAR212, VAR155,
VAR232, VAR115, VAR301, VAR215, VAR156, VAR199, VAR55, VAR293, VAR292, VAR63, VAR172... | apache-2.0 |
horia141/bachelor-thesis | prj/components/PushBtn/PushBtnInterface.v | 1,453 | module MODULE1(VAR2,reset,VAR5,VAR4);
parameter VAR3 = 40000;
parameter VAR6 = 16;
input wire VAR2;
input wire reset;
input wire VAR5;
output wire VAR4;
reg [VAR6-1:0] VAR7;
reg VAR8;
reg VAR1;
assign VAR4 = VAR1;
always @ (posedge VAR2) begin
if (reset) begin
VAR7 <= 0;
VAR8 <= 0;
VAR1 <= 0;
end
else begin
if (VAR5) b... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1.symbol.v | 1,360 | module MODULE1 (
input [3:0] VAR1,
output VAR2,
input [3:0] VAR7
);
supply1 VAR4;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_timer_cpu_s0.v | 6,809 | module MODULE1 (
address,
VAR15,
clk,
VAR2,
VAR28,
VAR21,
irq,
VAR17
)
;
output irq;
output [ 15: 0] VAR17;
input [ 2: 0] address;
input VAR15;
input clk;
input VAR2;
input VAR28;
input [ 15: 0] VAR21;
wire VAR31;
wire VAR30;
wire VAR14;
reg [ 3: 0] VAR13;
wire VAR9;
reg VAR5;
wire VAR11;
wire [ 31: 0] VAR24;
reg [ 31:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4/sky130_fd_sc_hd__or4_2.v | 2,231 | module MODULE2 (
VAR5 ,
VAR9 ,
VAR6 ,
VAR11 ,
VAR10 ,
VAR7,
VAR8,
VAR3 ,
VAR4
);
output VAR5 ;
input VAR9 ;
input VAR6 ;
input VAR11 ;
input VAR10 ;
input VAR7;
input VAR8;
input VAR3 ;
input VAR4 ;
VAR2 VAR1 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_dds_1.v | 3,435 | module MODULE1 #(
parameter VAR18 = 1,
parameter VAR13 = 16,
parameter VAR21 = 16) (
input clk,
input [VAR21-1:0] VAR25,
input [ 15:0] VAR9,
output reg [VAR13-1:0] VAR17);
localparam VAR28 = 1;
localparam VAR16 = 2;
wire [ VAR13-1:0] VAR10;
wire [VAR13+17:0] VAR7;
generate
if (VAR18 == VAR28) begin
VAR3 #(
.VAR6(VAR13)... | mit |
sabertazimi/hust-lab | verilog/labs/lab5/src/Mealy_FSM_ROM.v | 1,969 | module MODULE1(
input clk,
input reset,
input VAR2,
output reg [2:0] VAR3
);
reg [2:0] state, VAR4;
reg [5:0] VAR9 [0:11];
parameter VAR1 = 0, VAR10 = 1, VAR5 = 2, VAR6 = 3, VAR8 = 4, VAR7 = 5; | mit |
AngelTerrones/MUSB | Hardware/musb/musb_ifid_register.v | 2,145 | module MODULE1(
input clk, input rst, input [31:0] VAR4, input [31:0] VAR2, input [31:0] VAR6, input VAR11, input VAR3, input VAR12, input VAR5, output reg [31:0] VAR1, output reg [31:0] VAR7, output reg [31:0] VAR10, output reg VAR8, output reg VAR9 );
always @(posedge clk) begin
VAR1 <= (rst) ? 32'b0 : ((VAR5) ? VAR1... | mit |
csturton/wirepatch | system/hardware/cores/arbiter/arbiter_ibus.v | 10,185 | module MODULE1
(
VAR43,
VAR53,
VAR63,
VAR27,
VAR7,
VAR58,
VAR25,
VAR68,
VAR10,
VAR2,
VAR17,
VAR31,
VAR36,
VAR48,
VAR64,
VAR37,
VAR29,
VAR52,
VAR34,
VAR5,
VAR55,
VAR1,
VAR46,
VAR61,
VAR32,
VAR39,
VAR42,
VAR24,
VAR51,
VAR49,
VAR69,
VAR40,
VAR8,
VAR22,
VAR56,
VAR12,
VAR13,
VAR44
);
parameter VAR35 = 32;
parameter VAR57 = ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.functional.pp.v | 1,081 | module MODULE1( VAR12, VAR6, VAR14, VAR13, VAR7, VAR4, VAR10 );
input VAR14, VAR6, VAR12, VAR7, VAR4, VAR10;
output VAR13;
or VAR1( VAR9, VAR6, VAR12 );
VAR8( VAR3, 1'b0, 1'b0, VAR14, VAR9, VAR10 );
wire VAR11;
not VAR2( VAR11, VAR3 );
or VAR5( VAR13, VAR14, VAR11 );
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/s3_ddr_iob.v | 3,617 | module MODULE1(
VAR22,
VAR4,
VAR8,
VAR32,
VAR17,
VAR3,
VAR9,
reset);
inout VAR22;
input VAR4;
input VAR8;
input VAR17;
input VAR3;
input VAR9;
input reset;
output VAR32;
parameter VAR11 = 1'b0;
parameter VAR21 = 1'b1;
wire VAR24; wire VAR30; wire VAR18; wire VAR19;
assign VAR19 = ~ VAR9;
VAR6 VAR35
(.VAR2 (VAR30),
.VAR... | lgpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/sym_gen_4byte.v | 14,993 | module MODULE1
(
VAR1,
VAR26,
VAR28,
VAR9,
VAR21,
VAR5,
VAR27,
VAR3,
VAR11,
VAR16,
VAR7,
VAR12,
VAR25,
VAR18,
VAR15
);
input [0:1] VAR1; input [0:1] VAR26; input [0:1] VAR28; input [0:31] VAR9; input [0:1] VAR21; input VAR5;
input VAR27; input [0:3] VAR3; input [0:3] VAR11; input [0:3] VAR16;
input VAR7; input VAR12;
o... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/diode/sky130_fd_sc_ms__diode.blackbox.v | 1,214 | module MODULE1 (
VAR3
);
input VAR3;
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
merckhung/zet | cores/flash/flash16_dack.v | 2,957 | module MODULE1 #(
parameter VAR20 = 4
)
(
input VAR11,
input VAR2,
input [15:0] VAR4,
output [15:0] VAR18,
input VAR1,
input VAR8, input [ 1:0] VAR15,
input VAR13,
input VAR14,
output VAR16,
output [21:0] VAR17,
input [15:0] VAR10,
output VAR7,
output VAR12,
output VAR9,
output VAR5
);
wire VAR19;
wire VAR3;
reg [21:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha_1.v | 2,184 | module MODULE2 (
VAR4,
VAR1 ,
VAR9 ,
VAR6 ,
VAR8,
VAR5,
VAR10 ,
VAR7
);
output VAR4;
output VAR1 ;
input VAR9 ;
input VAR6 ;
input VAR8;
input VAR5;
input VAR10 ;
input VAR7 ;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7)
);
endmodule
module MODULE2... | apache-2.0 |
cpulabs/mist1032sa | src/dps/dps.v | 6,267 | module MODULE1(
input wire VAR34,
input wire VAR55, input wire VAR44,
input wire VAR78,
input wire [1:0] VAR19, input wire VAR77,
input wire VAR68,
input wire [1:0] VAR80,
input wire VAR10,
output wire VAR39,
input wire VAR71, input wire [31:0] VAR45,
input wire [31:0] VAR75,
output wire VAR58,
output wire [31:0] VAR57... | bsd-2-clause |
jairov4/accel-oil | solution_kintex7/impl/ip/hdl/verilog/nfa_accept_samples_generic_hw_indices_stride_if.v | 44,519 | module MODULE1
VAR104 = 1,
VAR162 = 32,
VAR15 = 32,
VAR52 = 1,
VAR143 = 1,
VAR18 = 1,
VAR61 = 1,
VAR59 = 1,
VAR89 = 8,
VAR129 = 32'h00000000,
VAR134 = 1'b0,
VAR76 = 3'b000,
VAR135 = 4'b0011
)(
input wire VAR79,
input wire VAR94,
output wire [VAR104-1:0] VAR27,
output wire [VAR162-1:0] VAR109,
output wire [7:0] VAR64,
o... | lgpl-3.0 |
eda-globetrotter/PicenoDecoders | viterbi/syn/src/viterbidec.v | 5,177 | module MODULE1 (VAR10, VAR9, clk, reset);
output VAR10;
input [1:0] VAR9;
input clk;
input reset;
wire VAR10;
wire [1:0] VAR17,VAR4,VAR22,VAR21;
wire [1:0] VAR25,VAR8,VAR32,VAR19;
wire VAR31,VAR2,VAR14,VAR15;
wire [3:0] VAR3,VAR7,VAR1,VAR18;
wire [3:0] VAR6, VAR29, VAR20, VAR30;
VAR23 VAR27 (VAR9[0], VAR9[1],
VAR17,VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor3/sky130_fd_sc_ls__xor3.symbol.v | 1,309 | module MODULE1 (
input VAR8,
input VAR7,
input VAR2,
output VAR4
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi/bench/verilog/wb_master_model.v | 5,722 | module MODULE1(clk, rst, VAR6, din, dout, VAR2, VAR1, VAR7, sel, ack, VAR5, VAR3);
parameter VAR9 = 32;
parameter VAR8 = 32;
input clk, rst;
output [VAR8 -1:0] VAR6;
input [VAR9 -1:0] din;
output [VAR9 -1:0] dout;
output VAR2, VAR1;
output VAR7;
output [VAR9/8 -1:0] sel;
input ack, VAR5, VAR3;
reg [VAR8 -1:0] VAR6;
reg... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_1_to_n_tagged.v | 1,392 | module MODULE1 #(
parameter VAR6(VAR16)
,parameter VAR14 = VAR8(VAR16)
)
(input VAR10
, input VAR15
, input VAR13
, input [VAR14-1:0] VAR2
, output VAR17
, output [VAR16-1:0] VAR19
, input [VAR16-1:0] VAR1
);
wire VAR18 = VAR10;
wire VAR7 = VAR15;
if (VAR16 == 1)
begin : VAR3
assign VAR19 = VAR13;
assign VAR17 = VAR1 &... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o.symbol.v | 1,367 | module MODULE1 (
input VAR6,
input VAR9,
input VAR7,
input VAR3,
output VAR5
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v | 2,583 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR10 ,
VAR2 ,
VAR4 ,
VAR12,
VAR6 ,
VAR7 ,
VAR11 ,
VAR9
);
output VAR3 ;
input VAR8 ;
input VAR10 ;
input VAR2 ;
input VAR4 ;
input VAR12;
input VAR6 ;
input VAR7 ;
input VAR11 ;
input VAR9 ;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR12(VAR12),
.VA... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/v7_enet_top.v | 4,051 | module MODULE1(
input VAR19,
input VAR37,
input VAR12,
output VAR20,
output [7:0] VAR41,
output VAR50,
output VAR42,
output VAR16,
input [7:0] VAR33,
input VAR13,
input VAR31,
input VAR29,
input VAR47,
input VAR44,
input VAR22,
input VAR40, input VAR28, output VAR32, output VAR10, input VAR15, input VAR26,
output VAR7,... | mit |
richard42/CoCo3FPGA | COCO3GEN.v | 6,743 | module MODULE1 (
address,
VAR32,
VAR14);
input [10:0] address;
input VAR32;
output [7:0] VAR14;
tri1 VAR32;
wire [7:0] VAR12;
wire [7:0] VAR14 = VAR12[7:0];
VAR7 VAR37 (
.VAR9 (VAR32),
.VAR11 (address),
.VAR50 (VAR12),
.VAR22 (1'b0),
.VAR21 (1'b0),
.VAR35 (1'b1),
.VAR29 (1'b0),
.VAR44 (1'b0),
.VAR30 (1'b1),
.VAR26 (1'b... | bsd-3-clause |
alexforencich/verilog-ethernet | rtl/eth_arb_mux.v | 13,246 | module MODULE1 #
(
parameter VAR27 = 4,
parameter VAR39 = 8,
parameter VAR40 = (VAR39>8),
parameter VAR14 = (VAR39/8),
parameter VAR93 = 0,
parameter VAR31 = 8,
parameter VAR24 = 0,
parameter VAR19 = 8,
parameter VAR20 = 1,
parameter VAR88 = 1,
parameter VAR25 = 0,
parameter VAR69 = 1
)
(
input wire clk,
input wire rst... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/oq_reg_instances.v | 40,786 | module MODULE1
parameter VAR128 = 13,
parameter VAR94 = 8,
parameter VAR36 = 2,
parameter VAR134 = 8,
parameter VAR170 = VAR20(VAR134),
parameter VAR35 = 11,
parameter VAR72 = VAR35-VAR20(VAR94),
parameter VAR144 = 2048/VAR94, parameter VAR168 = 60/VAR94 + 1,
parameter VAR23 = VAR20((2**VAR128)/VAR168)
)
(
output [VAR1... | apache-2.0 |
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