repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18.functional.pp.v | 1,866 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR6,
VAR1,
VAR3 ,
VAR12
);
output VAR9 ;
input VAR2 ;
input VAR6;
input VAR1;
input VAR3 ;
input VAR12 ;
wire VAR5 ;
wire VAR4;
buf VAR7 (VAR5 , VAR2 );
VAR8 VAR11 (VAR4, VAR5, VAR6, VAR1);
buf VAR10 (VAR9 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a.functional.pp.v | 2,188 | module MODULE1 (
VAR17 ,
VAR5 ,
VAR15 ,
VAR10 ,
VAR18 ,
VAR11 ,
VAR9,
VAR14,
VAR12 ,
VAR19
);
output VAR17 ;
input VAR5 ;
input VAR15 ;
input VAR10 ;
input VAR18 ;
input VAR11 ;
input VAR9;
input VAR14;
input VAR12 ;
input VAR19 ;
wire VAR8 ;
wire VAR7 ;
wire VAR4 ;
wire VAR16;
or VAR20 (VAR8 , VAR15, VAR5, VAR10 );
or... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_fpu_intfloat_conv_except.v | 5,439 | module MODULE1
(
clk, VAR20, VAR19, VAR28, VAR12, VAR25, VAR8, VAR1, VAR15,
VAR17, VAR26, VAR13, VAR16, VAR4, VAR6
);
input clk;
input [31:0] VAR20, VAR19;
output VAR28, VAR12, VAR25, VAR8, VAR1, VAR15;
output VAR17, VAR26;
output VAR13, VAR16;
output VAR4;
output VAR6;
wire [7:0] VAR21, VAR29; wire [22:0] VAR11, VAR5;... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_13.v | 11,426 | module MODULE3 (
clk,
reset,
VAR89,
VAR49,
VAR40,
VAR10,
VAR12
);
parameter VAR74 = 18;
parameter VAR24 = 13;
parameter VAR88 = 7;
localparam VAR16 = 14;
input clk;
input reset;
input VAR89;
input VAR49;
input [VAR74-1:0] VAR40; output VAR10;
output [VAR74-1:0] VAR12;
localparam VAR35 = 18; localparam VAR53 = 36; local... | mit |
RGD2/swapforth | j1a/icestorm/uart.v | 4,543 | module MODULE3(
input wire clk,
output wire VAR19);
localparam VAR13 = (VAR9 / VAR24) - 1;
localparam VAR6 = VAR28(VAR13);
wire [VAR6-1:0] VAR18 = VAR13;
reg [VAR6-1:0] counter;
assign VAR19 = (counter == VAR18);
always @(posedge clk)
counter <= VAR19 ? 0 : (counter + 1);
endmodule
module MODULE4(
input wire clk,
input... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbp/sky130_fd_sc_lp__sdfbbp.functional.pp.v | 2,572 | module MODULE1 (
VAR4 ,
VAR23 ,
VAR2 ,
VAR10 ,
VAR17 ,
VAR18 ,
VAR14 ,
VAR5,
VAR20 ,
VAR1 ,
VAR21 ,
VAR24
);
output VAR4 ;
output VAR23 ;
input VAR2 ;
input VAR10 ;
input VAR17 ;
input VAR18 ;
input VAR14 ;
input VAR5;
input VAR20 ;
input VAR1 ;
input VAR21 ;
input VAR24 ;
wire VAR9 ;
wire VAR7 ;
wire VAR16 ;
wire VAR1... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_multiplexer.v | 16,422 | module MODULE1
parameter VAR19 = 128,
parameter VAR52 = 12,
parameter VAR17 = 5,
parameter VAR20 = "VAR27",
parameter VAR65 = 10
)
(
input VAR31,
input VAR38,
input [VAR52-1:0] VAR12, input [(VAR52*VAR26)-1:0] VAR50, input [(VAR52*VAR35)-1:0] VAR15, input [(VAR52*VAR19)-1:0] VAR22, output [VAR52-1:0] VAR1, output [VAR5... | gpl-3.0 |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/synth/design_1_auto_pc_0.v | 15,739 | module MODULE1 (
VAR95,
VAR90,
VAR111,
VAR67,
VAR102,
VAR47,
VAR1,
VAR9,
VAR97,
VAR76,
VAR86,
VAR83,
VAR3,
VAR36,
VAR56,
VAR18,
VAR53,
VAR93,
VAR29,
VAR60,
VAR43,
VAR2,
VAR31,
VAR49,
VAR42,
VAR65,
VAR78,
VAR92,
VAR79,
VAR15,
VAR30,
VAR98,
VAR84,
VAR71,
VAR66,
VAR17,
VAR110,
VAR8,
VAR69,
VAR94,
VAR51,
VAR85,
VAR32,
VAR4... | gpl-3.0 |
asicguy/gplgpu | hdl/de/dex_reg.v | 47,462 | module MODULE1
(
input VAR118,
input VAR218,
input [159:0] VAR54,
input VAR29,
input VAR16,
input VAR197,
input VAR150,
input VAR206,
input VAR196,
input VAR36,
input [4:0] VAR180,
input [4:0] VAR121,
input [3:0] VAR34,
input [1:0] VAR60,
input VAR149,
input VAR236,
input VAR11,
input VAR49,
input VAR107,
input [3:0] V... | gpl-3.0 |
RECS-Tsukuba/fpga-filter-hardware | filter.v | 6,101 | module MODULE1 #(
parameter VAR51 = 32,
parameter VAR46 = 32,
parameter VAR43 = 2
) (
output reg VAR35, VAR13,
output reg VAR33, VAR28,
output reg VAR19,
output [VAR51 - 1: 0] VAR50, VAR52,
output reg [VAR43 - 1: 0] VAR16,
output reg [VAR46 - 1: 0] VAR41,
output reg VAR21,
output reg [31:0] VAR1,
output reg [31:0] VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3.pp.blackbox.v | 1,291 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR3;
input VAR4;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/FIFO_OPENFLOW/ram_128_49.v | 9,593 | module MODULE1 (
VAR62,
VAR16,
VAR21,
VAR47,
VAR59,
VAR27,
VAR9,
VAR31);
input VAR62;
input VAR16;
input [48:0] VAR21;
input [6:0] VAR47;
input VAR59;
input [6:0] VAR27;
input VAR9;
output [48:0] VAR31;
tri0 VAR62;
tri1 VAR16;
tri1 VAR59;
tri0 VAR9;
wire [48:0] VAR4;
wire [48:0] VAR31 = VAR4[48:0];
VAR40 VAR10 (
.VAR29... | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Lab8/CLK_DIV.v | 1,264 | module MODULE1(VAR15, VAR12, VAR3, VAR1, VAR13, clk);
input clk;
output VAR15, VAR12, VAR3, VAR1, VAR13;
wire VAR15, VAR12;
reg VAR3, VAR1, VAR13;
wire VAR16, VAR8, VAR14;
reg [15:0] VAR11;
wire [15:0] VAR9;
reg [5:0] VAR6, VAR4;
reg [25:0] VAR5, VAR7;
reg [25:0] VAR10, VAR2;
always @( posedge clk)begin
VAR11 <= VAR9;
... | mit |
mlab-upenn/pvs | hdl_harness/TopLevel.v | 8,468 | module MODULE1(
VAR77,
VAR87,
VAR32,
VAR60
);
input VAR77;
output [7:0] VAR87;
inout [33:0] VAR32;
input [1:0] VAR60;
wire VAR12; wire VAR36;
wire VAR52;
wire VAR69;
wire VAR39;
wire VAR26;
wire VAR7;
wire VAR84;
wire VAR20;
wire VAR17;
wire VAR15;
wire VAR48;
wire VAR18;
wire VAR23;
wire VAR25;
wire VAR88;
wire VAR30;... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/ethmac/eth_macstatus.v | 12,137 | module MODULE1(
VAR6, VAR25, VAR21, VAR48, VAR8, VAR32,
VAR7, VAR26, VAR34, VAR23, VAR53, VAR46, VAR31,
VAR2, VAR10, VAR13, VAR56,
VAR36, VAR24, VAR44, VAR15, VAR28, VAR49,
VAR27, VAR12, VAR20, VAR54, VAR22, VAR55, VAR37,
VAR4, VAR33, VAR45, VAR11, VAR1, VAR5, VAR52,
VAR43, VAR30, VAR14, VAR35, VAR50, VAR41, VAR19,
VAR... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/udp_reg_master.v | 5,782 | module MODULE1
parameter VAR8 = 0,
parameter VAR4 = 127,
parameter VAR27 = 'VAR18 VAR7,
parameter VAR5 = 2
)
(
input VAR20,
output reg VAR13,
input VAR26,
input [VAR29 - 1:0] VAR28,
output reg [VAR12 - 1:0]VAR24,
input [VAR12 - 1:0] VAR16,
output reg VAR14,
output reg VAR10,
output reg VAR2,
output reg [VAR29 - 1:0] VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2b/sky130_fd_sc_lp__and2b.behavioral.pp.v | 1,934 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR12 ,
VAR2,
VAR7,
VAR5 ,
VAR15
);
output VAR10 ;
input VAR3 ;
input VAR12 ;
input VAR2;
input VAR7;
input VAR5 ;
input VAR15 ;
wire VAR11 ;
wire VAR4 ;
wire VAR1;
not VAR14 (VAR11 , VAR3 );
and VAR8 (VAR4 , VAR11, VAR12 );
VAR9 VAR13 (VAR1, VAR4, VAR2, VAR7);
buf VAR6 (VAR10 , VAR1 );
... | apache-2.0 |
whitef0x0/EECE353-Lab4 | vga_adapter.v | 13,792 | module MODULE1(
VAR4,
VAR72,
VAR32,
VAR6, VAR8, VAR74,
VAR35,
VAR61,
VAR22,
VAR57,
VAR24,
VAR63,
VAR67,
VAR44);
parameter VAR33 = 1;
parameter VAR1 = "VAR13";
parameter VAR73 = "320x240";
parameter VAR15 = "VAR38.VAR51";
parameter VAR50 = "VAR13";
input VAR4;
input VAR72;
input [((VAR1 == "VAR30") ? (0) : (VAR33*3-1)):... | mit |
sehugg/8bitworkshop | presets/verilog-vga/scoreboard.v | 2,204 | module MODULE1(reset, VAR19, VAR15, VAR21, VAR6, VAR1);
input reset;
output reg [3:0] VAR19;
output reg [3:0] VAR15;
input VAR6;
output reg [3:0] VAR21;
input VAR1;
always @(posedge VAR6 or posedge reset)
begin
if (reset) begin
VAR19 <= 0;
VAR15 <= 0;
end else if (VAR19 == 9) begin
VAR19 <= 0;
VAR15 <= VAR15 + 1;
end e... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/pickle_40/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v | 2,364 | if (VAR21 == VAR13 && VAR32 == VAR12) \
begin: VAR9 \
VAR14 \
VAR11 \
(.VAR3 (VAR3) \
,.VAR1 (VAR1) \
,.VAR19 (VAR19) \
,.VAR6 (VAR6) \
,.VAR8 (VAR8) \
,.VAR17 (VAR17) \
,.VAR18 (VAR18) \
,.VAR25 (VAR25) \
); \
end: VAR9
module MODULE1 #( parameter VAR27(VAR21 )
, parameter VAR27(VAR32 )
, parameter VAR30 = VAR5(VAR21)... | bsd-3-clause |
kyzhai/NUNY | src/hardware/pass_new.v | 6,400 | module MODULE1 (
address,
VAR35,
VAR47);
input [11:0] address;
input VAR35;
output [11:0] VAR47;
tri1 VAR35;
wire [11:0] VAR37;
wire [11:0] VAR47 = VAR37[11:0];
VAR12 VAR43 (
.VAR36 (address),
.VAR20 (VAR35),
.VAR29 (VAR37),
.VAR13 (1'b0),
.VAR26 (1'b0),
.VAR25 (1'b1),
.VAR51 (1'b0),
.VAR33 (1'b0),
.VAR11 (1'b1),
.VAR9... | gpl-2.0 |
nyaxt/dmix | ise/tepla/ipcore_dir/nkmd_ddr3/example_design/rtl/infrastructure.v | 10,767 | module MODULE1 #
(
parameter VAR35 = 2500,
parameter VAR50 = 1,
parameter VAR76 = "VAR65",
parameter VAR19 = 1,
parameter VAR6 = 1,
parameter VAR17 = 16,
parameter VAR13 = 8,
parameter VAR53 = 2,
parameter VAR62 = 1
)
(
input VAR41,
input VAR71,
input VAR125,
input VAR105,
output VAR25,
output VAR107,
output VAR116,
ou... | mit |
bigeagle/riffa | fpga/riffa_hdl/riffa.v | 31,390 | module MODULE1
parameter VAR108 = 128,
parameter VAR94 = 12,
parameter VAR8 = 512, parameter VAR212 = 5, parameter VAR121 = "VAR21",
parameter VAR128 = "VAR93",
parameter VAR251 = 10
)
(
input VAR16,
input VAR282,
output VAR288,
input [VAR108-1:0] VAR105,
input VAR28,
input [(VAR108/32)-1:0] VAR284,
input VAR36,
input ... | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4SharedKES_v1_0_0/8069a058/src/d_KES_PE_ELU_NMLodr.v | 5,779 | module MODULE1 (
input wire VAR29,
input wire VAR12,
input wire VAR27,
input wire VAR26,
input wire [VAR20-1:0] VAR21,
input wire [VAR20-1:0] VAR28,
input wire [VAR20-1:0] VAR14,
input wire [VAR20-1:0] VAR5,
input wire [VAR20-1:0] VAR4,
input wire VAR17,
output reg [VAR20-1:0] VAR22,
output reg VAR18,
output reg [VAR20... | gpl-3.0 |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part6a/DE1_displ.v | 1,116 | module MODULE1 (
output reg [0:3] VAR3,
output reg [0:6] VAR2,
input wire [0:6] VAR10,
input wire [0:6] VAR11,
input wire [0:6] VAR7,
input wire [0:6] VAR9,
input wire clk
);
parameter
VAR5 = 2'b00,
VAR8 = 2'b01,
VAR4 = 2'b10,
VAR6 = 2'b11;
reg [1:0] state;
reg [1:0] VAR1;
always @* begin
VAR1 = state;
case (state)
VAR... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o31ai/sky130_fd_sc_hdll__o31ai.functional.v | 1,455 | module MODULE1 (
VAR2 ,
VAR1,
VAR5,
VAR6,
VAR9
);
output VAR2 ;
input VAR1;
input VAR5;
input VAR6;
input VAR9;
wire VAR7 ;
wire VAR10;
or VAR8 (VAR7 , VAR5, VAR1, VAR6 );
nand VAR4 (VAR10, VAR9, VAR7 );
buf VAR3 (VAR2 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.v | 2,601 | module MODULE1 (
VAR11 ,
VAR5 ,
VAR4 ,
VAR9 ,
VAR8 ,
VAR7,
VAR2 ,
VAR3 ,
VAR6 ,
VAR12
);
output VAR11 ;
output VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR8 ;
input VAR7;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR12 ;
VAR10 VAR1 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2... | apache-2.0 |
manu3193/TextEditor | text_editor_top.v | 18,903 | module MODULE1(
VAR119, VAR38, VAR96, VAR39, VAR4, VAR21, VAR24, VAR140, VAR67, VAR63, VAR51, VAR125, VAR123, VAR76, VAR6,
VAR90, VAR45, VAR13, VAR19, VAR142, VAR95, VAR65, VAR97, VAR108, VAR87, VAR32, VAR132, VAR34, VAR131, VAR16, VAR59, VAR89, VAR114, VAR115 );
input VAR21;
input VAR24;
inout VAR34, VAR131;
output VA... | mit |
cr88192/bgbtech_bjx1core | bjx1c32b1/DecOp3.v | 35,650 | module MODULE1(
clk,
VAR180,
VAR16,
VAR355,
VAR300,
VAR94,
VAR223,
VAR107,
VAR364,
VAR341
);
parameter VAR271 = 0; parameter VAR97 = 0; parameter VAR229 = 1;
input clk; input[47:0] VAR180; input[15:0] VAR16;
output[6:0] VAR355;
output[6:0] VAR300;
output[6:0] VAR94;
output[31:0] VAR223;
output[3:0] VAR107;
output[3:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkbuf/sky130_fd_sc_hd__clkbuf.behavioral.pp.v | 1,772 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR2,
VAR3,
VAR12 ,
VAR7
);
output VAR8 ;
input VAR6 ;
input VAR2;
input VAR3;
input VAR12 ;
input VAR7 ;
wire VAR10 ;
wire VAR5;
buf VAR1 (VAR10 , VAR6 );
VAR9 VAR11 (VAR5, VAR10, VAR2, VAR3);
buf VAR4 (VAR8 , VAR5 );
endmodule | apache-2.0 |
Lan-Hekary/ARM | memory.v | 2,771 | module MODULE1(input [31:0] VAR2,output reg [31:0] VAR4);
reg [31:0]VAR1[0:31];
integer VAR3; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and3/sky130_fd_sc_hvl__and3.pp.blackbox.v | 1,291 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR8 ,
VAR5 ,
VAR3,
VAR2,
VAR1 ,
VAR6
);
output VAR4 ;
input VAR7 ;
input VAR8 ;
input VAR5 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/basys3/abacus/bin_to_decimal.v | 1,101 | module MODULE1(
input [15:0] VAR2,
output reg [19:0] VAR4
);
reg [35:0] VAR1;
integer VAR3;
always @(*)
begin
for(VAR3 = 0; VAR3 <= 35; VAR3 = VAR3+1)
VAR1[VAR3] = 0;
VAR1[18:3] = VAR2;
repeat(13)
begin
if(VAR1[19:16] > 4)
VAR1[19:16] = VAR1[19:16] + 3;
if(VAR1[23:20] > 4)
VAR1[23:20] = VAR1[23:20] + 3;
if(VAR1[27:24] ... | apache-2.0 |
pdear/verilib | components/src/components-shiftreg.v | 1,496 | module MODULE1 #(
parameter VAR5 = 8,
parameter VAR8 = 0
) (
input clk,
input rst,
input VAR7,
input VAR9,
input [VAR5-1:0] VAR4,
input VAR3,
output [VAR5-1:0] VAR6,
output VAR1
);
reg [VAR5-1:0] VAR2;
always @(posedge clk) begin
if (rst == 1'b1)
VAR2 <= VAR8;
end
else if (VAR9 == 1'b1)
VAR2 <= VAR4;
else if (VAR7 == 1... | lgpl-3.0 |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/eeprom_v1_07_a/hdl/verilog/OWM.v | 6,606 | module MODULE1 (
VAR92, VAR83, VAR15, VAR36, VAR87, VAR70, VAR37, VAR72,
VAR78, VAR54, VAR91,
VAR57, VAR8, VAR61, VAR24, VAR18, VAR45, VAR48, VAR39,
VAR47, VAR28, VAR1, VAR49, VAR31, VAR75, VAR69, VAR55,
VAR82, VAR59, VAR46, VAR88, VAR14, VAR42, VAR73, VAR65);
input [2:0] VAR92; input VAR83; input VAR15; input VAR36; i... | bsd-2-clause |
wilsonxiao/machinekit | src/hal/drivers/pluto_servo_firmware/wdt.v | 1,240 | module MODULE1(clk, VAR4, VAR5, out);
input clk, VAR4, VAR5;
output out;
reg [6:0] VAR1;
wire VAR2 = (VAR1 == 7'd127);
reg VAR3;
wire out = VAR3 && VAR2;
always @(posedge clk) begin
if(VAR4) begin
VAR3 <= 1;
VAR1 <= 0;
end else if(VAR5 && !VAR2) VAR1 <= VAR1 + 7'd1;
end
endmodule | gpl-3.0 |
TokiSeven/schoolMIPS | board/nexys4_ddr/nexys4_ddr.v | 2,196 | module MODULE1
(
input VAR18,
input VAR27,
input VAR45,
input VAR43,
input VAR40,
input VAR42,
input VAR33,
input [15:0] VAR2,
output [15:0] VAR37,
output VAR10,
output VAR21,
output VAR47,
output VAR8,
output VAR14,
output VAR36,
output VAR34,
output VAR25,
output VAR1,
output VAR19,
output VAR46,
output VAR5,
output ... | mit |
asicguy/gplgpu | hdl/altera_plls/spll_bb.v | 12,190 | module MODULE1 (
VAR2,
VAR3,
VAR4,
VAR1,
VAR5);
input VAR2;
input VAR3;
output VAR4;
output VAR1;
output VAR5;
tri0 VAR2;
endmodule | gpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/txc_engine_ultrascale.v | 22,328 | module MODULE2
parameter VAR55 = 128,
parameter VAR157 = 1,
parameter VAR169 = 1,
parameter VAR53 = 10,
parameter VAR85 = 256
)
(
input VAR84,
input VAR97,
input [VAR1-1:0] VAR148,
input VAR122,
output VAR145,
output VAR99,
output [VAR55-1:0] VAR139,
output [(VAR55/32)-1:0] VAR116,
output [VAR113-1:0] VAR77,
input VAR9... | bsd-3-clause |
meteorcloudy/CPU_verilog | sccpu.v | 1,229 | module MODULE1;
reg clk;
reg VAR1;
wire [31:0] VAR6;
wire [31:0] VAR4;
wire [31:0] VAR10;
wire [31:0] VAR5;
wire [31:0] VAR8;
wire VAR11;
wire VAR2;
wire VAR3;
wire [1:0] VAR12;
VAR9 VAR7 (
.clk(clk),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc.pp.blackbox.v | 1,355 | module MODULE1 (
VAR2 ,
VAR5,
VAR4 ,
VAR7 ,
VAR1 ,
VAR6 ,
VAR3
);
output VAR2 ;
input VAR5;
input VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab02/lab02/Code/Display.v | 1,285 | module MODULE1(input clk,
input rst,
input VAR21,
input VAR26,
input VAR3,
input [31:0]VAR7,
input [7:0]VAR28,
input [7:0]VAR20,
output VAR5,
output VAR22,
output VAR11,
output VAR1
);
wire [63:0]VAR15,VAR17,VAR29;
assign VAR29 = VAR26 ? VAR15 : VAR17;
VAR23 VAR19(.VAR7(VAR7),
.VAR4(VAR28),
.VAR20(VAR20),
.VAR3(VAR3),
... | gpl-3.0 |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/hls_contrast_streeOg.v | 1,310 | module MODULE2(
input [9 - 1:0] VAR3,
input [23 - 1:0] VAR6,
input [31 - 1:0] VAR1,
output [32 - 1:0] dout);
wire signed [25 - 1:0] VAR15;
wire signed [18 - 1:0] VAR16;
wire signed [48 - 1:0] VAR8;
wire signed [43 - 1:0] VAR4;
wire signed [48 - 1:0] VAR13;
assign VAR15 = (VAR6);
assign VAR16 = (VAR3);
assign VAR8 = (VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai.behavioral.pp.v | 2,191 | module MODULE1 (
VAR17 ,
VAR6 ,
VAR13 ,
VAR10 ,
VAR11 ,
VAR2 ,
VAR20,
VAR4,
VAR5 ,
VAR9
);
output VAR17 ;
input VAR6 ;
input VAR13 ;
input VAR10 ;
input VAR11 ;
input VAR2 ;
input VAR20;
input VAR4;
input VAR5 ;
input VAR9 ;
wire VAR19 ;
wire VAR8 ;
wire VAR12 ;
wire VAR18;
nor VAR14 (VAR19 , VAR10, VAR6, VAR13 );
nor ... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v | 55,196 | module MODULE1
VAR212 = 2,
VAR143 = 2, VAR48 = 16, VAR61 = 16, VAR91 = 12, VAR78 = 3, VAR151 = 1,
VAR164 = 3,
VAR7 = 2,
VAR46 = 2,
VAR41 = 8,
VAR95 = 4,
VAR55 = 4,
VAR9 = 1,
VAR193 = 2,
VAR207 = 5,
VAR165 = 5,
VAR134 = 5,
VAR136 = 4,
VAR39 = 4,
VAR77 = 2
)
(
VAR161,
VAR26,
VAR180,
VAR102,
VAR10,
VAR195,
VAR34,
VAR211,
... | gpl-3.0 |
open-power/snap | hardware/hdl/nvme/nvme_host_wrap.v | 7,739 | module MODULE1
(
input wire VAR55,
input wire VAR63,
input wire [VAR66 - 1:0] VAR30,
input wire VAR23,
output wire VAR5,
input wire [31:0] VAR19,
input wire [3:0] VAR50,
input wire VAR6,
output wire VAR54,
output wire [1:0] VAR16,
output wire VAR45,
input wire VAR58,
input wire [VAR66 - 1:0] VAR73,
input wire VAR10,
ou... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/delay_calc.v | 3,071 | module MODULE1 (
VAR4,
rst,
VAR3,
VAR5,
VAR6,
VAR7,
VAR9,
VAR8,
VAR10,
VAR11
);
input VAR4;
input rst;
input [6:0] VAR3;
input [6:0] VAR5;
input [5:0] VAR6;
input VAR7;
output [5:0] VAR9;
output [5:0] VAR8;
output [5:0] VAR10;
output VAR11;
reg [5:0] VAR9;
reg [7:0] VAR1;
reg [7:0] VAR2;
always @(posedge VAR4) begin
if... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o.behavioral.v | 1,952 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR5 ,
VAR13 ,
VAR12,
VAR9
);
output VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR5 ;
input VAR13 ;
input VAR12;
input VAR9;
wire VAR5 VAR2 ;
wire VAR3 ;
wire VAR16;
and VAR7 (VAR2 , VAR6, VAR8, VAR1, VAR5 );
or VAR11 (VAR3 , VAR2, VAR13 );
VAR15 VAR14 (VAR16, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp_2.v | 2,441 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR2,
VAR4 ,
VAR8 ,
VAR10 ,
VAR5
);
output VAR9 ;
output VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR2;
input VAR4 ;
input VAR8 ;
input VAR10 ;
input VAR5 ;
VAR3 VAR7 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10)... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/ip_pcie/source/PCIeGen2x8If128_qpll_drp.v | 20,800 | module MODULE1 #
(
parameter VAR83 = "VAR1", parameter VAR73 = "3.0", parameter VAR62 = "VAR5", parameter VAR32 = 0, parameter VAR77 = 2'd3, parameter VAR23 = 3'd6
)
(
input VAR3,
input VAR26,
input VAR52,
input VAR31,
input VAR68,
input VAR50,
input [15:0] VAR84,
input VAR15,
output [ 7:0] VAR20,
output VAR37,
output ... | mit |
SymbiFlow/yosys-symbiflow-plugins | ql-qlf-plugin/qlf_k6n10f/brams_map.v | 6,864 | module \VAR26 (VAR18, VAR23, VAR3, VAR38, VAR22, VAR5, VAR28, VAR14);
parameter VAR10 = 10;
parameter VAR35 = 36;
parameter VAR24 = 4;
parameter VAR41 = 1;
parameter VAR1 = 1;
parameter [36863:0] VAR7 = 36864'VAR51;
input VAR18;
input VAR23;
input [VAR10-1:0] VAR3;
output [VAR35-1:0] VAR38;
input VAR22;
input [VAR10-1:... | isc |
alexforencich/xfcp | lib/eth/example/AU50/fpga_10g/rtl/fpga.v | 15,983 | module MODULE1 (
output wire VAR219,
output wire VAR60,
output wire VAR255,
output wire VAR267,
output wire VAR211,
output wire VAR298,
input wire VAR92,
input wire VAR88,
output wire VAR75,
output wire VAR243,
input wire VAR287,
input wire VAR206,
output wire VAR274,
output wire VAR265,
input wire VAR244,
input wire V... | mit |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/bram/bram_stub.v | 1,262 | module MODULE1(VAR2, VAR3, VAR5, VAR7, VAR1, VAR4, VAR6)
;
input VAR2;
input [0:0]VAR3;
input [10:0]VAR5;
input [15:0]VAR7;
input VAR1;
input [10:0]VAR4;
output [15:0]VAR6;
endmodule | gpl-2.0 |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/alu.v | 1,226 | module MODULE1 (VAR6, VAR4, VAR9, VAR2, clk, VAR1, VAR5);
input [3:0] VAR6;
input [31:0] VAR4, VAR9;
input clk;
output [31:0] VAR1;
output [31:0] VAR5;
output reg [31:0] VAR2;
reg [63:0] VAR8;
reg [31:0] VAR7, VAR3;
assign VAR1 = VAR7[31:0];
assign VAR5 = VAR3[31:0]; | mit |
ultraembedded/riscv | top_cache_axi/src_v/dcache_axi.v | 10,973 | module MODULE2
parameter VAR2 = 0
)
(
input VAR80
,input VAR12
,input VAR83
,input VAR54
,input VAR49
,input [ 1:0] VAR29
,input [ 3:0] VAR86
,input VAR41
,input VAR61
,input [ 31:0] VAR53
,input [ 1:0] VAR44
,input [ 3:0] VAR47
,input VAR74
,input [ 3:0] VAR84
,input VAR42
,input [ 7:0] VAR26
,input [ 31:0] VAR60
,inp... | bsd-3-clause |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v | 5,685 | module MODULE1 #
(
parameter integer VAR45 = 4
)
(
input wire clk,
input wire reset,
output wire [VAR45-1:0] VAR51,
output wire [1:0] VAR22,
output wire VAR32,
input wire VAR12,
input wire [1:0] VAR38,
input wire VAR21,
output wire VAR50,
input wire VAR35,
input wire [VAR45-1:0] VAR9,
input wire [7:0] VAR33,
input wire... | gpl-3.0 |
mbus/mbus | m3_mbus_releases/r04p2g/source/lname_mbus_member_ctrl.tsmc180.pmu.v | 11,958 | module MODULE1 (
input VAR57,
input VAR134,
input VAR117,
input VAR32,
input VAR133,
output VAR16,
output VAR105,
input VAR27,
input VAR5,
output VAR46,
output VAR132,
output VAR81,
output VAR66,
output VAR20,
output VAR115,
input VAR101,
output VAR123,
input VAR114,
input VAR89,
input [3:0] VAR64,
output [3:0] VAR13,
... | apache-2.0 |
GREO/GNU-Radio | usrp/fpga/megacells/accum32_bb.v | 1,626 | module MODULE1 (
VAR4,
VAR5,
VAR1,
VAR3,
VAR2);
input [31:0] VAR4;
input VAR5;
input VAR1;
input VAR3;
output [31:0] VAR2;
endmodule | gpl-3.0 |
lbl-cal/StanfordNoC | router/src/clib/c_mat_mult.v | 2,964 | module MODULE1
(VAR12, VAR16, VAR20);
parameter VAR4 = 1;
parameter VAR5 = 1;
parameter VAR14 = 1;
parameter VAR22 = VAR1;
parameter VAR15 = VAR9;
input [0:VAR4*VAR5-1] VAR12;
input [0:VAR5*VAR14-1] VAR16;
output [0:VAR4*VAR14-1] VAR20;
wire [0:VAR4*VAR14-1] VAR20;
generate
genvar VAR2;
for(VAR2 = 0; VAR2 < VAR4; VAR2 ... | bsd-2-clause |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_spram_512x20.v | 13,808 | module MODULE1(
VAR39, VAR4, VAR20,
clk, rst, VAR14, VAR9, VAR55, addr, VAR8, VAR18
);
parameter VAR36 = VAR1;
parameter VAR54 = VAR10;
input VAR39;
input [VAR57 - 1:0] VAR20;
output VAR4;
input clk; input rst; input VAR14; input VAR9; input VAR55; input [VAR36-1:0] addr; input [VAR54-1:0] VAR8; output [VAR54-1:0] VAR1... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_impctl_clnew.v | 11,626 | module MODULE1(VAR17 ,VAR80 ,clk ,VAR76
,VAR25 ,VAR96 ,VAR4 ,VAR61 ,VAR13 ,VAR12 ,VAR66 ,
VAR63 ,VAR31 ,VAR64 ,VAR104 );
output [7:0] VAR61 ;
input [7:0] VAR12 ;
output VAR80 ;
output VAR25 ;
output VAR66 ;
output VAR31 ;
input VAR17 ;
input clk ;
input VAR76 ;
input VAR96 ;
input VAR4 ;
input VAR13 ;
input VAR63 ;
inp... | gpl-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/softint_mon.v | 21,717 | module MODULE1(
VAR6,
VAR14,
VAR5,
VAR19,
VAR9,
VAR15,
VAR20,
VAR16,
VAR21,
VAR11,
VAR13,
VAR18,
VAR7,
VAR3,
VAR10,
VAR2,
VAR24,
VAR17,
VAR8
);
input [16:0] VAR6;
input [16:0] VAR14;
input [16:0] VAR5;
input [16:0] VAR19;
input [16:0] VAR9;
input [3:0] VAR15;
input [3:0] VAR20;
input [3:0] VAR16;
input [3:0] VAR21;
inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv_12.v | 2,001 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR3,
VAR5,
VAR2 ,
VAR8
);
output VAR1 ;
input VAR4 ;
input VAR3;
input VAR5;
input VAR2 ;
input VAR8 ;
VAR7 VAR6 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR3;
supply0 VAR5;... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_du.v | 46,442 | module MODULE1(
clk, rst,
VAR207, VAR107, VAR25, VAR55,
VAR191, VAR196,
VAR170, VAR185, VAR135, VAR89,
VAR72, VAR199,
VAR2, VAR68, VAR92, VAR13, VAR198, VAR81,
VAR210, VAR47, VAR209, VAR73,
VAR188, VAR117, VAR128, VAR125, VAR193,
VAR213, VAR139, VAR127, VAR28, VAR150, VAR197,
VAR202, VAR99, VAR57, VAR52, VAR133, VAR126... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.blackbox.v | 1,212 | module MODULE1 (
VAR3 ,
VAR2,
VAR1,
VAR4
);
output VAR3 ;
input VAR2;
input VAR1;
input VAR4 ;
endmodule | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/bv_9_12/lookup.v | 2,423 | module MODULE1(
clk,
reset,
VAR14,
VAR2,
VAR29,
VAR22,
VAR18,
VAR5,
VAR4,
VAR24,
VAR19,
VAR36,
VAR25,
VAR7,
VAR9,
VAR28,
VAR12,
VAR11,
VAR17,
VAR15,
VAR35,
VAR23,
VAR21,
VAR6,
VAR31,
VAR32,
VAR16,
VAR1,
VAR3
);
input clk;
input reset;
input VAR14;
input [7:0] VAR2;
input [127:0] VAR29;
input [127:0] VAR22;
input [71:0]... | apache-2.0 |
medav/conware | conware_final/system/hdl/system_v_axi4s_vid_out_0_wrapper.v | 2,533 | module MODULE1
(
VAR35,
rst,
VAR15,
VAR17,
VAR18,
VAR10,
VAR8,
VAR7,
VAR4,
VAR14,
VAR29,
VAR23,
VAR2,
VAR27,
VAR32,
VAR31,
VAR25,
VAR28,
VAR21,
VAR34,
VAR11,
VAR6,
VAR26,
VAR30,
VAR22,
VAR12
);
input VAR35;
input rst;
input VAR15;
input VAR17;
input [31:0] VAR18;
input VAR10;
output VAR8;
input VAR7;
input VAR4;
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufbuf/sky130_fd_sc_hd__bufbuf.pp.blackbox.v | 1,245 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR4,
VAR6,
VAR1 ,
VAR2
);
output VAR5 ;
input VAR3 ;
input VAR4;
input VAR6;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_project/dpram_128_32x32_be/dpram_128_32x32_be.v | 9,036 | module MODULE1 (
VAR12,
VAR9,
VAR33,
VAR43,
VAR36,
VAR16,
VAR10,
VAR18);
input [127:0] VAR12;
input VAR9;
input [3:0] VAR33;
input [5:0] VAR43;
input [15:0] VAR36;
input VAR16;
input VAR10;
output [31:0] VAR18;
wire [31:0] VAR14;
wire [31:0] VAR18 = VAR14[31:0];
VAR21 VAR28 (
.VAR40 (VAR9),
.VAR1 (VAR16),
.VAR29 (VAR10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi_4.v | 2,366 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR10 ,
VAR11 ,
VAR8 ,
VAR6,
VAR2,
VAR5 ,
VAR9
);
output VAR1 ;
input VAR7 ;
input VAR10 ;
input VAR11 ;
input VAR8 ;
input VAR6;
input VAR2;
input VAR5 ;
input VAR9 ;
VAR4 VAR3 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp.symbol.v | 1,413 | module MODULE1 (
input VAR8 ,
output VAR9 ,
output VAR1 ,
input VAR5,
input VAR6
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/hls_contrast_stredEe.v | 1,312 | module MODULE1(
input [8 - 1:0] VAR11,
input [23 - 1:0] VAR8,
input [29 - 1:0] VAR7,
output [30 - 1:0] dout);
wire signed [25 - 1:0] VAR13;
wire signed [18 - 1:0] VAR3;
wire signed [48 - 1:0] VAR17;
wire signed [43 - 1:0] VAR15;
wire signed [48 - 1:0] VAR1;
assign VAR13 = (VAR8);
assign VAR3 = (VAR11);
assign VAR17 = (... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_bram_7vx_cpl.v | 7,282 | module MODULE1 #(
parameter VAR19 = "VAR34", parameter VAR10 = "VAR29", parameter VAR33 = "500 VAR11", parameter VAR43 = "16 VAR45"
) (
input VAR41, input VAR12,
input [9:0] VAR2, input [9:0] VAR32, input [9:0] VAR15, input [9:0] VAR18, input [127:0] VAR6, input [15:0] VAR17, input VAR31, input VAR39, input VAR37, inpu... | gpl-3.0 |
olajep/oh | src/common/hdl/oh_clockgate.v | 1,185 | module MODULE1 (
input clk, input VAR12, input en, output VAR7 );
localparam VAR1 = VAR6;
generate
if(VAR1)
begin : VAR10
VAR4 VAR2 (.en(en),
.VAR12(VAR12),
.clk(clk),
.VAR7(VAR7));
end
else
begin : VAR3
wire VAR8;
wire VAR9;
assign VAR9 = en | VAR12;
VAR5 VAR11 (.out (VAR8),
.in (VAR9),
.clk (clk));
assign VAR7 = clk ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2_2.v | 2,132 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR1 ,
VAR3,
VAR5,
VAR4 ,
VAR6
);
output VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR3;
input VAR5;
input VAR4 ;
input VAR6 ;
VAR8 VAR7 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR2,
VAR9,
VAR1
);
output VAR2;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa_m.v | 2,275 | module MODULE1 (
VAR7,
VAR11 ,
VAR1 ,
VAR2 ,
VAR5 ,
VAR10,
VAR8,
VAR6 ,
VAR9
);
output VAR7;
output VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR10;
input VAR8;
input VAR6 ;
input VAR9 ;
VAR3 VAR4 (
.VAR7(VAR7),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR6(VAR6),
.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1.behavioral.pp.v | 1,733 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR3,
VAR8
);
output VAR10 ;
input VAR5 ;
input VAR3;
input VAR8;
wire VAR9 ;
wire VAR1;
buf VAR6 (VAR9 , VAR5 );
VAR2 VAR4 (VAR1, VAR9, VAR3, VAR8);
buf VAR7 (VAR10 , VAR1 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/thrfsm_mon.v | 12,940 | module MODULE1(
clk, VAR2, VAR24, VAR20, VAR13, VAR23,
VAR15, VAR6, VAR25, VAR10, VAR19,
VAR8, VAR5, VAR7, VAR22, VAR18, VAR21,
VAR1, VAR4, VAR26, VAR17, VAR28,
VAR16, VAR14, VAR12
);
input clk;
input VAR2;
input [3:0] VAR24;
input [3:0] VAR20;
input [3:0] VAR13;
input [4:0] VAR23;
input [4:0] VAR15;
input [4:0] VAR6;
... | gpl-2.0 |
dutra/vgacontroller | pll/pll_0002.v | 2,064 | module MODULE1(
input wire VAR8,
input wire rst,
output wire VAR7,
output wire VAR47
);
VAR36 #(
.VAR56("false"),
.VAR45("50.0 VAR19"),
.VAR21("VAR72"),
.VAR53(1),
.VAR64("40.0 VAR19"),
.VAR58("0 VAR11"),
.VAR40(50),
.VAR52("0 VAR19"),
.VAR50("0 VAR11"),
.VAR71(50),
.VAR57("0 VAR19"),
.VAR31("0 VAR11"),
.VAR22(50),
.VA... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_add_double.v | 1,512 | module MODULE1 (
VAR3,
VAR6,
VAR13,
VAR15,
VAR7,
enable);
input enable;
input VAR3, VAR6;
input [63:0] VAR13;
input [63:0] VAR15;
output [63:0] VAR7;
VAR12 VAR1(
.VAR3(VAR3),
.VAR6(VAR6),
.VAR13(VAR13),
.VAR15(VAR15),
.VAR7(VAR7),
.VAR9(),
.VAR10(),
.VAR8(),
.VAR5(),
.enable(enable));
endmodule | mit |
P3Stor/P3Stor | DDR3/phy/phy_clock_io.v | 4,869 | module MODULE1 #
(
parameter VAR16 = 100, parameter VAR3 = 2, parameter VAR5 = "VAR2", parameter VAR7 = "VAR14", parameter VAR13 = 300.0, parameter VAR8 = "VAR6" )
(
input VAR12, input clk, input rst, output [VAR3-1:0] VAR9, output [VAR3-1:0] VAR15 );
generate
genvar VAR1;
for (VAR1 = 0; VAR1 < VAR3; VAR1 = VAR1 + 1) b... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb_4.v | 2,323 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR9 ,
VAR3 ,
VAR8 ,
VAR1,
VAR5,
VAR2 ,
VAR10
);
output VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR1;
input VAR5;
input VAR2 ;
input VAR10 ;
VAR11 VAR4 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10... | apache-2.0 |
asicguy/gplgpu | hdl/de3d/des_smtri.v | 11,398 | module MODULE1
(
input VAR22,
input VAR17,
input VAR3,
input VAR34,
input VAR26,
input [1:0] VAR58,
input VAR7,
input VAR8,
input VAR48,
input VAR33,
input VAR64,
input [255:0] VAR6,
output reg VAR50,
output reg VAR42,
output reg VAR40,
output reg signed [15:0] VAR23, output reg signed [15:0] VAR9, output reg [7:0] VAR... | gpl-3.0 |
Cognoscan/BoostDSP | verilog/src/sigmaDelta/SigmaDelta2ndOrder.v | 2,779 | module MODULE1 #(
parameter VAR11 = 16, parameter VAR8 = 7.0/6.0, parameter VAR6 = 2, parameter VAR9 = 0 )
(
input clk,
input rst,
input en,
input signed [VAR11-1:0] in,
output VAR1
);
localparam integer VAR7 = 2.0**(VAR11-1);
localparam integer VAR3 = 2.0**(VAR11-1)*VAR8;
localparam VAR2 = VAR11+VAR6;
localparam VAR4 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp.pp.blackbox.v | 1,289 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3 ,
VAR5,
VAR7,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR5;
input VAR7;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_cmos_pad.v | 3,876 | module MODULE1(VAR12 ,VAR30 ,VAR23 ,VAR6 ,VAR2 ,VAR36 ,
VAR40 ,VAR32 ,VAR49 ,VAR35 ,VAR3 ,
VAR22 ,VAR1 ,VAR43 ,VAR28 ,VAR13, VAR45 );
output VAR1 ;
output VAR43 ;
input VAR12 ;
input VAR30 ;
input VAR23 ;
input VAR6 ;
input VAR2 ;
input VAR36 ;
input VAR40 ;
input VAR32 ;
input VAR49 ;
input VAR35 ;
input VAR3 ;
input ... | gpl-2.0 |
cynngah/virtualsynthesizer | gui.v | 5,673 | module MODULE2(VAR21,
reset,
VAR34,
VAR31,
VAR30,
VAR32,
VAR13,
VAR29);
input VAR21;
input reset;
input [3:0] VAR34;
output [2:0] VAR30;
output [7:0] VAR32;
output [6:0] VAR13;
output VAR29;
wire VAR14;
wire [3:0] VAR25;
wire [14:0] VAR28;
MODULE3 MODULE2(
.VAR21(VAR21),
.reset(reset),
.VAR29(VAR29),
.VAR34(VAR34),
.VA... | mit |
vipinkmenon/scas | hw/fpga/source/memory_if/v7_ddr_top.v | 50,413 | module MODULE1 #
(
parameter VAR23 = 3,
parameter VAR38 = 1,
parameter VAR120 = 10,
parameter VAR88 = 1,
parameter VAR135 = 1,
parameter VAR72 = 1,
parameter VAR44 = 4,
parameter VAR42 = 6,
parameter VAR21 = 8,
parameter VAR195 = 8,
parameter VAR124 = 64,
parameter VAR9 = 8,
parameter VAR52 = 3,
parameter VAR162 = 8,
p... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms2/kc705/system_top.v | 9,159 | module MODULE1 (
VAR35,
VAR93,
VAR2,
VAR30,
VAR77,
VAR40,
VAR4,
VAR107,
VAR38,
VAR65,
VAR56,
VAR110,
VAR1,
VAR98,
VAR75,
VAR39,
VAR101,
VAR5,
VAR32,
VAR72,
VAR99,
VAR11,
VAR50,
VAR96,
VAR25,
VAR76,
VAR20,
VAR55,
VAR26,
VAR68,
VAR105,
VAR92,
VAR111,
VAR108,
VAR60,
VAR74,
VAR82,
VAR73,
VAR70,
VAR46,
VAR42,
VAR87,
VAR51,
... | gpl-3.0 |
Elphel/x393_sata | x393/util_modules/fifo_cross_clocks.v | 5,993 | module MODULE1
parameter integer VAR4=16,
parameter integer VAR6=4 ) (
input rst, input VAR21, input VAR24, input VAR27, input VAR15, input VAR13, input VAR12, input [VAR4-1:0] VAR7, output [VAR4-1:0] VAR8, output VAR2, output VAR17 );
localparam integer VAR1=(1<<VAR6)-1;
reg [VAR4-1:0] VAR20 [0:VAR1];
reg [VAR6-1:0] V... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/CAM_monitor.v | 9,918 | module MODULE1
(
input clk,
input [3:0] VAR40,
input [11:0] VAR20,
input VAR53,
input reset,
output VAR49,
input VAR55,
input [3:0] VAR26,
input [31:0] VAR39,
input VAR52,
output VAR23,
output VAR27,
input VAR5,
input VAR21
);
parameter VAR46 = VAR17;
wire [11:0] VAR3;
wire [3:0] VAR15;
reg VAR6;
reg VAR12;
wire [31:0]... | mit |
amerc/TCP3 | NEXYS3/server.v | 357,698 | module MODULE1(VAR43,VAR46,VAR26,VAR21,VAR28,VAR50,clk,rst,VAR34,VAR31,VAR6,VAR37,VAR20,VAR51);
integer VAR11;
real VAR15;
input [15:0] VAR43;
input [15:0] VAR46;
input VAR26;
input VAR21;
input VAR28;
input VAR50;
input clk;
input rst;
output [15:0] VAR34;
output [15:0] VAR31;
output VAR6;
output VAR37;
output VAR20;
... | mit |
seyedmaysamlavasani/GorillaPP | chisel/Gorilla++/verilog/Top-harness-augmented-k-means.v | 1,836 | module MODULE1;
reg clk = 0;
reg reset = 1; | bsd-3-clause |
apotocnik/redpitaya_guide | projects/4_frequency_counter/signal_decoder.v | 1,624 | module MODULE1 #
(
parameter VAR1 = 14,
parameter VAR5 = 32,
parameter VAR4 = 4 )
(
input [VAR5-1:0] VAR6,
input VAR2,
input clk,
input rst,
output reg [7:0] VAR7
);
wire [2:0] VAR3;
assign VAR3 = VAR6[VAR1-VAR4-1:VAR1-VAR4-3];
always @(posedge clk)
if (~rst)
VAR7 <= 8'hFF;
else
case (VAR3)
3'b011 : VAR7 <= 8'b00000001... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi.behavioral.pp.v | 1,934 | module MODULE1 (
VAR12,
VAR10,
VAR7 ,
VAR11 ,
VAR4 ,
VAR8
);
input VAR12;
input VAR10;
output VAR7 ;
input VAR11 ;
input VAR4 ;
input VAR8 ;
wire VAR14 ;
wire VAR13 ;
wire VAR6;
and VAR9 (VAR14 , VAR11, VAR4 );
nor VAR5 (VAR13 , VAR8, VAR14 );
VAR3 VAR2 (VAR6, VAR13, VAR12, VAR10);
buf VAR1 (VAR7 , VAR6 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_4.behavioral.v | 2,113 | module MODULE1( VAR9, VAR10, VAR4 );
input VAR9, VAR10;
output VAR4;
reg VAR6;
VAR11 VAR7(.VAR9(VAR9),.VAR10(VAR10),.VAR4(VAR4),.VAR6(VAR6));
VAR11 VAR3(.VAR9(VAR9),.VAR10(VAR10),.VAR4(VAR4),.VAR6(VAR6));
not VAR5(VAR8,VAR10);
buf VAR1(VAR2,VAR10); | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v | 35,440 | module MODULE1 (
output wire VAR98, input wire VAR238, output wire VAR43, output wire [31:0] VAR58, output wire VAR160, input wire [0:0] VAR235, input wire [31:0] VAR119, input wire [10:0] VAR110, input wire VAR136, input wire VAR42, input wire [3:0] VAR125, input wire VAR213, output wire VAR256, output wire VAR134, in... | mit |
ychaim/FPGA-Litecoin-Miner | source/ltcminer.v | 6,076 | module MODULE1 (VAR33); else
module MODULE1 (VAR33, VAR3);
parameter VAR11 = VAR11;
parameter VAR11 = 25;
parameter VAR32 = VAR32;
parameter VAR32 = 1;
input VAR33;
output reg [7:0]VAR3; VAR43
wire VAR10;
VAR5 #(.VAR11(VAR11)) VAR8 (VAR33, VAR10);
assign VAR10 = VAR33;
reg [255:0] VAR31 = 256'd0;
reg [255:0] VAR21 = 25... | gpl-3.0 |
mbus/mbus | mbus_example/verilog/layer_ctrl.v | 19,810 | module MODULE1(
VAR62,
VAR35,
VAR74,
VAR80,
VAR34,
VAR37,
VAR17,
VAR58,
VAR102,
VAR65,
VAR15,
VAR88,
VAR67,
VAR95,
VAR69,
VAR20,
VAR71,
VAR93,
VAR97,
VAR98,
VAR28,
VAR3,
VAR46,
VAR42,
VAR89,
VAR18,
VAR52,
VAR22,
VAR87,
VAR12,
VAR55,
VAR4
);
parameter VAR23 = 24;
parameter VAR47 = 8; parameter VAR51 = 128;
parameter VAR... | apache-2.0 |
oblivioncth/DE0-Verilog-Processor | src/ID 10 Handler.v | 1,093 | module MODULE1 (VAR4,VAR7,VAR2);
input [13:0] VAR4;
output reg [15:0] VAR2;
output reg [25:0] VAR7;
always begin
case (VAR4[13:9])
5'VAR1: begin assign VAR7 = {8'b01100000,VAR4[10:8],14'b000101};
assign VAR2={VAR4[7],VAR4[7],VAR4[7],VAR4[7],VAR4[7],VAR4[7],VAR4[7],VAR4[7],VAR4[7:0]}; end 5'VAR3: begin assign VAR7 = {8'... | mit |
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