repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s.pp.symbol.v | 1,358 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR3 ,
input VAR5,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb_2.v | 2,323 | module MODULE2 (
VAR10 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR5 ,
VAR4,
VAR1,
VAR7 ,
VAR2
);
output VAR10 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR5 ;
input VAR4;
input VAR1;
input VAR7 ;
input VAR2 ;
VAR6 VAR11 (
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_sram_addr.v | 2,228 | module MODULE1 (
address,
VAR8,
clk,
VAR3,
VAR4,
VAR5,
VAR9,
VAR6
)
;
output [ 10: 0] VAR9;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR3;
input VAR4;
input [ 31: 0] VAR5;
wire VAR1;
reg [ 10: 0] VAR2;
wire [ 10: 0] VAR9;
wire [ 10: 0] VAR7;
wire [ 31: 0] VAR6;
assign VAR1 = 1;
assign V... | gpl-3.0 |
Triple-Z/COExperiment_Repo | Project_2_OC/RegisterFileOnBoard/regfile_display.v | 6,801 | module MODULE1(
input clk,
input VAR43,
input VAR42,
input [1:0] VAR11,
output VAR15,
output VAR6, output VAR32, output VAR1, output VAR5,
output VAR8,
output VAR28,
output VAR35,
output VAR12,
output VAR31,
inout[15:0] VAR7,
output VAR13,
inout VAR29,
inout VAR34,
output VAR41,
output VAR26
);
assign VAR15 = VAR42;
as... | mit |
calee0219/Course | DLAB/Lab07/ipcore_dir/Lab07_IP.v | 24,885 | module MODULE2 (
clk, VAR246, VAR265
);
input clk;
output [4 : 0] VAR246;
input [7 : 0] VAR265;
wire VAR7;
wire VAR292;
wire VAR302;
wire VAR82;
wire VAR320;
wire VAR103;
wire VAR52;
wire VAR14;
wire VAR28;
wire VAR175;
wire VAR11;
wire VAR105;
wire VAR291;
wire VAR144;
wire VAR303;
wire VAR153;
wire VAR172;
wire VAR73... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s.functional.v | 1,345 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
wire VAR2;
buf VAR3 (VAR2, VAR4 );
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/system/synthesis/submodules/system_mm_interconnect_1.v | 16,432 | module MODULE1 (
input wire VAR64, input wire VAR62, input wire [29:0] VAR1, output wire VAR31, input wire [0:0] VAR17, input wire [7:0] VAR86, input wire VAR11, output wire [63:0] VAR46, output wire VAR56, input wire VAR61, input wire [63:0] VAR100, input wire VAR85, output wire [3:0] VAR19, output wire VAR32, output ... | mit |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_uart/qmfir_240MHz/ISE_project/sasc_brg.v | 1,705 | module MODULE1(
VAR7, VAR5,
clk, VAR2
);
output VAR7; output VAR5;
input clk;
input VAR2;
reg VAR7;
reg VAR5;
parameter VAR1 = 103; parameter VAR11 = 319; parameter VAR4 = 479; parameter VAR6 = 173; parameter VAR9 = 260;
reg [8:0] VAR10;
reg [1:0] VAR8;
always @ (posedge clk or negedge VAR2)
if (~VAR2)
VAR10 <= 0;
else... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/conb/sky130_fd_sc_ms__conb.blackbox.v | 1,238 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
output VAR5;
supply1 VAR6;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
efabless/openlane | designs/aes128/src/aes128.v | 23,152 | module MODULE1(clk, state, VAR62, out);
input clk;
input [127:0] state, VAR62;
output [127:0] out;
reg [127:0] VAR10, VAR99;
wire [127:0] VAR79, VAR61, VAR64, VAR95, VAR48, VAR89, VAR46, VAR32, VAR66,
VAR81, VAR100, VAR12, VAR18, VAR78, VAR94, VAR50, VAR29, VAR3,
VAR73, VAR43, VAR68, VAR42, VAR21, VAR15, VAR5, VAR24, V... | apache-2.0 |
jotego/jt51 | hdl/jt51_lfo.v | 6,495 | module MODULE1(
input rst,
input clk,
input VAR19,
input [4:0] VAR50,
input [7:0] VAR9,
input [6:0] VAR24,
input [6:0] VAR56,
input [1:0] VAR26,
input VAR34,
input VAR5,
output reg VAR30,
output reg [7:0] VAR8,
output reg [7:0] VAR7
);
localparam [1:0] VAR39 = 2'd0,
VAR23 = 2'd1,
VAR25 = 2'd2,
VAR40 = 2'd3;
reg [14:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi.pp.blackbox.v | 1,391 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR8 ,
VAR3 ,
VAR1 ,
VAR4,
VAR5,
VAR2 ,
VAR9
);
output VAR6 ;
input VAR7 ;
input VAR8 ;
input VAR3 ;
input VAR1 ;
input VAR4;
input VAR5;
input VAR2 ;
input VAR9 ;
endmodule | apache-2.0 |
YoelRP/PROYECTO | bin/example/minialu.v | 6,579 | module MODULE1
(
input wire VAR32,
input wire VAR21,
output wire [7:0] VAR36
output wire VAR74,
output wire VAR52,
output wire VAR46,
output wire VAR23,
output wire VAR1
);
wire [15:0] VAR62,VAR40,VAR11;
reg VAR69,VAR64,VAR42,VAR63;
wire [27:0] VAR34;
wire [3:0] VAR24;
reg [15:0] VAR39;
wire [7:0] VAR30,VAR15,VAR71, VA... | gpl-3.0 |
bfarago/xmos_cpld_slice | doc/xmos_cpld_slice_empty.v | 2,063 | module MODULE1
(
VAR5,
VAR9,
VAR34,
VAR31,
VAR24,
VAR46,
VAR17,
VAR38,
VAR47,
VAR4,
VAR52,
VAR49,
VAR23,
VAR10,
VAR21,
VAR3,
VAR48,
VAR11,
VAR16,
VAR53,
VAR26,
VAR35,
VAR2,
VAR41,
VAR18,
VAR8,
VAR6,
VAR43,
VAR36,
VAR28,
VAR30,
VAR19,
VAR44,
VAR25,
VAR29,
VAR27,
VAR51,
VAR13,
VAR1,
VAR54,
VAR45,
VAR50,
VAR32,
VAR20,
VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31oi/sky130_fd_sc_ms__a31oi.pp.blackbox.v | 1,391 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR1 ,
VAR4 ,
VAR8 ,
VAR7,
VAR9,
VAR5 ,
VAR3
);
output VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR8 ;
input VAR7;
input VAR9;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/mpx/mpx_alu.v | 4,241 | module MODULE1
(
VAR1,
VAR6,
VAR3,
VAR4
);
input [31:0] VAR1 ;
input [31:0] VAR6 ;
input [3:0] VAR3 ;
output [31:0] VAR4 ;
reg [31:0] VAR4;
always @ (VAR3 or VAR1 or VAR6 )
begin
case (VAR3)
begin
if (VAR2(VAR1, VAR6) == 1'b1)
VAR4 = 32'h00000001;
end
else
VAR4 = 32'h00000000;
end
begin
if ((VAR2(VAR1, VAR6) == 1'b1) |... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/b9c82e235214f825/zynq_design_1_auto_pc_0_stub.v | 4,653 | module MODULE1(VAR60, VAR11, VAR42, VAR7,
VAR20, VAR39, VAR6, VAR3, VAR17, VAR33,
VAR51, VAR1, VAR29, VAR28, VAR10, VAR57,
VAR2, VAR24, VAR15, VAR46, VAR58, VAR8, VAR36,
VAR9, VAR4, VAR49, VAR50, VAR54, VAR37,
VAR19, VAR22, VAR38, VAR56, VAR27, VAR21,
VAR16, VAR26, VAR41, VAR34, VAR40, VAR47, VAR55,
VAR53, VAR32, VAR45... | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/interrupt_controller.v | 5,437 | module MODULE1 (
input VAR15, input VAR9, input VAR10, input VAR16, output VAR7, input VAR13, output VAR12, input VAR8, output VAR3 );
reg [2:0] VAR14=VAR18;
reg [2:0] VAR11=VAR18;
reg VAR19=0;
reg VAR2=0;
assign VAR7 = (VAR14 == VAR5);
assign VAR3 = VAR19;
assign VAR12 = VAR2;
always @(*) begin
case (VAR14)
if (VAR10)... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_dp_maca_r.v | 4,559 | module MODULE1(
VAR13, VAR3, VAR6,
VAR21, VAR28, VAR24,
VAR31, VAR2, VAR7, VAR17,
VAR33, VAR12
);
output [149:0] VAR13; output VAR3;
output VAR6;
input VAR21; input VAR28; input VAR24; input VAR31; input VAR2; input [149:0] VAR7; input VAR17;
input VAR33;
input VAR12;
wire VAR19;
wire [149:0] VAR32;
wire [149:0] VAR26,... | gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op_INPUT_STREAM_if.v | 11,201 | module MODULE1 (
input wire VAR84,
input wire VAR67,
input wire VAR29,
output wire VAR56,
input wire [23:0] VAR81,
input wire [2:0] VAR52,
input wire [2:0] VAR71,
input wire [0:0] VAR60,
input wire [0:0] VAR53,
input wire [0:0] VAR68,
input wire [0:0] VAR28,
output wire [23:0] VAR83,
output wire VAR72,
input wire VAR17... | gpl-2.0 |
Microsoft/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/Clock_module_FRL.v | 2,749 | module MODULE1(
input VAR14,
input rst,
output VAR19,
output VAR12
);
wire VAR2, VAR6;
wire VAR8, VAR18;
assign VAR12 = (~VAR2) & (~VAR6);
VAR16 VAR1(
.VAR5(VAR14),
.VAR7(rst),
.VAR15(VAR18),
.VAR3(VAR6)
);
VAR11 VAR9(
.VAR17(VAR18),
.VAR13(VAR19),
.VAR4(VAR8),
.VAR7(rst),
.VAR3(VAR2),
.VAR10()
);
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.behavioral.pp.v | 2,157 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR10 ,
VAR13,
VAR6 ,
VAR16 ,
VAR12 ,
VAR18
);
output VAR7 ;
input VAR8 ;
input VAR10 ;
input VAR13;
input VAR6 ;
input VAR16 ;
input VAR12 ;
input VAR18 ;
wire VAR1 ;
wire VAR2 ;
reg VAR14 ;
wire VAR11 ;
wire VAR3;
wire VAR21 ;
wire VAR9 ;
wire VAR20 ;
wire VAR5 ;
not VAR17 (VAR2 , VAR3 ... | apache-2.0 |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_SMP_CORE.v | 7,937 | module MODULE1 #(
parameter VAR31 = 0,
parameter VAR36 = 0
) (
output wire VAR38, input wire VAR50, output wire [11:0] VAR16, output wire [20:0] VAR15, output wire [3:0] VAR28, output wire [2:0] VAR37, output wire [1:0] VAR26, output wire [1:0] VAR25, output wire [3:0] VAR45, output wire [2:0] VAR44, output wire VAR40,... | gpl-2.0 |
somethingnew2-0/CS552-CPU | RoadRunner/off_by_one.tar.gz_extracted/CacheController.v | 3,947 | module MODULE1(clk, VAR3, VAR8, VAR14, VAR4, VAR28, VAR24, read, write, VAR20, VAR18, VAR13, VAR16, VAR17, VAR30, VAR1, VAR23, VAR15, VAR10, VAR6, VAR19, VAR5, VAR12, VAR9, VAR21, VAR25, VAR27);
input clk, VAR3, VAR20, VAR18, VAR13, VAR16, VAR28, VAR24, read, write;
input [7:0] VAR17;
input [15:0] VAR8, VAR14, VAR4;
in... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_17.v | 14,058 | module MODULE4 (
clk,
reset,
VAR99,
VAR73,
VAR105,
VAR35,
VAR48
);
parameter VAR64 = 18;
parameter VAR7 = 17;
parameter VAR43 = 9;
localparam VAR57 = 18;
input clk;
input reset;
input VAR99;
input VAR73;
input [VAR64-1:0] VAR105; output VAR35;
output [VAR64-1:0] VAR48;
localparam VAR66 = 18; localparam VAR93 = 36; loca... | mit |
theapi/de0-nano | vga/vga_800x480_buffered/vga.v | 2,288 | module MODULE1(
VAR25,
VAR21,
VAR34,
VAR12,
VAR6,
VAR37,
VAR24
);
input wire VAR25;
input wire [0:0] VAR21;
output wire VAR34;
output wire VAR12;
output wire VAR6;
output wire VAR37;
output wire VAR24;
wire VAR22;
wire VAR9;
wire VAR7;
wire VAR27;
wire [15:0] VAR30;
wire [10:0] VAR8;
wire [10:0] VAR11;
wire [15:0] VAR2... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/i2c/rtl/i2c_buf.v | 5,851 | module MODULE1 (
VAR30, VAR29, VAR9, VAR40, VAR25,
VAR22, clk, VAR26, VAR16, VAR24,
VAR15
);
parameter VAR36 = 8;
parameter VAR1 = 64; parameter VAR12 = 128; parameter VAR34 = 64;
input VAR22;
input clk;
input VAR26;
input [VAR36-1:0] VAR16;
output VAR30;
input VAR24;
output [VAR12-1:0] VAR29;
output VAR9;
input VAR15;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1.behavioral.v | 1,759 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR3,
VAR10
);
output VAR2 ;
input VAR8 ;
input VAR3;
input VAR10;
wire VAR6 ;
wire VAR1;
not VAR9 (VAR6 , VAR8 );
VAR5 VAR7 (VAR1, VAR6, VAR3, VAR10);
buf VAR4 (VAR2 , VAR1 );
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/DW_mult.v | 1,758 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR7,
input wire [VAR4-1:0] VAR3,
input wire [VAR4-1:0] VAR5,
output wire [2*VAR4-1:0] VAR10
);
reg [2*VAR4-1:0] VAR2;
always @* begin
VAR2 = VAR3 *VAR5 ;
end
VAR6 #(.VAR8(2*VAR4)) VAR11 ( .clk(clk),
.rst(rst),
.VAR1(VAR7),
.VAR12(VAR2),
.VAR9(VAR10)
);
endmod... | gpl-3.0 |
antmicro/yosys | techlibs/coolrunner2/cells_counter_map.v | 4,884 | module \VAR4 (VAR15, VAR10, VAR3, VAR14, VAR6, VAR9);
input wire VAR15;
input wire VAR10;
output wire VAR3;
output wire[VAR12-1:0] VAR14;
input wire VAR6;
input wire VAR9;
parameter VAR13 = 1;
parameter VAR11 = "VAR5";
parameter VAR2 = 0;
parameter VAR1 = 0;
parameter VAR7 = 0;
parameter VAR12 = 8;
parameter VAR8 = "VA... | isc |
mlarouche/sd2snes | verilog/sd2snes_cx4/dcm.v | 2,983 | module MODULE1 (
input VAR4,
output VAR20,
output VAR29,
input VAR25,
output[7:0] VAR8
);
VAR12 #(
.VAR21("VAR31"), .VAR22(2.0), .VAR23(1), .VAR40(4), .VAR39("VAR19"), .VAR7(41.667), .VAR35("VAR24"), .VAR11("VAR24"), .VAR30("VAR17"), .VAR15("VAR37"), .VAR36("VAR37"), .VAR14("VAR1"), .VAR34(16'hFFFF), .VAR9(0), .VAR10("... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x8_128/pci_express_compiler-library/altpcie_pll_15625_125.v | 10,115 | module MODULE1 (
VAR49,
VAR22,
VAR23);
input VAR49;
input VAR22;
output VAR23;
wire [5:0] VAR26;
wire [0:0] VAR10 = 1'h0;
wire [0:0] VAR51 = 1'h1;
wire [0:0] VAR25 = VAR26[0:0];
wire VAR23 = VAR25;
wire [5:0] VAR42 = {VAR10, VAR10, VAR10, VAR10, VAR10, VAR51};
wire VAR52 = VAR22;
wire [1:0] VAR47 = {VAR10, VAR52};
wire... | lgpl-3.0 |
varunnagpaal/Digital-Hardware-Modelling | tutorials/xilinx/hls/ug871-design-files/Using_IP_with_Zynq/lab1/hls_macc/vhls_prj/solution1/impl/ip/hdl/verilog/hls_macc.v | 8,249 | module MODULE1 (
VAR23,
VAR30,
VAR7,
VAR25,
VAR50,
VAR14,
VAR54,
VAR17,
VAR19,
VAR39,
VAR21,
VAR24,
VAR22,
VAR16,
VAR44,
VAR4,
VAR27,
VAR41,
VAR29,
interrupt
);
parameter VAR36 = 9'd1;
parameter VAR20 = 9'd2;
parameter VAR48 = 9'd4;
parameter VAR15 = 9'd8;
parameter VAR12 = 9'd16;
parameter VAR8 = 9'd32;
parameter VAR5... | mit |
swallat/yosys | techlibs/intel/common/brams_map.v | 4,325 | module \VAR1 (VAR8, VAR43, VAR60, VAR28, VAR13, VAR26, VAR16, VAR15);
parameter VAR6 = 8;
parameter VAR66 = 36;
parameter VAR69 = "1";
parameter VAR37 = "1";
parameter VAR72 = 1;
parameter VAR25 = 1;
input VAR8;
input VAR43;
output [VAR66-1:0] VAR28;
input [VAR6-1:0] VAR60;
input VAR13;
output [VAR66-1:0] VAR16;
input ... | isc |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_mem2reg.v | 12,626 | module MODULE1(addr, VAR24, VAR10, VAR12);
parameter VAR19 = VAR8;
input [1:0] addr;
input [VAR4-1:0] VAR24;
input [VAR19-1:0] VAR10;
output [VAR19-1:0] VAR12;
reg [7:0] VAR28;
reg [7:0] VAR6;
reg [7:0] VAR14;
reg [7:0] VAR25;
reg [VAR19-1:0] VAR1;
reg [3:0] VAR27, VAR20,
VAR13, VAR2;
assign VAR12 = {VAR28, VAR6, VAR14... | gpl-3.0 |
mshr-h/stopwatch_verilog | stopwatch.v | 1,456 | module MODULE1
(
input wire clk,
input wire VAR31,
input wire [1:0] VAR7,
output wire [7:0] VAR16,
output wire [7:0] VAR30,
output wire [7:0] VAR8,
output wire [7:0] VAR2
);
wire VAR6;
wire VAR23;
wire VAR17;
wire VAR32;
wire en;
wire [3:0] VAR10;
wire [3:0] VAR20;
wire [3:0] VAR5;
wire [3:0] VAR25;
wire VAR26;
wire VA... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_hdmi_rx.v | 10,584 | module MODULE1 (
VAR18,
VAR10,
VAR41,
VAR26,
VAR45,
VAR68,
VAR40,
VAR25,
VAR61,
VAR20,
VAR33,
VAR58,
VAR64,
VAR56,
VAR3,
VAR43,
VAR35,
VAR14,
VAR38,
VAR59,
VAR62,
VAR46,
VAR69,
VAR72,
VAR66,
VAR53,
VAR22,
VAR60);
localparam VAR65 = 32'h00040063;
parameter VAR1 = 0;
input VAR18;
output VAR10;
output VAR41;
output VAR26;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb_4.v | 2,314 | module MODULE1 (
VAR11 ,
VAR5 ,
VAR3 ,
VAR2 ,
VAR1 ,
VAR9,
VAR10,
VAR7 ,
VAR6
);
output VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR2 ;
input VAR1 ;
input VAR9;
input VAR10;
input VAR7 ;
input VAR6 ;
VAR4 VAR8 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR7(VAR7),
.... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_if_post_fifo.v | 8,567 | module MODULE1 #
(
parameter VAR18 = 100, parameter VAR19 = 4, parameter VAR9 = 32 )
(
input clk, input rst, input [3:0] VAR7,
input VAR16,
input [VAR9-1:0] din, output VAR31,
output VAR6,
output [VAR9-1:0] dout );
localparam VAR23
= (VAR19 == 2) ? 1 :
(((VAR19 == 3) || (VAR19 == 4)) ? 2 : 'VAR10);
integer VAR24;
reg [... | bsd-2-clause |
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s420.v | 8,957 | module MODULE1 (VAR208,VAR376,VAR455);
input VAR208,VAR455;
output VAR376;
wire VAR349,VAR66;
trireg VAR451,VAR109;
nmos VAR371 (VAR109,VAR455,VAR66);
not VAR7 (VAR349,VAR109);
nmos VAR421 (VAR451,VAR349,VAR208);
not VAR217 (VAR376,VAR451);
not VAR71 (VAR66,VAR208);
endmodule
module MODULE2(VAR86,VAR6,VAR208,VAR12,VAR1... | gpl-3.0 |
bgelb/digilite_zl | rtl/zl_lfsr.v | 1,772 | module MODULE1 #
(
parameter VAR8 = 0,
parameter VAR14 = 0,
parameter VAR3 = 0,
parameter VAR5 = 0
)
(
input clk,
input VAR6,
input VAR11,
input VAR4,
output [VAR14-1:0] VAR13,
output [VAR5-1:0] VAR2
);
reg [VAR14-1:0] VAR10;
reg [VAR14-1:0] VAR1;
reg [VAR5-1:0] VAR15;
integer VAR7;
function [VAR14-1:0] VAR12;
input [V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcin/sky130_fd_sc_hd__fahcin.functional.pp.v | 2,782 | module MODULE1 (
VAR19,
VAR21 ,
VAR8 ,
VAR12 ,
VAR16 ,
VAR28,
VAR4,
VAR26 ,
VAR22
);
output VAR19;
output VAR21 ;
input VAR8 ;
input VAR12 ;
input VAR16 ;
input VAR28;
input VAR4;
input VAR26 ;
input VAR22 ;
wire VAR7 ;
wire VAR11 ;
wire VAR17 ;
wire VAR18 ;
wire VAR23 ;
wire VAR2 ;
wire VAR10 ;
wire VAR5;
not VAR27 (V... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_mul_booth_4_block_rep.v | 3,224 | if ( VAR16 == VAR1 && VAR10 == VAR30 \
&& VAR5 == VAR13 && VAR9 == VAR20 && VAR31 == VAR6) \
begin : VAR33 \
VAR11 VAR3 (.*); \
end
module MODULE1 #(parameter [31:0] VAR1=1
,parameter VAR30=0
,parameter VAR13=0
,parameter VAR20=0
,parameter VAR6=0
)
( input [4:0][2:0] VAR19
, input VAR18
, input [VAR1-1:0][3:0][1:0] VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a_2.v | 2,422 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR11 ,
VAR9 ,
VAR4 ,
VAR6 ,
VAR3,
VAR2,
VAR12 ,
VAR10
);
output VAR7 ;
input VAR5 ;
input VAR11 ;
input VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR3;
input VAR2;
input VAR12 ;
input VAR10 ;
VAR8 VAR1 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi_4.v | 2,361 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR2 ,
VAR10 ,
VAR4 ,
VAR1,
VAR3,
VAR7 ,
VAR6
);
output VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR10 ;
input VAR4 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR6 ;
VAR11 VAR5 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/controller/rank_common.v | 15,522 | module MODULE1 #
(
parameter VAR68 = 100,
parameter VAR44 = "VAR40",
parameter VAR70 = 40,
parameter VAR11 = 4,
parameter VAR61 = 20,
parameter VAR52 = 2,
parameter VAR42 = 4,
parameter VAR37 = 39,
parameter VAR7 = 640000
)
(
VAR3, VAR13, VAR41, VAR28,
VAR83, VAR55, VAR35,
VAR12,
clk, rst, VAR16, VAR22, VAR63,
VAR1, VA... | lgpl-3.0 |
DreamSourceLab/DSLogic-hdl | src/sdramc/sdram_ctl.v | 29,653 | module MODULE1(
VAR144, VAR75,
VAR102, VAR129, VAR16, VAR72, VAR160,
VAR35, VAR115, VAR4, VAR134, VAR121,
VAR162, VAR51, VAR155, VAR66,
VAR33, VAR142, VAR135, VAR79, VAR39, VAR19, VAR11,
VAR20, VAR74, VAR38,
VAR34, VAR46,
VAR43, VAR112,
VAR118, VAR150, VAR77, VAR147,
VAR107, VAR17,
VAR67, VAR131, VAR3 );
input VAR144, ... | gpl-2.0 |
cmos3511/cmos_linux | python/pj/proj/rtl/LP/csa.v | 1,673 | module MODULE1(VAR10,VAR3,VAR11,VAR7,VAR9,VAR6,VAR5,VAR1);
parameter VAR2 = 16 ;
output [VAR2-1:0] VAR10,VAR3; output VAR11; input [VAR2-1:0] VAR7,VAR9,VAR6,VAR5; input VAR1;
wire [VAR2:0] VAR13 = {1'b0, VAR7 ^ VAR9 ^ VAR6 };
wire [VAR2:0] VAR4 = { VAR7&VAR9 | VAR7&VAR6 | VAR9&VAR6, VAR1 } ;
wire [VAR2:0] VAR14 = { 1'b... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fsb/bsg_front_side_bus_hop_out.v | 2,037 | module MODULE1 #(parameter VAR4(VAR10))
(input VAR9
, input VAR19
, input [1:0] VAR2 , input [1:0][VAR10-1:0] VAR18 , output VAR12 , output VAR16
, output VAR8 , output [VAR10-1:0] VAR11
, input VAR7 );
wire VAR1;
wire VAR3;
logic VAR17;
wire VAR5 = ~VAR2[0] | VAR17;
wire VAR20 = (VAR3 & VAR2[1]) & VAR5;
assign VAR16 =... | bsd-3-clause |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/niosII_system/synthesis/submodules/niosII_system_sysid_qsys_0.v | 1,415 | module MODULE1 (
address,
VAR1,
VAR3,
VAR2
)
;
output [ 31: 0] VAR2;
input address;
input VAR1;
input VAR3;
wire [ 31: 0] VAR2;
assign VAR2 = address ? 1422916617 : 0;
endmodule | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/lr0.v | 2,010 | module MODULE1(clk, addr, VAR20, VAR1, VAR24, en, reset);
input clk;
input [13:2] addr;
input [31:0] VAR20;
output [31:0] VAR1;
input [3:0] VAR24;
input en;
input reset;
VAR26 VAR10(
.VAR21 (reset),
.address (addr[13:2]),
.VAR17 (en),
.VAR13 (clk),
.VAR18 (VAR20[3:0]),
.VAR7 (VAR24[0]),
.VAR14 (VAR1[3:0])
);
VAR26 VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi.pp.blackbox.v | 1,436 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR1 ,
VAR8 ,
VAR2 ,
VAR3 ,
VAR9,
VAR10,
VAR4 ,
VAR7
);
output VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR9;
input VAR10;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
kevintownsend/convey_spmv | rtl/mac/intermediator.v | 11,029 | module MODULE1(clk, rst, VAR88, VAR83, VAR98, VAR72, VAR87, VAR114, VAR47, VAR96, VAR20, VAR8, VAR6, VAR48, VAR4, VAR1, VAR74);
parameter VAR46 = 1024;
parameter VAR9 = VAR19(VAR46 - 1);
input clk, rst, VAR88;
input [VAR9 - 1:0] VAR83;
input [65:0] VAR98;
input VAR72;
input [VAR9 - 1:0] VAR87;
input [65:0] VAR114;
outp... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/acl_pipeline.v | 4,429 | module MODULE1 (
VAR8,
VAR38,
VAR9,
VAR13,
VAR31,
VAR47,
VAR22,
VAR36,
VAR12,
VAR23,
VAR5,
VAR30,
VAR21,
VAR17,
VAR43,
VAR41,
VAR16
);
parameter VAR15 = 1;
parameter string VAR14 = "VAR19";
input VAR8, VAR38, VAR31, VAR22, VAR5, VAR17, VAR41;
output VAR47, VAR13, VAR23, VAR21, VAR43;
input VAR9, VAR12, VAR30;
output VA... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_rst_ps7_0_100M_0/gcd_block_design_rst_ps7_0_100M_0_stub.v | 1,909 | module MODULE1(VAR2, VAR7, VAR8,
VAR10, VAR5, VAR9, VAR3, VAR6,
VAR1, VAR4)
;
input VAR2;
input VAR7;
input VAR8;
input VAR10;
input VAR5;
output VAR9;
output [0:0]VAR3;
output [0:0]VAR6;
output [0:0]VAR1;
output [0:0]VAR4;
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.behavioral.v | 2,924 | module MODULE1( VAR3, VAR15, VAR11, VAR25 );
input VAR15, VAR3, VAR11;
output VAR25;
reg VAR19;
VAR2 VAR14(.VAR3(VAR3),.VAR15(VAR15),.VAR11(VAR11),.VAR25(VAR25),.VAR19(VAR19));
VAR2 VAR26(.VAR3(VAR3),.VAR15(VAR15),.VAR11(VAR11),.VAR25(VAR25),.VAR19(VAR19));
buf VAR8(VAR24,VAR11);
not VAR17(VAR13,VAR15);
and VAR12(VAR10... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/ssio_ddr_in_diff.v | 3,193 | module MODULE1 #
(
parameter VAR13 = "VAR30",
parameter VAR10 = "VAR12",
parameter VAR24 = "VAR2",
parameter VAR22 = 1
)
(
input wire VAR32,
input wire VAR25,
input wire [VAR22-1:0] VAR11,
input wire [VAR22-1:0] VAR20,
output wire VAR33,
output wire [VAR22-1:0] VAR4,
output wire [VAR22-1:0] VAR29
);
wire VAR21;
wire [V... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/spree/mul_shift_pipe1.v | 3,271 | module MODULE1(clk, VAR26,
VAR19, VAR7, VAR10,
VAR20,
en,
VAR2,
VAR3,
VAR11, VAR27);
parameter VAR24=32;
input clk;
input VAR26;
input [VAR24-1:0] VAR19;
input [VAR24-1:0] VAR7;
input [5-1:0] VAR10;
input [2:0] VAR20;
input en;
input VAR2;
output [VAR24-1:0] VAR3;
output [VAR24-1:0] VAR11;
output [VAR24-1:0] VAR27;
wir... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_jtag_streaming.v | 26,240 | module MODULE1 #(
parameter VAR105 = 0,
parameter VAR60 = 0,
parameter VAR29 = 0,
parameter VAR20 = 0
) (
input wire VAR34,
input wire VAR47,
output reg VAR85,
input wire [2:0] VAR119,
input wire VAR31,
input wire VAR81,
input wire VAR2,
input wire VAR109,
output wire [7:0] VAR79,
output wire VAR44,
input wire [7:0] VA... | mit |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/megacells/pll_bb.v | 1,498 | module MODULE1 (
VAR2,
VAR1);
input VAR2;
output VAR1;
endmodule | gpl-3.0 |
nyaxt/dmix | resampler_t.v | 2,970 | module MODULE1;
parameter VAR5 = 100000;
reg [15:0] VAR16 [VAR5-1:0];
reg [16:0] VAR33;
wire [15:0] VAR3 = VAR16[VAR33];
wire [23:0] VAR1 = {VAR3, 8'b0}; reg [23:0] VAR2;
parameter VAR13 = 10;
reg clk;
reg rst;
wire [(VAR34-1):0] VAR30 = 2'b00;
reg [(VAR34-1):0] VAR31;
reg [(24*VAR34-1):0] VAR32;
reg [(24*VAR34-1):0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxbp/sky130_fd_sc_ms__edfxbp.pp.blackbox.v | 1,398 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR8,
VAR9,
VAR4 ,
VAR1
);
output VAR2 ;
output VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o_2.v | 2,355 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR7 ,
VAR6 ,
VAR1 ,
VAR2,
VAR9,
VAR11 ,
VAR8
);
output VAR5 ;
input VAR10 ;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR2;
input VAR9;
input VAR11 ;
input VAR8 ;
VAR3 VAR4 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR11(VAR11),
.... | apache-2.0 |
quartushaters/project | M1/Part 1/raminout2.v | 10,427 | module MODULE1 (
VAR51,
VAR24,
VAR32,
VAR15,
VAR60,
VAR25,
VAR14,
VAR17,
VAR6);
input [9:0] VAR51;
input [9:0] VAR24;
input VAR32;
input [31:0] VAR15;
input [31:0] VAR60;
input VAR25;
input VAR14;
output [31:0] VAR17;
output [31:0] VAR6;
tri1 VAR32;
tri0 VAR25;
tri0 VAR14;
wire [31:0] VAR39;
wire [31:0] VAR53;
wire [31... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd/sky130_fd_sc_hs__tapvgnd.blackbox.v | 1,213 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/lsu_mon2.v | 618,142 | module MODULE1 (clk, VAR2);
input clk; input VAR2;
reg VAR1;
begin
end
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/syn/verilog/image_filter_Loop_1_proc.v | 80,818 | module MODULE1 (
VAR387,
VAR350,
VAR137,
VAR165,
VAR418,
VAR345,
VAR81,
VAR340,
VAR414,
VAR27,
VAR235,
VAR337,
VAR31,
VAR393,
VAR228,
VAR1,
VAR22,
VAR245,
VAR212,
VAR442,
VAR45,
VAR141,
VAR211,
VAR102,
VAR395,
VAR193,
VAR128
);
parameter VAR142 = 1'b1;
parameter VAR321 = 1'b0;
parameter VAR351 = 4'b1;
parameter VAR261 ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_4.behavioral.pp.v | 3,700 | module MODULE1( VAR34, VAR19, VAR31, VAR5, VAR26, VAR14 );
input VAR34, VAR19, VAR31;
inout VAR26, VAR14;
output VAR5;
reg VAR3;
VAR30 VAR33(.VAR34(VAR34),.VAR19(VAR19),.VAR31(VAR31),.VAR5(VAR5),.VAR26(VAR26),.VAR14(VAR14),.VAR3(VAR3));
VAR30 VAR32(.VAR34(VAR34),.VAR19(VAR19),.VAR31(VAR31),.VAR5(VAR5),.VAR26(VAR26),.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbp/sky130_fd_sc_ms__dlrbp.behavioral.pp.v | 2,490 | module MODULE1 (
VAR17 ,
VAR16 ,
VAR23,
VAR15 ,
VAR10 ,
VAR13 ,
VAR19 ,
VAR7 ,
VAR24
);
output VAR17 ;
output VAR16 ;
input VAR23;
input VAR15 ;
input VAR10 ;
input VAR13 ;
input VAR19 ;
input VAR7 ;
input VAR24 ;
wire VAR6 ;
reg VAR8 ;
wire VAR3 ;
wire VAR14 ;
wire VAR18 ;
wire VAR20;
wire VAR1 ;
wire VAR21 ;
wire VAR... | apache-2.0 |
manu3193/TextEditor | SVN/text_editor_top.v | 24,091 | module MODULE1(
VAR78, VAR106, VAR17, VAR80, VAR20,
VAR52,
VAR187,
VAR111,
VAR158,
VAR54,
VAR148,
VAR154,
VAR41,
VAR147,
VAR11,
VAR92,
VAR95,
VAR42,
VAR77,
VAR184,
VAR22,
VAR60
);
input VAR11,
VAR92,
VAR95,
VAR42,
VAR77;
input VAR60;
wire VAR171,
VAR119,
VAR137,
VAR50,
VAR155;
input VAR52;
input VAR187;
inout VAR111, V... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x4_128/pci_express_compiler-library/altpcie_pll_100_125.v | 10,521 | module MODULE1 (
VAR17,
VAR15,
VAR53,
VAR48);
input VAR17;
input VAR15;
output VAR53;
output VAR48;
wire [5:0] VAR33;
wire VAR57;
wire [0:0] VAR43 = 1'h0;
wire [0:0] VAR10 = 1'h1;
wire [0:0] VAR56 = VAR33[0:0];
wire VAR53 = VAR56;
wire VAR48 = VAR57;
wire [5:0] VAR24 = {VAR43, VAR43, VAR43, VAR43, VAR43, VAR10};
wire V... | lgpl-3.0 |
hanw/connectal | contrib/importverilog/regfile.v | 1,036 | module MODULE1 (VAR9, VAR12, VAR8, VAR5, VAR10,
VAR11, VAR4);
input VAR9;
input VAR12;
input [1:0] VAR8;
input [7:0] VAR5;
input VAR10;
input [1:0] VAR11;
output [7:0] VAR4;
reg [7:0] VAR2;
reg [7:0] VAR3;
reg [7:0] VAR7;
reg [7:0] VAR1;
reg [1:0] VAR6;
wire [7:0] VAR4;
assign VAR4 = (VAR6 == 0) ? VAR2 :
(VAR6 == 1) ? ... | mit |
The-OpenROAD-Project/asap7 | asap7sc7p5t_27/Verilog/asap7sc7p5t_SEQ_RVT_TT_201020.v | 73,237 | module MODULE1 (VAR4, VAR24, VAR9, VAR16, VAR15);
output VAR4;
input VAR24, VAR9, VAR16, VAR15;
reg VAR2;
wire VAR18, VAR26, VAR1, VAR6;
wire VAR8, VAR28, VAR20;
not (VAR8, VAR18);
VAR10 (VAR20, VAR6, VAR8, VAR1, VAR26);
VAR19 (VAR28, VAR2, VAR6, VAR8, VAR1, VAR26, VAR20);
buf (VAR4, VAR28);
wire VAR13, VAR7, VAR5;
wir... | bsd-3-clause |
hcabrera-/lancetfish | RTL/router/rtl/control_path.v | 18,780 | module MODULE1 #(
parameter VAR8 = 2,
parameter VAR9 = 2,
parameter VAR97 = 2,
parameter VAR6 = 2
)
(
input wire clk,
input wire reset,
output wire VAR23,
input wire [31:24] VAR32,
input wire [29:24] VAR5,
input wire VAR92,
output wire VAR82,
input wire [31:24] VAR85,
input wire [29:24] VAR94,
input wire VAR84,
output ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_1.behavioral.pp.v | 3,700 | module MODULE1( VAR22, VAR21, VAR34, VAR4, VAR9, VAR31 );
input VAR22, VAR21, VAR34;
inout VAR9, VAR31;
output VAR4;
reg VAR23;
VAR8 VAR25(.VAR22(VAR22),.VAR21(VAR21),.VAR34(VAR34),.VAR4(VAR4),.VAR9(VAR9),.VAR31(VAR31),.VAR23(VAR23));
VAR8 VAR10(.VAR22(VAR22),.VAR21(VAR21),.VAR34(VAR34),.VAR4(VAR4),.VAR9(VAR9),.VAR31(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh.functional.pp.v | 1,980 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR11 ,
VAR10 ,
VAR7,
VAR9 ,
VAR12
);
output VAR6 ;
input VAR13 ;
input VAR11 ;
input VAR10 ;
input VAR7;
input VAR9 ;
input VAR12 ;
wire VAR5;
wire VAR3 ;
VAR2 VAR8 (VAR5, VAR13, VAR7, VAR10 );
buf VAR1 (VAR3 , VAR5 );
VAR2 VAR4 (VAR6 , VAR3, VAR11, VAR10);
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/RegFPR.v | 4,882 | module MODULE1(
VAR34, reset,
VAR5, VAR30,
VAR37, VAR8,
VAR10, VAR12,
VAR19, VAR11,
VAR38, VAR33,
VAR18,
VAR32, VAR9
);
input VAR34;
input reset;
input[6:0] VAR5;
input[6:0] VAR37;
input[6:0] VAR10;
input[6:0] VAR19;
output[63:0] VAR30;
output[63:0] VAR8;
output[63:0] VAR12;
input[63:0] VAR11;
input[1:0] VAR38; input[1... | mit |
ymei/TMSPlane | Firmware/src/adc_cnv_sipo.v | 6,709 | module MODULE1
parameter VAR30 = 20
)
(
input VAR3,
input VAR44, input VAR24, input [7:0] VAR27, input [4:0] VAR9, input VAR19, input [3:0] VAR62,
output VAR59,
output VAR38,
input VAR32,
input VAR40,
output VAR26,
output VAR71,
output VAR5,
output VAR2,
input [VAR30-1:0] VAR74,
input [VAR30-1:0] VAR31,
output [VAR30-1... | bsd-3-clause |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GeArN8R1P3_syn.v | 7,403 | module MODULE1 ( VAR232, VAR117, VAR167, VAR18 );
input [15:0] VAR117;
input [15:0] VAR167;
output [16:0] VAR18;
input VAR232;
wire VAR286, VAR221, VAR6, VAR261, VAR292, VAR13, VAR45, VAR136, VAR77, VAR234, VAR155, VAR32, VAR26, VAR241,
VAR248, VAR126, VAR256, VAR42, VAR63, VAR132, VAR246, VAR105, VAR242, VAR93, VAR15,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3.functional.v | 1,309 | module MODULE1 (
VAR3,
VAR2,
VAR4,
VAR1
);
output VAR3;
input VAR2;
input VAR4;
input VAR1;
wire VAR7;
nor VAR5 (VAR7, VAR1, VAR2, VAR4 );
buf VAR6 (VAR3 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtn/sky130_fd_sc_ls__dfrtn.pp.symbol.v | 1,436 | module MODULE1 (
input VAR7 ,
output VAR1 ,
input VAR6,
input VAR3 ,
input VAR2 ,
input VAR4 ,
input VAR5 ,
input VAR8
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.behavioral.v | 2,510 | module MODULE1( VAR7, VAR3, VAR6, VAR1 );
input VAR3, VAR7, VAR6;
output VAR1;
VAR2 VAR5(.VAR7(VAR7),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1));
VAR2 VAR4(.VAR7(VAR7),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_spram_1024x32.v | 11,716 | module MODULE1(
VAR57, VAR30, VAR12,
clk, rst, VAR59, VAR11, VAR8, addr, VAR33, VAR49
);
parameter VAR32 = 10;
parameter VAR52 = 32;
input VAR57;
input [VAR37 - 1:0] VAR12;
output VAR30;
input clk; input rst; input VAR59; input VAR11; input VAR8; input [VAR32-1:0] addr; input [VAR52-1:0] VAR33; output [VAR52-1:0] VAR49... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp.pp.symbol.v | 1,402 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR8,
input VAR5 ,
input VAR7 ,
input VAR2 ,
input VAR3 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn.symbol.v | 1,335 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR1
);
supply1 VAR5;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/Raster_Laser_Projector_Video_In_video_csc.v | 6,995 | module MODULE1 (
clk,
reset,
VAR25,
VAR12,
VAR1,
VAR23,
VAR20,
VAR22,
VAR6,
VAR30,
VAR2,
VAR5,
VAR28,
VAR19
);
parameter VAR17 = 23;
parameter VAR3 = 23;
parameter VAR34 = 1;
parameter VAR31 = 1;
input clk;
input reset;
input [VAR17: 0] VAR25;
input VAR12;
input VAR1;
input [VAR34:0] VAR23;
input VAR20;
input VAR22;
ou... | gpl-3.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v2_0_rank_mach.v | 12,347 | module MODULE1 #
(
parameter VAR58 = "8",
parameter VAR32 = 4,
parameter VAR9 = "VAR14",
parameter VAR31 = 40,
parameter VAR46 = 4,
parameter VAR27 = 4,
parameter VAR22 = 2,
parameter VAR4 = 5,
parameter VAR18 = 5,
parameter VAR43 = 2,
parameter VAR24 = 30,
parameter VAR21 = 8,
parameter VAR13 = 4,
parameter VAR29 = 4,... | bsd-2-clause |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/start_for_Mat2AXImb6.v | 3,014 | module MODULE1 (
clk,
VAR5,
VAR12,
VAR20,
VAR11);
parameter VAR7 = 32'd1;
parameter VAR21 = 32'd2;
parameter VAR27 = 3'd3;
input clk;
input [VAR7-1:0] VAR5;
input VAR12;
input [VAR21-1:0] VAR20;
output [VAR7-1:0] VAR11;
reg[VAR7-1:0] VAR8 [0:VAR27-1];
integer VAR16;
always @ (posedge clk)
begin
if (VAR12)
begin
for (VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3/sky130_fd_sc_ls__or3.functional.v | 1,265 | module MODULE1 (
VAR6,
VAR7,
VAR4,
VAR5
);
output VAR6;
input VAR7;
input VAR4;
input VAR5;
wire VAR1;
or VAR2 (VAR1, VAR4, VAR7, VAR5 );
buf VAR3 (VAR6 , VAR1 );
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/bench/verilog/glbl.v | 1,172 | module MODULE1 ();
parameter VAR7 = 100000;
parameter VAR8 = 0;
wire VAR14;
wire VAR19;
wire VAR20;
reg VAR23;
reg VAR25;
reg VAR1;
wire VAR24;
wire VAR5;
wire VAR3;
wire VAR16;
wire VAR15;
reg VAR13;
reg VAR9;
reg VAR17;
reg VAR18;
reg VAR6 = 0;
reg VAR4 = 0 ;
reg VAR10 = 0;
reg VAR21 = 0;
reg VAR11 = 1'VAR12;
reg VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.pp.blackbox.v | 1,351 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR4,
VAR1,
VAR6 ,
VAR5
);
output VAR9 ;
input VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR4;
input VAR1;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o.behavioral.pp.v | 2,224 | module MODULE1 (
VAR12 ,
VAR20 ,
VAR4 ,
VAR8 ,
VAR1 ,
VAR9 ,
VAR2,
VAR19,
VAR3 ,
VAR16
);
output VAR12 ;
input VAR20 ;
input VAR4 ;
input VAR8 ;
input VAR1 ;
input VAR9 ;
input VAR2;
input VAR19;
input VAR3 ;
input VAR16 ;
wire VAR14 ;
wire VAR7 ;
wire VAR11 ;
wire VAR5;
and VAR13 (VAR14 , VAR8, VAR20, VAR4 );
and VAR1... | apache-2.0 |
JY-Kim/CA2016 | Sources/InstMemory.v | 1,742 | module MODULE1
(
input VAR5,
input VAR3,
input [31:0] VAR6,
output wire [31:0] VAR2
);
reg [31:0] VAR4[0:63];
reg [5:0] VAR1;
assign VAR2 = VAR4[VAR1];
always @ ( posedge VAR5 or posedge VAR3 )
begin
if ( VAR5 )
begin
VAR4[0] <= {6'd8, 5'd29, 5'd29, -16'd8}; VAR4[1] <= {6'd0, 5'd4, 5'd5, 5'd8, 5'd0, 6'd42}; VAR4[2] <= ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb.functional.pp.v | 1,201 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi.symbol.v | 1,402 | module MODULE1 (
input VAR9,
input VAR1,
input VAR10,
input VAR8,
input VAR2,
output VAR5
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_best_delta_seg_ch.v | 5,110 | module MODULE1 (
VAR38,
VAR50,
VAR41,
VAR17,
VAR46,
VAR43,
VAR10,
VAR16,
VAR19,
VAR25
);
parameter VAR51 = 2'b11;
parameter VAR48 = 2'b1;
parameter VAR28 = 2'b00;
parameter VAR30 = 7'b1111111;
parameter VAR9 = 32'b10;
parameter VAR12 = 32'b11;
parameter VAR2 = 2'b10;
parameter VAR29 = 32'b1;
parameter VAR45 = 4'b0000;
... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/pr_region_default_mm_bridge_0_bb.v | 1,885 | module MODULE1 #(
parameter VAR18 = 32,
parameter VAR15 = 8,
parameter VAR11 = 10,
parameter VAR3 = 1,
parameter VAR13 = 1,
parameter VAR7 = 1
) (
input wire clk, input wire VAR5, input wire [VAR18-1:0] VAR19, input wire VAR23, output wire [VAR3-1:0] VAR9, output wire [VAR18-1:0] VAR17, output wire [VAR11-1:0] VAR12, o... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/video_sys_Video_Scaler.v | 8,026 | module MODULE1 (
clk,
reset,
VAR21,
VAR1,
VAR2,
VAR14,
VAR24,
VAR7,
VAR3,
VAR11,
VAR4,
VAR6,
VAR17,
VAR27
);
parameter VAR22 = 15; parameter VAR19 = 0;
parameter VAR28 = 9; parameter VAR30 = 7; parameter VAR16 = 640;
parameter VAR23 = 4'b0101;
parameter VAR9 = 4'b0000;
parameter VAR25 = 8; parameter VAR26 = 320; parame... | gpl-2.0 |
solowandererY2K/FPGA-Quantum-Compiler | src/mult_unit_bb.v | 3,764 | module MODULE1 (
VAR2,
VAR1,
VAR3);
input [35:0] VAR2;
input [35:0] VAR1;
output [71:0] VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai.symbol.v | 1,379 | module MODULE1 (
input VAR7,
input VAR4,
input VAR1,
input VAR6,
output VAR5
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
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