repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
ShepardSiegel/ocpi | rtl/mkWciInitiator.v | 53,748 | module MODULE1(VAR126,
VAR237,
VAR198,
VAR132,
VAR199,
VAR146,
VAR87,
VAR69,
VAR152,
VAR144,
VAR250,
VAR15,
VAR251);
input VAR126;
input VAR237;
output [2 : 0] VAR198;
output VAR132;
output [3 : 0] VAR199;
output [31 : 0] VAR146;
output [31 : 0] VAR87;
input [1 : 0] VAR69;
input [31 : 0] VAR152;
input VAR144;
input [1 ... | lgpl-3.0 |
fredyamalves/Collision-detection-for-a-CPU-FPGA-heterogeneous-System | Verilog design/dCollideSpheres.v | 13,615 | module MODULE1( VAR76, VAR70, VAR22, VAR56, VAR8, VAR3, VAR154, VAR48, VAR86, VAR174, VAR18,
input[31:0] VAR76, VAR70, VAR22, VAR56, VAR8, VAR3, VAR154, VAR48;
input clk, rst;
input[31:0] VAR59, VAR111;
output reg[31:0] VAR86, VAR174, VAR18, VAR134, VAR152, VAR19, VAR6;
output reg VAR162, VAR34;
output reg[31:0] VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcon/sky130_fd_sc_ms__fahcon.blackbox.v | 1,369 | module MODULE1 (
VAR5,
VAR4 ,
VAR2 ,
VAR9 ,
VAR8
);
output VAR5;
output VAR4 ;
input VAR2 ;
input VAR9 ;
input VAR8 ;
supply1 VAR7;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/conb/sky130_fd_sc_hd__conb_1.v | 2,042 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR3,
VAR2,
VAR8 ,
VAR4
);
output VAR5 ;
output VAR6 ;
input VAR3;
input VAR2;
input VAR8 ;
input VAR4 ;
VAR1 VAR7 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR5,
VAR6
);
output VAR5;
output VAR6;
supply1 VAR3;
supply0 VAR... | apache-2.0 |
olajep/oh | src/common/hdl/oh_mux6.v | 1,125 | module MODULE1 #(parameter VAR4 = 1 ) (
input VAR9,
input VAR12,
input VAR5,
input VAR13,
input VAR3,
input VAR8,
input [VAR4-1:0] VAR6,
input [VAR4-1:0] VAR10,
input [VAR4-1:0] VAR7,
input [VAR4-1:0] VAR11,
input [VAR4-1:0] VAR1,
input [VAR4-1:0] VAR2,
output [VAR4-1:0] out );
assign out[VAR4-1:0] = ({(VAR4){VAR8}} & ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.pp.blackbox.v | 1,471 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR11 ,
VAR7 ,
VAR10 ,
VAR3 ,
VAR5,
VAR2 ,
VAR8 ,
VAR9 ,
VAR4
);
output VAR1 ;
output VAR6 ;
input VAR11 ;
input VAR7 ;
input VAR10 ;
input VAR3 ;
input VAR5;
input VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.v | 2,163 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR5,
VAR2,
VAR3 ,
VAR7
);
output VAR6 ;
input VAR4 ;
input VAR5;
input VAR2;
input VAR3 ;
input VAR7 ;
VAR1 VAR8 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR6,
VAR4
);
output VAR6;
input VAR4;
supply1 VAR5;
supply0 VAR2;... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_3/synth/design_1_xbar_3.v | 20,753 | module MODULE1 (
VAR15,
VAR92,
VAR76,
VAR14,
VAR21,
VAR43,
VAR115,
VAR49,
VAR128,
VAR108,
VAR10,
VAR38,
VAR103,
VAR74,
VAR107,
VAR7,
VAR68,
VAR20,
VAR17,
VAR59,
VAR53,
VAR5,
VAR129,
VAR41,
VAR55,
VAR54,
VAR56,
VAR52,
VAR4,
VAR114,
VAR91,
VAR96,
VAR106,
VAR123,
VAR44,
VAR112,
VAR33,
VAR77,
VAR22,
VAR18,
VAR86,
VAR127,
V... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_hdr_fifo.v | 7,754 | module MODULE1
parameter VAR6 = 128,
parameter VAR30 = 1,
parameter VAR10 = 1,
parameter VAR56 = "VAR14"
)
(
input VAR58,
input VAR20,
input VAR54,
input [(VAR6)-1:0] VAR29,
input [VAR57-1:0] VAR52,
input [VAR31-1:0] VAR3,
input [VAR11-1:0] VAR33,
input VAR51,
output VAR40,
output VAR4,
output [(VAR6)-1:0] VAR38,
outpu... | gpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_mm_interconnect_0_avalon_st_adapter.v | 6,152 | module MODULE1 #(
parameter VAR13 = 34,
parameter VAR24 = 0,
parameter VAR15 = 34,
parameter VAR1 = 0,
parameter VAR17 = 0,
parameter VAR9 = 0,
parameter VAR6 = 1,
parameter VAR5 = 1,
parameter VAR4 = 0,
parameter VAR23 = 34,
parameter VAR2 = 0,
parameter VAR10 = 1,
parameter VAR12 = 0,
parameter VAR11 = 1,
parameter V... | gpl-3.0 |
varunnagpaal/Digital-Hardware-Modelling | systemverilog/Sequential/FSM/moore_fsm.v | 3,190 | module MODULE1 ( input wire clk,
input wire rst,
input wire VAR6,
output reg VAR8,
output wire [2:0] VAR10,
output wire [2:0] VAR13
);
reg [2:0] VAR4;
reg [2:0] VAR14;
localparam VAR9 = 1'b0;
localparam VAR12 = 1'b1;
localparam VAR5 = 3'b000;
localparam VAR2 = 3'b001;
localparam VAR7 = 3'b010;
localparam VAR11 = 3'b011... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2/sky130_fd_sc_ms__and2.behavioral.v | 1,350 | module MODULE1 (
VAR6,
VAR3,
VAR8
);
output VAR6;
input VAR3;
input VAR8;
supply1 VAR5;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR4 ;
wire VAR9;
and VAR10 (VAR9, VAR3, VAR8 );
buf VAR7 (VAR6 , VAR9 );
endmodule | apache-2.0 |
gigglesninja/digital-system-design | uart/uart_rx.v | 5,291 | module MODULE1(clk, reset, VAR7, VAR40, din, dout, VAR48, addr);
input clk, reset, VAR7, VAR40;
input [7:0] din;
output [8:0] dout;
input VAR48; input [2:0] addr;
reg [8:0] dout, VAR43;
reg [9:0] VAR35;
reg [7:0] VAR32;
reg VAR47, VAR27, VAR19, VAR26, VAR30;
reg VAR34, VAR25, VAR12, VAR28, VAR22, VAR24;
reg [3:0] VAR21... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv.blackbox.v | 1,230 | module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v | 1,298 | module MODULE1 #(parameter VAR7(VAR6 )
, parameter VAR7(VAR5 )
)
(input [VAR6-1:0] VAR13
, output [VAR6-1:0] VAR9
, output VAR4
);
logic [VAR6-1:0] VAR10;
if (VAR6 == 1)
begin: VAR2
assign VAR9 = VAR13;
assign VAR4 = VAR13;
end
else
begin: VAR8
VAR3 #(.VAR6(VAR6)
,.VAR1 (1)
,.VAR5(VAR5)
) VAR12 (.VAR13 (VAR13)
,.VAR9(V... | bsd-3-clause |
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s510.v | 9,655 | module MODULE2 (VAR14,VAR175,VAR99);
input VAR14,VAR99;
output VAR175;
wire VAR223,VAR376;
trireg VAR91,VAR258;
nmos VAR461 (VAR258,VAR99,VAR376);
not VAR288 (VAR223,VAR258);
nmos VAR90 (VAR91,VAR223,VAR14);
not VAR390 (VAR175,VAR91);
not VAR227 (VAR376,VAR14);
endmodule
module MODULE1(VAR85,VAR133,VAR14,VAR18,VAR39,VA... | gpl-3.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T27-rom-param/genromleds.v | 1,314 | module MODULE1 (input wire clk,
output wire [4:0] VAR12);
parameter VAR7 = VAR4;
parameter VAR16 = "VAR17.VAR8";
parameter VAR13 = 5;
parameter VAR10 = 5;
reg [VAR13-1: 0] addr;
reg VAR5 = 0;
wire VAR11;
VAR9
.VAR13(VAR13),
.VAR10(VAR10))
VAR15 (
.clk(clk),
.addr(addr),
.VAR1(VAR12)
);
always @(negedge clk)
if (VAR5 ==... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.pp.symbol.v | 1,286 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR6 ,
input VAR3,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
lab11/M-ulator | platforms/HT_m3/hardware/ICE/hdl/toplevel.v | 1,742 | module MODULE1(
input VAR11,
input [4:1] VAR2, output [8:1] VAR1,
input VAR43,
output VAR31,
inout VAR7,
output VAR38,
output VAR41,
input VAR17,
input VAR5,
output VAR21,
output VAR3,
output VAR30,
output VAR4,
output VAR42,
output VAR45,
output VAR44,
output VAR29,
output VAR23,
input VAR35,
input VAR28
);
wire reset... | apache-2.0 |
aj-michael/Digital-Systems | Pong/Phase3/TermProjectPhase3/PongWithSound.v | 1,057 | module MODULE1(
input VAR2, VAR4, VAR19, VAR8,
output [2:0] VAR12,
output [2:0] VAR7,
output [1:0] VAR1,
output VAR5, VAR18,
output VAR15
);
wire [9:0] VAR6;
wire [9:0] VAR14;
parameter [9:0] VAR16=10'd640, VAR3=10'd480;
parameter [9:0] VAR20=10'd100, VAR11=10'd25;
VAR13 VAR10(VAR16, VAR3, VAR20, VAR11, VAR5, VAR18, VA... | mit |
travisg/cpu | rtl/sramcontroller.v | 4,114 | module MODULE1(
input clk,
input [29:0] addr,
input [31:0] VAR2,
output reg [31:0] VAR12,
input VAR13,
input VAR8,
output VAR11,
output VAR4,
input VAR5,
output reg [17:0] VAR7,
inout [15:0] VAR10,
output reg VAR3,
output reg VAR1,
output reg VAR6
);
reg [29:0] VAR9;
reg[1:0] state; | mit |
AbhishekShah212/School_Projects | ELEN232/pset7/Wholepart.v | 1,389 | module MODULE1 (
input [7:0] VAR12,
input VAR17,
input VAR4,
input VAR10,
output [7:0] VAR14
);
VAR5 VAR6 (
.VAR12(VAR12[0]),
.VAR7(VAR17),
.VAR16(VAR4),
.VAR3(VAR10),
.VAR14(VAR14[0])
);
VAR5 VAR1 (
.VAR12(VAR12[1]),
.VAR7(VAR17),
.VAR16(VAR4),
.VAR3(VAR10),
.VAR14(VAR14[1])
);
VAR5 VAR2 (
.VAR12(VAR12[2]),
.VAR7(VAR1... | mit |
vipinkmenon/scas | hw/fpga/source/memory_if/round_robin_arb.v | 7,531 | module MODULE1
parameter VAR3 = 100,
parameter VAR8 = 3
)
(
VAR20, VAR11,
clk, rst, req, VAR10, VAR4, VAR19
);
input clk;
input rst;
input [VAR8-1:0] req;
wire [VAR8-1:0] VAR1;
reg [VAR8*2-1:0] VAR17;
always @(VAR1)
VAR17 = {VAR1, VAR1};
reg [VAR8*2-1:0] VAR13;
always @(req) VAR13 = {req, req};
reg [VAR8-1:0] VAR2 = {V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc.functional.v | 1,421 | module MODULE1 (
VAR3 ,
VAR5,
VAR4
);
output VAR3 ;
input VAR5;
input VAR4 ;
wire VAR8 ;
wire VAR6;
not VAR1 (VAR8 , VAR5 );
and VAR2 (VAR6, VAR8, VAR4 );
buf VAR7 (VAR3 , VAR6 );
endmodule | apache-2.0 |
chiralhat/fpga-pulses-ice | ECP5/ecppll.v | 1,327 | module MODULE1
(
input VAR34, output VAR21, output VAR20
);
VAR40 #(
.VAR33("VAR13"),
.VAR16("VAR13"),
.VAR31("VAR13"),
.VAR9("VAR13"),
.VAR15("VAR12"),
.VAR32("VAR36"),
.VAR7("VAR2"),
.VAR23("VAR30"),
.VAR11(3),
.VAR39("VAR25"),
.VAR24(6),
.VAR3(2),
.VAR35(0),
.VAR37("VAR18"),
.VAR1(25)
) VAR28 (
.VAR22(1'b0),
.VAR10(... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1.pp.symbol.v | 1,324 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
toyoshim/tvcl | Multiplexer4.v | 1,050 | module MODULE1(
VAR7,
VAR9,
VAR2,
VAR1,
VAR5,
VAR10,
VAR12,
VAR8,
VAR4,
VAR3);
parameter VAR11 = 1;
input [VAR11 - 1:0] VAR7;
input [VAR11 - 1:0] VAR9;
input [VAR11 - 1:0] VAR2;
input [VAR11 - 1:0] VAR1;
input VAR5;
input VAR10;
input VAR12;
input VAR8;
output [VAR11 - 1:0] VAR4;
output VAR3;
wire [ 2:0] VAR6;
assign V... | bsd-3-clause |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_wbs.v | 23,265 | module MODULE1(
VAR2, VAR64, VAR98, VAR142, VAR137, VAR22, VAR91, VAR41, VAR28, VAR138, VAR36, VAR46, VAR78,
VAR154, VAR34, VAR63, VAR124,
VAR76, VAR27, VAR67,
VAR50,
VAR44, VAR59, VAR187, VAR199,
VAR18, VAR164, VAR149, VAR25,
VAR5, VAR84, VAR122, VAR75,
VAR165,
VAR68,
VAR118, VAR160, VAR168, VAR161,
VAR71, VAR94, VAR1... | gpl-3.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/ip/Encoder_IP/pulse_senor_read.v | 4,824 | module MODULE1(clk,VAR2,VAR8,address,write,VAR6,read,VAR18,VAR13,VAR19);
input clk;
input VAR2;
input VAR8;
input [1:0]address;
input write;
input [31:0] VAR6;
input read;
input [3:0] VAR18;
output [31:0] VAR13;
input [1:0]VAR19;
reg [31:0] VAR11;
reg [31:0] VAR3;
reg [31:0] VAR17;
reg [31:0] VAR16;
reg [31:0] VAR7;
re... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/mems/sirv_mrom.v | 4,416 | module MODULE1 # (
parameter VAR4 = 12,
parameter VAR7 = 32,
parameter VAR11 = 1024
)(
input [VAR4-1:2] VAR1,
output [VAR7-1:0] VAR13
);
wire [31:0] VAR5 [0:VAR11-1];
assign VAR13 = VAR5[VAR1];
genvar VAR8;
generate
if(1) begin: VAR3
for (VAR8=0;VAR8<1024;VAR8=VAR8+1) begin: VAR9
if(VAR8==0) begin: VAR2
assign VAR5[VAR... | apache-2.0 |
bangonkali/sram | sram.v | 7,282 | module MODULE1 (
address, VAR10, VAR1, VAR8, VAR7, reset
);
parameter VAR4 = 16;
parameter VAR9 = 8;
parameter VAR2 = 256;
input [VAR9-1:0] address;
input VAR1;
input VAR8;
input VAR7;
input reset;
inout [VAR4-1:0] VAR10 ;
reg [VAR4-1:0] VAR3 ;
reg [VAR4-1:0] VAR11 [0:VAR2-1];
assign VAR10 = (!VAR7 && VAR8) ? VAR3 : 16... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/ddr_ch_b.v | 53,530 | module MODULE1(VAR206 ,VAR114 ,VAR117 ,VAR205 ,VAR161 ,VAR20
,VAR17 ,VAR125 ,VAR92 ,VAR66 ,VAR129 ,VAR31
,VAR46 ,VAR33 ,VAR159 ,VAR160 ,
VAR177 ,VAR43 ,VAR185 ,VAR16 ,VAR196 ,
VAR150 ,VAR120 ,VAR85 ,VAR47 ,VAR98
,VAR164 ,VAR210 ,VAR111 ,VAR55 ,VAR88 , VAR130,
VAR53 ,VAR83 ,VAR52 ,VAR223 ,
VAR15 ,VAR91 ,VAR84 ,VAR224 ,
... | gpl-2.0 |
ThomasLee969/verilog-homework | homework1/4_thermometer_to_bcd/thermometer_to_bcd.v | 1,068 | module MODULE1(VAR2, VAR1);
output [7:0] VAR2;
input [15:0] VAR1;
assign VAR2 = (VAR1 == 16'b0) ? 0 :
(VAR1 == 16'b1) ? 1 :
(VAR1 == 16'b11) ? 2 :
(VAR1 == 16'b111) ? 3 :
(VAR1 == 16'b1111) ? 4 :
(VAR1 == 16'b11111) ? 5 :
(VAR1 == 16'b111111) ? 6 :
(VAR1 == 16'b1111111) ? 7 :
(VAR1 == 16'b11111111) ? 8 :
(VAR1 == 16'b1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a_4.v | 2,444 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR11 ,
VAR8 ,
VAR5 ,
VAR6 ,
VAR2,
VAR1,
VAR10 ,
VAR7
);
output VAR3 ;
input VAR9 ;
input VAR11 ;
input VAR8 ;
input VAR5 ;
input VAR6 ;
input VAR2;
input VAR1;
input VAR10 ;
input VAR7 ;
VAR4 VAR12 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VA... | apache-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_Leds/Spartan3AN_PicoBlaze_Leds.v | 3,117 | module MODULE1(
VAR11,
VAR7
);
parameter VAR15 = 8'h00;
input wire VAR11;
output wire [7:0] VAR7;
wire [7:0] VAR6;
wire [9:0] address;
wire [17:0] VAR8;
wire [7:0] VAR17;
wire [7:0] VAR10;
wire [7:0] VAR5;
wire VAR13;
wire VAR12;
wire interrupt;
wire reset;
VAR4 VAR18 (
.address(address),
.VAR8(VAR8),
.VAR17(VAR17),
.V... | gpl-3.0 |
jeremysalwen/combinatorial_aes | rtl/aes_256.v | 4,199 | module MODULE1 (state, VAR35, out);
input [127:0] state;
input [255:0] VAR35;
output [127:0] out;
reg [127:0] VAR63;
reg [255:0] VAR36, VAR33, VAR5;
wire [127:0] VAR47, VAR14, VAR28, VAR32, VAR46, VAR24, VAR41, VAR1,
VAR34, VAR6, VAR2, VAR15, VAR30;
wire [255:0] VAR43, VAR21, VAR51, VAR50, VAR17, VAR59, VAR22,
VAR11, V... | apache-2.0 |
tmolteno/TART | hardware/FPGA/fifo/sync/sfifo16.v | 3,961 | module MODULE1 (
VAR21,
VAR9,
VAR20,
VAR4,
VAR5,
VAR8,
VAR3,
VAR1
);
parameter VAR10 = 16;
parameter VAR18 = VAR10 - 1;
input VAR21;
input VAR9;
input VAR20;
input VAR4;
input [VAR18:0] VAR5;
output [VAR18:0] VAR8;
output VAR3;
output VAR1;
reg [4:0] VAR14 = 5'h0;
reg [4:0] VAR6 = 5'h0;
wire VAR11;
reg [VAR18:0] VAR13 ... | lgpl-3.0 |
Canaan-Creative/MM | verilog/superkdf9/components/twi/twi_core.v | 3,655 | module MODULE1 (
input clk ,
input rst ,
input wr , input [7:0] VAR17,input [7:0] VAR15,output [7:0] VAR30 ,
output [7:0] VAR13 ,
output VAR33 ,
input VAR32 ,
output VAR6
);
parameter VAR24 = 3 ;
parameter VAR20 = 600/VAR24+1 ;
parameter VAR18 = 700/VAR24+1 ;
parameter VAR22 = 600/VAR24+1 ;
parameter VAR26 = VAR20+100/... | unlicense |
defano/digital-design | uart/rtl/tx.v | 1,944 | module MODULE1 (
clk,
reset,
VAR7,
VAR6,
VAR4,
VAR3,
MODULE1);
input clk;
input reset;
input VAR7; input [7:0] VAR6; input VAR4; output VAR3; output MODULE1;
reg MODULE1;
reg [1:0] state;
reg [7:0] VAR2;
reg [2:0] VAR5;
parameter VAR1 = 2'd0;
parameter VAR10 = 2'd1;
parameter VAR9 = 2'd2;
parameter VAR8 = 2'd3;
assign ... | mit |
LoadCode/FPGA_CODIC | CORDIC.v | 6,723 | module MODULE1 (VAR14, VAR9, VAR5, VAR3, VAR12, VAR1);
parameter VAR18 = 16;
localparam VAR13 = VAR18;
input VAR14;
input signed [31:0] VAR9;
input signed [VAR18-1:0] VAR5;
input signed [VAR18-1:0] VAR3;
output signed [VAR18:0] VAR12;
output signed [VAR18:0] VAR1;
wire signed [31:0] VAR17 [0:30];
assign VAR17[00] = 32'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp.behavioral.pp.v | 2,792 | module MODULE1 (
VAR10 ,
VAR23 ,
VAR5 ,
VAR12 ,
VAR13 ,
VAR14 ,
VAR26 ,
VAR15,
VAR9,
VAR7 ,
VAR16
);
output VAR10 ;
output VAR23 ;
input VAR5 ;
input VAR12 ;
input VAR13 ;
input VAR14 ;
input VAR26 ;
input VAR15;
input VAR9;
input VAR7 ;
input VAR16 ;
wire VAR3 ;
reg VAR1 ;
wire VAR30 ;
wire VAR24 ;
wire VAR17;
wire VA... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/arSRLFIFO.v | 1,731 | module MODULE1 (VAR14,VAR5,VAR13,VAR3,VAR15,VAR2,VAR4,VAR8,VAR6);
parameter VAR16 = 128;
parameter VAR11 = 5;
localparam VAR1 = 2**VAR11;
input VAR14;
input VAR5;
input VAR6;
input VAR13;
input VAR3;
output VAR15;
output VAR2;
input[VAR16-1:0] VAR4;
output[VAR16-1:0] VAR8;
reg[VAR11-1:0] pos; reg[VAR16-1:0] VAR10[VAR1-... | lgpl-3.0 |
CatherineH/QubitekkCC | TDH/src/DE0Nano/verilog/twentyonecounter_bb.v | 3,909 | module MODULE1 (
VAR1,
VAR4,
VAR2,
VAR3);
input VAR1;
input VAR4;
input VAR2;
output [20:0] VAR3;
endmodule | mit |
benreynwar/fpga-sdrlib | verilog/flow/buffer_BB.v | 3,442 | module MODULE1
parameter VAR24 = 32,
parameter VAR10 = 64
)
(
input wire clk,
input wire VAR19,
input wire VAR7,
input wire [VAR24-1: 0] VAR21,
input wire VAR6,
output wire VAR14,
output wire [VAR24-1: 0] VAR3,
output wire VAR22
);
reg VAR17;
reg VAR1;
assign VAR22 = VAR17 | VAR1;
function integer VAR5;
input integer V... | mit |
jncronin/jca | cpu/uart.v | 6,426 | module MODULE1(clk, VAR7, VAR13, VAR17, VAR18, VAR14, VAR8, VAR24, VAR9);
input clk;
input [7:0] VAR13;
input VAR17;
output VAR7;
output VAR18;
input VAR14;
output [7:0] VAR8;
output VAR24;
input VAR9;
parameter VAR21 = 1302;
localparam VAR10 = VAR21 >> 3;
reg [7:0] VAR23 = 8'h48;
reg [7:0] state = 0;
reg [12:0] VAR26 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o.behavioral.pp.v | 2,070 | module MODULE1 (
VAR8 ,
VAR15 ,
VAR9 ,
VAR12 ,
VAR3 ,
VAR2 ,
VAR7,
VAR17,
VAR10 ,
VAR4
);
output VAR8 ;
input VAR15 ;
input VAR9 ;
input VAR12 ;
input VAR3 ;
input VAR2 ;
input VAR7;
input VAR17;
input VAR10 ;
input VAR4 ;
wire VAR13 ;
wire VAR1 ;
wire VAR18;
and VAR6 (VAR13 , VAR15, VAR9 );
or VAR11 (VAR1 , VAR3, VAR1... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/clocking/iodelay_ctrl.v | 7,616 | module MODULE1 #
(
parameter VAR18 = 100, parameter VAR12 = "VAR32", parameter VAR23 = "VAR35", parameter VAR34 = 1 )
(
input VAR15,
input VAR19,
input VAR25,
input VAR20,
output VAR13,
output VAR11
);
localparam VAR16 = 15;
wire VAR14;
wire VAR33;
wire VAR10;
reg [VAR16-1:0] VAR7 ;
wire VAR27;
wire VAR21;
assign VAR21... | lgpl-3.0 |
walkthetalk/fsref | ip/mm2s_adv/src/include/scale_1d.v | 2,022 | module MODULE1 #
(
parameter integer VAR13 = 12,
parameter integer VAR6 = 10,
parameter integer VAR20 = 32
)
(
input wire clk,
input wire VAR8,
input wire [VAR6-1:0] VAR2,
input wire [VAR13-1:0] VAR25,
input wire VAR15,
output wire VAR4,
output wire [VAR6-1:0] VAR16,
output wire [VAR13-1:0] VAR12,
output wire VAR21,
in... | gpl-3.0 |
tinkercnc/spi-fpga-driver | pluto_spi_servo_firmware/spi_servo_bbb.v | 8,637 | module MODULE1(in, out);
input in;
output out;
assign out = in ? 1'VAR39 : 1'b0;
endmodule
module MODULE2(clk, VAR19, VAR60, VAR17, VAR13, VAR43, VAR25, VAR29, VAR31, VAR40, VAR57, VAR30, VAR58, dout, din);
parameter VAR55=14;
input clk;
input VAR19, VAR13, VAR60, VAR29;
output VAR17, VAR25;
output VAR43;
output [3:0] ... | gpl-2.0 |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkDM_FPR_Tap.v | 7,754 | module MODULE1(VAR69,
VAR14,
VAR7,
VAR57,
VAR58,
VAR16,
VAR61,
VAR28,
VAR53,
VAR37,
VAR33,
VAR15,
VAR32,
VAR42,
VAR12,
VAR44,
VAR67);
input VAR69;
input VAR14;
input VAR7;
output [69 : 0] VAR57;
output VAR58;
input [64 : 0] VAR16;
input VAR61;
output VAR28;
input [69 : 0] VAR53;
input VAR37;
output VAR33;
input VAR15;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp.functional.v | 2,149 | module MODULE1 (
VAR14 ,
VAR6 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR17 ,
VAR3 ,
VAR12 ,
VAR18
);
input VAR14 ;
input VAR6 ;
output VAR9 ;
output VAR1 ;
input VAR5 ;
input VAR17 ;
input VAR3 ;
input VAR12 ;
input VAR18;
wire VAR2 ;
wire VAR15 ;
wire VAR7;
not VAR4 (VAR15 , VAR18 );
VAR11 VAR13 (VAR7, VAR17, VAR3, VAR12 );
VAR20 VAR... | apache-2.0 |
q3k/q3kmips | rtl/verilog/qm_execute.v | 2,499 | module MODULE1(
input wire [31:0] VAR4,
input wire [31:0] VAR2,
input wire [31:0] VAR20,
input wire [4:0] VAR22,
input wire [4:0] VAR19,
output wire [31:0] VAR11,
output wire [31:0] VAR23,
output wire [31:0] VAR7,
input wire VAR6,
input wire VAR15,
input wire VAR12,
input wire [3:0] VAR1,
input wire VAR14,
input wire V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcon/sky130_fd_sc_ls__fahcon.symbol.v | 1,358 | module MODULE1 (
input VAR5 ,
input VAR9 ,
input VAR6 ,
output VAR3,
output VAR7
);
supply1 VAR8;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
neale/CS-program | 474-VLSI/Lab_5/db/brightness_clk_2hz_altpll.v | 4,586 | module MODULE1
(
VAR2,
clk,
VAR7,
VAR6) ;
input VAR2;
output [4:0] clk;
input [1:0] VAR7;
output VAR6;
tri0 VAR2;
tri0 [1:0] VAR7;
reg VAR1;
wire [4:0] VAR3;
wire VAR4;
wire VAR5; | unlicense |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_altmemddr_0_ex_lfsr8.v | 1,405 | module MODULE1 (
clk, VAR7, enable, VAR5, VAR4, VAR1, VAR6);
parameter VAR3 = 32;
input clk;
input VAR7;
input enable;
input VAR5;
input VAR4;
output[8 - 1:0] VAR1;
wire[8 - 1:0] VAR1;
input[8 - 1:0] VAR6;
reg[8 - 1:0] VAR2;
assign VAR1 = VAR2 ;
always @(posedge clk or negedge VAR7)
begin
if (!VAR7)
begin
VAR2 <= VAR3[... | gpl-3.0 |
myriadrf/A2300 | hdl/main_128Dsp_32Msps.v | 19,008 | module MODULE1
(
VAR184, VAR44, VAR76, VAR188,
VAR95, VAR243, VAR14, VAR57, VAR42, VAR104, VAR105,
VAR151, VAR8, VAR23, VAR178, VAR232, VAR101, VAR159, VAR169,
VAR157, VAR186, VAR147, VAR237, VAR11, VAR63, VAR217, VAR238,
VAR224, VAR195,
VAR226, VAR37,
VAR90, VAR165,
VAR213, VAR7,
VAR48, VAR172,
VAR4,
VAR225, VAR182, V... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_lfsr72.v | 1,337 | module MODULE1(
clk,
VAR1,
VAR2,
word
);
input clk;
input VAR1;
input VAR2;
output reg [71:0] word;
always @(posedge clk or negedge VAR1) begin
if(~VAR1) begin
word <= 72'hAAF0F0AA55F0F0AA55;
end
else if(VAR2) begin
word[71] <= word[0];
word[70:66] <= word[71:67];
word[65] <= word[66] ^ word[0];
word[64:25] <= word[65:... | gpl-3.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/system/afifo.v | 4,620 | module MODULE1
parameter VAR10 = 32
)
(
input VAR16,
input VAR13,
input [VAR10-1:0] VAR8,
output [VAR10-1:0] VAR4,
input VAR11,
input VAR7,
output VAR5,
output VAR20
);
reg [2:0] VAR14 = 'd0, VAR2 = 'd0;
reg [2:0] VAR15 = 'd0, VAR17 = 'd0;
reg [2:0] VAR18 = 'd0, VAR3 = 'd0;
wire [2:0] VAR22, VAR6;
reg [VAR10-1:0] VAR12... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtn/sky130_fd_sc_ms__sdfrtn.functional.pp.v | 2,348 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR4 ,
VAR7 ,
VAR8 ,
VAR11,
VAR5 ,
VAR17 ,
VAR20 ,
VAR9
);
output VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR8 ;
input VAR11;
input VAR5 ;
input VAR17 ;
input VAR20 ;
input VAR9 ;
wire VAR1 ;
wire VAR3 ;
wire VAR22 ;
wire VAR21;
not VAR15 (VAR3 , VAR11 );
not VAR10 (VAR22 , VA... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_interpolator.v | 5,652 | module MODULE2 (
VAR8,
VAR5
);
parameter VAR2 = 16;
input [VAR2-1 :0] VAR8;
output [VAR7-1:0] VAR5;
assign VAR5 = ( VAR8 < 0 ) ? 'd0 :
( VAR8 > 255) ? 'd255 :
VAR8[VAR7-1:0];
endmodule
module MODULE1 (
VAR8,
VAR5
);
parameter VAR2 = 16;
input signed [VAR2-1 :0] VAR8;
output [VAR7-1:0] VAR5;
wire signed [10-1 :0] VAR12;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o_0.v | 2,248 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR10,
VAR2,
VAR4 ,
VAR1
);
output VAR8 ;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR10;
input VAR2;
input VAR4 ;
input VAR1 ;
VAR6 VAR9 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
mbus/mbus | mbus_example/verilog/lc_mbc_iso.v | 3,346 | module MODULE1
(
VAR14,
VAR9,
VAR23,
VAR21,
VAR18,
VAR19,
VAR4,
VAR20,
VAR6, VAR17, VAR7, VAR3, VAR15, VAR5, VAR22, VAR8,
VAR16,
VAR2,
VAR10, VAR1, VAR12, VAR13,
VAR11 );
input VAR14;
input [31:0] VAR9;
input [31:0] VAR23;
input VAR21;
input VAR18;
input VAR19;
input VAR4;
input VAR20;
output [31:0] VAR6;
output [31:0]... | apache-2.0 |
skyfex/svo-raycaster | raycaster1/raycast_core.v | 10,875 | module MODULE1
(
clk, rst,
VAR125,
VAR18,
VAR31,
VAR11, VAR69, VAR68,
VAR8, VAR60, VAR2,
VAR96, VAR103,
VAR10, VAR77,
VAR130,
VAR81, VAR36, VAR6, VAR40
);
parameter VAR116 = 32; parameter VAR122 = 8;
parameter VAR112 = 3;
parameter VAR99 = 32;
parameter VAR43 = 5;
input clk;
input rst;
input VAR125;
input [31:0] VAR18;... | mit |
jakubfi/mera400f | src/alu181.v | 1,079 | module MODULE1(
input [3:0] VAR10, VAR19,
input VAR17,
input VAR15,
input [3:0] VAR7,
output [3:0] VAR8,
output VAR13, VAR14,
output VAR6,
output VAR11
);
wire [3:0] VAR16 = {4{VAR7[0]}};
wire [3:0] VAR1 = {4{VAR7[1]}};
wire [3:0] VAR12 = {4{VAR7[2]}};
wire [3:0] VAR9 = {4{VAR7[3]}};
wire [3:0] VAR3 = ~((VAR10) | (VAR1... | gpl-2.0 |
jayant-sharma/uart | hdl/top_ADC.v | 2,393 | module MODULE1 (
input rst,
input clk,
input VAR8,
input VAR11,
input [VAR2-1:0] VAR18,
output reg VAR13,
output reg [VAR3-1:0] VAR19,
output reg [VAR17-1:0] VAR10,
output reg [VAR2-1:0] VAR22
);
wire VAR14, VAR1;
wire VAR6, VAR16, VAR9, VAR20, VAR15;
wire [4:0] VAR12;
wire [6:0] VAR5;
wire [16-1:0] dout, din;
wire rd,... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufkapwr/sky130_fd_sc_lp__bufkapwr.functional.pp.v | 1,839 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR11 ,
VAR12 ,
VAR2,
VAR1 ,
VAR13
);
output VAR3 ;
input VAR5 ;
input VAR11 ;
input VAR12 ;
input VAR2;
input VAR1 ;
input VAR13 ;
wire VAR4 ;
wire VAR7;
buf VAR6 (VAR4 , VAR5 );
VAR9 VAR8 (VAR7, VAR4, VAR2, VAR12);
buf VAR10 (VAR3 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv_8.v | 2,011 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR1,
VAR3,
VAR4 ,
VAR8
);
output VAR6 ;
input VAR2 ;
input VAR1;
input VAR3;
input VAR4 ;
input VAR8 ;
VAR7 VAR5 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR6,
VAR2
);
output VAR6;
input VAR2;
supply1 VAR1;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcon/sky130_fd_sc_hs__fahcon.blackbox.v | 1,333 | module MODULE1 (
VAR5,
VAR1 ,
VAR2 ,
VAR7 ,
VAR6
);
output VAR5;
output VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR6 ;
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/SPI_Controller/hdl/verilog/ourspi.v | 3,325 | module MODULE1 (
VAR9,
rst,
VAR81,
VAR60,
VAR53,
VAR63,
VAR39,
VAR16,
VAR25,
VAR19,
VAR57,
VAR4,
VAR38,
VAR12,
VAR29,
VAR77,
VAR67,
VAR33,
VAR10,
VAR7,
VAR73,
VAR28,
VAR22,
VAR79,
VAR6,
VAR30,
VAR20,
VAR35,
VAR31,
VAR21,
VAR71,
VAR70,
VAR69,
VAR72,
VAR17,
VAR18,
VAR32
);
parameter VAR52 = 32'h80000000, VAR41 = 32'h8000... | bsd-2-clause |
donnaware/AGC | rtl/de0/modules/ng_CMP.v | 10,618 | module MODULE1(
input VAR69, input [ 3:0] VAR58, input VAR42, input VAR30, input VAR11, input VAR40, input VAR32, input [ 3:0] VAR63, input VAR62, input VAR6, input VAR19, input VAR13, input [ 13:0] VAR33, input [ 5:0] VAR52, output [100:0] VAR35, output [ 7:0] VAR3, output [ 15:0] VAR50 );
assign VAR3 = {VAR19, VAR6, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3/sky130_fd_sc_ls__nor3.behavioral.v | 1,405 | module MODULE1 (
VAR1,
VAR10,
VAR9,
VAR3
);
output VAR1;
input VAR10;
input VAR9;
input VAR3;
supply1 VAR6;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR8 ;
wire VAR7;
nor VAR2 (VAR7, VAR3, VAR10, VAR9 );
buf VAR11 (VAR1 , VAR7 );
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v | 12,392 | module MODULE1(addr, VAR14, VAR1, VAR28);
parameter VAR10 = VAR18;
input [1:0] addr;
input [VAR21-1:0] VAR14;
input [VAR10-1:0] VAR1;
output [VAR10-1:0] VAR28;
reg [7:0] VAR6;
reg [7:0] VAR5;
reg [7:0] VAR16;
reg [7:0] VAR9;
reg [VAR10-1:0] VAR7;
reg [3:0] VAR23, VAR24,
VAR3, VAR8;
assign VAR28 = {VAR6, VAR5, VAR16, VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o_2.v | 2,212 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR9,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR9;
input VAR2;
VAR7 VAR8 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR5,
VAR1,
VAR3,
VAR4
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR9 ,
input VAR1 ,
output VAR4 ,
input VAR6 ,
input VAR8,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf.functional.pp.v | 1,772 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR10,
VAR1,
VAR8 ,
VAR5
);
output VAR9 ;
input VAR7 ;
input VAR10;
input VAR1;
input VAR8 ;
input VAR5 ;
wire VAR3 ;
wire VAR4;
buf VAR6 (VAR3 , VAR7 );
VAR2 VAR11 (VAR4, VAR3, VAR10, VAR1);
buf VAR12 (VAR9 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tap/sky130_fd_sc_ls__tap.blackbox.v | 1,208 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
jhennessy/parallella-hw-old | boards/archive/gen1.1/fpga/hdl/pulse2toggle.v | 1,319 | module MODULE1(
out,
clk, in, reset
);
input clk;
input in;
output out;
input reset;
reg out;
wire VAR1;
assign VAR1 = in ? ~out :
out;
always @ (posedge clk or posedge reset)
if(reset)
out <= 1'b0;
else
out <= VAR1;
endmodule | gpl-3.0 |
eda-globetrotter/PicenoDecoders | viterbi/syn/src/commschannel.v | 11,724 | module MODULE1();
wire VAR22; wire [1:0] VAR18; wire [1:0] VAR24; wire VAR19; wire [1:0] VAR31;
reg VAR10[0:255];
reg VAR28;
reg [7:0] VAR36;
reg VAR23;
reg VAR35;
reg [7:0] VAR12;
reg [1:0] VAR30;
reg [7:0] VAR6;
wire [1:0] VAR7;
wire [1:0] VAR17;
reg VAR15;
reg [7:0] VAR1;
reg [1:0] VAR5;
reg [1:0] VAR14;
reg VAR11;
... | mit |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/tx_buf.v | 13,499 | module MODULE1(
clk,
VAR396,
din,
VAR112,
VAR334,
dout,
VAR364,
VAR28,
VAR199,
VAR276,
VAR141
);
input clk;
input VAR396;
input [31 : 0] din;
input VAR112;
input VAR334;
output [31 : 0] dout;
output VAR364;
output VAR28;
output VAR199;
output VAR276;
output [6 : 0] VAR141;
VAR262 #(
.VAR347(0),
.VAR189(0),
.VAR225(0),
... | gpl-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/c_decr.v | 3,463 | module MODULE1
(VAR2, VAR5);
parameter VAR7 = 3;
parameter [0:VAR7-1] VAR1 = 0;
parameter [0:VAR7-1] VAR6 = (1 << VAR7) - 1;
localparam VAR8 = VAR6 - VAR1 + 1;
localparam VAR3 = VAR9(VAR8);
input [0:VAR7-1] VAR2;
output [0:VAR7-1] VAR5;
wire [0:VAR7-1] VAR5;
wire VAR4;
assign VAR4 = ~|VAR2[(VAR7-VAR3):VAR7-1];
wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21boi/sky130_fd_sc_hs__a21boi.functional.pp.v | 2,063 | module MODULE1 (
VAR1,
VAR11,
VAR10 ,
VAR8 ,
VAR16 ,
VAR2
);
input VAR1;
input VAR11;
output VAR10 ;
input VAR8 ;
input VAR16 ;
input VAR2;
wire VAR7 ;
wire VAR13 ;
wire VAR9 ;
wire VAR6;
not VAR12 (VAR7 , VAR2 );
and VAR14 (VAR13 , VAR8, VAR16 );
nor VAR4 (VAR9 , VAR7, VAR13 );
VAR15 VAR5 (VAR6, VAR9, VAR1, VAR11);
bu... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/triple_speed_ethernet-library/altera_tse_pcs_pma.v | 12,794 | module MODULE1 (
address,
clk,
VAR93,
VAR106,
VAR101,
VAR75,
VAR20,
VAR105,
VAR6,
VAR94,
read,
VAR32,
reset,
VAR35,
VAR69,
VAR76,
write,
VAR100,
VAR99,
VAR71,
VAR1,
VAR11,
VAR91,
VAR57,
VAR51,
VAR44,
VAR3,
VAR61,
VAR88,
VAR66,
VAR47,
VAR86,
VAR31,
VAR107,
VAR14,
VAR85,
VAR5,
VAR74,
VAR68,
VAR4,
VAR36,
VAR84,
VAR2,
VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3/sky130_fd_sc_hd__or3_2.v | 2,153 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR2,
VAR4,
VAR1 ,
VAR7
);
output VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR2;
input VAR4;
input VAR1 ;
input VAR7 ;
VAR3 VAR10 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE1 (... | apache-2.0 |
jmesmon/trifles | verilog/hw6/p13.v | 1,563 | module MODULE2
parameter VAR2 = VAR7)
(output reg VAR8,
input [VAR7-1:0] VAR12,
input [VAR2-1:0] VAR6,
input VAR11, VAR1);
reg [VAR7-1:0] VAR3;
always @(VAR1) begin
VAR3 <= VAR3 + 1;
end
reg [VAR7:0] VAR4;
wire VAR10 = VAR6[VAR2 - 1];
wire [VAR2 - 2:0] VAR9 = VAR6[VAR2-2:0];
always @(VAR3) begin
if (VAR8)
if (VAR10)
VA... | gpl-3.0 |
carstenbru/fpga-log | spartanmc/hardware/uart_light/src/uart_light_tx_ctrl.v | 3,777 | module MODULE1
parameter VAR9 = 2,
parameter VAR1 = 2'b00,
parameter VAR5 = 2'b01,
parameter VAR12 = 2'b10
)(
input wire reset,
input wire VAR10,
input wire VAR2,
output wire VAR17,
output wire VAR11,
input wire VAR15,
output reg VAR8,
output reg VAR16,
output reg VAR3,
input wire VAR13,
input wire VAR7,
output wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2.pp.symbol.v | 1,304 | module MODULE1 (
input VAR4 ,
input VAR7 ,
output VAR3 ,
input VAR6 ,
input VAR5,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/mem_reg.v | 3,615 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR5] out, input wire VAR23,
input wire VAR20, input wire VAR7,
input wire [VAR1] VAR14, input wire VAR16, input wire VAR31, input wire [VAR9] VAR4, input wire [VAR8] VAR25, input wire VAR10, input wire [VAR32] VAR24,
output reg [VAR1] VAR27, output reg VAR... | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/DCACHE.v | 12,301 | module MODULE1( VAR168, VAR73, VAR82, VAR35, VAR40, VAR74, VAR37, VAR4, VAR152, VAR13, VAR116, VAR140, VAR17, VAR144,
VAR102, VAR2, VAR124, VAR69, VAR86, VAR55, VAR14, VAR65, VAR150, VAR98, VAR166, VAR138, VAR23, VAR113,
VAR28, VAR91, VAR44, VAR142, VAR109, VAR105, VAR63, VAR106, VAR12, VAR51, VAR118, VAR83, VAR170,
VA... | gpl-3.0 |
ayaovi/yoda | UART/UART_Tx.v | 3,147 | module MODULE1 #(
parameter VAR3 = 5,
parameter VAR18 = 5'd29 )(
input VAR12,
input VAR15,
input [7:0]VAR17,
input VAR1,
output reg VAR4,
output reg VAR10 );
reg VAR6;
reg [ 7:0]VAR14;
reg [VAR3-1:0]VAR7;
reg [ 2:0]VAR16;
reg [1:0]VAR2;
localparam VAR9 = 2'b00;
localparam VAR11 = 2'b01;
localparam VAR5 = 2'b11;
localpa... | gpl-3.0 |
medav/conware | Prototype/hw/archive/axis_boilerplate.v | 8,231 | module MODULE1
(
VAR17,
VAR11,
VAR5,
VAR15,
VAR10,
VAR12,
VAR1,
VAR2,
VAR14,
VAR6
);
input VAR17;
input VAR11;
output VAR5;
input [31 : 0] VAR15;
input VAR10;
input VAR12;
output VAR1;
output [31 : 0] VAR2;
output VAR14;
input VAR6;
localparam VAR9 = 8;
localparam VAR3 = 8;
localparam VAR4 = 3'b100;
localparam VAR7 = 3... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v | 11,430 | module MODULE1(
input wire [7:0] VAR11,
input wire [7:0] VAR26,
output reg [7:0] VAR5,
input wire VAR1,
input wire VAR29,
output wire VAR53,
input wire VAR52,
input wire VAR28,
input wire VAR20,
output reg VAR22,
output wire VAR21, output reg VAR42,
output reg VAR34,
input wire VAR3 );
reg [7:0] VAR30; reg [7:0] VAR44;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22a/sky130_fd_sc_hdll__o22a.symbol.v | 1,371 | module MODULE1 (
input VAR3,
input VAR5,
input VAR9,
input VAR8,
output VAR7
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/controller/bank_cntrl.v | 25,514 | module MODULE1 #
(
parameter VAR22 = 100,
parameter VAR51 = "1T",
parameter VAR121 = 3,
parameter VAR36 = 2,
parameter VAR18 = "8",
parameter VAR138 = 12,
parameter VAR75 = 5,
parameter VAR73 = 8,
parameter VAR137 = "VAR17",
parameter VAR45 = "VAR7",
parameter VAR111 = 4,
parameter VAR114 = 4,
parameter VAR81 = 2,
para... | lgpl-3.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/arbiter_for_mem.v | 3,581 | module MODULE1( clk,
rst,
VAR6,
VAR16,
VAR15,
VAR1,
VAR10,
VAR5,
VAR7,
VAR11,
VAR4,
VAR13
);
input clk;
input rst;
input VAR6;
input VAR16;
input VAR15;
input VAR1;
output VAR10;
output VAR5;
output VAR7;
output VAR11;
output VAR4;
output VAR13;
parameter VAR14=2'b00;
parameter VAR9=2'b01;
parameter VAR8=2'b10;
paramet... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b_1.v | 2,311 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR1 ,
VAR6 ,
VAR5 ,
VAR8,
VAR4,
VAR9 ,
VAR7
);
output VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR8;
input VAR4;
input VAR9 ;
input VAR7 ;
VAR10 VAR11 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(V... | apache-2.0 |
AngelTerrones/MUSB | Hardware/uart/uart_min.v | 5,444 | module MODULE1 #(
parameter VAR6 = 8, parameter VAR1 = 100.0 )(
input clk,
input rst,
input write, input [7:0] VAR36, input read, output [7:0] VAR11, output VAR15, output [VAR6:0] VAR30, output [VAR6:0] VAR22, output VAR32, output VAR9, output VAR26, input VAR35, output VAR2 );
wire VAR24;
wire VAR40;
wire [7:0] VAR31;... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_31.v | 21,266 | module MODULE5 (
clk,
reset,
VAR12,
VAR134,
VAR115,
VAR151,
VAR187
);
parameter VAR174 = 18;
parameter VAR49 = 31;
parameter VAR60 = 16;
localparam VAR82 = 32;
input clk;
input reset;
input VAR12;
input VAR134;
input [VAR174-1:0] VAR115; output VAR151;
output [VAR174-1:0] VAR187;
localparam VAR102 = 18; localparam VAR1... | mit |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_reg_srl_fifo.v | 9,777 | module MODULE1 #
(
parameter VAR18 = "none", parameter integer VAR33 = 1, parameter integer VAR15 = 33, parameter integer VAR36 = 2, parameter VAR1 = 1 )
(
input wire VAR3, input wire VAR6, input wire [VAR33-1:0] VAR11, input wire VAR21, output wire VAR44, output wire [VAR33-1:0] VAR38, output wire VAR37, input wire VA... | gpl-3.0 |
lsnow/mips32 | gpr.v | 1,074 | module MODULE1(clk, VAR7, VAR6, VAR2, VAR8, VAR4, VAR1, VAR5
);
input clk;
input VAR7;
input [31:0] VAR6;
input [4:0] VAR2, VAR8;
input [4:0] VAR4;
output [31:0] VAR1, VAR5;
reg [31:0] VAR3 [31:0];
always @(posedge clk) begin
if(VAR7 && VAR4 != 5'h00)
VAR3[VAR4] <= VAR6;
end
assign VAR1 = (VAR2 == 5'b00) ? 32'b0 : VAR3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.v | 2,262 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR10 ,
VAR3,
VAR8,
VAR2,
VAR7 ,
VAR6
);
output VAR9 ;
output VAR1 ;
input VAR10 ;
input VAR3;
input VAR8;
input VAR2;
input VAR7 ;
input VAR6 ;
VAR4 VAR5 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1... | apache-2.0 |
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