repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
nczempin/NICNAC16 | src/avr_interface.v | 3,556 | module MODULE1 #(
parameter VAR46 = 50000000,
parameter VAR43 = 500000
)(
input clk,
input rst,
input VAR26,
output VAR10,
input VAR21,
input VAR27,
input VAR31,
output [3:0] VAR16,
output VAR49,
input VAR25,
input [3:0] VAR1,
output VAR8,
output [9:0] VAR28,
output [3:0] VAR51,
input [7:0] VAR32,
input VAR6,
output VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_2.functional.v | 1,043 | module MODULE1( VAR11, VAR2, VAR13, VAR5 );
input VAR5, VAR2, VAR13;
output VAR11;
wire VAR3;
and VAR12( VAR3, VAR5, VAR2 );
wire VAR8;
not VAR4( VAR8, VAR13 );
wire VAR1;
and VAR9( VAR1, VAR8, VAR5 );
wire VAR6;
and VAR10( VAR6, VAR2, VAR13 );
or VAR7( VAR11, VAR3, VAR1, VAR6 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.behavioral.pp.v | 3,497 | module MODULE1( VAR3, VAR8, VAR4, VAR7, VAR11, VAR6, VAR10, VAR5 );
input VAR4, VAR8, VAR3, VAR11, VAR6;
inout VAR10, VAR5;
output VAR7;
VAR1 VAR2(.VAR3(VAR3),.VAR8(VAR8),.VAR4(VAR4),.VAR7(VAR7),.VAR11(VAR11),.VAR6(VAR6),.VAR10(VAR10),.VAR5(VAR5));
VAR1 VAR9(.VAR3(VAR3),.VAR8(VAR8),.VAR4(VAR4),.VAR7(VAR7),.VAR11(VAR11)... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_gen.v | 7,892 | module MODULE1
parameter VAR18 = 72,
parameter VAR9 = 8,
parameter VAR1 = 64
)
(
VAR22
);
function integer VAR6 (input integer VAR10);
integer VAR19;
if (VAR10 == 1) VAR6 = 1;
else begin
VAR6 = 1;
for (VAR19=2; VAR19<=VAR10; VAR19=VAR19+1)
VAR6 = VAR6 * VAR19;
end
endfunction
function integer VAR3 (input integer VAR17,... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbn/sky130_fd_sc_hs__dlrbn.behavioral.pp.v | 2,513 | module MODULE1 (
VAR21 ,
VAR8 ,
VAR10 ,
VAR13 ,
VAR11,
VAR19 ,
VAR9
);
input VAR21 ;
input VAR8 ;
output VAR10 ;
output VAR13 ;
input VAR11;
input VAR19 ;
input VAR9 ;
wire VAR17 ;
wire VAR20 ;
reg VAR23 ;
wire VAR1 ;
wire VAR2 ;
wire VAR3 ;
wire VAR16;
wire VAR14 ;
wire VAR22 ;
wire VAR12 ;
wire VAR18 ;
not VAR24 (VAR... | apache-2.0 |
ServerTech/neptune | code/mult_core.v | 1,608 | module MODULE1(sel, VAR4, VAR3, out);
parameter VAR2 = 'd16;
input wire sel;
input wire [VAR2-1:0] VAR4, VAR3;
output reg [VAR2-1:0] out;
always@(sel, VAR4, VAR3) begin
case(sel) 1'b0: out [VAR2-1:0] = VAR4 [VAR2-1:0];
1'b1: out [VAR2-1:0] = VAR3 [VAR2-1:0];
default: out [VAR2-1:0] = {VAR2{1'b0}};
endcase
end
endmodule... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_1.v | 2,493 | module MODULE1 (
VAR5 ,
VAR11,
VAR2,
VAR8 ,
VAR1 ,
VAR7,
VAR4,
VAR3 ,
VAR10
);
output VAR5 ;
input VAR11;
input VAR2;
input VAR8 ;
input VAR1 ;
input VAR7;
input VAR4;
input VAR3 ;
input VAR10 ;
VAR6 VAR9 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR10(... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.behavioral.pp.v | 1,476 | module MODULE1( VAR4, VAR3, VAR8, VAR5, VAR1 );
input VAR3, VAR4;
inout VAR5, VAR1;
output VAR8;
VAR7 VAR2(.VAR4(VAR4),.VAR3(VAR3),.VAR8(VAR8),.VAR5(VAR5),.VAR1(VAR1));
VAR7 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR8(VAR8),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
gralco/click-clock-board | mojo_io_shield/source/mojo_top.v | 1,898 | module MODULE1(
input clk,
input VAR10,
input VAR16,
output[7:0]VAR18,
output VAR15,
input VAR11,
input VAR6,
input VAR17,
output [3:0] VAR23,
input VAR24, output VAR3, input VAR21, output [23:0] VAR7, output [7:0] VAR8, output [3:0] VAR25, input [3:0] VAR19,
input en,
output VAR1
);
wire rst = ~VAR10;
assign VAR15 = 1... | gpl-3.0 |
cwilkens/fpga-hero | sram_interface.v | 2,043 | module MODULE1(rst, clk, addr, dout, VAR7, VAR10, VAR8, VAR11, VAR12, VAR3, VAR5, VAR1, VAR6, VAR2, VAR4);
input clk, rst;
input [23:0] addr;
output reg [15:0] dout;
output VAR7;
output VAR10, VAR8, VAR11, VAR12, VAR3, VAR1, VAR6;
output [23:1] VAR4;
output VAR5;
inout [15:0] VAR2;
assign VAR10 = 0;
assign VAR8 = 0;
as... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_mux_2to1_n/sky130_fd_sc_hd__udp_mux_2to1_n.symbol.v | 1,289 | module MODULE1 (
input VAR2,
input VAR4,
output VAR1 ,
input VAR3
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_non_blocking_miss_fifo.v | 8,027 | module MODULE1
import VAR1::*;
,parameter VAR56(VAR68)
)
(
input VAR79
, input VAR74
, input [VAR41-1:0] VAR20
, input VAR52
, output logic VAR27
, output logic VAR33
, output logic [VAR41-1:0] VAR57
, input VAR18
, input VAR16 VAR46
, input VAR45
, output logic VAR80
, input VAR2
);
localparam VAR69 = VAR17(VAR68);
lo... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.behavioral.v | 1,250 | module MODULE1( VAR5, VAR7, VAR2, VAR3 );
input VAR5, VAR2, VAR7;
output VAR3;
VAR4 VAR1(.VAR5(VAR5),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3));
VAR4 VAR6(.VAR5(VAR5),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
freecores/sha3 | high_throughput_core/rtl/f_permutation.v | 2,050 | module MODULE1(clk, reset, in, VAR1, ack, out, VAR7);
input clk, reset;
input [575:0] in;
input VAR1;
output ack;
output reg [1599:0] out;
output reg VAR7;
reg [10:0] VAR8;
wire [1599:0] VAR12, VAR13;
wire [63:0] VAR11, VAR4;
wire VAR10;
wire VAR2;
reg VAR9;
assign VAR2 = VAR1 & (~ VAR9);
always @ (posedge clk)
if (res... | apache-2.0 |
nv1t/proxmark3 | fpga/fpga.v | 7,959 | module MODULE1(
VAR100, VAR57, VAR25, VAR28,
VAR41, VAR9, VAR11,
VAR79, VAR62, VAR24, VAR58, VAR68, VAR84,
VAR107, VAR55, VAR16,
VAR31, VAR126, VAR143, VAR131,
VAR70, VAR44,
VAR127
);
input VAR100, VAR25, VAR28;
output VAR57;
input VAR41, VAR9, VAR11;
output VAR79, VAR62, VAR24, VAR58, VAR68, VAR84;
input [7:0] VAR107;... | gpl-2.0 |
OrganicMonkeyMotion/fpga_experiments | bmax10/BeMicro_full_reference_project/ip/i2c_opencores/i2c_opencores.v | 1,972 | module MODULE1
(
VAR5, VAR13, VAR11, VAR10, VAR12,
VAR17, VAR9, VAR3, VAR21,
VAR15, VAR6
);
input VAR5; input VAR13;
input [2:0] VAR11; input [7:0] VAR10; output [7:0] VAR12; input VAR17; input VAR9; output VAR3; output VAR21;
inout VAR15; inout VAR6;
wire VAR8; wire VAR16;
wire VAR22;
wire VAR15;
wire VAR14;
assign VA... | unlicense |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v | 17,402 | module MODULE1 #
(
parameter VAR19 = "VAR3",
parameter VAR11 = 32,
parameter VAR6 = 32'h00000000
)
(
input wire VAR2,
input wire VAR16,
input wire [VAR11-1:0] VAR9,
input wire VAR8,
output wire VAR4,
output wire [VAR11-1:0] VAR18,
output wire VAR1,
input wire VAR15
);
generate
if (VAR6 == 32'h00000000) begin
assign VAR... | gpl-3.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_lsu_cappuccino.v | 26,889 | module MODULE1
parameter VAR166 = "VAR51",
parameter VAR136 = 32,
parameter VAR35 = 5,
parameter VAR10 = 9,
parameter VAR64 = 2,
parameter VAR93 = 32,
parameter VAR159 = "VAR51",
parameter VAR92 = "VAR51",
parameter VAR128 = "VAR51",
parameter VAR24 = 6,
parameter VAR158 = 1,
parameter VAR44 = "VAR85",
parameter VAR151... | mpl-2.0 |
MarcoVogt/basil | firmware/modules/utils/clock_divider.v | 2,463 | module MODULE1
parameter VAR5 = 40000000
)
(
input wire VAR2,
input wire VAR3,
output reg VAR1, output reg VAR6 );
integer VAR4;
VAR8 VAR4 = 0;
integer VAR7;
VAR8 VAR7 = 0;
VAR8 VAR6 = 1'b0;
VAR8 VAR1 = 1'b0;
always @ (posedge VAR2 or posedge VAR3)
begin
if (VAR3 == 1'b1)
begin
VAR1 <= 1'b0;
end
else
begin
if (VAR4 == ... | bsd-3-clause |
cpulabs/mist1032isa | src/core/core.v | 5,985 | module MODULE1
parameter VAR31 = 32'h0
)(
input wire VAR29,
input wire VAR18,
output wire VAR30,
output wire VAR40,
output wire [5:0] VAR35,
output wire VAR28,
output wire VAR32,
output wire [1:0] VAR59,
output wire VAR23,
input wire VAR52,
output wire [1:0] VAR47,
output wire [2:0] VAR21,
output wire [31:0] VAR34,
out... | bsd-2-clause |
ptracton/wb_soc_template | rtl/RISCV/picorv32/picorv32.v | 97,488 | module MODULE1 #(
parameter [ 0:0] VAR29 = 1,
parameter [ 0:0] VAR62 = 1,
parameter [ 0:0] VAR103 = 1,
parameter [ 0:0] VAR7 = 1,
parameter [ 0:0] VAR101 = 0,
parameter [ 0:0] VAR59 = 1,
parameter [ 0:0] VAR63 = 0,
parameter [ 0:0] VAR38 = 0,
parameter [ 0:0] VAR3 = 0,
parameter [ 0:0] VAR84 = 0,
parameter [ 0:0] VAR15... | mit |
tinkercnc/spi-fpga-driver | pluto_spi_servo_firmware/spi_servo_rspi.v | 8,685 | module MODULE1(clk, VAR10, VAR8, VAR3, VAR64, VAR37, VAR50, VAR46, VAR17, VAR35, VAR16, VAR9, VAR12, VAR33, dout, din);
parameter VAR14=14;
input clk;
input VAR10, VAR64, VAR8, VAR46;
output VAR3, VAR50, VAR17;
output VAR37;
input [7:0] din;
input [3:0] VAR35;
input [3:0] VAR16;
input [3:0] VAR9;
wire VAR59;
assign VAR... | gpl-2.0 |
ptracton/wb_dsp | rtl/equation_sum.v | 1,677 | module MODULE1 (
VAR20, VAR18, VAR12, VAR16, VAR7, VAR9,
VAR15, VAR2, VAR8,
VAR1, VAR14, VAR11, VAR13, VAR10, VAR4,
VAR3, VAR5
) ;
parameter VAR19 = 32;
parameter VAR6 = 32;
parameter VAR17 = 0;
input VAR1;
input VAR14;
output wire [VAR6-1:0] VAR20;
output wire [VAR19-1:0] VAR18;
output wire [3:0] VAR12;
output wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/maj3/sky130_fd_sc_hd__maj3_4.v | 2,174 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR2 ,
VAR10 ,
VAR3,
VAR1,
VAR4 ,
VAR8
);
output VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
input VAR3;
input VAR1;
input VAR4 ;
input VAR8 ;
VAR6 VAR5 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/apu/apu.v | 6,725 | module MODULE1(
input VAR52, input VAR4, input [ 3:0] VAR2, input [15:0] VAR22, input [ 7:0] din, input VAR54, output VAR71, output [ 7:0] dout );
localparam [15:0] VAR24 = 16'h4000;
localparam [15:0] VAR69 = 16'h4004;
localparam [15:0] VAR49 = 16'h4008;
localparam [15:0] VAR50 = 16'h400C;
localparam [15:0] VAR1 = 16'h... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_ctrl.v | 26,880 | module MODULE1(
clk, rst,
VAR58, VAR46, VAR72, VAR36, VAR23, VAR26, VAR41, VAR50,
VAR54, VAR87, VAR24, VAR47, VAR100, VAR91, VAR85, VAR74, VAR19, VAR15,
VAR75, VAR84, VAR71, VAR32, VAR48, VAR59, VAR9,
VAR7, VAR1,
VAR40, VAR70, VAR34, VAR17, VAR3, VAR27,
VAR99, VAR49, VAR93, VAR37, VAR2, VAR83, VAR11
);
input clk;
input... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_iddr_phy.v | 1,394 | module MODULE1
(input VAR1
,input [VAR2-1:0] VAR4
,output [2*VAR2-1:0] VAR7
);
logic [2*VAR2-1:0] VAR3;
logic [VAR2-1:0] VAR5, VAR6;
assign VAR7 = VAR3;
VAR8 @(posedge VAR1)
VAR6 <= VAR4;
VAR8 @(negedge VAR1)
VAR5 <= VAR4;
VAR8 @(posedge VAR1)
VAR3 <= {VAR5, VAR6};
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen/sky130_fd_io__top_refgen.pp.blackbox.v | 2,253 | module MODULE1 (
VAR11 ,
VAR14 ,
VAR8,
VAR16 ,
VAR13 ,
VAR17 ,
VAR12 ,
VAR4 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR18 ,
VAR6 ,
VAR15 ,
VAR9 ,
VAR10 ,
VAR1 ,
VAR5
);
output VAR11 ;
output VAR14 ;
inout VAR8;
input VAR16 ;
input VAR13 ;
input VAR17 ;
input VAR12 ;
input VAR4 ;
input VAR3 ;
input VAR2 ;
inout VAR7 ;
inout VAR18 ;
inou... | apache-2.0 |
bunnie/novena-sd-fpga | novena-sd.srcs/sources_1/imports/romulator.v | 16,817 | module MODULE1(
input wire clk,
input wire VAR59,
input wire VAR19,
input wire VAR28,
input wire VAR34,
output wire VAR26,
input wire VAR3,
input wire VAR51,
input wire [7:0] VAR45,
output wire [7:0] VAR35,
output wire VAR69,
output wire [15:0] VAR30,
output wire [7:0] VAR27,
input wire [7:0] VAR2,
output wire VAR33,
o... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.behavioral.pp.v | 1,388 | module MODULE1( VAR5, VAR1, VAR6, VAR7, VAR3, VAR10, VAR9 );
input VAR5, VAR1, VAR6, VAR7;
inout VAR10, VAR9;
output VAR3;
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1),.VAR6(VAR6),.VAR7(VAR7),.VAR3(VAR3),.VAR10(VAR10),.VAR9(VAR9));
VAR4 VAR8(.VAR5(VAR5),.VAR1(VAR1),.VAR6(VAR6),.VAR7(VAR7),.VAR3(VAR3),.VAR10(VAR10),.VAR9(VAR9)); | apache-2.0 |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen/pmem_2kB.v | 5,544 | module MODULE1(VAR6,VAR18,VAR88,VAR22,VAR61,VAR65,VAR91,VAR62);
input [7:0] VAR6;
output [7:0] VAR18;
input VAR88, VAR22;
input [10:0] VAR61, VAR65;
input VAR91;
input VAR62;
wire VAR12, VAR32;
VAR12 VAR77(.VAR56(VAR12));
VAR32 VAR51(.VAR56(VAR32));
VAR82 VAR5(.VAR20(VAR32), .VAR84(VAR61[10]),
.VAR9(VAR61[9]), .VAR31(V... | bsd-3-clause |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/ovl_delta.v | 1,975 | module MODULE1 (VAR11, reset, enable, VAR4, VAR13, VAR10, VAR3, VAR5);
parameter VAR23 = VAR1;
parameter VAR2 = 1;
parameter VAR12 = 1;
parameter VAR17 = VAR20;
parameter VAR18 = VAR9;
parameter VAR7 = VAR8;
parameter VAR24 = VAR27;
parameter VAR26 = VAR6;
parameter VAR16 = VAR14;
input VAR11, reset, enable;
input [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.functional.pp.v | 1,866 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR7,
VAR3,
VAR12 ,
VAR2
);
output VAR6 ;
input VAR4 ;
input VAR7;
input VAR3;
input VAR12 ;
input VAR2 ;
wire VAR9 ;
wire VAR5;
buf VAR1 (VAR9 , VAR4 );
VAR11 VAR10 (VAR5, VAR9, VAR7, VAR3);
buf VAR8 (VAR6 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb.symbol.v | 1,333 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR9,
input VAR8,
output VAR2
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.behavioral.pp.v | 2,231 | module MODULE1 (
VAR12 ,
VAR15,
VAR19,
VAR1 ,
VAR14 ,
VAR16,
VAR2,
VAR17 ,
VAR18
);
output VAR12 ;
input VAR15;
input VAR19;
input VAR1 ;
input VAR14 ;
input VAR16;
input VAR2;
input VAR17 ;
input VAR18 ;
wire VAR9 ;
wire VAR6 ;
wire VAR4 ;
wire VAR3;
and VAR13 (VAR9 , VAR1, VAR14 );
nor VAR7 (VAR6 , VAR15, VAR19 );
or... | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/alu.v | 4,350 | module MODULE1 (
input wire [VAR5] VAR7,
input wire [VAR5] VAR11,
input wire [VAR10] VAR3,
output reg [VAR5] out,
output reg VAR8
);
wire signed [VAR5] VAR2 = (VAR7);
wire signed [VAR5] VAR1 = (VAR11);
wire signed [VAR5] VAR4 = (out);
always @ begin
case (VAR3)
if (((VAR2 > 0) && (VAR1 > 0) && (VAR4 < 0)) ||
((VAR2 < 0... | apache-2.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/video_scaler_sdivhbi.v | 5,852 | module MODULE2
VAR38 = 32,
VAR31 = 32,
VAR32 = 32
)
(
input clk,
input reset,
input VAR30,
input VAR27,
input [VAR38-1:0] VAR15,
input [VAR31-1:0] VAR2,
input [1:0] VAR16,
output wire [1:0] VAR34,
output wire VAR19,
output wire [VAR32-1:0] VAR39,
output wire [VAR32-1:0] VAR3
);
localparam VAR9 = (VAR38 > VAR31)? VAR38 ... | mit |
Elphel/x393_sata | x393/util_modules/fifo_same_clock_fill.v | 6,619 | module MODULE1
parameter integer VAR13=16,
parameter integer VAR15=4
)
(
input rst, input clk, input VAR2, input VAR17, input VAR26, input [VAR13-1:0] VAR14, output [VAR13-1:0] VAR16, output VAR4, output reg VAR21, output reg VAR12, output reg VAR7, output reg [VAR15-1:0] VAR8,
output reg [VAR15-1:0] VAR9,
output [VAR1... | gpl-3.0 |
peteasa/oh | src/common/hdl/oh_rsync.v | 1,137 | module MODULE1 #(parameter VAR4 = 2 )
(
input clk,
input VAR7,
output VAR1
);
localparam VAR8 = VAR6;
generate
if(VAR8)
begin : VAR2
VAR3 VAR3 (.clk(clk),
.VAR7(VAR7),
.VAR1(VAR1));
end
else
begin :VAR2
reg [VAR4-1:0] VAR5;
always @ (posedge clk or negedge VAR7)
if(!VAR7)
VAR5[VAR4-1:0] <= 1'b0;
end
else
VAR5[VAR4-1:0]... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_51.v | 35,433 | module MODULE4 (
clk,
reset,
VAR198,
VAR151,
VAR165,
VAR219,
VAR281
);
parameter VAR195 = 18;
parameter VAR152 = 51;
parameter VAR78 = 26;
localparam VAR205 = 58;
input clk;
input reset;
input VAR198;
input VAR151;
input [VAR195-1:0] VAR165; output VAR219;
output [VAR195-1:0] VAR281;
localparam VAR142 = 18; localparam ... | mit |
olajep/oh | src/adi/hdl/library/axi_dmac/splitter.v | 2,339 | module MODULE1 #(
parameter VAR6 = 2)(
input clk,
input VAR2,
input VAR4,
output VAR7,
output [VAR6-1:0] VAR5,
input [VAR6-1:0] VAR3
);
reg [VAR6-1:0] VAR1;
assign VAR7 = &(VAR3 | VAR1);
assign VAR5 = VAR4 ? ~VAR1 : {VAR6{1'b0}};
always @(posedge clk)
begin
if (VAR2 == 1'b0) begin
VAR1 <= {VAR6{1'b0}};
end else begin
i... | mit |
Elphel/x353 | control/twelve_ios.v | 7,782 | module MODULE1 (VAR17, VAR52, VAR28, VAR46, VAR43, VAR44, VAR48, VAR55, VAR23, VAR19, VAR42); input VAR17;
input VAR52;
input [15:0] VAR28;
output [11:0] VAR46;
output [11:0] VAR43;
input [11:0] VAR44;
input [11:0] VAR48;
input [11:0] VAR55;
input [11:0] VAR23;
input [11:0] VAR19;
input [11:0] VAR42;
wire [11:0] VAR39;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b.symbol.v | 1,323 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR4 ,
input VAR1,
output VAR6
);
supply1 VAR5;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/switch_pio.v | 1,872 | module MODULE1 (
address,
clk,
VAR4,
VAR2,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 17: 0] VAR4;
input VAR2;
wire VAR5;
wire [ 17: 0] VAR1;
wire [ 17: 0] VAR6;
reg [ 31: 0] VAR3;
assign VAR5 = 1;
assign VAR6 = {18 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR2)
begin
if (... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ui_wr_data.v | 21,329 | module MODULE1 #
(
parameter VAR84 = 100,
parameter VAR12 = 256,
parameter VAR107 = 32,
parameter VAR50 = "VAR90",
parameter VAR88 = 2 ,
parameter VAR70 = "VAR90",
parameter VAR75 = 5
)
(
VAR1, VAR31, VAR27, VAR68, VAR99,
VAR4,
rst, clk, VAR93, VAR47, VAR16, VAR7,
VAR79, VAR38, VAR71, VAR94, VAR108,
VAR69, VAR43
);
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3/sky130_fd_sc_hd__nor3.pp.blackbox.v | 1,321 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR6 ,
VAR2 ,
VAR5,
VAR8,
VAR3 ,
VAR7
);
output VAR4 ;
input VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR5;
input VAR8;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl.symbol.v | 1,424 | module MODULE1 (
input VAR5,
output VAR6
);
supply1 VAR4 ;
supply0 VAR2 ;
supply1 VAR1;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_phy_10g.v | 4,260 | module MODULE1 #
(
parameter VAR7 = 64,
parameter VAR13 = (VAR7/8),
parameter VAR2 = 2,
parameter VAR19 = 0,
parameter VAR24 = 0,
parameter VAR22 = 0,
parameter VAR39 = 0,
parameter VAR30 = 0,
parameter VAR6 = 1,
parameter VAR14 = 8,
parameter VAR20 = 125000/6.4
)
(
input wire VAR1,
input wire VAR27,
input wire VAR33,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv.pp.symbol.v | 1,268 | module MODULE1 (
input VAR4 ,
output VAR5,
input VAR1 ,
input VAR3 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi.functional.pp.v | 2,172 | module MODULE1 (
VAR14 ,
VAR16 ,
VAR5 ,
VAR8,
VAR4,
VAR18,
VAR3 ,
VAR1
);
output VAR14 ;
input VAR16 ;
input VAR5 ;
input VAR8;
input VAR4;
input VAR18;
input VAR3 ;
input VAR1 ;
wire VAR17 ;
wire VAR10 ;
wire VAR15 ;
wire VAR12;
not VAR7 (VAR17 , VAR8 );
and VAR13 (VAR10 , VAR16, VAR5 );
nor VAR11 (VAR15 , VAR17, VAR1... | apache-2.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_transceiver_tile.v | 37,018 | module MODULE1 #
(
parameter VAR189 = "VAR351", parameter VAR304 = 0, parameter VAR259 = 9'h140,
parameter VAR220 = "VAR162", parameter VAR331 = 0,
parameter VAR52 = "VAR162", parameter VAR225 = 0 )
(
VAR300,
VAR443,
VAR418,
VAR112,
VAR251,
VAR62,
VAR55,
VAR335,
VAR229,
VAR3,
VAR285,
VAR277,
VAR339,
VAR385,
VAR356,
VAR... | gpl-3.0 |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11/regfile.v | 2,608 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR8,
input wire[VAR18] VAR2,
input wire[VAR16] VAR1,
input wire VAR10,
input wire[VAR18] VAR4,
output reg[VAR16] VAR5,
input wire VAR15,
input wire[VAR18] VAR9,
output reg[VAR16] VAR19
);
reg[VAR16] VAR3[0:VAR13-1];
always @ (posedge clk) begin
if (rst == VAR1... | gpl-3.0 |
orbancedric/DeepGate | src/interface/mojo/master_control.v | 9,450 | module MODULE1 (
input clk,
input rst,
input VAR21,
input VAR24,
input [7:0] VAR19,
output reg [7:0] VAR29 = 8'd0,
output reg VAR14 = 0,
input VAR31,
input VAR6,
input VAR37,
input [7:0] VAR26,
output reg [7:0] VAR47 = 8'd0,
output reg VAR39 = 0,
output reg VAR5 = 0,
input [VAR20 - 1'b1 : 0] VAR35,
output reg [VAR20 - ... | gpl-3.0 |
ineganov/flight_control | hard/alu.v | 4,498 | module MODULE1( input [7:0] VAR26,
input [31:0] VAR11,
input [31:0] VAR18,
input [4:0] VAR27,
output [31:0] VAR28 );
wire VAR22 = VAR26[7] ? VAR11[31] : 1'b0;
wire VAR12 = VAR26[7] ? VAR18[31] : 1'b0;
wire [32:0] VAR2 = {VAR22, VAR11};
wire [32:0] VAR25 = {VAR12, VAR18};
wire VAR10 = VAR26[3]; wire [32:0] VAR5 = VAR10 ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp.functional.v | 1,790 | module MODULE1 (
VAR9,
VAR1,
VAR7 ,
VAR3 ,
VAR4 ,
VAR5 ,
VAR6
);
input VAR9;
input VAR1;
output VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR6 ;
wire VAR8 ;
wire VAR12;
VAR11 VAR14 (VAR12, VAR4, VAR5, VAR6 );
VAR13 VAR10 VAR2 (VAR8 , VAR12, VAR3, VAR9, VAR1);
buf VAR15 (VAR7 , VAR8 );
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_POST_FIFO.v | 13,464 | module MODULE1(
rst,
VAR169,
VAR242,
din,
VAR151,
VAR380,
dout,
VAR174,
VAR195,
valid
);
input rst;
input VAR169;
input VAR242;
input [63 : 0] din;
input VAR151;
input VAR380;
output [255 : 0] dout;
output VAR174;
output VAR195;
output valid;
VAR372 #(
.VAR18(0),
.VAR402(0),
.VAR70(0),
.VAR154(0),
.VAR136(0),
.VAR104(0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o_1.v | 2,437 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR4 ,
VAR8 ,
VAR7 ,
VAR12 ,
VAR11,
VAR3,
VAR2 ,
VAR9
);
output VAR10 ;
input VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR12 ;
input VAR11;
input VAR3;
input VAR2 ;
input VAR9 ;
VAR5 VAR1 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.functional.pp.v | 1,416 | module MODULE1( VAR9, VAR15, VAR6, VAR12, VAR16, VAR11, VAR5 );
input VAR16, VAR12, VAR6, VAR15;
inout VAR11, VAR5;
output VAR9;
wire VAR13;
not VAR14( VAR13, VAR16 );
wire VAR3;
not VAR8( VAR3, VAR12 );
wire VAR2;
not VAR4( VAR2, VAR6 );
wire VAR1;
not VAR10( VAR1, VAR15 );
or VAR7( VAR9, VAR13, VAR3, VAR2, VAR1 );
en... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/rtl_model/ram_dp.v | 4,140 | module MODULE1 (
VAR19 ,
VAR3 ,
VAR17 ,
VAR7 ,
VAR21 ,
VAR13 ,
VAR4 ,
VAR10 ,
VAR9 ,
VAR1 ,
VAR11 ,
VAR8 ,
VAR16 ,
VAR12
);
parameter VAR5=32;
parameter VAR2=8;
input VAR19; input VAR3; input VAR17; input VAR7; input [VAR2-1:0] VAR21; input [VAR5-1:0] VAR4; output [VAR5-1:0] VAR13;
input VAR10; input VAR9; input VAR1; ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/phy/phy_top.v | 54,004 | module MODULE1 #
(
parameter VAR240 = 100,
parameter VAR54 = 2, parameter VAR69 = 3333, parameter VAR97 = 300.0, parameter VAR156 = "VAR328", parameter [7:0] VAR335 = 8'b00000001,
parameter [7:0] VAR228 = 8'b00000000,
parameter VAR198 = 2, parameter VAR283 = 1, parameter VAR205 = 10, parameter VAR207 = 1, parameter VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21o/sky130_fd_sc_hvl__a21o.pp.symbol.v | 1,348 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR8 ,
output VAR7 ,
input VAR4 ,
input VAR6,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
AngelTerrones/ADA | rtl/ada_idu.v | 16,409 | module MODULE1(
input [5:0] VAR34, input [5:0] VAR31, input VAR30,
output VAR4, output VAR15, output VAR11, output VAR23, output VAR36, output VAR26, output VAR18, output [4:0] VAR24, output [2:0] VAR16, output VAR35, output VAR20, output VAR17, output VAR6, output VAR9, output VAR12, output VAR33, output VAR5, output ... | mit |
neale/CS-program | 474-VLSI/Lab_5/db/frame_rate_altpll.v | 4,346 | module MODULE1
(
clk,
VAR5,
VAR32) ;
output [4:0] clk;
input [1:0] VAR5;
output VAR32;
tri0 [1:0] VAR5;
wire [4:0] VAR36;
wire VAR37;
wire VAR31;
VAR45 VAR16
(
.VAR42(),
.clk(VAR36),
.VAR23(),
.VAR3(VAR37),
.VAR28(VAR37),
.VAR5(VAR5),
.VAR32(VAR31),
.VAR25(),
.VAR6(),
.VAR20(),
.VAR43(),
.VAR8()
,
.VAR26(1'b0),
.VAR27(... | unlicense |
richard42/CoCo3FPGA | COCO3GEN_bb.v | 5,284 | module MODULE1 (
address,
VAR2,
VAR1);
input [10:0] address;
input VAR2;
output [7:0] VAR1;
tri1 VAR2;
endmodule | bsd-3-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_mmcm_drp.v | 7,536 | module MODULE1 (
clk,
VAR53,
VAR24,
VAR23,
VAR48,
VAR72,
VAR63,
VAR39,
VAR62,
VAR44,
VAR87,
VAR27,
VAR14);
parameter VAR40 = 0;
localparam VAR89 = 0;
localparam VAR33 = 1;
parameter VAR30 = 1.667;
parameter VAR9 = 6;
parameter VAR78 = 12.000;
parameter VAR12 = 2.000;
parameter VAR64 = 6;
input clk;
input VAR53;
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4bb/sky130_fd_sc_ms__nor4bb.functional.pp.v | 1,998 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8 ,
VAR17 ,
VAR6 ,
VAR3,
VAR16,
VAR13 ,
VAR10
);
output VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR17 ;
input VAR6 ;
input VAR3;
input VAR16;
input VAR13 ;
input VAR10 ;
wire VAR11 ;
wire VAR15 ;
wire VAR1;
nor VAR7 (VAR11 , VAR4, VAR8 );
and VAR12 (VAR15 , VAR11, VAR17, VAR6 );
VAR9 VA... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_jtag_sld_node.v | 6,693 | module MODULE1 (
VAR56,
VAR58,
VAR24,
VAR64,
VAR60,
VAR72,
VAR11,
VAR50,
VAR39,
VAR80,
VAR74,
VAR71,
VAR8
);
parameter VAR14 = 20;
localparam VAR7 = (1000/VAR14)/2;
localparam VAR22 = 3;
input [VAR22 - 1:0] VAR56;
input VAR58;
output reg [VAR22 - 1:0] VAR24;
output VAR64;
output reg VAR60 = 1'b0;
output VAR72;
output V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4/sky130_fd_sc_ls__nand4.behavioral.pp.v | 1,846 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR5 ,
VAR14 ,
VAR3 ,
VAR4,
VAR10,
VAR13 ,
VAR15
);
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR14 ;
input VAR3 ;
input VAR4;
input VAR10;
input VAR13 ;
input VAR15 ;
wire VAR7 ;
wire VAR6;
nand VAR12 (VAR7 , VAR3, VAR14, VAR5, VAR8 );
VAR1 VAR9 (VAR6, VAR7, VAR4, VAR10);
buf VAR11 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211o/sky130_fd_sc_hd__a211o.behavioral.pp.v | 2,032 | module MODULE1 (
VAR13 ,
VAR15 ,
VAR2 ,
VAR12 ,
VAR6 ,
VAR5,
VAR16,
VAR11 ,
VAR14
);
output VAR13 ;
input VAR15 ;
input VAR2 ;
input VAR12 ;
input VAR6 ;
input VAR5;
input VAR16;
input VAR11 ;
input VAR14 ;
wire VAR1 ;
wire VAR7 ;
wire VAR4;
and VAR9 (VAR1 , VAR15, VAR2 );
or VAR10 (VAR7 , VAR1, VAR6, VAR12 );
VAR17 VA... | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_branch_unit.v | 4,492 | module MODULE1 (
input [5:0] VAR19, input [31:0] VAR2, input [31:0] VAR7, input [31:0] VAR16, input [25:0] VAR14, output reg [31:0] VAR13, output reg VAR18 ) ;
wire VAR21;
wire VAR15;
wire VAR20;
wire VAR3;
wire VAR17;
wire VAR9;
wire [31:0] VAR11;
wire [31:0] VAR10;
wire [5:0] VAR12;
wire [4:0] VAR4;
assign VAR21 = VA... | mit |
CospanDesign/nysa-verilog | verilog/generic/adapter_axi_stream_2_block_fifo.v | 4,247 | module MODULE1 #(
parameter VAR14 = 32,
parameter VAR12 = VAR14 / 8,
parameter VAR13 = 0
)(
input rst,
input VAR4,
output VAR11,
input [VAR14 - 1:0] VAR10,
input [VAR12 - 1:0] VAR9,
input VAR17,
input VAR16,
output VAR3,
input VAR18,
output reg VAR19,
input [23:0] VAR2,
output reg VAR5,
output reg [VAR14 - 1:0] VAR1
);... | mit |
iori-yja/ball_detector | ball_color.v | 2,923 | module MODULE1(
input clk,
input [8:0] VAR18,
input [4:0] VAR10,
input [4:0] VAR33,
input write,
input [9:0] VAR15,
output reg VAR16,
output [7:0] VAR18,
output [4:0] VAR10,
output [4:0] VAR33,
output [2:0] VAR4
);
reg [7:0] VAR29;
reg [4:0] VAR28;
reg [4:0] VAR13;
reg [3:0] state;
parameter VAR34 = 4'h0,
VAR27 = 4'h1,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311a/sky130_fd_sc_ms__o311a.pp.symbol.v | 1,379 | module MODULE1 (
input VAR9 ,
input VAR7 ,
input VAR1 ,
input VAR4 ,
input VAR2 ,
output VAR6 ,
input VAR5 ,
input VAR8,
input VAR10,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41a/sky130_fd_sc_hs__o41a.functional.v | 1,939 | module MODULE1 (
VAR13,
VAR7,
VAR9 ,
VAR11 ,
VAR10 ,
VAR3 ,
VAR14 ,
VAR6
);
input VAR13;
input VAR7;
output VAR9 ;
input VAR11 ;
input VAR10 ;
input VAR3 ;
input VAR14 ;
input VAR6 ;
wire VAR14 VAR5 ;
wire VAR1 ;
wire VAR2;
or VAR12 (VAR5 , VAR14, VAR3, VAR10, VAR11 );
and VAR15 (VAR1 , VAR5, VAR6 );
VAR4 VAR8 (VAR2, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4.behavioral.pp.v | 1,870 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR2 ,
VAR5 ,
VAR15 ,
VAR14,
VAR10,
VAR3 ,
VAR1
);
output VAR8 ;
input VAR9 ;
input VAR2 ;
input VAR5 ;
input VAR15 ;
input VAR14;
input VAR10;
input VAR3 ;
input VAR1 ;
wire VAR11 ;
wire VAR7;
nor VAR12 (VAR11 , VAR9, VAR2, VAR5, VAR15 );
VAR4 VAR6 (VAR7, VAR11, VAR14, VAR10);
buf VAR13 ... | apache-2.0 |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/eth_dma_aggr.v | 7,268 | module MODULE1
parameter VAR44 = 64,
parameter VAR22 = VAR44/8,
parameter VAR20 = 1,
parameter VAR21 = 'hff,
parameter VAR29 = 32,
parameter VAR45 = VAR29/8
)
(input [VAR44-1:0] VAR46,
input [VAR22-1:0] VAR47,
input VAR58,
output VAR50,
input [VAR44-1:0] VAR34,
input [VAR22-1:0] VAR61,
input VAR24,
output VAR4,
output ... | lgpl-2.1 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.functional.pp.v | 1,772 | module MODULE1( VAR19, VAR10, VAR15, VAR8, VAR27, VAR12, VAR18 );
input VAR10, VAR8, VAR15;
inout VAR12, VAR18;
output VAR27, VAR19;
wire VAR29;
and VAR7( VAR29, VAR10, VAR8 );
wire VAR2;
and VAR13( VAR2, VAR10, VAR15 );
wire VAR3;
and VAR6( VAR3, VAR8, VAR15 );
or VAR21( VAR27, VAR29, VAR2, VAR3 );
wire VAR4;
and VAR1... | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_0_ecc_merge_enc.v | 5,947 | module MODULE1
parameter VAR29 = 100,
parameter VAR25 = 64,
parameter VAR19 = 72,
parameter VAR6 = 4,
parameter VAR3 = 1,
parameter VAR10 = 64,
parameter VAR11 = 72,
parameter VAR12 = 8,
parameter VAR20 = 4
)
(
VAR8, VAR5,
clk, rst, VAR4, VAR22, VAR1, VAR9, VAR24
);
input clk;
input rst;
input [2*VAR20*VAR25-1:0] VAR4;... | mit |
sirchuckalot/zet | cores/vga/rtl/vga_linear.v | 2,720 | module MODULE1 (
input clk,
input rst,
output [17:1] VAR6,
input [15:0] VAR4,
output VAR12,
input [9:0] VAR13,
input [9:0] VAR14,
input VAR3,
input VAR1,
output VAR2,
output [7:0] VAR17,
output VAR15
);
reg [ 9:0] VAR9;
reg [ 6:0] VAR16;
reg [14:1] VAR18;
reg [ 1:0] VAR5;
reg [ 1:0] VAR7;
reg [ 7:0] VAR11;
reg [4:0] VA... | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | contador_AD_MM_2dig.v | 4,708 | module MODULE1
(
input wire clk,
input wire reset,
input wire [3:0] VAR8,
input wire VAR7,
input wire VAR3,
output wire [7:0] VAR4
);
localparam VAR10 = 6; reg [VAR10-1:0] VAR9, VAR2;
wire [VAR10-1:0] VAR1;
reg [3:0] VAR6, VAR5;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR9 <= 6'b0;
end
else
begin
VAR9... | mit |
martinmiranda14/Digitales | Lab_6/Lab_6_prev_1.v | 2,199 | module MODULE1(
input VAR2,
input VAR3,
input VAR22,
input VAR6,
output VAR7,VAR19,VAR11,VAR18,VAR15,VAR24,VAR16,VAR26,
output [10:0] VAR10
);
wire reset;
wire VAR23;
reg VAR1,VAR21;
wire [2:0] VAR9;
wire [7:0] VAR20;
wire VAR12;
wire VAR8;
reg VAR14;
assign reset= ~VAR3;
assign VAR10[7:0]=VAR20;
assign VAR10[10:8]=VAR... | apache-2.0 |
tmolteno/TART | hardware/FPGA/fifo/async/afifo16.v | 6,828 | module MODULE1 #(
parameter VAR35 = 32,
parameter VAR14 = 4,
parameter VAR3 = VAR35 - 1,
parameter VAR18 = VAR14 - 1
) (
input VAR27,
input VAR40,
input VAR41,
output [VAR3:0] VAR22,
input VAR10,
input VAR7,
input [VAR3:0] VAR21,
output reg VAR39 = 1,
output reg VAR29 = 0,
output reg VAR5 = 0,
output reg VAR19 = 0
);
r... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbn/sky130_fd_sc_hd__sdfbbn.functional.pp.v | 2,700 | module MODULE1 (
VAR10 ,
VAR25 ,
VAR19 ,
VAR26 ,
VAR20 ,
VAR3 ,
VAR18 ,
VAR16,
VAR12 ,
VAR24 ,
VAR13 ,
VAR17
);
output VAR10 ;
output VAR25 ;
input VAR19 ;
input VAR26 ;
input VAR20 ;
input VAR3 ;
input VAR18 ;
input VAR16;
input VAR12 ;
input VAR24 ;
input VAR13 ;
input VAR17 ;
wire VAR27 ;
wire VAR5 ;
wire VAR2 ;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_1.v | 2,552 | module MODULE1 (
VAR4,
VAR11 ,
VAR2 ,
VAR10 ,
VAR5 ,
VAR3 ,
VAR7 ,
VAR1 ,
VAR6
);
input VAR4;
input VAR11 ;
input VAR2 ;
output VAR10 ;
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR6 ;
VAR9 VAR8 (
.VAR4(VAR4),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai.functional.pp.v | 2,065 | module MODULE1 (
VAR12 ,
VAR13 ,
VAR17 ,
VAR10 ,
VAR11 ,
VAR4 ,
VAR1,
VAR18,
VAR16 ,
VAR2
);
output VAR12 ;
input VAR13 ;
input VAR17 ;
input VAR10 ;
input VAR11 ;
input VAR4 ;
input VAR1;
input VAR18;
input VAR16 ;
input VAR2 ;
wire VAR5 ;
wire VAR8 ;
wire VAR6;
or VAR9 (VAR5 , VAR17, VAR13, VAR10 );
nand VAR14 (VAR8 ... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/ime/ime_best_mv_above_16.v | 32,008 | module MODULE1 (
clk ,
VAR35 ,
VAR197 ,
VAR142 ,
VAR102 ,
VAR160 ,
VAR6 ,
VAR135 ,
VAR64 , VAR156 , VAR69 , VAR93 ,
VAR16 , VAR41 , VAR188 , VAR57 ,
VAR153 , VAR136 , VAR190 , VAR30 ,
VAR22 , VAR119 , VAR72 , VAR163 ,
VAR74 ,
VAR116 ,
VAR165 , VAR191 ,
VAR187 , VAR14 ,
VAR182 , VAR140 ,
VAR112 , VAR141 ,
VAR81 , VAR97 ... | gpl-3.0 |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_mm_interconnect_0_avalon_st_adapter.v | 6,167 | module MODULE1 #(
parameter VAR18 = 34,
parameter VAR8 = 0,
parameter VAR11 = 34,
parameter VAR14 = 0,
parameter VAR13 = 0,
parameter VAR4 = 0,
parameter VAR9 = 1,
parameter VAR5 = 1,
parameter VAR2 = 0,
parameter VAR23 = 34,
parameter VAR1 = 0,
parameter VAR21 = 1,
parameter VAR10 = 0,
parameter VAR20 = 1,
parameter V... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.behavioral.v | 1,718 | module MODULE1( VAR1, VAR8, VAR9 );
input VAR8, VAR1;
output VAR9;
reg VAR11;
VAR2 VAR4(.VAR1(VAR1),.VAR8(VAR8),.VAR9(VAR9),.VAR11(VAR11));
VAR2 VAR10(.VAR1(VAR1),.VAR8(VAR8),.VAR9(VAR9),.VAR11(VAR11));
not VAR6(VAR7,VAR8);
buf VAR5(VAR3,VAR8); | apache-2.0 |
mdsalman729/flexpret_project | fpga/generated-src/4tf-32i-32d-mul-ti/Core.v | 161,873 | module MODULE1(input clk, input reset,
input [3:0] VAR3,
input [3:0] VAR19,
input [3:0] VAR204,
input [3:0] VAR55,
input [3:0] VAR247,
input [3:0] VAR195,
input [3:0] VAR123,
input [3:0] VAR60,
input [1:0] VAR106,
input [1:0] VAR24,
input [1:0] VAR18,
input [1:0] VAR78,
output[1:0] VAR144,
output VAR112
);
wire VAR133;... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.v | 2,163 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR1,
VAR8,
VAR4 ,
VAR2
);
output VAR7 ;
input VAR5 ;
input VAR1;
input VAR8;
input VAR4 ;
input VAR2 ;
VAR3 VAR6 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR7,
VAR5
);
output VAR7;
input VAR5;
supply1 VAR1;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22oi/sky130_fd_sc_hs__a22oi.symbol.v | 1,335 | module MODULE1 (
input VAR1,
input VAR4,
input VAR3,
input VAR6,
output VAR2
);
supply1 VAR5;
supply0 VAR7;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_36b_v1_00_a/hdl/verilog/cf_hdmi.v | 13,339 | module MODULE1 (
VAR12,
VAR17,
VAR55,
VAR36,
VAR15,
VAR56,
VAR44,
VAR37,
VAR66,
VAR90,
VAR80,
VAR46,
VAR39,
VAR28,
VAR70,
VAR54,
VAR10,
VAR43,
VAR1,
VAR96,
VAR81,
VAR92,
VAR27,
VAR84,
VAR29,
VAR52,
VAR33,
VAR51,
VAR26);
input VAR12;
output VAR17;
output VAR55;
output VAR36;
output [35:0] VAR15;
output VAR56;
output [ 8... | mit |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/core/pulse_synchronizer.v | 2,307 | module MODULE1
( input VAR15,
input VAR12,
output VAR6,
input VAR8,
input VAR14,
input VAR4
);
reg VAR10;
reg VAR13;
reg VAR3;
reg VAR2;
reg VAR1;
reg VAR11;
reg VAR5;
reg VAR9;
reg VAR7;
always @(posedge VAR12) begin
if(VAR14) begin
VAR10 <= 0;
end
else if(!VAR5 & VAR15) begin
VAR10 <= 1;
end
else if(VAR11) begin
VAR1... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpad/sky130_fd_io__top_power_hvc_wpad.blackbox.v | 1,601 | module MODULE1 (
VAR4 ,
VAR12,
VAR14
);
inout VAR4 ;
inout VAR12;
inout VAR14;
supply1 VAR10 ;
supply1 VAR16 ;
supply0 VAR2;
supply1 VAR15 ;
supply1 VAR7 ;
supply1 VAR1 ;
supply1 VAR17 ;
supply1 VAR11 ;
supply1 VAR5 ;
supply1 VAR13 ;
supply0 VAR3 ;
supply0 VAR6 ;
supply0 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2/sky130_fd_sc_hs__and2.functional.pp.v | 1,681 | module MODULE1 (
VAR4,
VAR8,
VAR10 ,
VAR6 ,
VAR5
);
input VAR4;
input VAR8;
output VAR10 ;
input VAR6 ;
input VAR5 ;
wire VAR2 ;
wire VAR3;
and VAR11 (VAR2 , VAR6, VAR5 );
VAR9 VAR7 (VAR3, VAR2, VAR4, VAR8);
buf VAR1 (VAR10 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb.behavioral.pp.v | 2,000 | module MODULE1 (
VAR17 ,
VAR4 ,
VAR16 ,
VAR7 ,
VAR15 ,
VAR2,
VAR10,
VAR5 ,
VAR6
);
output VAR17 ;
input VAR4 ;
input VAR16 ;
input VAR7 ;
input VAR15 ;
input VAR2;
input VAR10;
input VAR5 ;
input VAR6 ;
wire VAR12 ;
wire VAR13 ;
wire VAR3;
nand VAR14 (VAR12 , VAR15, VAR7 );
or VAR9 (VAR13 , VAR16, VAR4, VAR12 );
VAR11 ... | apache-2.0 |
aneez/nexys-fpga-exp | vSevenSegmentDisplay/clkEnable_gen.v | 1,035 | module MODULE1
parameter VAR7 = 5000000)
(
output reg enable,
input VAR2,
input VAR6
);
reg [31:0]VAR3;
reg VAR5;
wire rst;
VAR1 VAR3 =31'b1;
VAR1 VAR5 = 1;
VAR1 enable = 0;
assign rst = VAR6 | VAR5;
always @(posedge VAR2)
begin
if(rst)
VAR3 <= 1;
end
else
VAR3 <= VAR3+1;
end
always @*
begin
if(VAR3==VAR4)
begin
enable... | gpl-2.0 |
freecores/raggedstone | source/pcipargen.v | 1,871 | module MODULE1 (VAR8, VAR4, VAR11, VAR5, VAR6);
input VAR8;
input [31:0] VAR4;
input [3:0] VAR11;
input VAR5;
output VAR6;
wire [31:0] VAR1;
wire VAR9;
wire VAR3;
wire VAR7;
wire VAR2;
assign VAR1 = VAR4;
assign VAR9 = VAR1[0] ^ VAR1[1] ^ VAR1[2] ^ VAR1[3] ^ VAR1[4] ^ VAR1[5] ^ VAR1[6] ^ VAR1[7] ^
VAR1[8] ^ VAR1[9] ^ V... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.behavioral.pp.v | 1,187 | module MODULE1( VAR6, VAR4, VAR5, VAR1 );
input VAR6;
inout VAR5, VAR1;
output VAR4;
VAR2 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1));
VAR2 VAR7(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp.functional.v | 1,972 | module MODULE1 (
VAR15 ,
VAR9 ,
VAR10 ,
VAR3 ,
VAR6 ,
VAR14
);
output VAR15 ;
input VAR9 ;
input VAR10 ;
input VAR3 ;
input VAR6 ;
input VAR14;
wire VAR4 ;
wire VAR1 ;
wire VAR2;
not VAR11 (VAR1 , VAR14 );
VAR13 VAR12 (VAR2, VAR10, VAR3, VAR6 );
VAR16 VAR5 VAR8 (VAR4 , VAR2, VAR9, VAR1);
buf VAR7 (VAR15 , VAR4 );
endmo... | apache-2.0 |
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