repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
MeshSr/onetswitch30 | ons30-app21-ref_switch/vivado/onets_7030_4x_ref_switch/ip/ref_switch_core/src/udp/in_arb_regs.v | 6,789 | module MODULE1
parameter VAR38 = VAR25/8,
parameter VAR42 = 2
)
(
input VAR13,
input VAR30,
input VAR28,
input [VAR33-1:0] VAR35,
input [VAR36-1:0] VAR34,
input [VAR42-1:0] VAR1,
output reg VAR22,
output reg VAR19,
output reg VAR31,
output reg [VAR33-1:0] VAR44,
output reg [VAR36-1:0] VAR32,
output reg [VAR42-1:0] VAR4... | lgpl-2.1 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/011J1G2/hdl/periferico_altavoz/peripheral_pwm.v | 1,650 | module MODULE1(clk , rst , din , VAR3 , addr, dout, VAR1, VAR11, VAR4,VAR6);
input clk;
input rst;
input [15:0]din;
input VAR3;
input [3:0]addr; output [15:0]dout;
output VAR11;
output VAR1;
output VAR4;
output VAR6;
wire VAR5;
wire VAR2;
wire VAR14;
wire enable;
reg [2:0] VAR13;
VAR12 VAR7(.reset(rst), .clk(clk), .VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor2/sky130_fd_sc_ms__xor2_1.v | 2,117 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR9 ,
VAR6,
VAR7,
VAR5 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR6;
input VAR7;
input VAR5 ;
input VAR2 ;
VAR8 VAR4 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR1,
VAR3,
VAR9
);
output VAR1;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4.blackbox.v | 1,281 | module MODULE1 (
VAR1,
VAR9,
VAR4,
VAR7,
VAR5
);
output VAR1;
input VAR9;
input VAR4;
input VAR7;
input VAR5;
supply1 VAR6;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai.blackbox.v | 1,389 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR1 ,
VAR6
);
output VAR3 ;
input VAR8 ;
input VAR1 ;
input VAR6;
supply1 VAR5;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_gen_clock.v | 1,176 | module MODULE1(
VAR14,
VAR18,
VAR6,
VAR4,
VAR5,
VAR17
);
input VAR14;
output VAR18;
output VAR6;
output VAR4;
output VAR5;
output VAR17;
parameter VAR9 = 50;
parameter VAR12 = 50;
parameter VAR13 = 50;
parameter VAR11 = 50;
reg VAR10 = 1'b0;
reg VAR2 = 1'b0;
reg VAR7 = 1'b0;
reg VAR15 = 1'b0;
reg VAR18 = 1'b0;
assign V... | mit |
dingzh/piplined-MIPS-CPU | src/LAB3/Alu.v | 1,373 | module MODULE1(
input [31:0] VAR2,
input [31:0] VAR3,
input [3:0] VAR5,
output reg VAR1,
output reg [31:0] VAR4
);
always @(VAR2 or VAR3 or VAR5)
begin
case(VAR5)
'b0000: begin VAR4 = VAR2 & VAR3;
VAR1 = 0;
end
'b0001: begin VAR4 = VAR2 | VAR3;
VAR1 = 0;
end
'b0010: begin VAR4 = VAR2 + VAR3;
VAR1 = 0;
end
'b0110: begin... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a_0.v | 2,444 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR11 ,
VAR6 ,
VAR10 ,
VAR1 ,
VAR12,
VAR3,
VAR7 ,
VAR8
);
output VAR9 ;
input VAR4 ;
input VAR11 ;
input VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR12;
input VAR3;
input VAR7 ;
input VAR8 ;
VAR2 VAR5 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf.pp.symbol.v | 1,244 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR2 ,
input VAR1,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
richard42/CoCo3FPGA | disk02.v | 7,446 | module MODULE1 (
address,
VAR45,
VAR1,
VAR48,
VAR7);
input [10:0] address;
input VAR45;
input [7:0] VAR1;
input VAR48;
output [7:0] VAR7;
tri1 VAR45;
wire [7:0] VAR31;
wire [7:0] VAR7 = VAR31[7:0];
VAR43 VAR51 (
.VAR40 (VAR48),
.VAR33 (VAR45),
.VAR3 (address),
.VAR5 (VAR1),
.VAR9 (VAR31),
.VAR11 (1'b0),
.VAR15 (1'b0),
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o.pp.blackbox.v | 1,330 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR1 ,
VAR5 ,
VAR7 ,
VAR3,
VAR2
);
output VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR3;
input VAR2;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_4.behavioral.v | 1,093 | module MODULE1( VAR2, VAR4 );
input VAR2;
output VAR4;
VAR1 VAR5(.VAR2(VAR2),.VAR4(VAR4));
VAR1 VAR3(.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
huhydro/chriskyElbertV2FPGA | dht11_driver.v | 3,394 | module MODULE1(
input VAR11,
input VAR2,
input VAR15,
inout VAR8,
output reg [7:0] VAR3,
output reg[7:0] VAR1,
output reg [3:0]VAR13
);
integer VAR14;
integer VAR5;
integer VAR7;
reg VAR9;
wire VAR4;
reg VAR10;
reg [39:0] VAR12;
assign VAR8 = VAR9 ? 1'VAR6:VAR10;
assign VAR4 = VAR8;
reg[3:0] state;
always@(posedge VAR1... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/ecc/ecc_buf.v | 6,155 | module MODULE1
parameter VAR8 = 100,
parameter VAR26 = 64,
parameter VAR44 = 4,
parameter VAR28 = 1,
parameter VAR36 = 64
)
(
VAR35,
clk, rst, VAR39, VAR34, VAR45,
VAR17, VAR18, VAR2
);
input clk;
input rst;
input [VAR44-1:0] VAR39;
input [VAR28-1:0] VAR34;
wire [4:0] VAR5;
input [VAR44-1:0] VAR45;
input [VAR28-1:0] VA... | lgpl-3.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_adv_trigger.v | 3,727 | module MODULE1 #(
parameter VAR7 = 64
)
(
input VAR4,
input VAR5,
input VAR3,
output VAR1,
input VAR9,
input VAR2,
input [VAR7-1:0] VAR6 );
reg [VAR7-1:0] counter;
reg VAR8;
reg VAR10;
always @(posedge VAR4) begin
if (VAR5 == 1'b1) begin
VAR8 <= 1'b0;
VAR10 <= 1'b1;
counter <= VAR6;
end
else if (VAR10&(!VAR8)) begin
VA... | mit |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter.v | 6,245 | module MODULE1 #(
parameter VAR12 = 66,
parameter VAR22 = 0,
parameter VAR24 = 66,
parameter VAR10 = 0,
parameter VAR5 = 0,
parameter VAR4 = 0,
parameter VAR14 = 1,
parameter VAR16 = 1,
parameter VAR8 = 0,
parameter VAR2 = 66,
parameter VAR23 = 0,
parameter VAR20 = 1,
parameter VAR21 = 0,
parameter VAR7 = 1,
parameter ... | mit |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/dqs_delay.v | 3,195 | module MODULE1( VAR1,
VAR20,
VAR5);
input VAR1;
input [4:0] VAR20;
output VAR5;
wire VAR7;
wire VAR10;
wire VAR21;
wire VAR8;
wire VAR22;
parameter VAR16 = 1'b1;
VAR13 VAR14 (.VAR11(VAR16), .VAR2(VAR20[4]), .VAR18(VAR22), .VAR6(VAR1), .VAR15(VAR5));
VAR13 VAR12 (.VAR11(VAR1), .VAR2(VAR20[2]), .VAR18(VAR16), .VAR6(VAR2... | lgpl-3.0 |
jhol/butterflylogic | rtl/receiver.v | 4,950 | module MODULE1 #(
parameter [31:0] VAR22 = 100000000,
parameter [31:0] VAR25 = 115200,
parameter VAR6 = VAR22 / VAR25 )(
input wire VAR16,
input wire VAR13,
input wire reset,
input wire VAR12,
output wire [7:0] VAR20,
output wire [31:0] VAR2,
output reg VAR9
);
localparam [2:0]
VAR15 = 3'h0,
VAR17 = 3'h1,
VAR8 = 3'h2,
... | gpl-2.0 |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/TDP18Kx18_FIFO.v | 10,690 | module MODULE1 (
VAR2,
VAR14,
VAR85,
VAR82,
VAR35,
VAR5,
VAR32,
VAR26,
VAR3,
VAR27,
VAR70,
VAR60,
VAR22,
VAR36,
VAR10,
VAR44,
VAR46,
VAR73,
VAR66,
VAR15,
VAR58,
VAR18,
VAR80,
VAR8,
VAR23,
VAR53,
VAR21,
VAR74,
VAR68,
VAR61,
VAR49,
VAR30,
VAR39,
VAR17,
VAR20,
VAR16,
VAR63
);
parameter VAR54 = 1'b0;
parameter VAR75 = 1'b0... | apache-2.0 |
combinatorylogic/soc | backends/small1/hw/rtl/3rdparty/fifo.v | 2,439 | module MODULE1(input clk,
input reset,
input [31:0] VAR8,
input VAR16,
output reg [31:0] VAR2,
input VAR12,
output reg VAR17,
output reg VAR10
);
parameter VAR11 = 0;
reg [VAR14 :0] VAR15;
reg [VAR14 -1:0] VAR13, VAR7; reg [31:0] VAR4[VAR1 -1 : 0];
always @(VAR15)
begin
VAR10 = (VAR15==0);
VAR17 = (VAR15== VAR1);
end
a... | mit |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v | 1,152 | module MODULE1
VAR1 = 32,
VAR5 = 32,
VAR8 = 32,
VAR10 = 16, VAR4 = 32,
VAR2 = 8,
VAR6 = 1,
VAR3 = 8,
VAR7 = 1,
VAR9 = 1
) (
);
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_cycle_sequence.v | 1,648 | module MODULE1 (VAR17, reset, enable, VAR12, VAR11);
parameter VAR1 = VAR23;
parameter VAR22 = 2;
parameter VAR14 = VAR7;
parameter VAR13 = VAR21;
parameter VAR9 = VAR19;
parameter VAR2 = VAR15;
parameter VAR8 = VAR6;
parameter VAR3 = VAR4;
parameter VAR18 = VAR20;
input VAR17, reset, enable;
input [VAR22-1:0] VAR12;
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha.functional.v | 1,415 | module MODULE1 (
VAR1,
VAR2 ,
VAR5 ,
VAR4
);
output VAR1;
output VAR2 ;
input VAR5 ;
input VAR4 ;
wire VAR10;
wire VAR6 ;
and VAR3 (VAR10, VAR5, VAR4 );
buf VAR7 (VAR1 , VAR10 );
xor VAR8 (VAR6 , VAR4, VAR5 );
buf VAR9 (VAR2 , VAR6 );
endmodule | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/altera_avalon_st_idle_inserter.v | 2,766 | module MODULE1 (
input clk,
input VAR8,
output reg VAR3,
input VAR10,
input [7: 0] VAR2,
input VAR5,
output reg VAR4,
output reg [7: 0] VAR9
);
reg VAR6;
wire VAR7, VAR1;
assign VAR1 = (VAR2 == 8'h4a);
assign VAR7 = (VAR2 == 8'h4d);
always @(posedge clk or negedge VAR8) begin
if (!VAR8) begin
VAR6 <= 0;
end else begin
... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fah/sky130_fd_sc_lp__fah.functional.v | 1,648 | module MODULE1 (
VAR5,
VAR16 ,
VAR17 ,
VAR2 ,
VAR13
);
output VAR5;
output VAR16 ;
input VAR17 ;
input VAR2 ;
input VAR13 ;
wire VAR15;
wire VAR4 ;
wire VAR10 ;
wire VAR3 ;
wire VAR9;
xor VAR12 (VAR15, VAR17, VAR2, VAR13 );
buf VAR7 (VAR16 , VAR15 );
and VAR14 (VAR4 , VAR17, VAR2 );
and VAR6 (VAR10 , VAR17, VAR13 );
an... | apache-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/altera_up_character_lcd_communication.v | 9,935 | module MODULE1 (
clk,
reset,
VAR7,
enable,
VAR10,
VAR27,
VAR11,
VAR22,
VAR21,
VAR20,
VAR24,
VAR14,
VAR9,
VAR12,
VAR3,
VAR28
);
parameter VAR8 = 7'h7F; parameter VAR6 = 7; parameter VAR18 = 7'h01;
parameter VAR4 = 3; parameter VAR32 = 15; parameter VAR13 = 1; parameter VAR25 = 4; parameter VAR19 = 4'h1;
input clk;
input... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_clkgen/axi_clkgen.v | 6,771 | module MODULE1 (
clk,
VAR76,
VAR1,
VAR23,
VAR42,
VAR22,
VAR41,
VAR26,
VAR6,
VAR83,
VAR43,
VAR60,
VAR21,
VAR20,
VAR82,
VAR52,
VAR7,
VAR9,
VAR16,
VAR36,
VAR62,
VAR50);
parameter VAR85 = 0;
parameter VAR69 = 0;
parameter VAR56 = 5.0;
parameter VAR84 = 11;
parameter VAR40 = 49;
parameter VAR63 = 6;
parameter VAR89 = 6;
inp... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_flow_counter.v | 2,411 | module MODULE1 #(parameter VAR19(VAR10 )
, parameter VAR2 = 0
, parameter VAR20 = 0
, parameter VAR18 =
)
( input VAR1
, input VAR16
, input VAR9
, input VAR15
, input VAR5
, output [VAR18-1:0] VAR11
);
logic VAR14;
if (VAR20) begin: VAR17
assign VAR14 = VAR9;
end else begin: VAR17
assign VAR14 = VAR9 & VAR15;
end
gene... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.behavioral.pp.v | 1,167 | module MODULE1( VAR4, VAR5, VAR2, VAR6 );
input VAR4;
inout VAR2, VAR6;
output VAR5;
VAR1 VAR3(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6));
VAR1 VAR7(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ddr_phy_dqs_found_cal.v | 51,392 | module MODULE1 #
(
parameter VAR46 = 100, parameter VAR85 = 2, parameter VAR34 = 5, parameter VAR95 = "0",
parameter VAR137 = 5, parameter VAR66 = "VAR55", parameter VAR112 = 1, parameter VAR79 = 3, parameter VAR43 = 8, parameter VAR3 = 8, parameter VAR60 = "VAR17", parameter VAR143 = "VAR144", parameter VAR53 = 3, par... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/d_SC_deviders_p_lfs_XOR.v | 15,281 | module MODULE2(VAR31, VAR5, VAR3);
input wire [VAR23-1:0] VAR31;
input wire [VAR13-1:0] VAR5;
output wire [VAR13-1:0] VAR3;
wire [VAR13*(VAR23+1)-1:0] VAR18;
genvar VAR1;
generate
for (VAR1=0; VAR1<VAR23; VAR1=VAR1+1)
begin: VAR8
VAR11 VAR25(
.VAR31(VAR31[VAR1]),
.VAR5(VAR18[VAR13*(VAR1+2)-1:VAR13*(VAR1+1)]),
.VAR3(VAR... | gpl-3.0 |
alexforencich/xfcp | lib/eth/example/ExaNIC_X10/fpga/rtl/fpga.v | 12,077 | module MODULE1 (
input wire VAR168,
input wire VAR188,
output wire [1:0] VAR126,
output wire [1:0] VAR218,
output wire [1:0] VAR226,
input wire VAR81,
input wire VAR113,
output wire VAR110,
output wire VAR145,
input wire VAR244,
input wire VAR191,
output wire VAR73,
output wire VAR46,
input wire VAR29,
input wire VAR15... | mit |
esonghori/TinyGarble | circuit_synthesis/knns/k_nns_seq.v | 2,485 | module MODULE1
(
parameter VAR19 = 15,
parameter VAR32 = 4
)
(
clk,
rst,
VAR12,
VAR3,
VAR15
);
function integer VAR1;
input [31:0] VAR33;
reg [31:0] VAR2;
begin
VAR2 = VAR33;
for (VAR1=0; VAR2>0; VAR1=VAR1+1)
VAR2 = VAR2>>1;
end
endfunction
localparam VAR9 = VAR1(VAR19);
input clk;
input rst;
input [VAR19-1:0] VAR12;
i... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/DRAM/src/ip_dram/phy/mig_7series_v2_3_poc_cc.v | 5,456 | module MODULE1 #
(parameter VAR32 = 100,
parameter VAR25 = 0,
parameter VAR2 = 95,
parameter VAR13 = 8,
parameter VAR30 = 128,
parameter VAR17 = 7)
(
VAR11, VAR12, VAR34,
VAR7, VAR18, VAR16, clk, rst, VAR24,
VAR21, VAR9, VAR10,
VAR26, VAR8, VAR37,
VAR35, VAR20, VAR28, VAR15,
VAR6, VAR4, VAR31,
VAR19, VAR1
);
localparam... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/d_SC_evaluation_matrices.v | 30,020 | module MODULE23(VAR1, VAR3);
input wire [11:0] VAR1;
output wire [VAR2-1:0] VAR3;
assign VAR3[0] = VAR1[0];
assign VAR3[1] = VAR1[1];
assign VAR3[2] = VAR1[2];
assign VAR3[3] = VAR1[3];
assign VAR3[4] = VAR1[4];
assign VAR3[5] = VAR1[5];
assign VAR3[6] = VAR1[6];
assign VAR3[7] = VAR1[7];
assign VAR3[8] = VAR1[8];
assi... | gpl-3.0 |
Obijuan/ACC | hw/roadmap/11-ACC1/ACC1.v | 10,577 | module MODULE1 (
input wire clk, input wire VAR34, input wire VAR6,
output wire VAR75, output wire VAR18,
output wire VAR40,
output wire VAR30,
output wire VAR58,
output wire VAR28,
output wire VAR37,
output wire VAR16
);
localparam VAR70 = 1'b1;
localparam VAR64 = 1'b0;
localparam VAR17 = 24; localparam VAR41 = 22; lo... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build4/sipo.v | 5,796 | module MODULE1(VAR5, VAR3, VAR4, VAR8, VAR6, clk);
output [7:0] VAR5;
output VAR3;
input VAR4;
input clk;
input VAR6;
input VAR8;
reg VAR3; reg [7:0] VAR5; reg [7:0] VAR1; reg VAR13; reg VAR2; reg VAR14; reg VAR7; reg VAR9; reg VAR11; reg VAR10; reg VAR12;
always @(~VAR6)
begin
VAR3<=1'd0;
VAR5<=8'd0;
VAR1<=8'd0;
VAR13... | mit |
intelligenttoasters/CPC2.0 | FPGA/rtl/spi_client.v | 6,876 | module MODULE1 #(
parameter VAR1 = 9
) (
input VAR45, input VAR16,
output VAR65,
input VAR8,
input VAR28,
output VAR19,
input VAR20,
input VAR57,
input VAR38,
input [3:0] VAR5, input [7:0] VAR7,
output [7:0] VAR12,
input VAR13,
input VAR43,
output VAR48,
input VAR23, output [15:0] VAR66, output [7:0] VAR53,
output VAR6... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/0_default_implementation/syn/verilog/convolve_kernel_fcud.v | 1,880 | module MODULE1
VAR11 = 2,
VAR1 = 4,
VAR2 = 32,
VAR14 = 32,
VAR21 = 32
)(
input wire clk,
input wire reset,
input wire VAR23,
input wire [VAR2-1:0] VAR24,
input wire [VAR14-1:0] VAR13,
output wire [VAR21-1:0] dout
);
wire VAR6;
wire VAR25;
wire VAR10;
wire [31:0] VAR22;
wire VAR9;
wire [31:0] VAR12;
wire VAR3;
wire [31:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufbuf/sky130_fd_sc_hs__bufbuf_8.v | 1,903 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR6,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR6;
input VAR2;
VAR3 VAR1 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR6;
supply0 VAR2;
VAR3 VAR1 (
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/util_delay.v | 2,632 | module MODULE1 #(
parameter VAR1 = 1,
parameter VAR5 = 1) (
input clk,
input reset,
input din,
output [VAR1-1:0] dout);
reg [VAR1-1:0] VAR2[0:(VAR5-1)];
always @(posedge clk) begin
if (reset) begin
VAR2[0] <= 0;
end else begin
VAR2[0] <= din;
end
end
generate
genvar VAR4;
for (VAR4 = 1; VAR4 < VAR5; VAR4=VAR4+1) begin:... | mit |
VerticalResearchGroup/miaow | src/verilog/rtl/decode/flag_generator.v | 60,929 | module MODULE1(
VAR8,
VAR26,
VAR15,
VAR11,
VAR32,
VAR31,
VAR27,
VAR10,
VAR22,
VAR25,
VAR13,
VAR33,
VAR6,
VAR12,
VAR19,
VAR3,
VAR20,
VAR16,
VAR9,
VAR30,
VAR5,
VAR24,
VAR17,
VAR28,
VAR23,
VAR29
);
input [31:0] VAR8;
input [1:0] VAR26;
output VAR15;
output VAR11;
output VAR32;
output VAR31;
output VAR27;
output VAR10;
out... | bsd-3-clause |
secworks/sha256 | src/rtl/sha256.v | 8,433 | module MODULE1(
input wire clk,
input wire VAR39,
input wire VAR38,
input wire VAR49,
input wire [7 : 0] address,
input wire [31 : 0] VAR44,
output wire [31 : 0] VAR52,
output wire VAR18
);
localparam VAR21 = 8'h00;
localparam VAR6 = 8'h01;
localparam VAR7 = 8'h02;
localparam VAR2 = 8'h08;
localparam VAR20 = 0;
localpa... | bsd-2-clause |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/data_write.v | 5,490 | module MODULE1 (
VAR16,
VAR9,
VAR13,
VAR12,
VAR25,
VAR10,
VAR15,
VAR24,
VAR1,
VAR23,
VAR11
);
input [143:0]VAR16;
input VAR9;
input VAR13;
input VAR12;
input VAR25;
output VAR10;
output VAR15;
output [71:0]VAR24;
output [71:0]VAR1;
output [8:0]VAR23;
output [8:0]VAR11;
reg VAR10;
reg VAR15;
reg VAR19;
reg VAR17;
reg VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_pr_pp_pg/sky130_fd_sc_hs__udp_dlatch_pr_pp_pg.blackbox.v | 1,384 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR4 ,
VAR2,
VAR1 ,
VAR3
);
output VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
kylemsguy/FPGA-Litecoin-Miner | experimental/CM1/hub_core.v | 1,755 | module MODULE1 (VAR6, VAR8, VAR9, VAR3, VAR7, VAR11);
parameter VAR10 = 2;
input VAR6;
input [VAR10-1:0] VAR8;
input [VAR10*32-1:0] VAR11;
output [31:0] VAR9;
output VAR3;
input VAR7;
reg VAR4;
assign VAR3 = VAR4;
reg [VAR10-1:0] VAR5 = 0;
reg [VAR2(VAR10)+1:0] VAR13 = 0;
reg [VAR10*32-1:0] VAR12;
assign VAR9 = VAR12[3... | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/eth_grx.v | 2,660 | module MODULE1
(input VAR37,
input [3:0] VAR48,
input VAR20,
input VAR31,
output [7:0] VAR40,
output VAR8,
output VAR36);
wire [7:0] VAR30;
wire VAR27;
wire VAR49;
VAR1 #(.VAR10(5)) VAR19
(.VAR18(~VAR20),
.VAR51({VAR31, VAR48}),
.VAR23({VAR49, VAR30[7:4]}),
.VAR46({VAR27, VAR30[3:0]}),
.VAR35(1'b0), .VAR6(1'b0), .VAR4(... | apache-2.0 |
mbus/mbus | mbus/verilog/no_pwr_gating_ben/mbus_master_sleep_ctrl_Ben.v | 3,069 | module MODULE1
(
output reg VAR20,
output VAR13,
output reg VAR1,
output VAR19,
output VAR17,
output VAR11,
output VAR14,
output VAR8,
input VAR16,
input VAR18,
input VAR6,
input VAR2,
input VAR10,
input VAR12,
input VAR3
);
reg VAR7;
reg VAR4;
assign VAR13 = ~VAR20;
assign VAR19 = ~VAR1;
reg VAR15;
assign VAR11 = ~VAR... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_reduced_normalize_double.v | 12,128 | module MODULE1(
VAR49, VAR43,
VAR41, VAR15, VAR24,
VAR22, VAR33, VAR32, VAR23,
enable,
VAR55, VAR34, VAR6);
parameter VAR38 = 1;
parameter VAR26 = 0;
parameter VAR19 = 1;
parameter VAR35 = 1;
parameter VAR52 = 1;
input VAR49, VAR43;
input VAR22, VAR33;
output VAR32, VAR23;
input enable;
input [56:0] VAR41;
input [11:0]... | mit |
Nrpickle/ECE272 | Lab5_TekBotSM/Source Files/Clock_Counter.v | 1,250 | module MODULE1(
input VAR3, input VAR1,
output reg VAR4
);
reg [18:0] VAR2;
always @ (posedge VAR3, negedge VAR1)
begin
VAR2 <= VAR2 + 1; if(!VAR1)
begin
VAR4 <= 0;
VAR2 <= 0; end
else
if(VAR2 >= 415999) begin VAR4 <= ~VAR4;
VAR2 <= 0; end
end
endmodule | mit |
gralco/mojo-ide | Mojo IDE/build/shared/base/mojo-v2/source/serial_tx.v | 1,932 | module MODULE1 #(
parameter VAR13 = 50,
parameter VAR17 = 6
)(
input clk,
input rst,
output VAR9,
input VAR6,
output VAR22,
input [7:0] VAR15,
input VAR26
);
localparam VAR25 = 2;
localparam VAR3 = 2'd0,
VAR19 = 2'd1,
VAR7 = 2'd2,
VAR23 = 2'd3;
reg [VAR17-1:0] VAR10, VAR8;
reg [2:0] VAR18, VAR12;
reg [7:0] VAR11, VAR14... | gpl-3.0 |
walkthetalk/fsref | ip/fsa_v2/src/include/fsa_stream_v2.v | 8,113 | module MODULE1 #(
parameter integer VAR93 = 24, parameter integer VAR12 = 1,
parameter integer VAR70 = 12,
parameter integer VAR75 = 12,
parameter integer VAR30 = 12, parameter integer VAR88 = 8,
parameter integer VAR34 = 1
)(
input clk,
input VAR73,
input wire [VAR70-1:0] VAR78 ,
input wire [VAR75-1:0] VAR3 ,
input wi... | gpl-3.0 |
babykiss4ever/MipsCPU | CPU/sccomp_top.v | 1,049 | module MODULE1(VAR3, VAR5, VAR22, VAR12, VAR23, VAR9, VAR7, VAR11, VAR4, VAR17, VAR14, VAR8 );
input VAR3, VAR5;
output [31:0] VAR22, VAR12, VAR23, VAR9;
output [6:0] VAR7;
output [3:0] VAR11;
output VAR4;
input [4:0] VAR17;
input VAR14;
input VAR8;
wire VAR19;
MODULE2 MODULE2(VAR3, VAR5, VAR19);
wire [31:0] VAR16;
wir... | apache-2.0 |
mlarouche/sd2snes | verilog/sd2snes_obc1/mcu_cmd.v | 12,815 | module MODULE1(
input clk,
input VAR17,
input VAR51,
input [7:0] VAR27,
input [7:0] VAR12,
output [2:0] VAR8,
output VAR43,
output VAR45,
output VAR18,
input VAR9,
output [7:0] VAR33,
input [7:0] VAR41,
output [7:0] VAR49,
input [31:0] VAR14,
input [2:0] VAR7,
output [23:0] VAR22,
output [23:0] VAR10,
output [23:0] VAR... | gpl-2.0 |
wyvernSemi/lm32fpga | HDL/rtl/alt_lm32.v | 22,033 | module MODULE1 (
VAR224, VAR212, VAR96, VAR26,
VAR149,
VAR167,
VAR130, VAR156, VAR35, VAR114,
VAR157, VAR78,
VAR71, VAR69,
VAR98, VAR62, VAR94, VAR106, VAR23, VAR146, VAR141, VAR87, VAR112, VAR206, VAR172, VAR170,
VAR221, VAR178, VAR47, VAR165, VAR197, VAR219,
VAR92, VAR116, VAR54, VAR128, VAR204, VAR209, VAR129,
VAR13... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr.behavioral.pp.v | 1,878 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3,
VAR13 ,
VAR9 ,
VAR11 ,
VAR8
);
output VAR6 ;
input VAR4 ;
input VAR3;
input VAR13 ;
input VAR9 ;
input VAR11 ;
input VAR8 ;
wire VAR12 ;
wire VAR7;
not VAR5 (VAR12 , VAR4 );
VAR2 VAR10 (VAR7, VAR12, VAR3, VAR9);
buf VAR1 (VAR6 , VAR7 );
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_gsu/ipcore_dir/gsu_fmult.v | 10,130 | module MODULE2 (
clk, VAR18, VAR28, VAR21
);
input clk;
output [31 : 0] VAR18;
input [15 : 0] VAR28;
input [15 : 0] VAR21;
wire \VAR70/VAR82 ;
wire \VAR70/VAR80 ;
wire \VAR70/VAR78 ;
wire \VAR70/VAR9 ;
wire \VAR70/VAR55 ;
wire \VAR70/VAR88 ;
wire \VAR70/VAR10 ;
wire \VAR70/VAR63 ;
wire \VAR70/VAR19 ;
wire \VAR70/VAR42 ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb.functional.v | 1,422 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR8 ,
VAR10,
VAR1
);
output VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR10;
input VAR1;
wire VAR2;
wire VAR4;
nand VAR3 (VAR2, VAR1, VAR10 );
or VAR9 (VAR4, VAR8, VAR5, VAR2);
buf VAR6 (VAR7 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb.behavioral.pp.v | 2,000 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR9 ,
VAR15 ,
VAR3 ,
VAR16,
VAR4,
VAR14 ,
VAR7
);
output VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR15 ;
input VAR3 ;
input VAR16;
input VAR4;
input VAR14 ;
input VAR7 ;
wire VAR6 ;
wire VAR13 ;
wire VAR10;
nand VAR11 (VAR6 , VAR3, VAR15 );
or VAR12 (VAR13 , VAR9, VAR2, VAR6 );
VAR5 VAR1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o.blackbox.v | 1,360 | module MODULE1 (
VAR1 ,
VAR8,
VAR3,
VAR5,
VAR9
);
output VAR1 ;
input VAR8;
input VAR3;
input VAR5;
input VAR9;
supply1 VAR6;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/system/wb_xs6_ddr3_bridge.v | 8,752 | module MODULE1 #(
parameter VAR35 = 32,
parameter VAR3 = 4
)(
input VAR41,
input VAR20,
input [31:0] VAR5,
input [VAR3-1:0] VAR33,
input VAR28,
output reg [VAR35-1:0] VAR21 = 'd0,
input [VAR35-1:0] VAR29,
input VAR46,
input VAR31,
output VAR10,
output VAR4,
output VAR15, output reg [2:0] VAR42 = 'd0, output reg [29:0] ... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_mem.v | 2,732 | module MODULE1 #(
parameter VAR10 = 16,
parameter VAR8 = 5) (
input VAR3,
input VAR7,
input [(VAR8-1):0] VAR11,
input [(VAR10-1):0] VAR5,
input VAR9,
input VAR4,
input [(VAR8-1):0] VAR2,
output reg [(VAR10-1):0] VAR6);
reg [(VAR10-1):0] VAR1[0:((2**VAR8)-1)];
always @(posedge VAR3) begin
if (VAR7 == 1'b1) begin
VAR1[VA... | mit |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/clocking/mig_7series_v1_9_clk_ibuf.v | 4,796 | module MODULE1 #
(
parameter VAR13 = "VAR8",
parameter VAR15 = "VAR5"
)
(
input VAR4, input VAR16,
input VAR22,
output VAR19
);
wire VAR17 ;
generate
if (VAR13 == "VAR8") begin: VAR23
VAR14 #
(
.VAR7 (VAR15),
.VAR12 ("VAR11")
)
VAR10
(
.VAR20 (VAR4),
.VAR21 (VAR16),
.VAR9 (VAR17)
);
end else if (VAR13 == "VAR2") begin:... | mit |
pwwu/FPGA | VGAbased/final/vga_game_text.v | 9,561 | module MODULE1
(
input wire clk,
input wire [1:0] VAR16,
input wire [3:0] VAR21, VAR6,
input wire [9:0] VAR19, VAR3,
output wire [3:0] VAR1,
output reg [2:0] VAR10
);
wire [10:0] VAR14;
reg [6:0] VAR27, VAR23, VAR26,
VAR15, VAR33;
reg [3:0] VAR5;
wire [3:0] VAR11, VAR20, VAR30, VAR9;
reg [2:0] VAR18;
wire [2:0] VAR24, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi_1.v | 2,352 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR11 ,
VAR9,
VAR2,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR11 ;
input VAR9;
input VAR2;
input VAR3 ;
input VAR6 ;
VAR5 VAR10 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR... | apache-2.0 |
PeterMagnusson/modexp | src/rtl/blockmem_rw32_r128.v | 5,579 | module MODULE1(
input wire clk,
input wire VAR6,
input wire [07 : 0] VAR3,
input wire [31 : 0] VAR7,
output wire [31 : 0] VAR11,
input wire [05 : 0] VAR26,
output wire [127 : 0] VAR27
);
reg [31 : 0] VAR18 [0 : 63];
reg [31 : 0] VAR4 [0 : 63];
reg [31 : 0] VAR10 [0 : 63];
reg [31 : 0] VAR1 [0 : 63];
reg [31 : 0] VAR21;... | bsd-2-clause |
bobnewgard/fcs | ver/uut_512_top.v | 11,746 | module MODULE1
(
output wire [31:0] VAR49,
output wire [31:0] VAR35,
output wire [31:0] VAR69,
output wire [15:0] VAR7,
output wire VAR22,
input wire [511:0] VAR10,
input wire [5:0] VAR8,
input wire VAR27,
input wire VAR64,
input wire VAR80
);
localparam VAR44 = 1'b0;
localparam VAR37 = 1'b1;
localparam [511:0] VAR16 =... | gpl-3.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CoreAPB3/4.0.100/rtl/vlog/core_obfuscated/coreapb3_iaddr_reg.v | 2,639 | module
MODULE1
(
VAR1
,
VAR6
,
VAR4
,
VAR5
,
VAR10
,
VAR9
,
VAR11
,
VAR3
,
VAR7
)
;
parameter
[
5
:
0
]
VAR2
=
32
;
parameter
[
5
:
0
]
VAR12
=
32
;
input
VAR1
;
input
VAR6
;
input
VAR4
;
input
VAR5
;
input
[
31
:
0
]
VAR10
;
input
VAR9
;
input
[
31
:
0
]
VAR11
;
output
[
31
:
0
]
VAR3
;
output
[
31
:
0
]
VAR7
;
reg
[
... | mit |
sorgelig/ZX_Spectrum-128K_MIST | sys/scandoubler.v | 4,040 | module MODULE1 #(parameter VAR31, parameter VAR20)
(
input VAR25,
input VAR8,
input VAR13,
input VAR19,
input VAR12,
input VAR7,
input VAR22,
input [VAR42:0] VAR24,
input [VAR42:0] VAR23,
input [VAR42:0] VAR34,
input VAR21,
output reg VAR35,
output VAR29,
output [VAR42:0] VAR41,
output [VAR42:0] VAR16,
output [VAR42:0]... | gpl-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Ultrasonico/ultrasonic_control.v | 1,513 | module MODULE1 (
input clk ,
input enable ,
input VAR4 ,
output reg VAR14 ,
output [15:0] VAR15
) ;
reg [2:0] state ;
reg VAR13 ;
reg VAR8 ;
reg VAR7 ;
wire [31:0] VAR3 ;
wire VAR1 ;
localparam VAR16 = 3'b000 ;
localparam VAR5 = 3'b001 ;
localparam VAR11 = 3'b010 ;
localparam VAR6 = 3'b011 ;
always @ ( negedge clk )
if... | mit |
hanw/sonic-lite | hw/verilog/traffic_controller/shiftreg_ctrl.v | 4,667 | module MODULE1 (
VAR12,
VAR10,
VAR7,
VAR17,
VAR9,
VAR6);
input VAR12;
input VAR10;
input VAR7;
input [5:0] VAR17;
output [5:0] VAR9;
output [5:0] VAR6;
wire [5:0] VAR3;
wire [5:0] VAR11;
wire [5:0] VAR6 = VAR3[5:0];
wire [5:0] VAR9 = VAR11[5:0];
VAR5 VAR14 (
.VAR10 (VAR10),
.VAR12 (VAR12),
.VAR7 (VAR7),
.VAR17 (VAR17),... | mit |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/Calculator_Full_Adder.v | 1,110 | module MODULE1
parameter VAR1 = 4
)
(
input [VAR1-1:0] VAR8,
input [VAR1-1:0] VAR6,
input VAR7,
output [VAR1-1:0] VAR4,
output VAR2
);
wire signed [VAR1:0] VAR5;
wire signed [VAR1:0] VAR3;
assign VAR5 = { VAR8[VAR1-1], VAR8 };
assign VAR3 = { VAR6[VAR1-1], VAR6 };
assign { VAR2, VAR4 } = VAR5 + VAR3 + VAR7;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.functional.pp.v | 2,593 | module MODULE1 (
VAR8 ,
VAR19 ,
VAR18 ,
VAR24 ,
VAR21 ,
VAR10 ,
VAR6 ,
VAR2,
VAR22 ,
VAR15
);
output VAR8 ;
output VAR19 ;
input VAR18 ;
input VAR24 ;
input VAR21 ;
input VAR10 ;
input VAR6 ;
input VAR2;
input VAR22 ;
input VAR15 ;
wire VAR16 ;
wire VAR9 ;
wire VAR7 ;
wire VAR17 ;
wire VAR14;
not VAR1 (VAR16 , VAR2 );
... | apache-2.0 |
fabugo/witnesses-of-jhon | rtl/single_port_rom.v | 2,030 | module MODULE1 #(
parameter VAR5 = 16,
parameter VAR3 = 16
)(
clk,
address, VAR1, VAR4, VAR11 ) ;
input clk;
input [VAR5-1:0] VAR6;
output [VAR3-1:0] VAR9;
input VAR7, VAR2;
reg [VAR3-1:0] VAR10 [0:(2**VAR5)-1] ;
reg [VAR3-1:0] VAR9;
reg [8*40:1] VAR8;
begin
begin | gpl-2.0 |
asicguy/gplgpu | hdl/de_temp/dex_smlblt.v | 16,319 | module MODULE1
(
input VAR7,
input VAR50,
input VAR26,
input VAR31,
input VAR77,
input VAR54,
input VAR16,
input VAR13,
input VAR91,
input VAR76,
input VAR2,
input VAR41,
input VAR143,
input VAR112,
input VAR144,
input VAR27,
input VAR81,
input VAR79,
input VAR108,
input VAR126,
input VAR116,
input VAR72,
input VAR48,
... | gpl-3.0 |
ineganov/flight_control | hard/system.v | 13,029 | module MODULE1 ( input VAR100,
output VAR13,
output VAR33,
output VAR147,
input VAR43,
input [1:0] VAR132,
input [3:0] VAR45,
output [7:0] VAR16,
input [5:0] VAR50,
inout VAR141,
inout VAR103,
input VAR58,
output VAR51,
output VAR12,
output [3:0] VAR71,
output [1:0] VAR76 );
wire VAR138, VAR85, VAR142, VAR98, VAR24, VA... | gpl-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/utils/fifo_32_to_8.v | 1,502 | module MODULE1 #(
parameter VAR5 = 1024*4
) (
input wire VAR11,
input wire VAR10,
input wire VAR3,
input wire VAR6,
input wire [31:0] VAR14,
output wire VAR12,
output wire VAR23,
output wire [7:0] VAR16
);
reg [1:0] VAR8;
wire VAR9, VAR20;
wire [31:0] VAR1;
assign VAR23 = VAR8==0 & VAR9;
assign VAR20 = (VAR8==0 & !VAR9... | bsd-3-clause |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/mem_data.v | 3,851 | module MODULE1
parameter integer VAR2 = 9,
parameter integer VAR8 = 6
)
(
input VAR1,
input reset,
input [VAR2-1:0] VAR4,
input [VAR8-1:0] VAR7,
input [VAR8-1:0] VAR3,
output reg [VAR2-1:0] VAR5
);
reg [VAR2-1:0] VAR6 [0:2**VAR8-1];
always@(posedge VAR1 or negedge reset)
begin
if (!reset)
begin
VAR6[0] <= {(VAR2){1'b0}... | gpl-3.0 |
Franderg/CE-4301-Arqui1 | Processor/Processor.v | 4,607 | module MODULE1(clk,VAR113,VAR3,VAR29,VAR35,VAR40,VAR129, VAR38, VAR47,VAR92,VAR56,VAR55,VAR124);
input clk, VAR113;
output [31:0] VAR3;
output [31:0] VAR29;
output [4:0] VAR35;
output [31:0] VAR40;
output [31:0] VAR129;
output [31:0] VAR38,VAR47;
output VAR92;
output [4:0] VAR56;
output [31:0]VAR55,VAR124;
reg [0:0] VA... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_c0.v | 19,528 | module MODULE1 (
input wire VAR2, input wire VAR174, input wire VAR47, output wire VAR125, output wire VAR46, output wire VAR153, output wire [25:0] VAR162, output wire [5:0] VAR113, output wire [1:0] VAR10, output wire [1:0] VAR34, output wire [1:0] VAR165, output wire [1:0] VAR122, output wire [1:0] VAR104, output wi... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min.v | 36,521 | module MODULE1 (
VAR236, VAR30, VAR213,
VAR200, VAR89, VAR201,
VAR122, VAR155, VAR68,
VAR44, VAR10, VAR8,
VAR130, VAR73, VAR152,
VAR32, VAR16, VAR198,
VAR33, VAR204,
VAR169, VAR78,
VAR99, VAR82, VAR212,
VAR172, VAR85,
VAR168, VAR51,
VAR15, VAR234,
VAR166, VAR224,
VAR194, VAR52, VAR1,
VAR9, VAR148,
VAR237, VAR156, VAR29... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/verilog/convolve_kernel_fcud.v | 1,881 | module MODULE1
VAR23 = 17,
VAR7 = 5,
VAR6 = 32,
VAR19 = 32,
VAR11 = 32
)(
input wire clk,
input wire reset,
input wire VAR21,
input wire [VAR6-1:0] VAR3,
input wire [VAR19-1:0] VAR25,
output wire [VAR11-1:0] dout
);
wire VAR5;
wire VAR17;
wire VAR10;
wire [31:0] VAR1;
wire VAR4;
wire [31:0] VAR14;
wire VAR13;
wire [31:... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_2.functional.pp.v | 1,681 | module MODULE1( VAR5, VAR7, VAR8, VAR3, VAR9, VAR16, VAR22, VAR19 );
input VAR3, VAR8, VAR5, VAR7, VAR16, VAR22, VAR19;
output VAR9;
wire VAR25;
not VAR6( VAR25, VAR8 );
wire VAR23;
not VAR13( VAR23, VAR5 );
wire VAR18;
and VAR10( VAR18, VAR25, VAR23 );
wire VAR20;
not VAR2( VAR20, VAR7 );
wire VAR21;
and VAR4( VAR21, ... | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/adc_frontend.v | 5,473 | module MODULE1 (
input wire clk, input wire reset,
output wire VAR29,
input wire VAR31,
input wire VAR28,
input wire [31:0] VAR14,
output reg [31:0] VAR19,
input wire [25:0] addr,
output wire VAR27,
input wire [7:0] VAR26,
input wire [7:0] VAR8,
input wire [7:0] VAR23,
input wire [7:0] VAR10,
input wire [7:0] VAR13,
in... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai.functional.pp.v | 2,212 | module MODULE1 (
VAR4 ,
VAR12 ,
VAR13 ,
VAR3 ,
VAR17 ,
VAR7 ,
VAR15,
VAR16,
VAR2 ,
VAR20
);
output VAR4 ;
input VAR12 ;
input VAR13 ;
input VAR3 ;
input VAR17 ;
input VAR7 ;
input VAR15;
input VAR16;
input VAR2 ;
input VAR20 ;
wire VAR11 ;
wire VAR9 ;
wire VAR8 ;
wire VAR6;
or VAR10 (VAR11 , VAR17, VAR3 );
or VAR14 (VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.v | 2,162 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR5,
VAR1,
VAR2,
VAR9 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR2;
input VAR9 ;
input VAR4 ;
VAR7 VAR6 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR8 ,
VAR3 ,
VAR5
);
output VAR8 ;... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/axi_basic_top.v | 11,105 | module MODULE1 #(
parameter VAR13 = 128, parameter VAR17 = "VAR11", parameter VAR29 = "VAR40", parameter VAR15 = "VAR40", parameter VAR2 = 1,
parameter VAR37 = (VAR13 == 128) ? 2 : 1, parameter VAR53 = VAR13 / 8 ) (
input [VAR13-1:0] VAR41, input VAR21, output VAR7, input [VAR53-1:0] VAR16, input VAR34, input [3:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi.pp.symbol.v | 1,376 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR7 ,
input VAR5 ,
output VAR6 ,
input VAR8 ,
input VAR3,
input VAR9,
input VAR4
);
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/mem_stage.v | 6,983 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR15, input wire VAR12, output wire VAR42,
output wire [VAR35] VAR14,
input wire [VAR35] VAR13, output wire [VAR4] VAR11, output wire VAR22, output wire VAR30, output wire [VAR35] VAR7,
input wire [VAR35] VAR21, input wire VAR34, input wire VAR32, output wi... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_wbmux.v | 5,392 | module MODULE1(
clk, rst,
VAR2, VAR12,
VAR5, VAR6, VAR15, VAR9, VAR1,
VAR8, VAR7, VAR10
);
parameter VAR14 = VAR3;
input clk;
input rst;
input VAR2;
input [VAR16-1:0] VAR12;
input [VAR14-1:0] VAR5;
input [VAR14-1:0] VAR6;
input [VAR14-1:0] VAR15;
input [VAR14-1:0] VAR9;
input [VAR14-1:0] VAR1;
output [VAR14-1:0] VAR8;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_lp_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_lp_pp_pg_n.symbol.v | 1,444 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR2 ,
input VAR3,
input VAR1 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxtp/sky130_fd_sc_ms__edfxtp.functional.pp.v | 1,947 | module MODULE1 (
VAR13 ,
VAR9 ,
VAR11 ,
VAR6 ,
VAR8,
VAR5,
VAR10 ,
VAR15
);
output VAR13 ;
input VAR9 ;
input VAR11 ;
input VAR6 ;
input VAR8;
input VAR5;
input VAR10 ;
input VAR15 ;
wire VAR1 ;
wire VAR7;
VAR14 VAR3 (VAR7, VAR1, VAR11, VAR6 );
VAR12 VAR16 VAR4 (VAR1 , VAR7, VAR9, , VAR8, VAR5);
buf VAR2 (VAR13 , VAR1 ... | apache-2.0 |
jayrandez/Processor | mem_arbiter.v | 1,067 | module MODULE1(
output wire[31:0] VAR6,
output wire[31:0] VAR11,
output wire VAR8,
output wire VAR3,
input wire[31:0] VAR7,
input wire[31:0] VAR12,
input wire VAR10,
input wire VAR14,
input wire[31:0] VAR17,
input wire[31:0] VAR2,
input wire VAR9,
input wire VAR16,
input wire[31:0] VAR15,
input wire[31:0] VAR1,
input w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2/sky130_fd_sc_hd__or2.behavioral.pp.v | 1,774 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR13 ,
VAR3,
VAR4,
VAR1 ,
VAR10
);
output VAR6 ;
input VAR5 ;
input VAR13 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR10 ;
wire VAR8 ;
wire VAR11;
or VAR9 (VAR8 , VAR13, VAR5 );
VAR7 VAR12 (VAR11, VAR8, VAR3, VAR4);
buf VAR2 (VAR6 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_2.v | 2,219 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR3 ,
VAR6,
VAR2,
VAR4 ,
VAR1
);
output VAR9 ;
input [7:0] VAR5 ;
input [7:0] VAR3 ;
input VAR6;
input VAR2;
input VAR4 ;
input VAR1 ;
VAR8 VAR7 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR9,
VAR5,
VAR3
);
o... | apache-2.0 |
rbarzic/ml-ahb-gen | chisel/Ahbmli.v | 48,620 | module MODULE1(input clk, input reset,
input [31:0] VAR15,
input VAR105,
input [2:0] VAR83,
input [2:0] VAR7,
input [3:0] VAR73,
input [1:0] VAR91,
input VAR18,
input [31:0] VAR77,
output[31:0] VAR2,
output VAR101,
output VAR23,
output[31:0] VAR87,
output VAR103,
output[2:0] VAR12,
output[2:0] VAR55,
output[3:0] VAR28,... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/address_generator.v | 4,799 | module MODULE1 (
input clk,
input VAR9,
input VAR23,
output reg VAR11,
input [31:VAR14] VAR5,
input [3:0] VAR12,
output reg [VAR8-1:0] VAR13,
input [VAR8-1:0] VAR17,
input VAR20,
input VAR4,
input enable,
input VAR24,
output reg VAR15,
input VAR1,
output reg VAR16,
output [31:0] addr,
output [ 7:0] VAR2,
output [ 2:0] ... | mit |
bmartini/verilog-arbiter | src/arbiter.v | 2,939 | module MODULE1
VAR1 = 6,
VAR2 = ((VAR1 > 1) ? VAR5(VAR1) : 1))
(input clk,
input rst,
input [VAR1-1:0] request,
output reg [VAR1-1:0] VAR7,
output reg [VAR2-1:0] select,
output reg VAR3
);
localparam VAR6 = 2*VAR1;
function [VAR2-1:0] VAR8 (
input [VAR1-1:0] in
);
reg VAR9;
integer VAR4;
begin
VAR9 = 1'b0;
VAR8 = 'b0;
... | mit |
sh-chris110/chris | FPGA/chris.system.dma.ok/Qsys/soc_design/synthesis/submodules/altera_up_rs232_out_serializer.v | 6,267 | module MODULE1 (
clk,
reset,
VAR6,
VAR7,
VAR22,
VAR29
);
parameter VAR1 = 9; parameter VAR27 = 433;
parameter VAR26 = 216;
parameter VAR23 = 11; parameter VAR5 = 9;
input clk;
input reset;
input [VAR5: 0] VAR6;
input VAR7;
output reg [ 7: 0] VAR22;
output reg VAR29;
wire VAR8;
wire VAR25;
wire VAR13;
wire VAR24;
wire V... | gpl-2.0 |
sh-chris110/chris | FPGA/atlas_linux_ghrd/soc_system/synthesis/submodules/soc_system_master_secure.v | 21,783 | module MODULE1 #(
parameter VAR38 = 0,
parameter VAR42 = 50000,
parameter VAR45 = 2
) (
input wire VAR13, input wire VAR7, output wire [31:0] VAR34, input wire [31:0] VAR37, output wire VAR46, output wire VAR11, output wire [31:0] VAR36, input wire VAR10, input wire VAR47, output wire [3:0] VAR40, output wire VAR48 );
... | gpl-2.0 |
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