repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2_1.v | 2,075 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR2 ,
VAR3,
VAR5,
VAR7 ,
VAR4
);
output VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR3;
input VAR5;
input VAR7 ;
input VAR4 ;
VAR9 VAR6 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1,
VAR8,
VAR2
);
output VAR1;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.functional.pp.v | 2,230 | module MODULE1 (
VAR10,
VAR8 ,
VAR13,
VAR14 ,
VAR23,
VAR4,
VAR1 ,
VAR16
);
output VAR10;
input VAR8 ;
input VAR13;
input VAR14 ;
input VAR23;
input VAR4;
input VAR1 ;
input VAR16 ;
wire VAR22 ;
wire VAR12 ;
wire VAR18 ;
wire VAR15 ;
wire VAR19 ;
wire VAR17 ;
wire VAR11;
wire VAR2 ;
not VAR3 (VAR12 , VAR22 );
not VAR6 (... | apache-2.0 |
dimitdim/pineapple | veriloge/inputconditioner.v | 2,798 | module MODULE1(clk, VAR9, VAR8, VAR13, VAR14);
output reg VAR8 = 0;
output reg VAR13 = 0;
output reg VAR14 = 0;
input clk, VAR9;
parameter VAR6 = 5;
parameter VAR1 = 10;
reg[VAR6-1:0] counter = 0;
reg VAR3 = 0;
reg VAR10 = 0;
always @(posedge clk) begin
if (VAR8 == VAR10) begin
counter <= 0;
VAR13 <= 0;
VAR14 <= 0;
end... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4.symbol.v | 1,288 | module MODULE1 (
input VAR7,
input VAR6,
input VAR9,
input VAR4,
output VAR5
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s.functional.pp.v | 1,868 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR9,
VAR12,
VAR8 ,
VAR7
);
output VAR4 ;
input VAR3 ;
input VAR9;
input VAR12;
input VAR8 ;
input VAR7 ;
wire VAR10 ;
wire VAR1;
buf VAR5 (VAR10 , VAR3 );
VAR6 VAR11 (VAR1, VAR10, VAR9, VAR12);
buf VAR2 (VAR4 , VAR1 );
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/wb_ram/rtl/verilog/wb_ram_xilinx.v | 2,089 | module MODULE1 (
dout,
clk, rst, VAR1, din, VAR3, VAR2
) ;
input clk;
input rst;
input [3:0] VAR1;
input [31:0] din;
input [14:0] VAR3;
input [14:0] VAR2;
output wire [31:0] dout; | mit |
linuxbest/lzs | common/synchronizer_flop.v | 5,230 | module MODULE1 (
VAR6, VAR1, VAR3, VAR2
);
parameter VAR4 = 1 ;
parameter VAR5 = 0 ;
input [VAR4-1:0] VAR6;
input VAR1;
output [VAR4-1:0] VAR3;
input VAR2;
reg [VAR4-1:0] VAR3;
always @(posedge VAR1 or posedge VAR2)
begin
if (VAR2 == 1'b1)
begin
VAR3 <= VAR5;
end
else
begin
VAR3 <= VAR6;
end
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.v | 2,034 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR7,
VAR4,
VAR5 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR7;
input VAR4;
input VAR5 ;
input VAR1 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR7;
supply0 VAR4;... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/descriptor_buffers.v | 18,736 | module MODULE1 (
clk,
reset,
VAR17,
write,
VAR57,
VAR73,
VAR5,
VAR60,
VAR55,
VAR9,
VAR28,
VAR79,
VAR81,
VAR62,
VAR80,
VAR93,
VAR21,
VAR50,
VAR22,
VAR84,
VAR91,
VAR52,
VAR31,
VAR11,
VAR69
);
parameter VAR26 = 0;
parameter VAR88 = 256;
parameter VAR76 = 32;
parameter VAR70 = 128;
parameter VAR96 = 7;
input clk;
input res... | gpl-3.0 |
HeTpro/Verilog | S4/S4L2.v | 1,988 | module MODULE1(VAR14, VAR3, VAR2, VAR6,VAR5);
input VAR14; output reg VAR3;
output reg [6:0] VAR2 = 7'h3F; output reg VAR6 = 0; output reg [3:0] VAR5 = 0; reg [25:0] VAR15 = 0; parameter [6:0] VAR12 = ~7'h3F;
parameter [6:0] VAR11 = ~7'h06;
parameter [6:0] VAR16 = ~7'h5B;
parameter [6:0] VAR9 = ~7'h4F;
parameter [6:0] ... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp_2.v | 2,437 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR5 ,
VAR11 ,
VAR10 ,
VAR3 ,
VAR8 ,
VAR6,
VAR2
);
output VAR7 ;
output VAR9 ;
input VAR5 ;
input VAR11 ;
input VAR10 ;
input VAR3 ;
input VAR8 ;
input VAR6;
input VAR2;
VAR4 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),... | apache-2.0 |
tommythorn/yari | shared/rtl/target/niosdevkit-1c20/pll.v | 16,155 | module MODULE1 (
VAR37,
VAR17,
VAR65,
VAR80);
input VAR37;
output VAR17;
output VAR65;
output VAR80;
wire [5:0] VAR25;
wire VAR30;
wire [3:0] VAR48;
wire [0:0] VAR60 = 1'h0;
wire [0:0] VAR79 = VAR25[0:0];
wire VAR17 = VAR79;
wire VAR80 = VAR30;
wire [0:0] VAR22 = VAR48[0:0];
wire VAR65 = VAR22;
wire VAR11 = VAR37;
wire... | gpl-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_audio_config.v | 16,103 | module MODULE1 (
clk,
reset,
address,
VAR28,
read,
write,
VAR56,
VAR60,
VAR16,
VAR37,
irq,
VAR62,
VAR72
);
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] VAR28;
input read;
input write;
input [31: 0] VAR56;
inout VAR60;
output reg [31: 0] VAR16;
output VAR37;
output irq;
output VAR62;
output VAR72;
localp... | mit |
darrylring/verilog | phase_ramp.v | 1,312 | module MODULE1 #
(
parameter integer VAR4 = 16,
parameter integer VAR13 = 13
)
(
input wire VAR9,
input wire VAR14,
input wire VAR12,
input wire [VAR13-1:0] VAR3,
output wire [VAR4-1:0] VAR1,
input wire VAR6,
output wire VAR5
);
reg [VAR13:0] VAR7;
reg [VAR13:0] VAR10;
reg VAR11, VAR2, VAR8;
reg reset;
always @(posedge... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/small_async_fifo.v | 6,565 | module MODULE3
parameter VAR19 = 8,
parameter VAR25 = 3,
parameter VAR27 = 5,
parameter VAR40 = 3
)
(
output VAR6,
output VAR36,
input [VAR19-1:0] VAR26,
input VAR37, VAR29, VAR5,
output [VAR19-1:0] VAR20,
output VAR32,
output VAR1,
input VAR14, VAR18, VAR44
);
wire [VAR25-1:0] VAR12, VAR42;
wire [VAR25:0] VAR35, VAR30... | mit |
mbuesch/toprammer | libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.v | 8,960 | module MODULE1(VAR16, VAR10, write, read, VAR22, VAR2);
inout [7:0] VAR16;
input VAR10;
input write;
input read;
input VAR22;
inout [48:1] VAR2;
wire VAR11;
reg [7:0] address;
reg [7:0] VAR26;
wire VAR13, VAR37;
assign VAR13 = 0;
assign VAR37 = 1;
reg [1:0] VAR3;
reg [3:0] VAR39;
reg [3:0] VAR15;
reg [16:0] VAR28;
para... | gpl-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/ExShad32.v | 4,449 | module MODULE1(
VAR25, reset,
VAR7, VAR41,
VAR23, VAR46
);
input VAR25;
input reset;
input[31:0] VAR7;
input[ 7:0] VAR41;
input[ 2:0] VAR46;
output[31:0] VAR23;
reg[31:0] VAR49;
assign VAR23 = VAR49;
reg[31:0] VAR8;
reg[31:0] VAR12;
reg[ 7:0] VAR22;
always @*
begin
VAR8=0;
VAR12=0;
VAR49 = 0;
VAR22 = 0;
case(VAR46)
3'h... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.behavioral.v | 1,093 | module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR4 VAR2(.VAR1(VAR1),.VAR3(VAR3));
VAR4 VAR5(.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v | 20,617 | module MODULE1(
VAR49,
VAR41,
VAR29,
VAR21,
VAR58,
VAR35,
VAR7,
VAR69,
VAR57,
VAR45,
VAR61,
VAR48,
VAR68,
VAR14,
VAR23,
VAR36,
VAR26,
VAR67, VAR25, VAR20 );
input VAR49; input VAR41; input VAR29; input VAR21; output VAR58; output VAR35;
output VAR7;
output VAR69;
output VAR57;
output VAR45;
output VAR61;
output VAR48;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o.symbol.v | 1,388 | module MODULE1 (
input VAR5,
input VAR7,
input VAR4,
input VAR3,
input VAR8,
output VAR2
);
supply1 VAR1;
supply0 VAR6;
endmodule | apache-2.0 |
jcowgill/BfProcessor | data_ram.v | 2,262 | module MODULE1(VAR5, clk, address, VAR4, write);
parameter VAR8 = 8;
parameter VAR1 = 15;
parameter VAR6 = 1;
output [VAR8 - 1:0] VAR5;
input clk;
input [VAR1 - 1:0] address; input [VAR8 - 1:0] VAR4; input write;
reg [VAR8 - 1:0] VAR3[0:(1 << VAR1) - 1];
reg [VAR8 - 1:0] VAR7;
assign VAR5 = VAR7;
integer VAR2;
begin
be... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.pp.blackbox.v | 1,287 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR7,
VAR5,
VAR6,
VAR2 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR7;
input VAR5;
input VAR6;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv.functional.pp.v | 1,748 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR3,
VAR1,
VAR12 ,
VAR10
);
output VAR7 ;
input VAR5 ;
input VAR3;
input VAR1;
input VAR12 ;
input VAR10 ;
wire VAR2 ;
wire VAR4;
not VAR8 (VAR2 , VAR5 );
VAR6 VAR11 (VAR4, VAR2, VAR3, VAR1);
buf VAR9 (VAR7 , VAR4 );
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_satd_gen.v | 27,839 | module MODULE1 (
clk ,
VAR17 ,
VAR77 ,
VAR113 ,
VAR49 ,
VAR99 ,
VAR40 ,
VAR38 ,
VAR104 ,
VAR9 ,
VAR73 ,
VAR118 ,
VAR82 ,
VAR80 ,
VAR5 ,
VAR95 ,
VAR31 ,
VAR69 ,
VAR24 ,
VAR83 ,
VAR106 ,
VAR128 ,
VAR15 ,
VAR10 ,
VAR61 ,
VAR67 ,
VAR33 ,
VAR102 ,
VAR98 ,
VAR103 ,
VAR116 ,
VAR48 ,
VAR109 ,
VAR108 ,
VAR126 ,
VAR71 ,
VAR7 ,
V... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/romsel.v | 1,079 | module MODULE1(
input [3:0] VAR7,
output [7:0] do,
input [7:0] VAR12,
input [7:0] VAR5,
input [7:0] VAR14,
input [7:0] VAR2,
input [7:0] VAR9,
input [7:0] VAR1,
input [7:0] VAR3,
input [7:0] VAR13,
input [7:0] VAR8,
input [7:0] VAR16,
input [7:0] VAR11,
input [7:0] VAR6,
input [7:0] VAR17,
input [7:0] VAR10,
input [7:0... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.behavioral.v | 3,306 | module MODULE1( VAR4, VAR9, VAR3, VAR5, VAR8, VAR6 );
input VAR8, VAR6, VAR5, VAR3, VAR9;
output VAR4;
VAR2 VAR7(.VAR4(VAR4),.VAR9(VAR9),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR6(VAR6));
VAR2 VAR1(.VAR4(VAR4),.VAR9(VAR9),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR6(VAR6)); | apache-2.0 |
Jside/pdp1 | pdp1_sbs16.v | 1,856 | module MODULE1(VAR13, VAR9,
VAR10, VAR12, VAR3, VAR4, VAR2,
VAR6, VAR5);
input VAR13;
input VAR9;
output VAR10;
output VAR12;
output VAR3;
output VAR4;
input VAR2;
input VAR6;
input [0:11] VAR5;
wire [0:5] VAR7;
wire [0:5] VAR1;
assign VAR7 = VAR5[0:5];
assign VAR1 = VAR5[6:11];
reg [0:15] VAR11;
reg [0:15] VAR8;
alway... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_sprites_shifter.v | 3,610 | module MODULE1
(
input clk, input VAR6,
input reset, input VAR20, input [1:0] address, input [8:0] VAR8, input [15:0] VAR14,
input VAR19,
input [48-1:0] VAR13,
input [15:0] VAR9, output [1:0] VAR15, output reg VAR12 );
parameter VAR10 = 2'b00;
parameter VAR3 = 2'b01;
parameter VAR7 = 2'b10;
parameter VAR16 = 2'b11;
reg... | gpl-3.0 |
myriadrf/A2300 | hdl/wca/WcaPortWrite.v | 3,053 | module MODULE1(
input wire reset,
input wire VAR8,
input wire VAR1, input wire VAR5, input wire [31:0] VAR14,
output wire VAR10, output wire VAR23,
output wire VAR4, output wire VAR15,
inout [31:0] VAR17, input wire [(VAR11+2):0] VAR9, output wire [1:0] VAR7
);
parameter VAR2 = 0;
parameter VAR11 = 2;
parameter VAR19 =... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc_8.v | 2,319 | module MODULE2 (
VAR6 ,
VAR5,
VAR7 ,
VAR9 ,
VAR4 ,
VAR8 ,
VAR3
);
output VAR6 ;
input VAR5;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR8 ;
input VAR3 ;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6 ,
VAR5,
VAR7
);
output VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.behavioral.pp.v | 6,220 | module MODULE1( VAR6, VAR25, VAR57, VAR53, VAR48, VAR1, VAR9 );
input VAR57, VAR6, VAR25, VAR53;
inout VAR1, VAR9;
output VAR48;
reg VAR64;
VAR26 VAR60(.VAR6(VAR6),.VAR25(VAR25),.VAR57(VAR57),.VAR53(VAR53),.VAR48(VAR48),.VAR1(VAR1),.VAR9(VAR9),.VAR64(VAR64));
VAR26 VAR12(.VAR6(VAR6),.VAR25(VAR25),.VAR57(VAR57),.VAR53(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbn/sky130_fd_sc_lp__dlrbn.behavioral.pp.v | 2,608 | module MODULE1 (
VAR1 ,
VAR15 ,
VAR2,
VAR3 ,
VAR10 ,
VAR13 ,
VAR24 ,
VAR7 ,
VAR6
);
output VAR1 ;
output VAR15 ;
input VAR2;
input VAR3 ;
input VAR10 ;
input VAR13 ;
input VAR24 ;
input VAR7 ;
input VAR6 ;
wire VAR17 ;
wire VAR26 ;
reg VAR23 ;
wire VAR16 ;
wire VAR22 ;
wire VAR19 ;
wire VAR11;
wire VAR12 ;
wire VAR18 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai.functional.v | 1,929 | module MODULE1 (
VAR1,
VAR11,
VAR4 ,
VAR7 ,
VAR14 ,
VAR3
);
input VAR1;
input VAR11;
output VAR4 ;
input VAR7 ;
input VAR14 ;
input VAR3 ;
wire VAR2 ;
wire VAR13 ;
wire VAR8;
or VAR10 (VAR2 , VAR14, VAR7 );
nand VAR12 (VAR13 , VAR3, VAR2 );
VAR9 VAR6 (VAR8, VAR13, VAR1, VAR11);
buf VAR5 (VAR4 , VAR8 );
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_jtag.v | 16,400 | module MODULE1 (
VAR60,
VAR9,
VAR31,
VAR50,
VAR55,
VAR14,
VAR48,
VAR22,
VAR58,
VAR39,
VAR68,
VAR5,
VAR24,
VAR1,
VAR17,
VAR13,
VAR36,
VAR56,
VAR16,
VAR35,
VAR59,
VAR7,
VAR15,
VAR46,
VAR52,
VAR18
);
parameter VAR54 = VAR65;
input VAR60; input VAR9;
input VAR31; input VAR50; input [VAR11] VAR55; input [2:0] VAR14;
input [... | lgpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaE_dma/interrupts/interrupts.v | 1,303 | module MODULE1(
VAR12,
VAR9,
VAR8,
VAR10,
VAR2
);
parameter VAR13 = 100;
input VAR12;
input VAR9;
input VAR8;
input VAR10;
output reg VAR2;
reg [9:0] VAR3;
reg VAR11;
reg VAR1,VAR5,VAR14;
reg VAR6,VAR7;
reg VAR4;
always @(posedge VAR12)
begin
if( VAR3 == 10'd639 )
VAR3 <= 10'd0;
end
else
VAR3 <= VAR3 + 10'd1;
if( VAR3 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b.functional.v | 1,412 | module MODULE1 (
VAR9 ,
VAR3,
VAR7 ,
VAR10 ,
VAR4
);
output VAR9 ;
input VAR3;
input VAR7 ;
input VAR10 ;
input VAR4 ;
wire VAR5 ;
wire VAR1;
not VAR6 (VAR5 , VAR3 );
and VAR2 (VAR1, VAR5, VAR7, VAR10, VAR4);
buf VAR8 (VAR9 , VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_1.functional.v | 1,046 | module MODULE1( VAR7, VAR8, VAR1 );
input VAR8, VAR7;
output VAR1;
wire VAR4;
not VAR2( VAR4, VAR8 );
wire VAR3;
not VAR6( VAR3, VAR7 );
or VAR5( VAR1, VAR4, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf.behavioral.v | 1,345 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR2;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR6 ;
wire VAR1;
buf VAR8 (VAR1, VAR4 );
buf VAR9 (VAR5 , VAR1 );
endmodule | apache-2.0 |
argonnexraydetector/RoachFirmPy | ANLYellowBlocks/mkid_dacadc_4x/ise/mkiddac/ipcore_dir/mmcm_mkid.v | 7,527 | module MODULE1
( input VAR63,
input VAR23,
output VAR82,
output VAR15,
output VAR79,
output VAR72,
output VAR61,
output VAR7
);
VAR26 VAR70
(.VAR58 (VAR16),
.VAR45 (VAR63));
wire [15:0] VAR35;
wire VAR60;
wire VAR52;
wire VAR3;
wire VAR53;
wire VAR55;
wire VAR69;
wire VAR41;
wire VAR86;
wire VAR54;
wire VAR17;
wire VAR... | gpl-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_wbmux.v | 5,879 | module MODULE1(
clk, rst,
VAR8, VAR4,
VAR13, VAR1, VAR2, VAR11,
VAR7, VAR9, VAR12
);
parameter VAR10 = VAR5;
input clk;
input rst;
input VAR8;
input [VAR3-1:0] VAR4;
input [VAR10-1:0] VAR13;
input [VAR10-1:0] VAR1;
input [VAR10-1:0] VAR2;
input [VAR10-1:0] VAR11;
output [VAR10-1:0] VAR7;
output [VAR10-1:0] VAR9;
output... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_SRAM_FF_210930.v | 242,336 | module MODULE1 (VAR11, VAR2, VAR9, VAR7, VAR13, VAR10);
output VAR11;
input VAR2, VAR9, VAR7, VAR13, VAR10;
wire VAR8, VAR1, VAR5;
wire VAR12, VAR3, VAR6;
wire VAR4;
not (VAR3, VAR10);
not (VAR12, VAR13);
not (VAR5, VAR7);
and (VAR6, VAR5, VAR12);
not (VAR1, VAR9);
not (VAR8, VAR2);
and (VAR4, VAR8, VAR1, VAR12);
or (V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/conb/sky130_fd_sc_lp__conb_1.v | 2,042 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR8,
VAR1,
VAR3 ,
VAR6
);
output VAR7 ;
output VAR4 ;
input VAR8;
input VAR1;
input VAR3 ;
input VAR6 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7,
VAR4
);
output VAR7;
output VAR4;
supply1 VAR8;
supply0 VAR... | apache-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii/synthesis/submodules/niosii_nios2_gen2_0.v | 5,770 | module MODULE1 (
input wire clk, input wire VAR13, input wire VAR17, output wire [22:0] VAR3, output wire [3:0] VAR4, output wire VAR16, input wire [31:0] VAR10, input wire VAR20, output wire VAR14, output wire [31:0] VAR2, output wire VAR6, output wire [22:0] VAR9, output wire VAR25, input wire [31:0] VAR1, input wire... | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v | 3,360 | module MODULE1(
VAR58,
VAR34,
VAR65,
VAR40,
VAR17,
VAR48,
VAR5,
VAR66,
VAR11,
VAR26,
VAR61,
VAR49,
VAR8,
VAR13,
VAR39,
VAR53,
VAR19,
VAR32,
VAR51,
VAR18,
VAR9,
VAR56,
VAR6,
VAR1,
VAR20,
VAR15,
VAR63,
VAR64,
VAR42,
VAR59,
VAR27,
VAR21,
VAR7,
VAR67,
VAR30,
VAR50,
VAR55,
VAR43
);
input VAR58;
input VAR34;
input [VAR2-1:0]... | mit |
velizarefremov/MIPS | Part 2/Verilog Code/muxparam.v | 1,559 | module MODULE1
parameter VAR9 = 16)
( output [(VAR9-1):0] VAR11,
input [(VAR9*VAR2-1):0] VAR7,
input [(VAR10(VAR2)-1):0] sel
);
localparam VAR12 = VAR10(VAR2);
integer VAR3, VAR5, VAR1;
wire [(VAR9-1):0] VAR4 [(VAR2-1):0];
reg [(VAR9-1):0] VAR6 [VAR12:0][(2**VAR12-1):0];
genvar VAR13;
generate
for (VAR13=0; VAR13 < VAR... | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_spram_128x32.v | 7,515 | module MODULE1(
VAR5, VAR8, VAR2,
clk, rst, VAR22, VAR15, VAR25, addr, VAR26, VAR6
);
parameter VAR20 = 7;
parameter VAR12 = 32;
input VAR5;
input [VAR17 - 1:0] VAR2;
output VAR8;
input clk; input rst; input VAR22; input VAR15; input VAR25; input [VAR20-1:0] addr; input [VAR12-1:0] VAR26; output [VAR12-1:0] VAR6;
VAR9 ... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/src/stubs/hdl/PLLE2_BASE.v | 1,589 | module MODULE1 (
VAR19, VAR4, VAR15, VAR14, VAR12, VAR9, VAR3,
VAR21,
VAR20, VAR17, VAR16, VAR37
);
parameter VAR27 = 0;
parameter VAR26 = 0;
parameter VAR22 = 0;
parameter VAR25 = 0;
parameter VAR11 = 0;
parameter VAR7 = 0;
parameter VAR1 = 0;
parameter VAR8 = 0;
parameter VAR5 = 0;
parameter VAR31 = 0;
parameter VAR3... | gpl-3.0 |
olajep/oh | src/elink/hdl/erx_clocks.v | 7,275 | module MODULE1 (
VAR24, VAR36, VAR106, VAR50, VAR45,
VAR40, VAR34, VAR44, VAR29, VAR69
);
parameter VAR14 = 300;
parameter VAR19 = 200;
parameter VAR85 = 0; parameter VAR57 = 4; parameter VAR83 = VAR13; parameter VAR39 = VAR35;
parameter VAR8 = 4; else
parameter VAR8 = 8; VAR20
localparam real VAR6 = 1000.000000 / VAR1... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_qpll_reset.v | 13,712 | module MODULE1 #
(
parameter VAR27 = "VAR17", parameter VAR12 = "VAR15", parameter VAR40 = 1, parameter VAR7 = 1
)
(
input VAR6,
input VAR50,
input VAR43,
input [VAR40-1:0] VAR41,
input [(VAR40-1)>>2:0]VAR39,
input [(VAR40-1)>>2:0]VAR36,
input [ 1:0] VAR2,
input [VAR40-1:0] VAR14,
input [VAR40-1:0] VAR29,
output VAR37,... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtn/sky130_fd_sc_hd__dfrtn.behavioral.pp.v | 2,391 | module MODULE1 (
VAR2 ,
VAR14 ,
VAR12 ,
VAR17,
VAR23 ,
VAR21 ,
VAR10 ,
VAR16
);
output VAR2 ;
input VAR14 ;
input VAR12 ;
input VAR17;
input VAR23 ;
input VAR21 ;
input VAR10 ;
input VAR16 ;
wire VAR11 ;
wire VAR9 ;
wire VAR19 ;
reg VAR15 ;
wire VAR1 ;
wire VAR20;
wire VAR6 ;
wire VAR4 ;
wire VAR8 ;
wire VAR7 ;
not VAR... | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/clk_bluetooth/clk_bluetooth_stub.v | 1,286 | module MODULE1(VAR1, VAR2, VAR3, VAR5, VAR4)
;
output VAR1;
output VAR2;
input VAR3;
output VAR5;
input VAR4;
endmodule | gpl-3.0 |
hydai/Verilog-Practice | DigitalDesign/Final/final/final_101062124/risc_t.v | 3,734 | module MODULE1;
parameter VAR27 = 32;
parameter VAR16 = 32;
parameter VAR35 = 2048;
parameter VAR18 = 7;
parameter VAR54 = 5;
parameter VAR63 = 15;
parameter period = 20;
parameter delay = 1;
parameter VAR55 = "03division-VAR13.VAR15";
parameter VAR8 = "03division-VAR33.VAR15";
parameter VAR67 = "VAR59.VAR47";
paramete... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.behavioral.v | 1,620 | module MODULE1( VAR3, VAR7, VAR2, VAR6 );
input VAR6, VAR7, VAR2;
output VAR3;
VAR4 VAR5(.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6));
VAR4 VAR1(.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
asicguy/gplgpu | hdl/ramdac_sp/pix_pll.v | 14,492 | module MODULE1
(
input VAR46,
input VAR79,
input [2:0] VAR53,
input [1:0] VAR94,
input VAR41,
input [7:0] VAR13, VAR25,
input [7:0] VAR30, VAR69,
input [7:0] VAR85, VAR15,
input [7:0] VAR67, VAR20,
input VAR87,
output reg [6:0] VAR97,
output reg [5:0] VAR98,
output reg [2:0] VAR31,
output reg VAR39,
output reg VAR52,
o... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_on_screen_display/rtl/character_buffer.v | 21,113 | module MODULE1 #(
parameter VAR60 = 12,
parameter VAR53 = 5,
parameter VAR62 = 8,
parameter VAR84 = 80,
parameter VAR75 = 34,
parameter VAR45 = VAR84 * VAR75
)(
input clk,
input rst,
input VAR20,
input VAR42,
input [2:0] VAR68,
input VAR54,
input [7:0] VAR56,
output VAR83,
input VAR31,
input VAR73,
output reg VAR79,
ou... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/d5e322d2745b1271/zynq_design_1_axi_bram_ctrl_0_0_stub.v | 4,089 | module MODULE1(VAR27, VAR35, VAR10,
VAR17, VAR33, VAR39, VAR29, VAR49, VAR25,
VAR30, VAR50, VAR34, VAR7, VAR48, VAR2,
VAR41, VAR51, VAR23, VAR18, VAR36, VAR37, VAR46,
VAR28, VAR22, VAR9, VAR26, VAR45, VAR42,
VAR47, VAR4, VAR13, VAR8, VAR15, VAR43, VAR3,
VAR5, VAR14, VAR24, VAR12, VAR6, VAR32, VAR11,
VAR38, VAR40, VAR16... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.functional.v | 1,778 | module MODULE1( VAR16, VAR1, VAR19, VAR8, VAR7 );
input VAR8, VAR7, VAR1, VAR16;
output VAR19;
wire VAR15;
not VAR22( VAR15, VAR8 );
wire VAR3;
not VAR18( VAR3, VAR1 );
wire VAR12;
and VAR2( VAR12, VAR15, VAR3 );
wire VAR6;
not VAR20( VAR6, VAR16 );
wire VAR11;
and VAR14( VAR11, VAR15, VAR6 );
wire VAR4;
not VAR13( VAR... | apache-2.0 |
secworks/sha512 | src/rtl/sha512_w_mem.v | 8,594 | module MODULE1(
input wire clk,
input wire VAR30,
input wire [1023 : 0] VAR8,
input wire VAR19,
input wire VAR38,
output wire [63 : 0] VAR36
);
reg [63 : 0] VAR17 [0 : 15];
reg [63 : 0] VAR29;
reg [63 : 0] VAR26;
reg [63 : 0] VAR11;
reg [63 : 0] VAR22;
reg [63 : 0] VAR9;
reg [63 : 0] VAR5;
reg [63 : 0] VAR14;
reg [63 :... | bsd-2-clause |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v | 17,128 | module MODULE1 (VAR47, VAR24, VAR5, VAR42, VAR49, VAR39, VAR12,
VAR73, VAR78, VAR15, VAR37, VAR86, VAR31, VAR88, VAR14, VAR38,
VAR30, VAR25, VAR2, VAR43, VAR50, VAR64,
VAR53, VAR81, VAR66, VAR29, VAR80, VAR67, VAR3, VAR16,
VAR85, VAR41, VAR4, VAR1, VAR75,
VAR21, VAR74, VAR59, VAR40
);
input VAR47; input VAR24; input VA... | gpl-2.0 |
Tao-J/nexys3MIPSSoC | ctrl.v | 8,729 | module MODULE1(clk,
reset,
VAR48,
VAR23,
VAR5,
VAR26,
VAR51,
VAR10,
VAR6,
VAR32,
VAR47,
VAR17,
VAR2,
VAR1,
VAR27,
VAR21,
VAR11,
VAR20,
VAR7,
VAR18,
VAR14,
VAR38,
VAR53,
VAR56,
VAR24,
VAR34,
VAR25,
VAR45,
VAR8
);
input clk,reset;
input VAR23,VAR5,VAR26,VAR25,VAR8;
input [31:0] VAR48;
output [2:0] VAR6,VAR21,VAR7;
output... | gpl-3.0 |
AnttiLukats/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_sha256/rtl/verilog/sha256_W.v | 3,360 | module MODULE1 (
input clk,
input VAR17,
input VAR9,
input [511:0] VAR21,
output [31:0] VAR12
);
reg [31:0] VAR29[15:0];
reg [31:0] VAR6, VAR28, VAR24, VAR18, VAR4, VAR20, VAR26, VAR27;
reg [31:0] VAR7, VAR10, VAR15, VAR22, VAR19, VAR5, VAR25, VAR13;
reg [31:0] VAR2;
reg [31:0] h0, h1, VAR14, VAR30;
always @(posedge cl... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.functional.v | 1,734 | module MODULE1( VAR21, VAR9, VAR24, VAR11, VAR20, VAR23, VAR5 );
input VAR11, VAR24, VAR21, VAR20, VAR9, VAR5;
output VAR23;
not VAR13( VAR19, VAR20 );
wire VAR12;
not VAR1( VAR12, VAR24 );
wire VAR7;
not VAR17( VAR7, VAR21 );
wire VAR3;
and VAR10( VAR3, VAR12, VAR7 );
wire VAR14;
not VAR25( VAR14, VAR9 );
wire VAR4;
a... | apache-2.0 |
laoreja/MineSweeperM | code/vga_640_480_stripes.v | 2,036 | module MODULE1(
input wire clk,
input wire VAR1,
output reg VAR4,
output reg VAR12,
output reg [9:0] hc,
output reg [9:0] VAR5,
output reg VAR11
);
parameter VAR10 = 10'b1100100000, VAR7 = 10'b1000001001, VAR2 = 10'b0010010000, VAR6 = 10'b1100010000, VAR9 = 10'b0000011111, VAR3 = 10'b0111111111;
reg VAR8;
always @(pose... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b.pp.symbol.v | 1,318 | module MODULE1 (
input VAR9 ,
input VAR2 ,
input VAR6 ,
input VAR8 ,
output VAR1 ,
input VAR3 ,
input VAR5,
input VAR4,
input VAR7
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/vhd/mkBiasWorker4B.v | 3,766 | module MODULE1(
input VAR57,
input VAR24,
input [2 : 0] VAR7,
input VAR27,
input [3 : 0] VAR23,
input [31 : 0] VAR1,
input [31 : 0] VAR9,
output [1 : 0] VAR62,
output [31 : 0] VAR49,
output VAR65,
output [1 : 0] VAR22,
input [1 : 0] VAR42,
input [2 : 0] VAR15,
input VAR45,
input VAR46,
input [11 : 0] VAR41,
input [31 :... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.functional.pp.v | 2,257 | module MODULE1 (
VAR18 ,
VAR14 ,
VAR5 ,
VAR2 ,
VAR10 ,
VAR13 ,
VAR19 ,
VAR16,
VAR20,
VAR17 ,
VAR21
);
output VAR18 ;
output VAR14 ;
input VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR13 ;
input VAR19 ;
input VAR16;
input VAR20;
input VAR17 ;
input VAR21 ;
wire VAR8 ;
wire VAR11;
wire VAR4 ;
VAR22 VAR12 (VAR11, VAR4, VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b_2.v | 2,163 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR3 ,
VAR4,
VAR1,
VAR2 ,
VAR8
);
output VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR2 ;
input VAR8 ;
VAR5 VAR6 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR9 ,
VAR7,
VAR3
);
output VAR9 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.v | 2,065 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR3,
VAR4,
VAR1 ,
VAR7
);
output VAR6 ;
input VAR2 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR7 ;
VAR8 VAR5 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR6,
VAR2
);
output VAR6;
input VAR2;
supply1 VAR3;
supply0 VAR4;... | apache-2.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/pippo_operandmuxes.v | 2,196 | module MODULE1(
VAR11, VAR4, VAR1, VAR12,
VAR3, VAR5,
VAR10, VAR6
);
parameter VAR9 = VAR7;
input [VAR9-1:0] VAR11;
input [VAR9-1:0] VAR4;
input [VAR9-1:0] VAR1;
input [VAR9-1:0] VAR12;
input [VAR2-1:0] VAR3;
input [VAR2-1:0] VAR5;
output [VAR9-1:0] VAR10;
output [VAR9-1:0] VAR6;
reg [VAR9-1:0] VAR10;
reg [VAR9-1:0] VA... | gpl-2.0 |
skyfex/svo-raycaster | raycaster2/raycaster_cache_mem.v | 6,365 | module MODULE1(
VAR4,
VAR10,
VAR6,
VAR5,
VAR11,
VAR3,
VAR1,
VAR2,
VAR8,
VAR7
);
input VAR4;
input [0 : 0] VAR10;
input [8 : 0] VAR6;
input [31 : 0] VAR5;
output reg [31 : 0] VAR11;
input VAR3;
input [0 : 0] VAR1;
input [8 : 0] VAR2;
input [31 : 0] VAR8;
output reg [31 : 0] VAR7;
reg [31:0] VAR9[0:511];
always @(posedge... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/minsoc_top.v | 21,120 | module MODULE1 (
clk,reset
, VAR259,VAR433,VAR451,
VAR161,VAR85,VAR235
, VAR316, VAR432, VAR59, VAR453
, VAR288,VAR184
, VAR271, VAR179, VAR180, VAR100,
VAR201, VAR382, VAR132, VAR358,
VAR363, VAR472, VAR75, VAR79,
VAR205, VAR135
);
input clk;
input reset;
output VAR316;
input VAR432;
output VAR59;
output [1:0] VAR453;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn_1.v | 2,601 | module MODULE2 (
VAR3 ,
VAR2 ,
VAR12 ,
VAR9 ,
VAR4 ,
VAR11,
VAR6 ,
VAR7 ,
VAR8 ,
VAR10
);
output VAR3 ;
output VAR2 ;
input VAR12 ;
input VAR9 ;
input VAR4 ;
input VAR11;
input VAR6 ;
input VAR7 ;
input VAR8 ;
input VAR10 ;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR11),
.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinv/sky130_fd_sc_hd__clkinv.behavioral.pp.v | 1,774 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR12,
VAR3,
VAR10 ,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR12;
input VAR3;
input VAR10 ;
input VAR2 ;
wire VAR4 ;
wire VAR1;
not VAR7 (VAR4 , VAR6 );
VAR11 VAR9 (VAR1, VAR4, VAR12, VAR3);
buf VAR8 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux4/sky130_fd_sc_hd__mux4_4.v | 2,444 | module MODULE2 (
VAR2 ,
VAR10 ,
VAR9 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR12,
VAR7,
VAR5 ,
VAR8
);
output VAR2 ;
input VAR10 ;
input VAR9 ;
input VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR12;
input VAR7;
input VAR5 ;
input VAR8 ;
VAR13 VAR11 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlxtn/sky130_fd_sc_hdll__dlxtn.functional.v | 1,599 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR9
);
output VAR4 ;
input VAR7 ;
input VAR9;
wire VAR3 ;
wire VAR2;
not VAR6 (VAR3 , VAR9 );
VAR1 VAR5 (VAR2 , VAR7, VAR3 );
buf VAR8 (VAR4 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd.pp.blackbox.v | 1,234 | module MODULE1 (
VAR1,
VAR3,
VAR2 ,
VAR4
);
input VAR1;
input VAR3;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/cpu_id.v | 4,702 | module MODULE1(rst, clk, VAR33, VAR46, VAR51, VAR22,
VAR52, VAR13, VAR15, VAR29, VAR19,
VAR40, VAR6, VAR32, VAR39, VAR18,
VAR9, VAR44, VAR36, VAR47, VAR17,
VAR12, VAR25, VAR28, VAR21, VAR34, VAR4, VAR49);
input rst, clk, VAR33;
input [31:0] VAR46;
input [31:0] VAR51;
input VAR22;
input [4:0] VAR52;
input [31:0] VAR13;
... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/flow_classification.v | 8,725 | module MODULE1
(
input VAR76,
output [63:0] VAR41,
output [23:0] VAR84,
output VAR19,
output reg VAR38,
input VAR64,
output VAR37,
output VAR63,
output [63:0] VAR14,
output [23:0] VAR13,
output VAR56,
output reg VAR75,
input VAR34,
output VAR10,
output VAR5,
output [63:0] VAR74,
output [23:0] VAR73,
output VAR72,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3b/sky130_fd_sc_lp__and3b_4.v | 2,218 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR10 ,
VAR3 ,
VAR4,
VAR7,
VAR1 ,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR10 ;
input VAR3 ;
input VAR4;
input VAR7;
input VAR1 ;
input VAR2 ;
VAR9 VAR5 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/BLK_MEM_GEN_V2_8.v | 49,479 | module MODULE1
parameter VAR5 = 0,
parameter VAR12 = "0",
parameter VAR11 = 0,
parameter VAR24 = 0,
parameter VAR21 = 0,
parameter VAR10 = "VAR6",
parameter VAR20 = "VAR6",
parameter VAR22 = 0,
parameter VAR25 = 0,
parameter VAR15 = 1,
parameter VAR8 = 100)
(input VAR4,
input VAR23,
input VAR1,
input VAR7,
input [VAR14... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probec_p/sky130_fd_sc_hd__probec_p.functional.pp.v | 1,793 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR6,
VAR8 ,
VAR7 ,
VAR11
);
output VAR5 ;
input VAR9 ;
input VAR6;
input VAR8 ;
input VAR7 ;
input VAR11;
wire VAR10 ;
wire VAR1;
buf VAR2 (VAR10 , VAR9 );
VAR12 VAR3 (VAR1, VAR10, VAR11, VAR6);
buf VAR4 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.pp.symbol.v | 1,521 | module MODULE1 (
input VAR1 ,
output VAR7 ,
input VAR4,
input VAR10 ,
input VAR3 ,
input VAR5 ,
input VAR6 ,
input VAR2 ,
input VAR9 ,
input VAR8
);
endmodule | apache-2.0 |
gbraad/minimig-de1 | rtl/sdram/sdram_ctrl.v | 18,802 | module MODULE1(
input wire VAR50,
input wire VAR13,
input wire VAR17,
input wire VAR47,
output wire VAR27,
input wire VAR71,
output reg [ 12-1:0] VAR56,
output reg [ 4-1:0] VAR35,
output reg [ 2-1:0] VAR40,
output reg VAR68,
output reg VAR2,
output reg VAR39,
output reg [ 2-1:0] VAR8,
inout wire [ 16-1:0] VAR95,
input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai_4.v | 2,441 | module MODULE2 (
VAR5 ,
VAR11 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR12 ,
VAR7,
VAR8,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR11 ;
input VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR12 ;
input VAR7;
input VAR8;
input VAR2 ;
input VAR1 ;
VAR9 VAR10 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR7(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b.pp.symbol.v | 1,297 | module MODULE1 (
input VAR7 ,
input VAR5 ,
input VAR1 ,
input VAR6 ,
output VAR4 ,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ethmac/ethmac.v | 33,872 | module MODULE1 (
VAR159, VAR4, VAR237, VAR161,
VAR95, VAR9, VAR43, VAR235, VAR32, VAR3, VAR206,
VAR258, VAR125, VAR83,
VAR135, VAR279, VAR234,
VAR109, VAR251, VAR221,
VAR208, VAR186,
VAR165, VAR150, VAR56, VAR12,
VAR156, VAR19, VAR146, VAR87, VAR72,
VAR288,
VAR97, VAR178, VAR256, VAR23,
VAR55
,
VAR74, VAR115, VAR93 VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbn/sky130_fd_sc_ms__dfbbn.pp.blackbox.v | 1,481 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR6 ,
VAR2 ,
VAR5 ,
VAR8,
VAR3 ,
VAR9 ,
VAR4 ,
VAR7
);
output VAR10 ;
output VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR8;
input VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_experimental/solution1/impl/ip/hdl/verilog/contact_discoverybkb.v | 1,801 | module MODULE1 (VAR10, VAR1, VAR5, VAR12, VAR8, VAR6, VAR3, VAR7, clk);
parameter VAR9 = 512;
parameter VAR11 = 7;
parameter VAR4 = 128;
input[VAR11-1:0] VAR10;
input VAR1;
input[VAR9-1:0] VAR5;
input VAR12;
output reg[VAR9-1:0] VAR8;
input[VAR11-1:0] VAR6;
input VAR3;
output reg[VAR9-1:0] VAR7;
input clk;
reg [VAR9-1:... | gpl-3.0 |
kielfriedt/ece472 | lab3/ALU4_LA.v | 1,372 | module MODULE1(VAR1, VAR12, VAR16, VAR13, VAR4, sel, out, VAR9, VAR6);
input VAR4;
input [3:0] VAR1, VAR12;
input [2:0] sel;
input VAR16;
output [3:0] out;
output VAR9,VAR6;
output VAR13;
wire [2:0] VAR8;
wire [3:0] VAR2, VAR14;
VAR7 VAR11(VAR1[0], VAR12[0], VAR16, VAR4, sel, out[0], VAR2[0], VAR14[0]);
VAR7 VAR15(VAR1... | gpl-3.0 |
bunnie/novena-gpbb-fpga | novena-gpbb.srcs/sources_1/imports/imports/i2c_slave.v | 23,666 | module MODULE1 (
input wire VAR36, input wire VAR37,
output reg VAR50,
input wire clk, input wire VAR35, input wire [7:0] VAR34,
output wire [7:0] VAR6, output wire [7:0] VAR65,
input wire [7:0] VAR41, input wire [7:0] VAR10,
input wire [7:0] VAR44,
input wire [7:0] VAR52, input wire [7:0] VAR45,
input wire [7:0] VAR16... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi.functional.pp.v | 2,026 | module MODULE1 (
VAR16 ,
VAR12 ,
VAR15 ,
VAR4 ,
VAR8,
VAR5,
VAR3 ,
VAR7
);
output VAR16 ;
input VAR12 ;
input VAR15 ;
input VAR4 ;
input VAR8;
input VAR5;
input VAR3 ;
input VAR7 ;
wire VAR2 ;
wire VAR9 ;
wire VAR14;
and VAR10 (VAR2 , VAR12, VAR15 );
nor VAR11 (VAR9 , VAR4, VAR2 );
VAR1 VAR13 (VAR14, VAR9, VAR8, VAR5);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.functional.v | 1,429 | module MODULE1 (
VAR4 ,
VAR5,
VAR3
);
output VAR4 ;
input VAR5;
input VAR3 ;
wire VAR7 ;
wire VAR1;
not VAR2 (VAR7 , VAR5 );
and VAR8 (VAR1, VAR7, VAR3 );
buf VAR6 (VAR4 , VAR1 );
endmodule | apache-2.0 |
Elphel/x353 | compressor/csconvert_mono.v | 10,819 | module MODULE1 (en,
clk,
din,
VAR31,
VAR15,
VAR21,
VAR26,
VAR14);
input en;
input clk; input [7:0] din; input VAR31; output [7:0] VAR15; output [7:0] VAR21; output VAR26; output VAR14;
wire VAR14= VAR31;
wire [7:0] VAR15= {~din[7],din[6:0]};
reg [7:0] VAR21;
reg VAR26;
always @ (posedge clk) begin
VAR26 <= en & (VAR31 ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_4.behavioral.pp.v | 1,784 | module MODULE1( VAR4, VAR1, VAR12, VAR11, VAR9 );
input VAR1, VAR4;
inout VAR11, VAR9;
output VAR12;
reg VAR3;
VAR8 VAR2(.VAR4(VAR4),.VAR1(VAR1),.VAR12(VAR12),.VAR11(VAR11),.VAR9(VAR9),.VAR3(VAR3));
VAR8 VAR13(.VAR4(VAR4),.VAR1(VAR1),.VAR12(VAR12),.VAR11(VAR11),.VAR9(VAR9),.VAR3(VAR3));
not VAR5(VAR7,VAR1);
buf VAR10(V... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff_reset.v | 4,353 | if (VAR6 && VAR11==VAR13) \
begin: VAR5 \
VAR12 VAR10(.VAR1 \
,.VAR9 \
,.VAR2(~VAR8) \
,.VAR3); \
end
module MODULE1 #(VAR11=-1, VAR6=1)
(input VAR1
,input VAR8
,input [VAR11-1:0] VAR9
,output [VAR11-1:0] VAR3
);
else VAR4(89)
else VAR4(88)
else VAR4(87)
else VAR4(86)
else VAR4(85)
else VAR4(84)
else VAR4(83)
else VAR4... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.v | 2,030 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR6,
VAR4,
VAR3 ,
VAR1
);
output VAR7 ;
input VAR2 ;
input VAR6;
input VAR4;
input VAR3 ;
input VAR1 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7,
VAR2
);
output VAR7;
input VAR2;
supply1 VAR6;
supply0 VAR4;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1.blackbox.v | 1,305 | module MODULE1 (
VAR5,
VAR6,
VAR4
);
output VAR5;
input [15:0] VAR6;
input [15:0] VAR4;
supply1 VAR2;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/example_mods.v | 10,516 | module MODULE1( VAR5, VAR15, VAR19, VAR23, VAR9, VAR10, VAR26, VAR7, VAR24,
VAR14, VAR8, VAR2, VAR3, VAR22 );
input VAR5;
input VAR15;
input VAR23,VAR9;
input [31:28] VAR10;
input [3:0] VAR26;
input [31:0] VAR2;
input [7:0] VAR8;
input [31:0] VAR3;
output reg [31:0] VAR7;
output reg VAR19;
output reg VAR22;
output VAR2... | gpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_jtag_uart.v | 23,341 | module MODULE2 (
clk,
VAR63,
VAR4,
valid
)
;
input clk;
input [ 7: 0] VAR63;
input VAR4;
input valid;
reg [31:0] VAR76; VAR58 VAR76 =
always @(posedge clk) begin
if (valid && VAR4) begin
("%VAR62", ((VAR63 == 8'hd) ? 8'ha : VAR63));
VAR7 (VAR76);
end
end
endmodule
module MODULE5 (
clk,
VAR52,
VAR12,
VAR46,
VAR27,
VAR31... | mit |
olajep/oh | src/adi/hdl/library/axi_dmac/axi_register_slice.v | 4,022 | module MODULE1 #(
parameter VAR1 = 32,
parameter VAR8 = 0,
parameter VAR2 = 0)(
input clk,
input VAR5,
input VAR9,
output VAR3,
input [VAR1-1:0] VAR14,
output VAR10,
input VAR11,
output [VAR1-1:0] VAR17
);
wire [VAR1-1:0] VAR16;
wire VAR12;
wire VAR19;
wire [VAR1-1:0] VAR6;
wire VAR15;
wire VAR7;
generate if (VAR8 == 1... | mit |
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