agent/: verified PTX, CUDA C++, Triton and CuTe references

Adds agent/ref/ (ptx, cuda-cpp, triton, cute-cutlass) and agent/tools/check_toolchain.py.

Every instruction and API was compiled with the container's own nvcc on sm_90a / CUDA 12.8: 39/41 PTX instructions assemble (tcgen05 is Blackwell-only and recorded as such), 24/24 CUDA C++ constructs compile, and the Triton tables come from introspecting the installed 3.6.0.

Measured facts that are easy to get wrong: wgmma.m64nNk16.f32 needs exactly N/2 accumulator registers per thread, so an m64n256k16 tile spends 128 registers on the accumulator alone; and Triton 3.6 accepts cache_modifier='.cg' with eviction_policy='evict_first' but ptxas rejects the pair.

check_toolchain.py re-derives the tables on whatever GPU the agent actually has.

agent/README.md

@@ -14,9 +14,9 @@ Copy into a project so Claude Code can find it:
 
 ```bash
 mkdir -p .claude/skills/kernel-optimization .claude/agents
-cp -r agent/*.md agent/tools .claude/skills/kernel-optimization/
+cp -r agent/*.md agent/ref agent/tools .claude/skills/kernel-optimization/
 cp agent/agents/kernel-*.md .claude/agents/
-rm .claude/skills/kernel-optimization/README.md      # this file; not part of the skill
+rm .claude/skills/kernel-optimization/README.md          # this file; not part of the skill
 chmod +x .claude/skills/kernel-optimization/tools/*.sh   # exec bits do not survive the download
 ```
 
@@ -35,6 +35,26 @@ faster", "implement a fused attention kernel", or "solve this KBench task".
 | `pitfalls.md` | measurement lies, correctness traps, and how to read a profile without chasing a healthy-looking counter |
 | `references.md` | which open-source kernel demonstrates which technique |
 
+### Language references (`ref/`)
+
+| file | covers |
+|---|---|
+| `ref/ptx.md` | inline PTX: constraints, cache hints, `cp.async`, TMA, `mbarrier`, `mma`/`wgmma`, `ldmatrix`/`stmatrix`, `setmaxnreg`, fast-math opcodes |
+| `ref/cuda-cpp.md` | CUDA C++: opt-in shared memory, `cuda::pipeline`, cooperative groups, clusters/DSMEM, host-side TMA descriptors, build and debug flags |
+| `ref/triton.md` | the Triton 3.6 API surface, launch knobs, idioms, and where it caps out |
+| `ref/cute-cutlass.md` | CuTe layout algebra, swizzles, atoms, and where CUTLASS lives in the image |
+
+**These are verified, not recalled.** Every instruction and API was compiled with the container's own
+`nvcc` on `sm_90a` / CUDA 12.8: 39/41 PTX instructions assemble (the two that do not are recorded —
+`tcgen05` is Blackwell-only), 24/24 CUDA C++ constructs compile, and the Triton tables come from
+introspecting the installed 3.6.0.
+
+Two examples of what that buys you. `wgmma.m64nNk16.f32` needs exactly **N/2 accumulator registers per
+thread** — measured across five shapes — so an `m64n256k16` tile spends 128 registers on the accumulator
+alone, which is what forces warp specialisation. And Triton 3.6 *accepts* `cache_modifier=".cg"`
+together with `eviction_policy="evict_first"` but ptxas rejects the pair; the full combination matrix is
+in `ref/triton.md`.
+
 ### Tools (`tools/`)
 
 - **`roofline.py`** — measures the device rather than quoting a datasheet, then gives the floor and
@@ -47,6 +67,9 @@ faster", "implement a fused attention kernel", or "solve this KBench task".
   how you confirm the MMA you intended actually issued and that nothing spilled.
 - **`occupancy.py`** — finds the occupancy limiter and checks a persistent grid for the co-residency
   deadlock.
+- **`check_toolchain.py`** — re-derives every table in `ref/` by compiling on the machine you are
+  actually on. The docs were verified on sm_90a / CUDA 12.8; on a different GPU or toolkit some rows
+  change, and this tool wins over the docs.
 - **`ledger.md`** — one row per variant. The column that matters records whether an abandoned variant
   was *slower* or merely *broken*; dropping a good optimization over a fixable bug is the most common
   way to leave 2x on the table.

agent/SKILL.md

@@ -12,6 +12,19 @@ percent still rank.
 Read `profiling.md`, `toolchain.md`, `algorithms.md`, `hardware.md` and `pitfalls.md` in this directory
 as you hit the corresponding phase. Tools are in `tools/`.
 
+**`ref/` holds the language references** — reach for them while writing code, not while planning:
+
+| file | when |
+|---|---|
+| `ref/ptx.md` | inline PTX: cache hints, `cp.async`, TMA, `mbarrier`, `mma`/`wgmma`, `ldmatrix`, `setmaxnreg` |
+| `ref/cuda-cpp.md` | CUDA C++: opt-in shared memory, pipelines, cooperative groups, clusters, TMA descriptors, build flags |
+| `ref/triton.md` | Triton 3.6 API surface, launch knobs, idioms, and the traps |
+| `ref/cute-cutlass.md` | CuTe layout algebra and where CUTLASS lives in the image |
+
+Every instruction and API in `ref/` was verified by compiling it on the container toolchain (sm_90a,
+CUDA 12.8) — but **you may not be on that machine**. Run `python3 tools/check_toolchain.py` to
+re-derive the tables for the GPU you actually have; where it disagrees with the docs, it wins.
+
 ## The loop
 
 ```
@@ -114,6 +127,12 @@ registers spilled, and whether the compiler hoisted what you expected.
 flash-attention, CUTLASS, DeepGEMM, ThunderKittens, Liger). Read for *technique*, not copy-paste — and
 note that in a graded KBench environment those libraries are deliberately absent.
 
+For the instruction- and API-level detail those kernels are built from, use `ref/` (above). A worked
+example of why it is there: `wgmma.m64nNk16.f32` needs exactly **N/2 accumulator registers per thread**,
+so an `m64n256k16` tile spends 128 registers on the accumulator alone — half the architectural maximum.
+That single fact decides whether your warpgroup tile needs warp specialisation, and it is the kind of
+thing that costs an hour to rediscover by compile error.
+
 ## Sub-agents
 
 For a substantial optimization, delegate: `kernel-algorithmist` (restructure the maths),

agent/agents/kernel-implementer.md

@@ -8,6 +8,12 @@ model: opus
 You turn a specification into a correct, fast kernel. Read
 `.claude/skills/kernel-optimization/toolchain.md`, `hardware.md` and `pitfalls.md` first.
 
+While writing code, the language references are in `.claude/skills/kernel-optimization/ref/` —
+`ptx.md` (cache hints, `cp.async`, TMA, `mbarrier`, `mma`/`wgmma`, `ldmatrix`, `setmaxnreg`),
+`cuda-cpp.md` (opt-in shared memory, pipelines, cooperative groups, clusters, TMA descriptors, build
+flags), `triton.md` and `cute-cutlass.md`. They were verified by compiling on sm_90a / CUDA 12.8; run
+`python3 tools/check_toolchain.py` to confirm against the machine you are actually on.
+
 ## Rules
 
 1. **Query the device; never hardcode it.** `torch.cuda.get_device_properties(0)` for

agent/agents/kernel-profiler.md

@@ -21,6 +21,10 @@ You return a diagnosis, never a wall of counters. Read
 3. **Then find the mechanism.** Sectors/request for coalescing, bank conflicts for swizzle, warp stall
    reasons for latency, SASS for spills and whether the MMA issued.
 
+When the SASS does not contain the instruction you expected, `.claude/skills/kernel-optimization/ref/`
+tells you what the instruction should have been — `ptx.md` for the MMA/async-copy families and
+`ref/triton.md` for what Triton 3.6 will and will not emit.
+
 `ncu` needs performance counters: `--cap-add SYS_ADMIN` on the container, or
 `NVreg_RestrictProfilingToAdminUsers=0` on the host. `ncu --version` succeeding proves nothing — it
 never touches a counter. Without access you get `ERR_NVGPUCTRPERM`.

agent/ref/cuda-cpp.md

@@ -0,0 +1,171 @@
+# CUDA C++ reference for kernel authors
+
+Every API below **compiled with `nvcc -arch=sm_90a -std=c++17` on CUDA 12.8**, the toolchain in the task
+containers. 24/24 of the constructs listed here were verified; nothing is quoted from memory.
+
+## Building inside a task container
+
+```python
+from torch.utils.cpp_extension import load_inline
+mod = load_inline(name="k", cpp_sources=cpp, cuda_sources=cu,
+                  functions=["run"], extra_cuda_cflags=["-O3", "-arch=sm_90a", "--use_fast_math"])
+```
+or drive `nvcc` yourself and `torch.ops.load_library`. Use `-arch=sm_90a` rather than `sm_90`: the `a`
+("architecture-specific") target is what enables `wgmma`, TMA and `setmaxnreg`.
+
+Useful flags: `-lineinfo` (maps SASS back to source in `ncu`), `-Xptxas -v` (prints register and shared
+memory usage per kernel — check this before you profile), `--use_fast_math` (turns `expf` into
+`ex2.approx`, and changes results — make sure the tolerance allows it).
+
+## Shared memory beyond 48 KB
+
+The default limit is 48 KB per block. Hopper has ~227 KB opt-in, but you must ask for it **on the host**:
+
+```cpp
+cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, 200*1024);
+kernel<<<grid, block, 200*1024>>>(...);
+```
+Query the real number rather than hardcoding it — `torch.cuda.get_device_properties(0)
+.shared_memory_per_block_optin`. Forgetting the attribute gives a launch failure, not a slow kernel.
+
+## Occupancy control
+
+```cpp
+__global__ void __launch_bounds__(256, 2) k(...)   // 256 threads/block, ≥2 blocks/SM
+```
+The second argument caps registers per thread so the requested blocks fit. It is how you *force* a
+tradeoff — but check `pitfalls.md` first: low occupancy is often correct, and a GEMM that wants 168
+registers should keep them.
+
+## Async copy — three levels of control
+
+```cpp
+// 1. Highest level: pipeline object
+#include <cuda/pipeline>
+__shared__ cuda::pipeline_shared_state<cuda::thread_scope_block, 2> state;
+auto p = cuda::make_pipeline(cooperative_groups::this_thread_block(), &state);
+p.producer_acquire(); cuda::memcpy_async(dst, src, 16, p); p.producer_commit();
+p.consumer_wait(); /* use dst */ p.consumer_release();
+
+// 2. Mid level: raw cp.async, you manage the groups
+#include <cuda_pipeline.h>
+__pipeline_memcpy_async(smem, gmem, 16);
+__pipeline_commit();
+__pipeline_wait_prior(0);
+
+// 3. Lowest level: inline PTX (see ptx.md) when you need the exact issue point
+```
+
+`cuda::barrier<cuda::thread_scope_block>` with `arrive_and_wait()` is the composable barrier; it is the
+C++ face of `mbarrier` and what TMA completion is signalled through.
+
+## TMA descriptors (host side)
+
+```cpp
+#include <cuda.h>
+CUtensorMap map;
+cuuint64_t size[2] = {W, H}; cuuint64_t stride[1] = {W * sizeof(bf16)};
+cuuint32_t box[2] = {64, 64}; cuuint32_t elem_stride[2] = {1, 1};
+cuTensorMapEncodeTiled(&map, CU_TENSOR_MAP_DATA_TYPE_BFLOAT16, 2, ptr, size, stride, box, elem_stride,
+                       CU_TENSOR_MAP_INTERLEAVE_NONE, CU_TENSOR_MAP_SWIZZLE_128B,
+                       CU_TENSOR_MAP_L2_PROMOTION_L2_128B, CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE);
+```
+Build it **once in untimed setup**, pass it as a kernel argument (or `__grid_constant__`), then issue
+copies from PTX. `CU_TENSOR_MAP_SWIZZLE_128B` is what makes the shared-memory tile bank-conflict-free —
+the swizzle happens in hardware, so do not also pad. Link with `-lcuda` for the driver API.
+
+## Cooperative groups
+
+```cpp
+#include <cooperative_groups.h>
+#include <cooperative_groups/reduce.h>
+namespace cg = cooperative_groups;
+
+auto tile = cg::tiled_partition<32>(cg::this_thread_block());
+float s = cg::reduce(tile, v, cg::plus<float>());     // warp reduction, no shuffle by hand
+
+auto grid = cg::this_grid(); grid.sync();             // needs cudaLaunchCooperativeKernel
+```
+
+**`grid.sync()` deadlocks unless every block is resident.** Launch with
+`cudaLaunchCooperativeKernel` and size the grid from `cudaOccupancyMaxActiveBlocksPerMultiprocessor ×
+SM count` — this is the single most common way a persistent/megakernel hangs. `tools/occupancy.py`
+checks it for you.
+
+## Clusters and distributed shared memory (Hopper)
+
+```cpp
+__global__ void __cluster_dims__(2, 1, 1) k(...) {
+  auto c = cg::this_cluster();
+  int* peer = c.map_shared_rank(smem, 0);   // read another block's shared memory
+  c.sync();
+}
+```
+DSMEM lets blocks in a cluster share tiles without a round trip to global — useful when several blocks
+consume the same B tile of a GEMM.
+
+## Data types
+
+```cpp
+#include <cuda_bf16.h>   __nv_bfloat162 v = __floats2bfloat162_rn(a, b);  v = __hfma2(v, v, v);
+#include <cuda_fp16.h>   __half2 h = __floats2half2_rn(a, b);
+#include <cuda_fp8.h>    __nv_fp8_e4m3 q(1.5f); float back = (float)q;
+```
+Always use the **packed** (`x2`) intrinsics for 16-bit types: one instruction, two values. Scalar
+`__hadd` on bf16 wastes half of every ALU slot.
+
+## Warp intrinsics
+
+```cpp
+__shfl_xor_sync(0xffffffff, v, 16);      // butterfly step
+__reduce_add_sync(0xffffffff, u);        // one-instruction integer warp reduce (sm_80+)
+__ballot_sync(0xffffffff, pred);
+__syncwarp();
+```
+Always the `_sync` forms with an explicit mask — the legacy non-sync intrinsics are removed.
+
+## Atomics
+
+```cpp
+atomicAdd(p, v);                                    // device scope
+atomicAdd_block(p, v);                              // block scope: much cheaper when that suffices
+atomicAdd((__nv_bfloat162*)p, __floats2bfloat162_rn(a, b));   // packed
+```
+Prefer a warp/block reduction followed by one atomic per block over one atomic per thread. Note that
+atomics make a kernel **non-deterministic** in floating point — if your correctness check compares two
+runs, that is where the mismatch comes from.
+
+## Loads
+
+```cpp
+__ldg(p);    // read-only cache
+__ldcs(p);   // streaming, evict-first
+__ldlu(p);   // last-use, do not keep
+const float4* q = (const float4*)__builtin_assume_aligned(p, 16);
+float4 v = *q;                                       // 128-bit load
+```
+
+## wmma vs mma vs wgmma
+
+`#include <mma.h>` gives `nvcuda::wmma` — portable, easy, and leaves performance on the table because
+you do not control the fragment layout. Use it to get correct, then move to `mma.sync` (per-warp) or
+`wgmma` (warpgroup) from `ptx.md` when you need the last 2x.
+
+## Scheduling
+
+```cpp
+__nanosleep(100);                              // spin-loop backoff
+cudaGridDependencySynchronize();               // PDL: wait for the prior kernel's data
+cudaTriggerProgrammaticLaunchCompletion();     // let the next kernel start early
+```
+
+## Debugging
+
+```bash
+compute-sanitizer --tool memcheck ./a.out     # OOB and misaligned access
+compute-sanitizer --tool racecheck ./a.out    # shared-memory races
+cuobjdump -sass k.cubin | grep -cE 'LDL|STL'  # register spills
+nvcc -Xptxas -v ...                           # registers/smem per kernel, at compile time
+```
+Run `racecheck` once on any kernel with a hand-written barrier. A missing `__syncthreads()` usually
+produces *correct* results at small shapes and garbage at graded ones.

agent/ref/cute-cutlass.md

@@ -0,0 +1,105 @@
+# CuTe and CUTLASS
+
+Verified in the task container: CUTLASS headers at **`/opt/pytorch/third_party/cutlass/include`** (96
+example directories alongside them), and the Python CuTe DSL as **`cutlass` 4.6.1** with
+`cutlass.cute` importable. A CuTe kernel compiles with:
+
+```bash
+nvcc -arch=sm_90a -std=c++17 -I/opt/pytorch/third_party/cutlass/include \
+     --expt-relaxed-constexpr -cubin -o /dev/null k.cu
+```
+
+`--expt-relaxed-constexpr` is required; without it the layout algebra fails to instantiate.
+
+## The one idea to internalise
+
+**A layout is a function from a logical coordinate to a memory offset.** Everything else in CuTe follows
+from that.
+
+```cpp
+#include <cute/tensor.hpp>
+using namespace cute;
+
+auto layout = make_layout(make_shape(Int<8>{}, Int<16>{}), LayoutRight{});
+auto t      = make_tensor(make_gmem_ptr(ptr), layout);
+t(3, 5);                       // coordinate -> element, offset computed by the layout
+```
+
+A layout is a `(Shape, Stride)` pair, and both can be **hierarchical**: `((4,2),(8,1))` is a perfectly
+ordinary shape. Static extents are `Int<N>{}` (compile-time, folded away); dynamic ones are plain
+integers. Prefer static wherever the shape is known — that is where the address arithmetic disappears.
+
+## Operations you actually use
+
+| operation | meaning |
+|---|---|
+| `composition(A, B)` | apply B then A — **a swizzle is just a composition** |
+| `logical_divide(L, tile)` | split an axis into (tile, rest) — this is tiling |
+| `zipped_divide` / `tiled_divide` | the same, arranged for thread/value partitioning |
+| `local_tile(t, tile, coord)` | the tile this block owns |
+| `local_partition(t, layout, idx)` | the elements this thread owns |
+| `make_fragment_like(t)` | register tensor matching a partition |
+| `size(L)`, `rank(L)`, `shape(L)`, `stride(L)` | introspection, mostly at compile time |
+
+The pattern in nearly every CuTe kernel:
+
+```
+global tensor -> local_tile   (block's tile)
+             -> local_partition (thread's elements)
+             -> make_fragment_like + copy   (into registers)
+             -> gemm(mma, acc, a_frag, b_frag, acc)
+```
+
+## Copy and MMA atoms
+
+```cpp
+copy(copy_atom, src, dst);      // one call; the atom knows if it is cp.async, TMA, or plain ld/st
+gemm(mma_atom, acc, a, b, acc); // one call; the atom knows if it is mma.sync or wgmma
+```
+
+The value of atoms is that the *partitioning* is described once and the instruction selection is
+separate. Swapping `SM80_CP_ASYNC_CACHEALWAYS` for an `SM90_TMA_LOAD` atom changes how data arrives
+without touching the loop structure.
+
+## Swizzles
+
+```cpp
+auto swizzled = composition(Swizzle<3,3,3>{}, smem_layout);
+```
+`Swizzle<B,M,S>` XORs bits of the offset so that consecutive rows land in different shared-memory banks.
+Use it **instead of padding**, especially for 2-byte types where padding wastes a whole bank and breaks
+128-bit vectorisation. If you use TMA with `CU_TENSOR_MAP_SWIZZLE_128B`, the hardware already swizzles —
+do not swizzle again.
+
+## Debugging layouts
+
+```cpp
+print(layout);            print_layout(layout);     // ASCII table of coord -> offset
+print_tensor(t);
+if (thread0()) { ... }                              // guard host-style printing
+```
+`print_layout` on a 2-D layout prints the actual offset grid. When a kernel produces transposed or
+interleaved garbage, print the layout before you read any SASS — it is almost always a partitioning
+mistake, not an instruction mistake.
+
+## The Python CuTe DSL
+
+```python
+import cutlass, cutlass.cute as cute
+```
+Version 4.6.1 is installed. It expresses the same layout algebra in Python and JIT-compiles, which makes
+it far quicker to iterate on a tiling scheme than a C++ rebuild. The concepts transfer exactly, so
+prototype the partitioning here and port to C++ if you need the last increment of control.
+
+## Reading CUTLASS itself
+
+96 example directories ship in the container. Two things are worth reading before writing a Hopper GEMM:
+
+- **the collective mainloop** — how a producer warp issuing TMA and consumer warps issuing `wgmma` are
+  actually wired together, including where the `mbarrier` phases flip
+- **the epilogue** — how the accumulator is transformed and written back with a different tiling from
+  the mainloop, which is where fused activations and scaling belong
+
+Read them for the *structure*. Copying a CUTLASS kernel wholesale into a task rarely works, because the
+task's shapes and fusion are not the ones the example was tuned for — and in a graded container the
+library may not be importable at all.

agent/ref/ptx.md

@@ -0,0 +1,169 @@
+# PTX quick reference
+
+Every instruction below was **assembled with `nvcc -arch=sm_90a` on CUDA 12.8** — the toolchain in the
+task containers. Nothing here is from memory. Where something does *not* work, that is recorded too.
+
+You reach for PTX when the compiler will not emit what you need: a specific cache policy, an async copy
+you want issued at a precise point, an MMA shape the C++ API does not expose, or a warpgroup
+instruction. For everything else, write CUDA C++ and read the SASS.
+
+## Inline asm syntax
+
+```cpp
+asm volatile("instr.mod %0, [%1];" : "=f"(dst) : "l"(ptr) : "memory");
+//            ^template              ^outputs   ^inputs     ^clobbers
+```
+
+| constraint | binds to |
+|---|---|
+| `"f"` / `"d"` | `.f32` / `.f64` register |
+| `"r"` / `"l"` | `.u32` / `.u64` register — **shared-memory addresses are `"r"` (32-bit)**, global are `"l"` |
+| `"h"` | `.u16` (fp8 pairs, bf16 halves) |
+| `"=f"` output, `"+f"` read-modify-write | |
+
+`volatile` stops the compiler sinking or duplicating the instruction; add `"memory"` when it orders
+other accesses. Convert a shared pointer with `__cvta_generic_to_shared(ptr)` before passing it as `"r"`.
+
+## Loads and stores — cache control
+
+| instruction | effect |
+|---|---|
+| `ld.global.nc.f32` | read-only/`__ldg` path, uses the texture cache |
+| `ld.global.L2::128B.f32` | prefetch a 128B L2 sector |
+| `ld.global.L1::no_allocate.f32` | streaming: do not pollute L1 |
+| `st.global.cs.f32` | evict-first store — for data nobody reads again |
+| `ld.global.v4.f32 {a,b,c,d}` | one 128-bit transaction; **the single most reliable bandwidth win** |
+
+Vectorize first. A `.v4.f32` (or `.v4.b32` for two bf16x2) load moves 16B per instruction, quartering
+the instruction count and hitting the ideal 4 sectors/request that `ncu` reports.
+
+## Async copy (Ampere+) — `cp.async`
+
+```
+cp.async.ca.shared.global [%smem], [%gmem], 16;   // through L1
+cp.async.cg.shared.global [%smem], [%gmem], 16;   // bypass L1, for streamed tiles
+cp.async.commit_group;
+cp.async.wait_group 1;                            // let 1 group stay in flight
+```
+
+Sizes are 4, 8 or 16 bytes; 16 is the one worth using. This is what double buffering is built from:
+issue group N+1, then `wait_group 1` and compute on group N.
+
+## TMA (Hopper) — bulk tensor copy
+
+```
+cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes
+    [%smem], [%tmap, {%x, %y}], [%mbar];
+cp.reduce.async.bulk.tensor.2d.global.shared::cta.add.tile.bulk_group
+    [%tmap, {%x, %y}], [%smem];      // accumulate a tile straight back to global
+```
+
+One thread issues the copy for the whole tile; the descriptor (`%tmap`) is built **on the host** with
+`cuTensorMapEncodeTiled` (see `cuda-cpp.md`). TMA does the address arithmetic, the bounds checking and
+the swizzle in hardware — this is why Hopper kernels spend so few instructions on addressing.
+
+## Barriers
+
+| instruction | use |
+|---|---|
+| `mbarrier.init.shared.b64 [%bar], %count` | initialise, once, by one thread |
+| `mbarrier.arrive.expect_tx.shared::cta.b64` | arrival that also declares the incoming TMA byte count |
+| `mbarrier.try_wait.parity.shared::cta.b64` | phase-flipping wait; the loop-friendly form |
+| `fence.proxy.async.shared::cta` | order async-proxy writes (TMA/wgmma) against generic ones |
+| `barrier.cluster.arrive` / `.wait` | Hopper cluster-wide sync |
+
+`fence.proxy.async` is the one people forget: TMA writes shared memory through a *different proxy* than
+ordinary stores, so without the fence your MMA can read a tile that is not there yet.
+
+## Tensor cores
+
+**Per-warp (`mma.sync`)** — portable back to Ampere:
+```
+mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32  {d0..d3}, {a0..a3}, {b0,b1}, {c0..c3};
+mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32  {d0..d3}, {a0..a3}, {b0,b1}, {c0..c3};
+```
+
+**Warpgroup (`wgmma`, Hopper)** — issued by 128 threads, operands read straight from shared memory via
+a 64-bit descriptor:
+```
+wgmma.fence.sync.aligned;
+wgmma.mma_async.sync.aligned.m64nNk16.f32.bf16.bf16 {d...}, %desc_a, %desc_b, 1,1,1,0,0;
+wgmma.commit_group.sync.aligned;
+wgmma.wait_group.sync.aligned 0;
+```
+
+**Accumulator size, measured** — `m64nNk16.f32` needs exactly **N/2 f32 registers per thread**:
+
+| shape | acc regs/thread |
+|---|---|
+| `m64n8k16` | 4 |
+| `m64n16k16` | 8 |
+| `m64n64k16` | 32 |
+| `m64n128k16` | 64 |
+| `m64n256k16` | 128 |
+
+Getting this wrong is a compile error (`Argument vector size mismatch`), not a silent bug — but it also
+tells you the register budget up front: an `m64n256k16` accumulator alone is 128 registers, half the
+architectural maximum, which is why big-N warpgroup tiles force warp specialisation.
+
+**Feeding the MMA:**
+```
+ldmatrix.sync.aligned.m8n8.x4.shared.b16        {r0..r3}, [%smem];
+ldmatrix.sync.aligned.m8n8.x4.trans.shared.b16  {r0..r3}, [%smem];   // transposed, free
+stmatrix.sync.aligned.m8n8.x4.shared.b16        [%smem], {r0..r3};
+```
+`ldmatrix` loads a fragment in exactly the layout the MMA wants. `.trans` transposes for free — never
+transpose in registers by hand.
+
+## Warp-level
+
+| instruction | note |
+|---|---|
+| `shfl.sync.bfly.b32` | butterfly reduction: `log2(32)` = 5 steps |
+| `redux.sync.add.u32` | whole-warp integer reduction in **one** instruction (sm_80+) |
+| `elect.sync` | pick one leader lane — cheaper than `laneid == 0` |
+| `vote.sync.ballot.b32` | predicate mask across the warp |
+
+## Warp specialisation (Hopper)
+
+```
+setmaxnreg.dec.sync.aligned.u32 24;    // producer warps: give registers back
+setmaxnreg.inc.sync.aligned.u32 232;   // consumer warps: take them
+```
+
+This is the mechanism behind producer/consumer kernels: DMA warps need almost no registers, MMA warps
+need a great many, and the register file is redistributed at runtime rather than sized for the worst
+case.
+
+## Scheduling and math
+
+| instruction | note |
+|---|---|
+| `griddepcontrol.wait` / `.launch_dependents` | programmatic dependent launch — overlap the tail of one kernel with the head of the next |
+| `nanosleep.u32 N` | back off inside a spin loop; without it, spinning starves the warps you are waiting on |
+| `ex2.approx.f32` | **the softmax primitive** — compute `exp(x)` as `ex2(x * 1.4427)`; far cheaper than `exp` |
+| `rcp.approx.f32`, `rsqrt.approx.f32`, `tanh.approx.f32` | fast paths for normalisation and gelu |
+| `cvt.rn.satfinite.e4m3x2.f32` | pack two floats into fp8x2 with saturation, one instruction |
+| `cvt.rn.bf16x2.f32` | pack two floats into bf16x2 |
+
+## Atomics
+
+```
+red.global.add.f32 [%p], %v;             // fire-and-forget: no return value, no latency to hide
+atom.global.add.v2.f32 {%d0,%d1}, [%p], {%v0,%v1};   // vector atomic
+```
+Use `red` whenever you discard the old value — `atom` makes the warp wait for a result you never read.
+
+## Not available on sm_90a
+
+`tcgen05.*` (Blackwell 5th-gen tensor core instructions) fails with *"Instruction not supported on
+.target sm_90a"*. If you are targeting Hopper, `wgmma` is the top of the ladder.
+
+## Verifying what you wrote
+
+```bash
+nvcc -arch=sm_90a -cubin -o /dev/null probe.cu     # does it assemble?
+cuobjdump -sass kernel.cubin | grep -E "HMMA|QGMMA|LDL|STL"
+```
+`LDL`/`STL` in the SASS means registers spilled. Zero `HMMA`/`QGMMA` where you expected tensor cores
+means the MMA never issued — the commonest cause of a "why is my kernel at 5% of peak".

agent/ref/triton.md

@@ -0,0 +1,129 @@
+# Triton reference
+
+Verified against **Triton 3.6.0 / torch 2.11 / CUDA 12.8** — the versions in the task containers. The
+API surface below was enumerated by introspection and the kernels were run on an H200.
+
+## What exists in 3.6
+
+| group | available |
+|---|---|
+| core | `dot`, `load`, `store`, `arange`, `zeros`, `full`, `where`, `sum`, `max`, `min`, `reduce`, `associative_scan`, `cumsum`, `sort`, `trans`, `permute`, `reshape`, `expand_dims`, `broadcast_to`, `split`, `join`, `interleave` |
+| math | `exp`, `exp2`, `log`, `log2`, `sqrt`, `rsqrt`, `sigmoid`, `softmax`, `erf`, `sin`, `fma`, `maximum`, `minimum`, `clamp`, `abs`, `floor`, `ceil` |
+| precision | `dot_scaled`, `cast`, `inline_asm_elementwise` |
+| memory | `make_block_ptr`, `advance`, `atomic_add`, `atomic_cas`, `atomic_xchg`, `atomic_max`, `make_tensor_descriptor`, `load_tensor_descriptor`, `store_tensor_descriptor` |
+| program | `program_id`, `num_programs`, `static_assert`, `static_print`, `device_print`, `assume`, `range`, `multiple_of`, `max_contiguous` |
+| random | `rand`, `randn`, `randint`, `philox` |
+
+Top level: `triton.jit`, `triton.autotune`, `triton.heuristics`, `triton.Config`, `triton.cdiv`,
+`triton.next_power_of_2`, `triton.set_allocator`.
+
+Cast with the **method** form, `x.to(tl.float32)` — there is no `tl.to`.
+
+## Signatures worth knowing exactly
+
+```python
+tl.load(pointer, mask=None, other=None, boundary_check=(), padding_option='',
+        cache_modifier='', eviction_policy='', volatile=False)
+
+tl.dot(input, other, acc=None, input_precision=None, allow_tf32=None,
+       max_num_imprecise_acc=None, out_dtype=tl.float32)
+```
+
+`tl.dot(a, b, acc)` accumulates into `acc` — pass it rather than writing `acc += tl.dot(a, b)`, which
+materialises a temporary. `out_dtype=tl.float32` is the default and is what you want; fp16/bf16
+accumulation drifts.
+
+## A gotcha that costs a compile cycle — measured
+
+`cache_modifier` and `eviction_policy` are accepted by Triton but **rejected by ptxas in combination**:
+
+| `cache_modifier` | `eviction_policy` | result |
+|---|---|---|
+| none | none / `evict_first` / `evict_last` | ok |
+| `.ca` | none | ok |
+| `.ca` | `evict_first` / `evict_last` | **PTXAS error** |
+| `.cg` | none | ok |
+| `.cg` | `evict_first` / `evict_last` | **PTXAS error** |
+| `.cs` | anything | **Triton CompilationError** |
+
+`ptxas` says *"Modifier '.evict_first' cannot be combined with modifier '.cg'"*. Use one or the other,
+never both, and do not use `.cs` at all in this version.
+
+## The launch knobs
+
+```python
+kernel[grid](args..., BLOCK=128, num_warps=8, num_stages=4)
+```
+- **`num_stages`** — depth of the software pipeline in a `for` loop over K. This is where `cp.async`
+  double buffering comes from; 3-5 is typical. Too many and you run out of shared memory.
+- **`num_warps`** — 4 or 8 for most kernels. 8 for big `tl.dot` tiles.
+- Autotune over them and **cache the winner** per shape class:
+
+```python
+@triton.autotune(
+    configs=[triton.Config({'BM':128,'BN':128,'BK':64}, num_warps=8, num_stages=4),
+             triton.Config({'BM':64, 'BN':128,'BK':64}, num_warps=4, num_stages=5)],
+    key=['M','N','K'])          # re-tunes when these change
+@triton.jit
+def kernel(...): ...
+```
+
+## Idioms
+
+**Masked load/store** — always, unless the shape is guaranteed divisible:
+```python
+off = tl.program_id(0) * BLOCK + tl.arange(0, BLOCK)
+m = off < N
+x = tl.load(X + off, mask=m, other=0.0)
+```
+`other=0.0` matters for reductions: the identity must not perturb the result (use `-inf` for a max).
+
+**Block pointers** — let Triton reason about contiguity instead of raw arithmetic:
+```python
+p = tl.make_block_ptr(base=A, shape=(M, K), strides=(K, 1), offsets=(pid*BM, 0),
+                      block_shape=(BM, BK), order=(1, 0))
+a = tl.load(p, boundary_check=(0, 1))
+p = tl.advance(p, (0, BK))
+```
+
+**TMA (Hopper)** — `make_tensor_descriptor` / `load_tensor_descriptor` / `store_tensor_descriptor` are
+present in 3.6. This is how you get hardware descriptor copies without dropping to CUDA.
+
+**Online softmax** — the running-max reformulation, in Triton:
+```python
+m_new = tl.maximum(m, tl.max(s, 1))
+alpha = tl.exp2((m - m_new) * 1.4426950408889634)
+acc = acc * alpha[:, None] + tl.dot(p, v)
+```
+Use `exp2` rather than `exp`; it maps to `ex2.approx.f32`, one instruction.
+
+**`tl.dot_scaled`** — block-scaled MXFP4/MXFP8 matmul without unpacking scales by hand.
+
+**Compile-time specialisation** — mark everything you can `tl.constexpr`, and help the compiler:
+```python
+tl.assume(stride_am > 0)
+tl.multiple_of(off, 16)
+tl.max_contiguous(off, BLOCK)
+```
+
+## When Triton is the wrong tool
+
+Triton chooses layouts and schedules for you. That is why it is fast to write and why it caps out. Drop
+to CUDA/CuTe when you need:
+
+- an exact MMA fragment layout, or `wgmma` with a specific descriptor
+- warp specialisation with `setmaxnreg` register reallocation
+- a persistent kernel with a grid-wide barrier and precise co-residency control
+- TMA choreography more intricate than descriptor load/store
+
+See `toolchain.md` for the decision table.
+
+## Reading what Triton generated
+
+```bash
+TRITON_KERNEL_DUMP=1 TRITON_DUMP_DIR=/tmp/d TRITON_ALWAYS_COMPILE=1 python3 k.py
+# then: /tmp/d/*/k.ttgir  (layouts Triton chose)   k.ptx  (what it emitted)   k.cubin
+```
+`tools/dump_ir.sh triton <cmd>` does this and points you at the artifacts. Read the **`.ttgir`** to see
+the layouts — that is where Triton's decisions are visible, and where you learn whether it picked the
+swizzle you assumed.

agent/tools/check_toolchain.py

@@ -0,0 +1,180 @@
+"""What does THIS machine actually support? Re-derives the tables in ref/ by compiling.
+
+    python3 check_toolchain.py [sm_90a]
+
+The reference docs were verified on sm_90a / CUDA 12.8. On a different GPU or toolkit some rows change
+-- tcgen05 appears on Blackwell, wgmma disappears below Hopper. Run this instead of trusting the tables.
+"""
+import json, os, subprocess, sys, tempfile
+
+ARCH = sys.argv[1] if len(sys.argv) > 1 else None
+
+
+def _arch():
+    if ARCH:
+        return ARCH
+    try:
+        import torch
+        cc = torch.cuda.get_device_capability(0)
+        a = f"sm_{cc[0]}{cc[1]}"
+        return a + "a" if cc[0] >= 9 else a       # the 'a' target enables wgmma/TMA/setmaxnreg
+    except Exception:
+        return "sm_90a"
+
+
+PTX = [
+    ("ld.global.nc",        r'asm volatile("ld.global.nc.f32 %0, [%1];" : "=f"(f) : "l"(pf));', ""),
+    ("ld.global.L2::128B",  r'asm volatile("ld.global.L2::128B.f32 %0, [%1];" : "=f"(f) : "l"(pf));', ""),
+    ("ld.global.v4.f32",    r'asm volatile("ld.global.v4.f32 {%0,%1,%2,%3}, [%4];" : "=f"(v0),"=f"(v1),"=f"(v2),"=f"(v3) : "l"(pf));', "float v0,v1,v2,v3;"),
+    ("cp.async.cg",         r'asm volatile("cp.async.cg.shared.global [%0], [%1], 16;" :: "r"(smem), "l"(pf));', ""),
+    ("cp.async.bulk.tensor (TMA)", r'asm volatile("cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%0], [%1, {%2, %3}], [%4];" :: "r"(smem), "l"(pf), "r"(x), "r"(y), "r"(bar));', ""),
+    ("mbarrier.arrive.expect_tx", r'asm volatile("mbarrier.arrive.expect_tx.shared::cta.b64 %0, [%1], %2;" : "=l"(l) : "r"(smem), "r"(x));', ""),
+    ("fence.proxy.async",   r'asm volatile("fence.proxy.async.shared::cta;");', ""),
+    ("barrier.cluster",     r'asm volatile("barrier.cluster.arrive;"); asm volatile("barrier.cluster.wait;");', ""),
+    ("mma.sync m16n8k16 bf16", r'asm volatile("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%0,%1,%2,%3};" : "+f"(v0),"+f"(v1),"+f"(v2),"+f"(v3) : "r"(a0),"r"(a1),"r"(a2),"r"(a3),"r"(b0),"r"(b1));', "float v0,v1,v2,v3; unsigned a0=0,a1=0,a2=0,a3=0,b0=0,b1=0;"),
+    ("mma.sync m16n8k32 fp8", r'asm volatile("mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%0,%1,%2,%3};" : "+f"(v0),"+f"(v1),"+f"(v2),"+f"(v3) : "r"(a0),"r"(a1),"r"(a2),"r"(a3),"r"(b0),"r"(b1));', "float v0,v1,v2,v3; unsigned a0=0,a1=0,a2=0,a3=0,b0=0,b1=0;"),
+    ("wgmma.fence/commit/wait", r'asm volatile("wgmma.fence.sync.aligned;"); asm volatile("wgmma.commit_group.sync.aligned;"); asm volatile("wgmma.wait_group.sync.aligned 0;");', ""),
+    ("ldmatrix .x4",        r'asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0,%1,%2,%3}, [%4];" : "=r"(a0),"=r"(a1),"=r"(a2),"=r"(a3) : "r"(smem));', "unsigned a0,a1,a2,a3;"),
+    ("stmatrix .x4",        r'asm volatile("stmatrix.sync.aligned.m8n8.x4.shared.b16 [%0], {%1,%2,%3,%4};" :: "r"(smem),"r"(a0),"r"(a1),"r"(a2),"r"(a3));', "unsigned a0=0,a1=0,a2=0,a3=0;"),
+    ("redux.sync.add",      r'asm volatile("redux.sync.add.u32 %0, %1, -1;" : "=r"(x) : "r"(y));', ""),
+    ("elect.sync",          r'asm volatile("{.reg .pred p; .reg .b32 r; elect.sync r|p, -1; }");', ""),
+    ("setmaxnreg",          r'asm volatile("setmaxnreg.inc.sync.aligned.u32 232;");', ""),
+    ("griddepcontrol",      r'asm volatile("griddepcontrol.wait;");', ""),
+    ("cvt e4m3x2",          r'asm volatile("cvt.rn.satfinite.e4m3x2.f32 %0, %1, %2;" : "=h"(h) : "f"(f), "f"(f));', ""),
+    ("ex2.approx.f32",      r'asm volatile("ex2.approx.f32 %0, %1;" : "=f"(f) : "f"(f));', ""),
+    ("red.global.add.f32",  r'asm volatile("red.global.add.f32 [%0], %1;" :: "l"(pf), "f"(f));', ""),
+    ("tcgen05 (Blackwell)", r'asm volatile("tcgen05.fence::before_thread_sync;");', ""),
+]
+
+TPL = """#include <cuda_fp16.h>
+__global__ void k(float* pf, unsigned* pu) {{
+  float f = 0.f; unsigned x = 0, y = 0, smem = 0, bar = 0; unsigned short h = 0;
+  unsigned long long l = 0;
+  {decls}
+  {body}
+  if (f == 1.f) pf[0] = f; pu[0] = x + h;
+}}
+"""
+
+
+def compile_ok(src, arch, extra=()):
+    with tempfile.NamedTemporaryFile("w", suffix=".cu", delete=False) as fh:
+        fh.write(src); p = fh.name
+    try:
+        r = subprocess.run(["nvcc", f"-arch={arch}", "-std=c++17", *extra, "-cubin", "-o", os.devnull, p],
+                           capture_output=True, text=True)
+        return r.returncode == 0
+    finally:
+        os.unlink(p)
+
+
+def wgmma_acc(arch):
+    """wgmma.m64nNk16.f32 needs N/2 accumulator registers per thread -- confirm on this target."""
+    out = {}
+    for N in (8, 16, 64, 128, 256):
+        n = N // 2
+        regs = ",".join(f"%{i}" for i in range(n))
+        outs = ",".join(f'"+f"(d[{i}])' for i in range(n))
+        src = f"""__global__ void k(float* o) {{
+  unsigned long long da=0, db=0; float d[{n}];
+  #pragma unroll
+  for (int i=0;i<{n};++i) d[i]=0.f;
+  asm volatile("wgmma.fence.sync.aligned;");
+  asm volatile("wgmma.mma_async.sync.aligned.m64n{N}k16.f32.bf16.bf16 {{{regs}}}, %{n}, %{n+1}, 1,1,1,0,0;"
+      : {outs} : "l"(da), "l"(db));
+  asm volatile("wgmma.commit_group.sync.aligned;");
+  for (int i=0;i<{n};++i) o[i]=d[i];
+}}"""
+        out[f"m64n{N}k16"] = (n, compile_ok(src, arch))
+    return out
+
+
+def triton_report():
+    try:
+        import torch, triton, triton.language as tl
+    except Exception as e:
+        return {"error": f"{type(e).__name__}: {e}"}
+    names = ["dot", "dot_scaled", "make_block_ptr", "make_tensor_descriptor",
+             "load_tensor_descriptor", "store_tensor_descriptor", "associative_scan",
+             "inline_asm_elementwise", "assume", "range", "sort", "histogram", "gather"]
+    rep = {"version": triton.__version__,
+           "present": [n for n in names if hasattr(tl, n)],
+           "absent": [n for n in names if not hasattr(tl, n)]}
+    # the cache_modifier x eviction_policy combination trap
+    import itertools
+    @triton.jit
+    def _k(X, Y, N, BLOCK: tl.constexpr, CM: tl.constexpr, EP: tl.constexpr):
+        o = tl.program_id(0) * BLOCK + tl.arange(0, BLOCK)
+        m = o < N
+        tl.store(Y + o, tl.load(X + o, mask=m, other=0.0, cache_modifier=CM, eviction_policy=EP), mask=m)
+    x = torch.randn(4096, device="cuda"); y = torch.empty_like(x)
+    combos = {}
+    # a rejected combination makes Triton dump the whole failing PTX to the console; the point here is
+    # the verdict, not the dump, so silence both fds around the probe.
+    import contextlib, io
+    for cm, ep in itertools.product(["", ".ca", ".cg", ".cs"], ["", "evict_first", "evict_last"]):
+        buf = io.StringIO()
+        devnull = os.open(os.devnull, os.O_WRONLY)
+        saved = os.dup(1), os.dup(2)
+        try:
+            # flush FIRST: piped stdout is block-buffered, and anything still pending would other-
+            # wise be flushed into /dev/null once fd 1 is redirected -- silently eating the report.
+            sys.stdout.flush(); sys.stderr.flush()
+            os.dup2(devnull, 1); os.dup2(devnull, 2)
+            with contextlib.redirect_stdout(buf), contextlib.redirect_stderr(buf):
+                try:
+                    _k[(4,)](x, y, x.numel(), BLOCK=1024, CM=cm, EP=ep); torch.cuda.synchronize()
+                    v = "ok"
+                except Exception as e:
+                    v = "PTXAS" if "ptxas" in str(e).lower() else type(e).__name__
+        finally:
+            sys.stdout.flush(); sys.stderr.flush()
+            os.dup2(saved[0], 1); os.dup2(saved[1], 2)
+            os.close(devnull); os.close(saved[0]); os.close(saved[1])
+        combos[f"{cm or 'none'}|{ep or 'none'}"] = v
+    rep["load_modifier_combos"] = combos
+    return rep
+
+
+def main():
+    arch = _arch()
+    nvcc = subprocess.run(["nvcc", "--version"], capture_output=True, text=True).stdout.strip().splitlines()
+    print(f"target {arch}   {nvcc[-1] if nvcc else 'nvcc not found'}\n")
+
+    print("PTX instructions")
+    res = {}
+    for label, body, decls in PTX:
+        ok = compile_ok(TPL.format(body=body, decls=decls), arch)
+        res[label] = ok
+        print(f"  {'ok  ' if ok else 'NO  '} {label}")
+
+    print("\nwgmma accumulator registers per thread (N/2 expected)")
+    for shape, (n, ok) in wgmma_acc(arch).items():
+        print(f"  {'ok  ' if ok else 'NO  '} {shape:12s} {n} regs")
+
+    print("\nCuTe / CUTLASS")
+    for inc in ("/opt/pytorch/third_party/cutlass/include", "/usr/local/cutlass/include"):
+        if os.path.isdir(inc + "/cute"):
+            ok = compile_ok('#include <cute/tensor.hpp>\n__global__ void k(){}', arch,
+                            (f"-I{inc}", "--expt-relaxed-constexpr"))
+            print(f"  {'ok  ' if ok else 'NO  '} headers at {inc}")
+            break
+    else:
+        print("  --  no cute headers found")
+
+    print("\nTriton")
+    t = triton_report()
+    if "error" in t:
+        print("  " + t["error"])
+    else:
+        print(f"  version {t['version']}")
+        print(f"  present: {', '.join(t['present'])}")
+        if t["absent"]:
+            print(f"  absent : {', '.join(t['absent'])}")
+        bad = [k for k, v in t["load_modifier_combos"].items() if v != "ok"]
+        print(f"  tl.load cache_modifier|eviction_policy combos that FAIL: {', '.join(bad) or 'none'}")
+    print("\n(ref/*.md was verified on sm_90a / CUDA 12.8; anything above that disagrees wins.)")
+
+
+if __name__ == "__main__":
+    main()