# NVIDIA official documentation — a working guide for agents The other files in `ref/` are verified summaries of what *works*. This file is about the **authorities**: what each official document contains, which chapter answers which question, and how to consult them with no internet. Section numbers below were read out of the **CUDA 12.8** documents, the version in the task containers. --- ## 1. Getting them offline Task containers have network at **image build time** and none at run time. So fetch during the build: ```dockerfile RUN bash fetch_nvidia_docs.sh /opt/nvidia-docs 12.8.0 ``` or by hand: ```bash tools/fetch_nvidia_docs.sh /opt/nvidia-docs # auto-matches your CUDA version KDOCS=/opt/nvidia-docs tools/search_docs.sh "mbarrier.arrive.expect_tx" ``` The fetcher writes `.html` and **`.txt`** per document (~11 MB total). The `.txt` is the one that matters: a 700-page reference is only usable offline if you can `grep` it. Code examples keep their indentation, so a worked TMA example reads correctly. **PDFs are deliberately not fetched.** They cannot be grepped, are read in 20-page slices, and cost ~30 MB for no capability you do not already have. **If you have no fetched corpus**, you are not stuck — `ref/ptx.md`, `ref/cuda-cpp.md`, `ref/triton.md` and `ref/cute-cutlass.md` cover the working set, `tools/check_toolchain.py` tells you what compiles, and `$CUDA_HOME/include` has the headers. ### Licence — why the documents are not in this repo > © NVIDIA Corporation. All rights reserved. CUDA EULA: NVIDIA's documentation is copyrighted and **not redistributable**. The EULA distributes only what its **Attachment A** enumerates — runtime libraries such as `libcudart.so` — and documentation is not in that list. §1.2.5 separately forbids using the SDK in a way that subjects it to a licence requiring it be "redistributable at no charge". You fetch your own copy under NVIDIA's terms; do not re-publish it. ### Match the version to your toolkit `docs.nvidia.com/cuda/` always serves the **newest** CUDA. Archives live at `docs.nvidia.com/cuda/archive//`. | toolkit | PTX ISA | |---|---| | CUDA 12.8 (KBench containers) | **8.7** | | current live docs | 9.3 | Reading 9.3 while compiling with 12.8 is how you reach for an instruction `ptxas` rejects with *"not supported on target"*. --- ## 2. CUDA C++ Programming Guide — the semantics authority 22 chapters. The reference for *what a construct means*. Four chapters carry almost everything a kernel author needs. **§2 Programming Model** — thread/block/cluster/grid hierarchy, memory spaces, the fact that blocks are scheduled in **no guaranteed order**. Read the cluster part before writing anything Hopper-specific. **§5 Performance Guidelines** — the official statement of the three levers: maximize utilization, maximize memory throughput, maximize instruction throughput. Where coalescing rules are stated normatively. **§7 C++ Language Extensions** — the chapter you will actually live in. 43 sections; the ones that matter: | § | topic | why you care | |---|---|---| | 7.5 | Memory Fence Functions | `__threadfence*`, and what ordering each actually guarantees | | 7.6 | Synchronization Functions | `__syncthreads`, `__syncwarp`, and the variants with predicates | | 7.10–7.12 | Read-only / cache-hint load and store | `__ldg`, `__ldcs`, `__ldlu`, `__stcs` — the C++ face of the PTX cache modifiers | | 7.14 | Atomic Functions | scopes (`_block`, `_system`), which types have native atomics | | 7.19–7.22 | Warp vote / match / reduce / shuffle | `__ballot_sync`, `__reduce_add_sync`, `__shfl_xor_sync` | | 7.24 | Warp Matrix Functions | the `wmma` fragment API | | 7.26 | Asynchronous Barrier | `cuda::barrier`, the C++ face of `mbarrier` | | 7.27–7.28 | Asynchronous Data Copies (+ `cuda::pipeline`) | `memcpy_async`, the pipeline object, and how `cp.async` groups commit | | 7.29–7.30 | TMA transfers, encoding a tensor map | the worked TMA example — read this before writing your own descriptor code | | 7.38–7.39 | Launch Bounds, Max Registers per Thread | `__launch_bounds__` and how it caps registers | | 7.40 | `#pragma unroll` | | **§16 Compute Capabilities** — the per-architecture tables: registers per SM, shared memory per block, max blocks per SM, warp scheduler counts. When you need a hard architectural number, this is the source — but prefer querying the device (see below), which cannot go stale. Also: §8 Cooperative Groups (tiles, `grid_group::sync` and its co-residency requirement), §19 Unified Memory, §18 Environment Variables. --- ## 3. PTX ISA — the instruction authority 14 chapters. Consult it for *exact syntax, every modifier, and which `.target` an instruction needs*. **§9.7 Instruction Set** is the bulk, organized by family: | § | family | contains | |---|---|---| | 9.7.3–9.7.5 | Floating-point, half, mixed precision | `fma`, `ex2.approx`, `rcp.approx`, `cvt` including the fp8 packing forms | | 9.7.8 | Logic and shift | | | 9.7.9 | **Data Movement and Conversion** | `ld`/`st` with every cache modifier, `cp.async`, `cp.async.bulk.tensor` (TMA), `ldmatrix`, `stmatrix` | | 9.7.12 | Control flow | | | 9.7.13 | **Parallel Synchronization and Communication** | `bar`, `mbarrier` (init/arrive/expect_tx/try_wait), `fence` including `fence.proxy.async`, `redux`, `vote`, `shfl`, `elect`, cluster barriers, `atom`/`red` | | 9.7.14 | Warp-level MMA | `mma.sync` — every shape and dtype combination | | 9.7.15 | **Warpgroup** | `wgmma.mma_async` and its descriptors — Hopper's top instruction | | 9.7.16 | TensorCore 5th generation | `tcgen05` — **Blackwell only**, will not assemble on sm_90a | **§8 Memory Consistency Model** — the formal ordering rules. Go here when a hand-written barrier is "almost" working: it defines what `.relaxed`/`.acquire`/`.release` and each `.scope` actually promise, and why `fence.proxy.async` is required between a TMA write and a generic read. **§5 State Spaces, Types, Variables** and **§6 Instruction Operands** — how `.shared`/`.global`/`.param` differ and the addressing rules. Relevant when an inline-asm constraint will not bind: shared addresses are 32-bit (`"r"`), global are 64-bit (`"l"`). **§10 Special Registers** — `%laneid`, `%warpid`, `%smid`, `%clock`, `%globaltimer`. --- ## 4. Inline PTX Assembly — the glue Short. Read it once, fully. Operand constraint letters, how `%0` numbering maps to the output-then-input order, `volatile`, the `"memory"` clobber, and why a multi-instruction `asm` block needs `{ }` and `.reg` declarations. Every inline-asm bug you will hit is described here. ## 5. Best Practices Guide — the optimization argument Read **§9 Memory Optimizations** (coalescing, shared memory bank conflicts, the cost of each memory space), **§10 Execution Configuration** (occupancy and *why more is not always better*), **§11 Instruction Optimization**, **§12 Control Flow** (warp divergence). §3 Application Profiling states the profile-first discipline. Ignore the deployment chapters (§13–§18). ## 6. Architecture tuning guides — what changed, per generation Each is short (12–20 KB of text) and worth reading end to end for the architecture you target. The fetcher pulls all four. | guide | target | what it adds | |---|---|---| | Ampere Tuning Guide | sm_80/86 | `cp.async`, async barriers, 3rd-gen tensor cores, the 164 KB shared memory | | **Ada Tuning Guide** | sm_89 | 4th-gen tensor cores with **fp8**, and little else structurally — the programming model stays Ampere-class | | Hopper Tuning Guide | sm_90 | thread block clusters + distributed shared memory, TMA, `wgmma`, transaction barriers, 227 KB shared memory | | **Blackwell Tuning Guide** | sm_100/120 | occupancy, clusters, HBM3, L2 capacity, unified smem/L1, NVLink 5 — **not** `tcgen05` (see below) | **Naming trap:** the Lovelace guide is published as **`ada-tuning-guide`** — there is no `lovelace-tuning-guide` URL, and searching for "Lovelace" on docs.nvidia.com will not find it. **The tuning guides are thinner than you expect.** The Blackwell guide covers occupancy, clusters, HBM3, L2 capacity, unified shared memory/L1 and NVLink — it does **not** document `tcgen05` or tensor memory at all. For the 5th-gen tensor cores go to **PTX ISA §9.7.16**, and specifically §9.7.16.1 for tensor memory: a dedicated on-chip two-dimensional store of *lanes* × *columns*, which on sm_100a is 128 rows × 512 columns of 32-bit cells per CTA, addressed by a packed lane/column index. That structure is why Blackwell's accumulator does not live in registers the way Hopper's `wgmma` accumulator does — and why the register-pressure reasoning that sizes a Hopper tile does not carry over. Read the guide for your target *before* choosing a technique. The structural differences are large and asymmetric: see the verified matrix in `ref/ptx.md` and the ladder in `hardware.md`, but the short version is that `wgmma` is Hopper-only, `tcgen05` is datacenter-Blackwell-only, and Ada has none of the Hopper machinery despite having fp8. ## 7. Nsight Compute Profiling Guide + CLI The Profiling Guide defines **what each metric means** and which section reports it — the authority when you are unsure whether a counter says what you think. The CLI reference covers `--section`, `--metrics`, `--kernel-name regex:`, `--launch-skip/--launch-count`, and `--replay-mode` (use `application` for persistent or grid-synchronizing kernels, which kernel replay breaks). See `profiling.md` for the practical order — nsys before ncu — and `pitfalls.md` for reading counters without chasing a healthy-looking number. --- ## 8. Routing table | question | where | |---|---| | What does this CUDA C++ construct mean? | Programming Guide §7 | | Exact PTX syntax / modifiers / required target | PTX ISA §9.7 | | Is my barrier actually ordered correctly? | PTX ISA §8 | | How do I write inline asm and bind operands? | Inline PTX Assembly | | Why is my access pattern slow? | Best Practices §9 | | Should I raise occupancy? | Best Practices §10, then `pitfalls.md` | | What is new on this architecture? | the matching tuning guide (Ampere / **Ada** for Lovelace / Hopper / **Blackwell**) | | Does this instruction exist on my target? | `tools/check_toolchain.py --matrix`, or the table in `ref/ptx.md` | | What does this ncu metric mean? | Nsight Compute Profiling Guide | | What is my device's SM count / shared memory / registers? | **query the device** — see below | | What is the signature of a runtime call? | **the installed headers** — see below | ## 9. Two things NOT to look up on the web **Device properties — query them.** Any hard number you copy from a table is wrong on the next GPU: ```python p = torch.cuda.get_device_properties(0) p.multi_processor_count, p.shared_memory_per_block_optin, p.regs_per_multiprocessor ``` Measured on the H200 NVL in this environment: 132 SMs, 232,448 B opt-in shared memory per block, 233,472 B per SM, 65,536 registers per SM, 2,048 threads per SM, 60 MB L2. Those are *this* machine's numbers, quoted to show the shape of the answer — not to be pasted into a kernel. **Runtime API signatures — grep the headers.** `$CUDA_HOME/include` is authoritative, always present, and never version-skewed against your compiler. The Runtime API web page is only a table of contents (its content is on generated subpages), which is why the fetcher skips it. ```bash grep -rn "cuTensorMapEncodeTiled" /usr/local/cuda/targets/*/include/ ``` ## 10. Precedence 1. **The compiler.** If `nvcc`/`ptxas` rejects it, it does not exist on your target, whatever any document says. `tools/check_toolchain.py` settles this in seconds. 2. **The device.** For counts and capacities, query it. 3. **The official docs.** For *meaning* — semantics, ordering, modifier effects — NVIDIA is the authority. 4. **`ref/*.md`.** Verified working sets and the traps, but summaries; where they disagree with NVIDIA on semantics, NVIDIA wins.