# Choosing a toolchain

Triton is the default reflex and is often **not** the right answer. Pick deliberately.

| workload | first choice | why |
|---|---|---|
| elementwise / reduction fusion | **Triton** | fast to write, autotunes well, this is its sweet spot |
| standard GEMM shapes | **cuBLAS / CUTLASS** | already at the hardware limit; do not rewrite it |
| GEMM + unusual epilogue or prologue | **CUTLASS / CuTe DSL** | epilogue fusion with full layout control |
| quantised GEMM (fp8/int4/mxfp4/nvfp4) | **CUTLASS / CUDA** | the dequant must fuse into the MMA pipeline; no library does it for you |
| attention variants (masks, sparsity, sinks) | **CUDA or Triton** | no library kernel applies as-is; Triton is viable if the mask is regular |
| persistent kernel / grid-wide sync | **CUDA** | Triton can do it (atomics + spin) but it is awkward and fragile |
| whole-model fusion (megakernel) | **CUDA** | needs instruction scheduling, async weight staging, warp specialization |
| sub-byte packing, bit tricks | **CUDA** | `lop3`, `prmt`, byte permutes have no Triton expression |
| variable-length / ragged batching | **Triton or CUDA** | both fine; Triton's masking is convenient |

## Where Triton specifically loses

- **Fine-grained warp specialization** — producer/consumer warp roles are not directly expressible.
- **TMA multicast, cluster/DSMEM (sm_90+), `tcgen05` (sm_100+)** — either unavailable or awkward.
- **Custom epilogues with awkward layouts** — you get what the compiler decides.
- **Sub-byte dtypes** — 4-bit packing needs bit manipulation Triton does not express well.
- **Register pressure control** — no direct control; spills appear and are hard to fix.
- **Persistent kernels with device-wide barriers** — possible via `tl.atomic_add` + a spin loop, and it
  works, but the grid must stay **co-resident** or the spinning blocks deadlock. Verify block count
  against `multi_processor_count` before relying on it.

## Where Triton wins

Iteration speed, autotuning over `num_warps`/`num_stages`/tiles, automatic masking for ragged shapes,
and readable reduction code. For a bandwidth-bound fusion it will usually reach near-peak with far less
effort than CUDA.

## The pragmatic path

Prototype in Triton to establish correctness and a baseline number, dump its PTX/SASS to see what it
generated, then decide whether hand-written CUDA can beat it. Frequently the Triton version is already
at bandwidth and the answer is to stop; for MMA-heavy work it usually is not.