diff --git "a/collect/lowRISC/lowRISC__ibex_s01_02_issue_linked_prs.jsonl" "b/collect/lowRISC/lowRISC__ibex_s01_02_issue_linked_prs.jsonl"
new file mode 100644--- /dev/null
+++ "b/collect/lowRISC/lowRISC__ibex_s01_02_issue_linked_prs.jsonl"
@@ -0,0 +1,457 @@
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It tracks whether the current\nor previous retired instruction increments the `instret` count. If there\nis a bubble before an `minstret` read, the counter will be updated, but\n`wb_count_q` and therefore `perf_instr_ret_wb_spec_o` will incorrectly\nsuggest speculatively incrementing the counter further. This led to the\n`instret` counter being one instruction ahead every time we read it\nafter a stall cycle.\n\nWe fix this by validating `wb_count_q` and only incrementing\nspeculatively if we actually have to. That is, when we are executing instructions back-to-back and the counter hasn't updated yet."}, {"sha": "a3156a1abd2d5bea183d27f460e9061aca4f9b9e", "parents": ["caf5d182152e83703145bb0147779aa8d6489986"], "message": "[rtl] Fix incrementing `minstret` after setting it\n\nAccording to the Specification Section 6.1 CSR Instructions:\n\nSome CSRs, such as the instructions-retired counter, instret, may be\nmodified as side effects of instruction execution. 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Since the compressed decoder has state\nnow (through the Zcmp extension), this improper handshake led to some of\nthe expanded instructions to get lost.\n\nAt the same time, we also take this signal into account for the enable\nsignal of the pipeline stage to avoid unnecessary switching."}, {"sha": "67432d609ebd67ae7ecc1f9bf5f217bc96cd987b", "parents": ["64e3f79ca8ec7d0c1fb54e0e35416737e925dc66"], "message": "[rtl] Add explanations to the Zcmp state machine"}, {"sha": "8328363a21872bbac0023895c7972b18e70ca208", "parents": ["67432d609ebd67ae7ecc1f9bf5f217bc96cd987b"], "message": "[rtl] Optimize the Zcmp FSM\n\nMerge the two cm.mv* states into a single one. This should still be easy\nto understand and saves us an extra bit in the encoding."}, {"sha": "50634fdc76208fee7aa3dd152041f54d6a5a5f82", "parents": ["8328363a21872bbac0023895c7972b18e70ca208"], "message": "[rtl] Only start the push/pop FSM if the instruction is valid"}, {"sha": "900ea8c01be66fc06b429f57752cdb733aa0f0bf", "parents": ["50634fdc76208fee7aa3dd152041f54d6a5a5f82"], "message": "[rtl] Add assertion to ensure the push/pop FSM only advances if valid"}, {"sha": "c9fb2ceb3652bfc2869dd8b8ca69ca8074e4b540", "parents": ["900ea8c01be66fc06b429f57752cdb733aa0f0bf"], "message": "[rtl] Compute `gets_expanded_o` only if the instruction is valid"}, {"sha": "3074de4865eb55430d7bedfc96abeb2be2874c0b", "parents": ["c9fb2ceb3652bfc2869dd8b8ca69ca8074e4b540"], "message": "[rtl] Make Zcmp state registers resettable"}, {"sha": "c9081f857af3aca70d8804fa957c6385348c490f", "parents": ["3074de4865eb55430d7bedfc96abeb2be2874c0b"], "message": "[formal] Disable the Zc* extensions for formal verification"}], "resolved_issues": [2324]}
+{"org": "lowRISC", "repo": "ibex", "number": 2339, "state": "closed", "title": "Vendor in latest OpenTitan IPs", "body": "Update the `vendor/lowrisc_ip` directory to align Ibex with the latest version of the prims and fusesoc 2.4.3. The current prims were vendored in almost 1.5 years ago.\r\n\r\nThis PR includes the following:\r\n\r\n- [x] Include Ibex patches from OpenTitan\r\n- [x] Vendor-in latest OpenTitan prims\r\n- [x] Align Ibex with the new prims\r\n- [x] Update `fusesoc` to align with OpenTitan's version\r\n- [x] Check whether the `dv/uvm/core_ibex/common/prim` can be removed entirely. Yes, removed.\r\n- [x] Update the formal flow to use the same version of fusesoc\r\n- [x] Verify that the updated Ibex will work in OpenTitan. See: https://github.com/lowRISC/opentitan/pull/28974\r\n\r\nWhile updating Ibex to the latest version of Ibex I came across a few things that we should fix. Most small things I fixed immediately, but there are a few things which require a bit more time and I propose to create separate issues for those later: \r\n- [ ] Replace hardcoded filelists with dynamic fusesoc output (e.g. `dv/uvm/core_ibex/ibex_dv.f`)\r\n- [ ] The `shared` folder with prims for xilinx and simulators could probably be handled by fusesoc directly without duplication of prims.", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/2339", "id": 3059930363, "node_id": "PR_kwDOBfEjEc62YtT7", "html_url": "https://github.com/lowRISC/ibex/pull/2339", "diff_url": "https://github.com/lowRISC/ibex/pull/2339.diff", "patch_url": "https://github.com/lowRISC/ibex/pull/2339.patch", "issue_url": "https://api.github.com/repos/lowRISC/ibex/issues/2339", "created_at": "2025-12-01T16:12:36+00:00", "updated_at": "2025-12-19T15:43:18+00:00", "closed_at": "2025-12-19T15:36:35+00:00", "merged_at": "2025-12-19T15:36:35+00:00", "merge_commit_sha": "246849ed1063828355cae8a22c6f1aa95250c3b6", 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upstream repository\nhttps://github.com/lowRISC/opentitan to revision\n3424e7fb4bc3ac92eb640d6af070055d293bc710\n\n* [dv] Avoid passing default name/parent to uvm_component constructors\n  (Rupert Swarbrick)\n* [prim] Add a prim_pkg to define technology primitive specific\n  parameters (Robert Schilling)\n* [hw,prim_rom,rtl] Move rvalid in prim_rom instead of generating it\n  (Robert Schilling)\n* [hw,prim,rtl] prim_rst_sync might have a technology-dependent\n  implementation for DFT (Robert Schilling)\n* [lint] Waive too long lines on ral_pkg (Robert Schilling)\n* [pwm,dv] fix include path (Michael Gautschi)\n* [utils] Add python script to find potential issues in netlist\n  (Michael Gautschi)\n* [hw/prim] Addition of prim_sdc_example for constraints checking\n  (Michael Gautschi)\n* [hw,prim_sha2,rtl] Add missing includes of prim_assert.h (Robert\n  Schilling)\n* [hw,prim_intr_hw,rtl] Add missing includes of prim_assert.h (Robert\n  Schilling)\n* [alert,fpv] Fix the AlertPingOk_A assertion for async alerts (Rupert\n  Swarbrick)\n* [dv] Add uvm_object_utils call to dv_report_server (Rupert\n  Swarbrick)\n* [dv] Make it possible for a sequence to copy information to children\n  (Rupert Swarbrick)\n* [prim] Add parameter to control saturation behavior of prim_sum_tree\n  (Pirmin Vogel)\n* [dv] Allow a test to add extra sequencers to a virtual sequence\n  (Rupert Swarbrick)\n* [prim,fpv] Make HungHandShake_A and ReqTimeout_A bounded assertions\n  (Rupert Swarbrick)\n* [seeds] Rename dev to testing seed (Robert Schilling)\n* [c++17,hw] Update hw/ to use C++17 on Master (Collin MacDonald)\n* [c++,hw] Update hw/ to use C++17 (Collin MacDonald)\n* [dv] Add an access lock to dv_base_reg (Rupert Swarbrick)\n* [topgen] Add a per-top seed configuration (Robert Schilling)\n* [corefiles] Properly use prim_legacy_pkg and remove virtual chip_env\n  core (Robert Schilling)\n* [prim,fpv] Avoid prim_clock_mux2 using $isunknown in FPV (Rupert\n  Swarbrick)\n* [chip, dv] Added a switch to get different randomization per\n  instance (Kinza Qamar)\n* [prim] remove $clog2 workaroud for Xcelium < 19.10 (Gary Guo)\n* [dv] Downgrade more errors when building vcs simv with newer\n  compilers (Harry Callahan)\n* [alert,fpv] Add missing definitions of SkewCycles in FPV tbs (Rupert\n  Swarbrick)\n* [hw,prim_sha2,lint] Remove wildcard waiver on *reg_top.sv (Robert\n  Schilling)\n* [hw,prim_alert,dv] Add 3 cycles clock skew to the testbench config\n  (Robert Schilling)\n* [membkdr] Provide a tile adapter to access internal rows (Robert\n  Schilling)\n* [hw,ips,rtl] Use SkewCycles in prim_esc_(sender|receiver) (Robert\n  Schilling)\n* [hw,ips,rtl] Expose SkewCycles parameter on all comportable IPs\n  (Robert Schilling)\n* [prim_(alert|esc)_(sender|receiver),rtl] Integrate SkewCycles\n  parameter (Robert Schilling)\n* [hw,prim_diff_decode,rtl] Support for parametrizable skew between\n  diff pair (Robert Schilling)\n* Fixes utils.py for missed .name (Chih-Hsueh \"Josh\" Huang)\n* [prim,doc] Expand prim/README.md to add more context and examples\n  (Harry Callahan)\n* [util,cleanup] Fix typos in misc comments/docs (Elliot Baptist)\n* [dvsim,cleanup] Fix typos in comments/docs (Elliot Baptist)\n* [membkdr_util] Support for custom tile suffix (Robert Schilling)\n* [hw,prim_edge_detector,lint] Remove unused waiver inclusion (Robert\n  Schilling)\n* [util,secded_gen] Support parameterized secded instantiation\n  (Guillermo Maturana)\n* [dv] Fix typo dv_fcov_macros.svh (Elliot Baptist)\n* [dv] Fix common typo in env_cov files (Elliot Baptist)\n* [dv] Fix common typo in scoreboards (Elliot Baptist)\n* [tlul, prim] Fix typos in typos fix (Elliot Baptist)\n* [dvsim,hjson] Remove all dead code 'design_level'\n  references/overrides (Harry Callahan)\n* [doc] Fix links and typos for some DV docs (Martin Velay)\n* [prim,doc] Updated the main documentation for the post primgen world\n  (Hugo McNally)\n* [prim,doc] Edited main page to conform to style guide. (Hugo\n  McNally)\n* [dv] Fix typos in comments/docs (Elliot Baptist)\n* [prim,tlul] Fix typos in comments (Elliot Baptist)\n* [dv] Downgrade error when building vcs simv with newer compiler\n  builds (Harry Callahan)\n* [dv] Allow unsupported OS when running jg for UNR (Harry Callahan)\n* [doc] Replace some https links with relative paths (Elliot Baptist)\n* [doc] Update old docs.opentitan links (Elliot Baptist)\n* [prim, rtl] Deadcode else statement when state_q is IsStd (Kinza\n  Qamar)\n* [hw,prim_flop_no_rstm,rtl] Fixup generic RTL implementation (Robert\n  Schilling)\n* [hw,prim,corefile] Remove dangling prim_flop_no_rst core file\n  (Robert Schilling)\n* [flash] Move assertion from `flash_ctrl` to `prim_flash` (Andreas\n  Kurth)\n* [dv, push_pull_monitor] call super. in run_phase (Antonio Martinez\n  Zambrana)\n* [dv, push_pull_agent_cov] call super. in build_phase (Antonio\n  Martinez Zambrana)\n* [dv, push_pull_agent] call super. in run_phase (Antonio Martinez\n  Zambrana)\n* [dv, dv_base_vseq] Remove uvm_fatal from the body (Antonio Martinez\n  Zambrana)\n* [dv, dv_base_test] call super. in run_phase (Antonio Martinez\n  Zambrana)\n* [dv, dv_base_monitor] call super. in run_phase (Antonio Martinez\n  Zambrana)\n* [dv, dv_base_driver] call super. in run_phase (Antonio Martinez\n  Zambrana)\n* [rv_timer, verissimo] UVM new() function (Kinza Qamar)\n* [dv, dv_utils_pkg] Add full_name to UVM reporting macros (Antonio\n  Martinez Zambrana)\n* [dv, csr_utils_pkg] Add full_name to UVM reporting macros (Antonio\n  Martinez Zambrana)\n* [dv, dv_base_reg] Add full_name to UVM reporting macros (Antonio\n  Martinez Zambrana)\n* [dv] Rewrite verilator_memutil.cc to avoid exceptions (Rupert\n  Swarbrick)\n* [doc] Include image files in doc build (James Wainwright)\n* [bazel] Add `doc_files` groups for mdbook sources (James Wainwright)\n* [prim_*] Leave macros out of prim_generic:all (Hugo McNally)\n* [prim] Rename all files to match virtual cores (Hugo McNally)\n* [prim] Replace primgen with virtual prim cores (Hugo McNally)\n* [otp_macro] Clean up straggling core (Hugo McNally)\n* [dv] Pass \"id\" more cleanly to error messages in dv_utils_pkg\n  (Rupert Swarbrick)\n* [dv] Use `gfn in dv_base_env_cfg::create_ral_by_name (Rupert\n  Swarbrick)\n* [dv] Tidy up id argument for uvm_fatal in dv_base_reg_pkg.sv (Rupert\n  Swarbrick)\n* [dv] Use `gfn in dv_base_mem (Rupert Swarbrick)\n* [dv] Tidy up id argument for uvm_info calls in csr_utils_pkg (Rupert\n  Swarbrick)\n* [prim,fpv] Fix width warnings in prim_fifo_sync_assert_fpv (Rupert\n  Swarbrick)\n* [hw,prim] Include `flop_no_rst` to `:all` core file (Hugo McNally)\n* [ipgen] Fix missing deps for various reg tops (Alexander Williams)\n* [rtl,prim] Add a missing dependency on prim:count (Rupert Swarbrick)\n* [prim,rtl] Add a NeverClears parameter to prim_fifo_sync(_cnt)\n  (Rupert Swarbrick)\n* [prim,rtl] Pass PossibleActions parameter inside prim_fifo_sync_cnt\n  (Rupert Swarbrick)\n* [hw,prim_diff_flop,rtl] No generic instantiation of prim_flop_2sync\n  (Robert Schilling)\n* [hw,prim_subreg,rtl] Assert qe only on SW writes (Robert Schilling)\n* [hw,dv_base_reg_block,dv] Fix Xcelium 24.09 warning of passing a\n  string to an int arg (Robert Schilling)\n* [rtl,sec] Define more precise version of ASSERT_ERROR_TRIGGER_ALERT\n  (Rupert Swarbrick)\n* [prim_lfsr, Xcelium] Function called as a task without 'void()\n  (Kinza Qamar)\n* [dv] Simplify use of dv_base_reg::atomic_en_shadow_wr (Rupert\n  Swarbrick)\n* [dv] Constant-initialise a dynamic array more nicely (Rupert\n  Swarbrick)\n* [dv] Add a GUI debug mode for Riviera (Dariusz Stachanczyk)\n* [racl] Add generic RACL testplan (Robert Schilling)\n* [top,otp_macro] Move prim_otp out of otp_ctrl (Guillermo Maturana)\n* [format,flash_ctrl] Format flash_ctrl core per verible-verilog-\n  format (Guillermo Maturana)\n* [rtl,flash_ctrl] Create top specific package (Guillermo Maturana)\n* [prim,rtl] Avoid using inside in a constant expression (Rupert\n  Swarbrick)\n* [dv] Correct foreach syntax in dv_report_catcher (Rupert Swarbrick)\n* [prim_alert] Permit testing with xcelium (Adrian Lees)\n* [corefiles] Let top_racl_pkg depend on concrete top_pkg (Robert\n  Schilling)\n* [darjeeling] Fix undriven input ports (Adrian Lees)\n* [dv] Fix uvm_component_param_utils call in dv_base_monitor (Rupert\n  Swarbrick)\n* [sw] disable clang-format in all vendor directories (James\n  Wainwright)\n* [hw,prim_diff,rtl] Use _po/_no and _pi/_ni suffix (Robert Schilling)\n* [hw,prim_diff_to_alert,rtl] Fix RTL bugs that were not linted!\n  (Robert Schilling)\n* [hw,sram_ctrl,rtl] Ability to correct single-bit errors and log\n  error (Robert Schilling)\n* [hw,alert2diff,rtl] Add prims to translate between alerters and\n  differential signals (Robert Schilling)\n* [hw,prim_diff_encode,rtl] Add primitive to differentially encode a\n  signal (Robert Schilling)\n* [dvsim] Add -fs option for --fixed-seed (Martin Velay)\n* [dv] Check types properly in DV_EOT_PRINT_TLM_FIFO_CONTENTS (Rupert\n  Swarbrick)\n* [dv] Simplify DV_EOT_PRINT_TLM_FIFO_CONTENTS macro (Rupert\n  Swarbrick)\n* [fusesoc,otp_ctrl] Change otp_ctrl_prim_reg_top core to template\n  (Guillermo Maturana)\n* [dv,sv] Fix simple typos (Guillermo Maturana)\n* [hw,ram,params]  is not synthesizable, drop it... (Robert Schilling)\n* [dv_utils] Fix and improvements (Martin Velay)\n* [tools,ipgen] Improve VLNV renaming (Guillermo Maturana)\n* [dvsim] Fix dvsim makefile for Darjeeling bring up (Adrian Lees)\n* [dv] Remove m_access from dv_base_mem (Rupert Swarbrick)\n* [dv] Reorder dv_base_mem to use out-of-block definitions (Rupert\n  Swarbrick)\n* [prim] Add mubix_logic_test_true_strict function (Martin Velay)\n* [hw,prim_xilinx_ram_1p,rtl] Don't use string, the tools don't like\n  it (Robert Schilling)\n* [prim,dv] Fix a failure mode for ASSERT_FPV_LINEAR_FSM (Rupert\n  Swarbrick)\n* [dv]Minor update in the base sequencer class (Marcelo Carvalho\n  Faleiro de Almeida)\n* [tool,doc] Fix path to uvmdvgen in README file (Rupert Swarbrick)\n* [hw,ac_ranges,rtl] Compute denied range index using PPC (Robert\n  Schilling)\n* [darjeeling] Changes to support Darjeeling bring up (Adrian Lees)\n* [racl] Distribute access address on RACL error (Robert Schilling)\n* [hw,prim_xilinx_ram_1p] Explicitly cast MemInitFile to string\n  (Robert Schilling)\n* Included functions to dv_base_virtual_sequencer (Marcelo Carvalho\n  Faleiro de Almeida)\n* [dv,mem_bkdr_util] Separate out ROM, SRAM and flash-specific\n  behavior (Adrian Lees)\n* [python] Move uvmdvgen out of its own package (James Wainwright)\n* [dvsim] fix bug in busy launcher reschedule strategy (James\n  McCorrie)\n* [prim,rtl] Get rid of a trivial combinatorial variable (Rupert\n  Swarbrick)\n* [prim,rtl] Rewrite a case as if/else to avoid unreachable case\n  (Rupert Swarbrick)\n* [prim] Add flop without reset (Robert Schilling)\n* [python] Apply Ruff auto-fixes (James Wainwright)\n* [python] Remove importlib_resources polyfill (James Wainwright)\n* [python] Resolve bodges for old Python versions (James Wainwright)\n* [racl] Add an error log arbiter primitive (Robert Schilling)\n* [dvsim] more robust local launcher process management (James\n  McCorrie)\n* [dvsim] Lint fixes (James McCorrie)\n* [fusesoc] Move all cores under the hw directory (Alexander Williams)\n* [membkdr] Pass tiling parameters from sram bkdr util down (Robert\n  Schilling)\n* [membkdr] read32 only return 32-bit (Robert Schilling)\n* [dd, prim] Simplyfing condition to ease coverage closure (Antonio\n  Martinez Zambrana)\n* [prim_xilinx,englishbreakfast] Remove ROM dependency (Alexander\n  Williams)\n* [dd, prim_reg_cdc_arb] state signal width reduction (Antonio\n  Martinez Zambrana)\n* [dv,mem_bkdr_util] Memory back door specializations (Adrian Lees)\n* [rtl, prim_reg_cdc_arb] Conditional coverage simplification (Antonio\n  Martinez Zambrana)\n* [hw,prim_subreg_shadow,rtl] Add Mubi Support to prim_subreg_shadow\n  (Robert Schilling)\n* [hw,prim_generic_ram_1r1w,lint] Rename signal in waiver that changed\n  in RTL (Robert Schilling)\n* [prim_ram_1r1w_async_adv,lint] rst_a/b_ni are legal async reset\n  (Robert Schilling)\n* [hmac, rtl] Increase coverage through minor RTL restructure (Andrea\n  Caforio)\n* [membkdr] Add support for bkdr preloading (Robert Schilling)\n* [membkdr] Switch to uint32_t in constructor (Robert Schilling)\n* [membkdr] Add RAM tiling to membkdr utility (Robert Schilling)\n* [hw,otp_ctrl,rtl] Parametrize the DFT config and response port\n  (Robert Schilling)\n* [hmac,dv] Allow reset w/o CSR accesses complete (Martin Velay)\n* [prim,rtl] Remove ~under_rst from the expression for fifo_incr_wptr\n  (Rupert Swarbrick)\n* [hw,otp_ctrl,rtl] Provide a DFT config and response port (Robert\n  Schilling)\n* [bazel,hw] exclude DV files from hw/ip/*/BUILD globs (Gary Guo)\n* [hw] remove unneeded DV dependencies (Gary Guo)\n* [dv,mem_bkdr_util] Move otp specific code to otp_ctrl (Guillermo\n  Maturana)\n* [mem_bkdr_util] Temporarily fix build for an otp_ctrl parameter\n  (Rupert Swarbrick)\n* [rom_ctrl, dv] Conditional coverage hole in tlul_adapter_sram fifos\n  (Kinza Qamar)\n* [ipgen,otp_ctrl] Change otp_ctrl to ipgen (Guillermo Maturana)\n* [flash_ctrl] Uniquify VLNVs and clean up core hierarchy (Alexander\n  Williams)\n* [prim] Add hacky prim_flop dependency to prim_flop_2sync (Alexander\n  Williams)\n* [prim_mubi] Split off constants to prim_mubi_pkg core (Alexander\n  Williams)\n* [dv, base_reg] Adding a prediction flag to field and mask to reg\n  (Antonio Martinez Zambrana)\n* [hmac,dv] Wipe secret assertions (Martin Velay)\n* [prim_fifo_sync,rtl] Specialize for Depth == 1 (Rupert Swarbrick)\n* [prim_generic] Depened on the tech ram_pkg within the tech lib\n  (Robert Schilling)\n* [hw,prim_ram_1r1w,rtl] Fix DFT response port (Robert Schilling)\n* [hw,prim_generic_ram_1r1w,rtl] Add reset inputs (Robert Schilling)\n* [hw,prim_ram,rtl] Make default assignment and not reference struct\n  (Robert Schilling)\n* [hw,prim_rom_pkg,rtl] Move prim_rom_pkg to tech-lib (Robert\n  Schilling)\n* [prim_ram_1p] Ram tiling for sram_ctrl and prim_ram_1p (Robert\n  Schilling)\n* [hw,prim_ram_1p,rtl] Add reset input to prim_ram_1p (Robert\n  Schilling)\n* [hw,prim,ram_2p] Add DFT response channel (Robert Schilling)\n* [hw,prim,ram_1p] Add DFT response channel (Robert Schilling)\n* [prim/doc] Add pointer to hardened Keccak implementation in\n  prim_keccak (Pirmin Vogel)\n* [hw,prim_rom,rtl] Add reset input to prim_rom (Robert Schilling)\n* [hmac, rtl] Do not skip padding after a hash stop command (Andrea\n  Caforio)\n* [prim,earlgrey,fpga] Add specialized ram_1p prim (Alexander\n  Williams)\n* [dv] Be more careful not to leave orphan processes in clk_rst_if\n  (Rupert Swarbrick)\n* [hmac,rtl] Fix hang after stop lowRISC/opentitan#24767 (Martin\n  Velay)\n* [dv] Fix DVSim after GUI_DEBUG addition (Martin Velay)\n* [prim,rtl] Rewrite a loop to avoid needing signed values (Rupert\n  Swarbrick)\n* [prim,lint] Remove dead waivers for prim_fifo_*sync.sv (Rupert\n  Swarbrick)\n* [prim,rtl] Remove dead code in prim_fifo_async_sram_adapter (Rupert\n  Swarbrick)\n* [prim,lint] Remove waiver for prim_subreg.sv (Rupert Swarbrick)\n* [prim,lint] Remove waiver for prim_sram_arbiter.sv (Rupert\n  Swarbrick)\n* [prim,rtl] Rephrase a term in prim_reg_cdc.sv (Rupert Swarbrick)\n* [prim,fpv] Connect and check err_o for prim_fifo_sync (Rupert\n  Swarbrick)\n* [prim,fpv] Connect and check full_o (Rupert Swarbrick)\n* [prim_fifo_sync,rtl] Fix full_o behaviour when Depth == 0 (Rupert\n  Swarbrick)\n* [hw,prim_ram_1r1w,lint] Add lint rule for input not read (Robert\n  Schilling)\n* [hw,prim_ram_1r1w,lint] rst_a_ni is only used in assertions in some\n  configs (Robert Schilling)\n* [prim] Exclude mem init dynamic `if` from synthesis (Elliot Baptist)\n* [dv] Exclude some secded generation modules from coverage (Rupert\n  Swarbrick)\n* [dv] Add a GUI debug mode (Martin Velay)\n* [dvsim] Improve error handling on slurm launcher (Robert Schilling)\n* [dvsim] Be a bit clearer about how modes get merged (Rupert\n  Swarbrick)\n* [dvsim] Avoid comparing types in FlowCfg.py (Rupert Swarbrick)\n* [dvsim] Avoid comparing types in Deploy.py (Rupert Swarbrick)\n* [prim_pulse_sync] Add missing `include \"prim_assert.sv\"` (Andreas\n  Kurth)\n* [dv, dvsim] Add job queue/lic wait timeout in addition to run\n  timeout (Venkat Krishnan)\n* [dvsim] Remove unneeded check since exports are always defined\n  (Robert Schilling)\n* [dvsim] Add slurm launcher (Robert Schilling)\n* [dv] Teach dv_base_reg to allow mubi regwen fields (Rupert\n  Swarbrick)\n* [dv, dvsim] Update nc flag for interactive sim (Venkat Krishnan)\n* [dv, dvsim] Use file descriptors to share logfile across processes\n  (Venkat Krishnan)\n* [dv, dvsim] remove support for post_cmd in nc run call (Venkat\n  Krishnan)\n* [dv, dvsim] : Override NC node's TMPDIR with custom value (Venkat\n  Krishnan)\n* [dv, dvsim] stability fixes for the nc job scheduler (Venkat\n  Krishnan)\n* [prim,fpga] Add FPGA-specific primitive implementations for\n  prim_xnor2 (Pirmin Vogel)\n* [prim] Remove prim_clock_gp_mux2 (Rupert Swarbrick)\n* [dv,vcs] Tidy up the comments where we disable coverage in a prim\n  (Rupert Swarbrick)\n* [csr_utils_pkg,dv] Avoid bug on reset in csr_spinwait (Rupert\n  Swarbrick)\n* [fpv,prim] Fix AlertPingOk_A in prim_alert_rxtx_async_assert_fpv\n  (Rupert Swarbrick)\n* [prim,fpv] Fix AlertCheck0_A in prim_alert_rxtx_async_assert_fpv\n  (Rupert Swarbrick)\n* [fpv,prim] Factor out FSM exprs in prim_alert_rxtx_async_assert_fpv\n  (Rupert Swarbrick)\n* [prim,fpv] Increase timeouts in prim_alert_rxtx_async_assert_fpv\n  (Rupert Swarbrick)\n* [prim,fpv] Fix bind statements in prim_alert_rxtx_async*_bind_fpv\n  (Rupert Swarbrick)\n* fix job status poll logic when timeout is not specified (venkatk-ot)\n* Added support for another job scheduler. (Venkat Krishnan)\n* [ci, sival] Make testplan validator need bazel if si_stage != NA\n  (Alex Jones)\n* [ci, sival] Create a validator for the testplans (Douglas Reis)\n* [python] remove pkg_resources usage (Gary Guo)\n* [prim,fpv] Remove initialisation before a test (Rupert Swarbrick)\n* [ascon, prim_ascon_duplex] add/connect error register (Michael\n  Tempelmeier)\n* [ascon, prim_ascon_duplex] change no_ad and no_msg to mubi4 (Michael\n  Tempelmeier)\n* [ascon, prim_ascon_duplex] add FSM State Output and connect to debug\n  reg. (Michael Tempelmeier)\n* [dv] Avoid so many copies of count in csr_spinwait (Rupert\n  Swarbrick)\n* [dv] Add some comments to csr_spinwait (Rupert Swarbrick)\n* [dv] Remove pre_reset_dly_clks argument from clk_rst_if.apply_reset\n  (Rupert Swarbrick)\n* [prim,fpv] Fix the bind statement in prim_alert_rxtx_fatal_bind_fpv\n  (Rupert Swarbrick)\n* [prim,fpv] Fix hierarchical names in prim_alert_rxtx_assert_fpv\n  (Rupert Swarbrick)\n* [prim,fpv] Fix the bind statement in prim_alert_rxtx_bind_fpv\n  (Rupert Swarbrick)\n* [prim,fpv] Get rid of ASSERT_KNOWN in an FPV context (Rupert\n  Swarbrick)\n* [prim,fpv] Fix reset check in prim_esc_rxtx_assert_fpv (Rupert\n  Swarbrick)\n* [prim,fpv] Fix hierarchical names in prim_esc_rxtx_assert_fpv\n  (Rupert Swarbrick)\n* [prim,fpv] Fix binding in prim_esc_rxtx_fpv (Rupert Swarbrick)\n* [prim,fpv] Tweak DataKnown_A assertion in prim_fifo_sync.sv (Rupert\n  Swarbrick)\n* [prim,fpv] Strengthen CntErrReported_A assertion in prim_count.sv\n  (Rupert Swarbrick)\n* [dv,vcs] Tidy up how coverage is collected in assertion modules\n  (Rupert Swarbrick)\n* [top_earlgrey] Reduce number of PRINCE half rounds for main SRAM\n  (Pirmin Vogel)\n* [mem_bkdr_util] Support varying No. of PRINCE half rounds for\n  scrambling (Pirmin Vogel)\n* [ascon, prim_ascon_duplex] fix MuBi coding style (Michael\n  Tempelmeier)\n* [prim_ascon_duplex] fix asynchronous reset (Michael Tempelmeier)\n* [ascon, prim_ascon] improv .core-files naming (Michael Tempelmeier)\n* [ascon] integrate prim_ascon_duplex into comportable ip (Michael\n  Tempelmeier)\n* [prim,fpv] Fix delays in assertions of prim_fifo_async_sram_adapter\n  (Rupert Swarbrick)\n* [prim,fpv] Explicitly delay wready_o assertions by a cycle (Rupert\n  Swarbrick)\n* [dvsim] Speed up gsutil operations. (Miguel Osorio)\n* [prim_ascon_duplex] change to mux and ready/valid implementation\n  (Michael Tempelmeier)\n* [prim_ascon_duplex] add TB for prim_ascon_duplex (Michael\n  Tempelmeier)\n* [prim_ascon_duplex] add ascon duplex prim (Michael Tempelmeier)\n* [bazel] Update rules_python to upstream 0.34.0 (James Wainwright)\n* [tools,vcs] Fix compilation warnings (Guillermo Maturana)\n* [dv] Allow assertions from ASSERT_FPV_LINEAR_FSM to complete (Rupert\n  Swarbrick)\n* [prim_ascon] add testbench for ascon round function (Michael\n  Tempelmeier)\n* [prim_ascon_sbox] add verilator-rule to prevent false UNOPTFLAT\n  warnings (Michael Tempelmeier)\n* [prim_ascon] add unmasked ascon sbox and round function (Michael\n  Tempelmeier)\n* [prim_ascon] add dpi model (Michael Tempelmeier)\n* Add vendor code from ascon/ascon-c@46f35c0 (Michael Tempelmeier)\n* [dv] Manually apply specialisation for mubi32_cov (Rupert Swarbrick)\n* [top_earlgrey,cdc] Transition to MeridianCDC (Andreas Kurth)\n* Revert \"[dv] Add a quick exit in csr_rd_sub when in reset\" (Rupert\n  Swarbrick)\n* [util] Get rid of \"type\" field in Modes (Rupert Swarbrick)\n* [prim_esc_receiver] Register esc_req_o to avoid potential CDC issues\n  (Pirmin Vogel)\n* [prim_count] Register err_o to avoid potential CDC issues downstream\n  (Pirmin Vogel)\n* [dv] Add a quick exit in csr_rd_sub when in reset (Rupert Swarbrick)\n* [dv] Tidy up how reset lengths get calculated (Rupert Swarbrick)\n* [dv] Add writes_ignore_errors flag to reggen / dv_base_reg (Rupert\n  Swarbrick)\n* [dv, csr_spinwait] debug printout (Antonio Martinez Zambrana)\n* [dv] update the ROM self hash GLS test (Tim Trippel)\n* [pinmux] Remove scan clocks from wakeup detector inputs (Alexander\n  Williams)\n* [dvsim] Correctly handle fixed-seed=0 (Rupert Swarbrick)\n* [dv,chip_level] Fix chip_sw_lc_ctrl_program_error (Guillermo\n  Maturana)\n* [dv] Improve debug prints from register aliasing sequence (Rupert\n  Swarbrick)\n* [prim/lint] Move AscentLint waiver rules for prim_gf_mult into own\n  file (Pirmin Vogel)\n* [top, rom_ctrl] Add missing TEST port for ROM macro (Pirmin Vogel)\n* [prim] Waive AscentLint errors inside prim_generic_pad_wrapper\n  (Pirmin Vogel)\n* [dvsim] Get rid of unnecessary find_and_merge_modes function (Rupert\n  Swarbrick)\n* [dvsim] Tweak find_and_merge_modes to be simpler to understand\n  (Rupert Swarbrick)\n* [prim] Update AscentLint waiver file for prim_generic_clock_div\n  (Pirmin Vogel)\n* [prim] Update lint waiver rule for prim_lfsr.sv (Pirmin Vogel)\n* [lint] Waive USE_BEFORE_DECL AscentLint errors for SV functions\n  (Pirmin Vogel)\n* [prim] Waive SAME_NAME_TYPE AscentLint error (Pirmin Vogel)\n* [dv] Fix info message in csr_seq_lib.sv (Rupert Swarbrick)\n* [dv] Expand documentation comments about gaps in bit_bash_seq\n  (Rupert Swarbrick)\n* [dv] Change a variable name in bash_register task (Rupert Swarbrick)\n* [dv] Add a default to a case statement in the bash_register task\n  (Rupert Swarbrick)\n* [dv] Factor out part of task in csr_bit_bash_seq (Rupert Swarbrick)\n* [dv] Expand documentation comment above bash_kth_bit task (Rupert\n  Swarbrick)\n* [prim] Waive lint warnings and errors in prim_[generic_]_flop_2sync\n  (Pirmin Vogel)\n* [dv] Fix typo in prints in push_pull_monitor (Rupert Swarbrick)\n* [top_earlgrey,prim_ram_*_pkg] Connect memory test port (Andreas\n  Kurth)\n* [prim/rtl] Allow for tech-specific impls of `prim_flop_2sync`\n  (Andreas Kurth)\n* [dv] Fix ROM e2e JTAG tests. (Miguel Osorio)\n* [hmac,rtl/dv] DV synchronization and error handling fixes (Ghada\n  Dessouky)\n* [kmac,prim_sha2/rtl] Fix lint error in `conv_endian32` (Andreas\n  Kurth)\n* [kmac,prim_sha2/rtl] Remove unused `conv_endian64` function (Andreas\n  Kurth)\n* [prim,fpv] Avoid warning message from Jasper with ASSERT_AT_RESET\n  (Rupert Swarbrick)\n\nSigned-off-by: Samuel Riedel <sriedel@lowrisc.org>"}, {"sha": "0cea883e7e089246ca21ad53111d23add1395656", "parents": ["bc70622680a204375b479faecb47f1006647560f"], "message": "[fusesoc] Align fusesoc version with OpenTitan (2.4.3)\n\nThis requires fixing the mapping and paths in core files and updating\n`check_tool_requirements`. It also updates fusesoc in the formal flow,\nwhich has its own toolset."}, {"sha": "cb9ff538c148b2eeccccdf0247404b38f63ac9eb", "parents": ["0cea883e7e089246ca21ad53111d23add1395656"], "message": "[rtl,dv] Align rtl with new prims from OpenTitan\n\nThis commit ports the OpenTitan patches over to Ibex to align it with\nthe version that is currently used in OpenTitan. It also removes\nredundant prims."}, {"sha": "1adcd833114a22b95663f63f9af4c82f382e2cbd", "parents": ["cb9ff538c148b2eeccccdf0247404b38f63ac9eb"], "message": "[rtl] Fix linter warnings"}], "resolved_issues": [24767]}
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Several things had to be fixed:\r\n\r\n- Simulator compatibility: DSim requires that enum values must use enum constants\r\n    - Use `ZERO` enum constant instead of `'0` and `0` for instr enums: [dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv](https://github.com/lowRISC/ibex/pull/2286/files#diff-cdd6748ace94acd8de318154673012ab57d1cc2b087742d0d9f14f22cb1af84e)\r\n    - Add Ibex-specific CSRs (`CPUCTRLSTS`, `SECURESEED`) to `privileged_reg_t` and replace enum constants into `implemented_csr[]`: [vendor/google_riscv-dv/src/riscv_instr_pkg.sv](https://github.com/lowRISC/ibex/pull/2286/files#diff-c06d7c563009dd742c6749fbab5eb261d2957a7c5938534bf787b21766b7921e), [vendor/google_riscv-dv/euvm/riscv/gen/riscv_instr_pkg.d](https://github.com/lowRISC/ibex/pull/2286/files#diff-3bcab4b7587e07f4642e454723299c9273c6302f25154e52ca39477da2a5b3d8), [dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv](https://github.com/lowRISC/ibex/pull/2286/files#diff-aafd82f9e9be85898fe3c5a41c9187ac08ee202c39b01fcd988db2e18f6e2f4d)\r\n- Simulator compatibility: DSim does not appear to respect \"re-exports\"\r\n    - Replace all re-exported `ibex_mem_intf_agent_pkg::ADDR_WIDTH` and  `ibex_mem_intf_agent_pkg::DATA_WIDTH` with `ibex_mem_intf_pkg::ADDR_WIDTH` and  `ibex_mem_intf_pkg::DATA_WIDTH`: [dv/uvm/core_ibex/tests/core_ibex_base_test.sv](https://github.com/lowRISC/ibex/pull/2286/files#diff-622f2e7b478a78c9507e35247fb6b867904ce2449ccbd0a32cb4df1133908616), [dv/uvm/core_ibex/tests/core_ibex_test_lib.sv](https://github.com/lowRISC/ibex/pull/2286/files#diff-682db8ff51859b07b7ba0548d9779d6737c3d15827e3e73d9e7173031f0ef557), [dv/uvm/core_ibex/tests/core_ibex_vseq.sv](https://github.com/lowRISC/ibex/pull/2286/files#diff-1e4da7fbecc115d2c4e299f4cf6714588d2e454097f4f72ff972de2ff1a03e1b)\r\n- Simulator compatibility: Unroll loops for 2D arrays to support DSim in [rtl/ibex_core.sv](https://github.com/lowRISC/ibex/pull/2286/files#diff-7290a764a1649d05221e96494db6c6dc7ec4612c47afaf81d23cafe7f047d8dd)\r\n- Simulator compatibility: Add `#0` to allow clock to properly start in [dv/uvm/core_ibex/tb/core_ibex_tb_top.sv](https://github.com/lowRISC/ibex/pull/2286/files#diff-3aa7d35f40ca9dbb9fbcd1ca9a18cca245e1f8d8690d177e3e887498cf8bc470)\r\n- Script fix: Add co-simulation support for DSim in [dv/uvm/core_ibex/yaml/rtl_simulation.yaml](https://github.com/lowRISC/ibex/pull/2286/files#diff-01ac65450dedc1df3421dee3e0874335b0bb15d6b8db2035aef4b0d77af903cd)\r\n- Script fix: Add DSim case for `reloc_word` in [dv/uvm/core_ibex/scripts/run_instr_gen.py](https://github.com/lowRISC/ibex/compare/master...Silimate:ibex:dsim_fixes?expand=1#diff-5415dd86d435fd7155622795acb1fb1c440b6e2e595c0c1a857b891fdc6d9e65)\r\n- Script fix: Replace `dsim_compile_opts` with `dsim_opts` and apply correct defparams and +defines in [util/ibex_config.py](https://github.com/lowRISC/ibex/compare/master...Silimate:ibex:dsim_fixes?expand=1#diff-0a9f6797b07226a176327f28cfe58b039f1eb20d18e7bdee723ec94668f3be01)\r\n- Misc. fix: PC mismatch should remove 64-bit sign extension when printing ISS PC [dv/cosim/spike_cosim.cc](https://github.com/lowRISC/ibex/pull/2286/files#diff-459556bd92cc560978d1721a1e82718aed51811d323898f9bdb9e7dcb026f098)\r\n\r\nWith these fixes, I was able to get most of the UVM tests running with `SIMULATOR=dsim ITERATIONS=1`:\r\n\r\n```\r\n82.14% PASS 46 PASSED, 10 FAILED\r\n```\r\n\r\nFuture enhancements:\r\n- Fix remaining DSim failures\r\n- Coverage support for DSim\r\n- Fix `METADATA-DIR` make variable issue\r\n- #2299", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/2297", "id": 2672179025, "node_id": "PR_kwDOBfEjEc6fRjdR", "html_url": "https://github.com/lowRISC/ibex/pull/2297", "diff_url": "https://github.com/lowRISC/ibex/pull/2297.diff", "patch_url": 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Because `ibex_top` is the module actually implementing Ibex, it felt logical to put the dependency there instead of the wrapper to make `ibex_top`'s dependency list complete on its own. However, in my current understanding, this dependency actually serves to define the **instantiation mapping**. Because `ibex_top` already declares its source dependencies virtually, hardcoding `prim_generic` there stripped away the ability for wrappers to cleanly set their own primitives' implementation.\r\n\r\nThe original mistake stemmed from our documentation, which instructs users to run linting or generate filelists targeting `ibex_top` directly. Doing so bypasses the standard wrappers, leaving FuseSoC with no idea which implementation of the virtual prims to use, and to choose randomly, which then failed.\r\n\r\nTo fix this cleanly now, this PR:\r\n* Removes the global `prim_generic` dependency from `ibex_top.core` again and moves it back to `ibex_top_tracing.core`.\r\n* Explicitly maps the virtual prims to `prim_generic` **only for the linter and Verilator targets** within `ibex_top`.\r\n\r\nThis restores FPGA builds and ensures the documented linting/filelist workflows still work.", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/2443", "id": 3781619368, "node_id": "PR_kwDOBfEjEc7hZu6o", "html_url": "https://github.com/lowRISC/ibex/pull/2443", "diff_url": "https://github.com/lowRISC/ibex/pull/2443.diff", "patch_url": "https://github.com/lowRISC/ibex/pull/2443.patch", "issue_url": "https://api.github.com/repos/lowRISC/ibex/issues/2443", "created_at": "2026-06-01T14:29:52+00:00", "updated_at": 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This is done to resolve the\nprimitive mappings rather than to fix missing source dependencies. The\ndependencies are all listed as virtual `prim`s in `ibex_top`. Keeping\nthis mapping isolated ensures that other wrappers can cleanly bind\n`ibex_top` to alternative backends, such as `prim_xilinx` for FPGA\ntargets."}, {"sha": "4cd7bfde3bb775930717cdc49e358ee34af63823", "parents": ["1d8e5c8106cf9287d15522a886d5ab729973bbb5"], "message": "[rtl] Explicitly define mapping to `prim_generic` for linter targets\n\nAdding a dependency on a specific implementation (`prim_generic`) of the\nvirtual `prim` core for linter and Verilator targets forces FuseSoC to\nuse the correct instances, thereby allowing us to lint or export\nfilelists of `ibex_top` without a wrapper defining the virtual core's\nimplementation."}], "resolved_issues": [2397]}
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mode\n\nThe RISC-V Debug Specification (current release 1.0.0-rc4) in Section\nA.2 states that the PMP must not disallow accesses to addresses of the\nDebug Module when the hart is in debug mode, regardless of how the PMP\nis configured.  This commit changes the PMP accordingly.\n\nSigned-off-by: Andreas Kurth <adk@lowrisc.org>"}], "resolved_issues": [2233]}
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false, "has_pages": false, "has_discussions": false, "forks_count": 749, "mirror_url": null, "archived": false, "disabled": false, "open_issues_count": 248, "license": {"key": "apache-2.0", "name": "Apache License 2.0", "spdx_id": "Apache-2.0", "url": "https://api.github.com/licenses/apache-2.0", "node_id": "MDc6TGljZW5zZTI="}, "allow_forking": true, "is_template": false, "web_commit_signoff_required": false, "has_pull_requests": true, "pull_request_creation_policy": "all", "topics": ["cpucore", "hardware", "risc-v", "rv32"], "visibility": "public", "forks": 749, "open_issues": 248, "watchers": 1920, "default_branch": "master"}}, "commits": [{"sha": "b30abd4eb2d06238c175ec398c59b71751ce7bb5", "parents": ["54985d21b055967c39d0a77b45ae0d573b55b0f7"], "message": "Revert \"[rtl] Fix counter reset value on FPGA\"\n\nThis reverts commit 54985d21b055967c39d0a77b45ae0d573b55b0f7."}], "resolved_issues": [2226]}
+{"org": "lowRISC", "repo": "ibex", "number": 2270, "state": "closed", "title": "Disable Verilator's IMPERFECTSCH warnings", "body": "Our current version of Verilator issues \"IMPERFECTSCH\" warnings, which sometimes appear spurious. According to the [manual](https://verilator.org/guide/latest/warnings.html#cmdoption-arg-IMPERFECTSCH) this warning is disabled by default, but we explicitly enabled it a while back in https://github.com/lowRISC/ibex/pull/1250 and created some RTL workarounds to avoid it in https://github.com/lowRISC/ibex/pull/2129.\r\n\r\nNow, the same warning has reappeared at the same point due to the changes in https://github.com/lowRISC/ibex/pull/2267. However, this PR does not touch the code that leads to the warning, which is why I propose removing the warning altogether now and updating Verilator in the near future. Alternatively, we could disable it for the specific lines where it appears in https://github.com/lowRISC/ibex/pull/2267 as a hotfix.\r\n\r\nThis PR disables the warning in Verilator and reverts the workarounds introduced in https://github.com/lowRISC/ibex/pull/2129.\r\n\r\nFor reference, this is the warning triggered by https://github.com/lowRISC/ibex/pull/2267:\r\n```sh\r\nINFO: verilator -f lowrisc_ibex_ibex_simple_system_cosim_0.vc --trace --trace-fst --trace-structs --trace-params --trace-max-array 1024 -CFLAGS \"-std=c++14 -Wall -DVL_USER_STOP -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g `pkg-config --cflags riscv-riscv riscv-disasm riscv-fdt`\" -LDFLAGS \"-pthread -lutil -lelf `pkg-config --libs riscv-riscv riscv-disasm riscv-fdt`\" -Wall -Wwarn-IMPERFECTSCH --unroll-count 72\r\n\r\nERROR: %Warning-IMPERFECTSCH: ../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_lockstep.sv:131:45: Imperfect scheduling of variable: 'ibex_simple_system.u_top.u_ibex_top.gen_lockstep.u_ibex_lockstep.rst_shadow_set_single_bit'\r\n                                                                                   : ... In instance ibex_simple_system\r\n  131 |   logic                       rst_shadow_n, rst_shadow_set_single_bit;\r\n      |                                             ^~~~~~~~~~~~~~~~~~~~~~~~~\r\n                       ... For warning description see https://verilator.org/warn/IMPERFECTSCH?v=4.210\r\n                       ... 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LSU\n  Most of these properties now prove without time-bound on the response\n  from memory due to alternative LSUs\n- Check memory even with Smepmp errors:\n  Continues on top of https://github.com/riscv/sail-riscv/pull/196\n- CSR verification\n- Checks for instruction types such as B-Type, I-Type, R-Type\n- Check illegal instructions and WFI instructions\n- Using psgen language for proof generation\n- Documentation on how to use the setup\n- Wrap around proof that proves instructions executed in a row still\n  match the specification.\n- Liveness proof to guarantee instructions will retire within a upper\n  bound of cycles.\n\nAll of these proofs make heavy use of the concept of k-induction. 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All dependencies are fetched and built upon entering the\nshell (nix develop .#formal), except for the proprietary Cadence Jasper.\n\nThe dev shell (nix develop .#formal-dev) is identical to the normal\nshell, but prints some information on how to swap out components. This\nis also documented in the README.\n\nDocumentation on how to use this environment is added to the dv/formal/README.md\nThe provided Makefile/.tcl scripts make assumptions about the environment\nthey are run within which are provided by the Nix environment. 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This also improves the proof script, which\nshould be faster now."}], "resolved_issues": [2193]}
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Adding a spurious key won't cause\nany problems, but we actually need it for the next commit, which grabs\nthe current version of dvsim from OpenTitan. That version of dvsim\nexpects the \"book\" key to have been set in common_project_cfg.hjson.\n\nSplitting the two commits like this should make it a bit more obvious\nwhere things have come from."}, {"sha": "dccba1e965a8d8c10ebc1bb7c692ed110ebd08b4", "parents": ["b6bee413c1bd414beb9b328d494459b3685cb60c"], "message": "Update lowrisc_ip to lowRISC/opentitan@e6a0e9a136\n\nUpdate code from upstream repository\nhttps://github.com/lowRISC/opentitan to revision\ne6a0e9a1363d33789283ea6ba3c4d94d41f2dee5\n\n* [dvsim] fix seed in json report (Gary Guo)\n* [prim_prince,rtl] Split data_state array into two pieces (Rupert\n  Swarbrick)\n* [prim_prince] Move the split_var verilator hint to prim_cipher.vlt\n  (Rupert Swarbrick)\n* [bazel] Use the new rules for building ROMs (Chris Frantz)\n* [hw,rtl,prim] Switch AND/OR for Mubi W1S/W1C (Robert Schilling)\n* [util] Error out if secure_prng seed is less than 256 bits (Vladimir\n  Rozic)\n* [dv] Update dv_sim to support sram new targets (Miguel Osorio)\n* [flash_ctrl,dv] update expected double bit error set (Jaedon Kim)\n* [bazel] Update the binary/test rules for building ROMs (Chris\n  Frantz)\n* [bazel] Prepare `dvsim` to work with the new rules (Chris Frantz)\n* [mubi,gen] Fix comments (Guillermo Maturana)\n* [reggen] Add mubi support SWAccess that sets/clears a reg (Robert\n  Schilling)\n* [doc] Fixing a few typos in xoshiro PRNG documentation (Vladimir\n  Rozic)\n* [doc] Testplan's are now generated as markdown. (Hugo McNally)\n* [bazel,dvsim] Prevent dvsim from (trying to) copy irrelevant files\n  (Amaury Pouly)\n* [doc] Moved badges over to using hosted images (Hugo McNally)\n* [doc] Fixed links to the getting started section. (Hugo McNally)\n* [dvsim] Avoid checking for gsutil when we just need gcloud (Rupert\n  Swarbrick)\n* [dvsim] Simplify the code that copies files up to GCP (Rupert\n  Swarbrick)\n* [dvsim] Use new results_server methods to list cleanly (Rupert\n  Swarbrick)\n* [dvsim] Wrap logic to move \"latest\" directory into results_server.py\n  (Rupert Swarbrick)\n* [dvsim] Add an object representing connections to results server\n  (Rupert Swarbrick)\n* [dv/cov] Fix coverage handling in some common items (Guillermo\n  Maturana)\n* [prim] Convert prim_clock_div to abtract (Alexander Williams)\n* [dv/top-level] Fix sram data integrity error injection (Guillermo\n  Maturana)\n* [tools,vcs] Make flops use the sampled value of data to avoid races\n  (Guillermo Maturana)\n* [prim lfsr] Replace randomize() calls with $urandom in prim_lfsr_tb\n  (Vladimir Rozic)\n* [doc] Update LFSR coeffs descriprion. (Vladimir Rozic)\n* [prim_lfsr] Remove redundant list of LFSR_COEFF (Vladimir Rozic)\n* [dv/top-level] Harden chip_sw_data_integrity_escalation (Guillermo\n  Maturana)\n* [otbn,dv] Wait more carefully for secure wipes in vseqs (Rupert\n  Swarbrick)\n* [doc,report] Fix the dvsim report links to the testplans (Harry\n  Callahan)\n* [doc] Add the block-dashboards to the primative page (Harry\n  Callahan)\n* [prim_subreg] Fix RC access corner case (Michael Schaffner)\n* [prim_lc_dec] Fix Xcelium compile error (Michael Schaffner)\n* [misc] Use lc_tx_t testing functions at endpoints (Michael\n  Schaffner)\n\nSigned-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>"}], "resolved_issues": [19785]}
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Where this has\nresulted in Ibex producing a memory request that spike would not we\nremove it from the list of memory requests to check after checking that\nthe request passes PMP within spike."}, {"sha": "2a80fc989a7bc1de03c4501ffd404cf276a23f36", "parents": ["327d177b418a5c0704f08e1925ba7427027d016f"], "message": "[dv] Update testbench to use new 'pre_val' MIP\n\nThe 'pre_val' MIP addresses the scenario where MIP changes as an\ninstruction is excuting, this means a CSR instruction can observe a\ndifferent MIP from the one that decides whether or not that instruction\nwill be interrupted."}, {"sha": "822c20b765eb37ddbb67657074fc10f306aa4022", "parents": ["2a80fc989a7bc1de03c4501ffd404cf276a23f36"], "message": "[cosim] Correctly deal with checking top of range memory accesses\n\nThe cosimulation environment does not know if a memory access from spike\nis due to an instruction fetch or a data memory access. It uses a\nheuristic to differentiate the two. Any access between the PC and the PC\n+ 8 is considered an instruction fetch.\n\nThis heuristic did not correctly handle addresses at the top of the\nrange where the PC + 8 calculation overflows. This commit fixes the top\nof range handling."}, {"sha": "c6c776917a6886dec1c70763a434a53cc28f5214", "parents": ["822c20b765eb37ddbb67657074fc10f306aa4022"], "message": "[dv] Output warning message on problematic MIP changes\n\nWhen an interrupt is raised the Ibex controller will move from the\nDECODE state to the IRQ_TAKEN state when it chooses to handle the\ninterrupt. When in IRQ_TAKEN it's possible for the interrupt state to\nchange again which aborts the interrupt entry. This leads to mis-matches\nagainst cosim.\n\nThis change adds a warning to flag up cases where this has occurred to\nenable quick triage of failures related to this scenario."}, {"sha": "6172f8f50922984c44d72d9a4c7d8b58b73db46a", "parents": ["c6c776917a6886dec1c70763a434a53cc28f5214"], "message": "[ci] Bump co-sim version"}, {"sha": "d5d3f37e765e02bb73447f8c9fbdc36f2a1831e4", "parents": ["6172f8f50922984c44d72d9a4c7d8b58b73db46a"], "message": "[cosim] Clang lint fix"}], "resolved_issues": [25]}
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(e.g., when signals are otherwise optimized away such\nas when not dumping waves) and the probe functions are apparently much\nfaster than `uvm_hdl_read()`, which seems to be implemented as foreign\nfunction.\n\nSigned-off-by: Andreas Kurth <adk@lowrisc.org>"}, {"sha": "01d1e3ac03a43f4cdb35350b02f45a35faaed0da", "parents": ["8f01d6d2e7c2d8ffa560a7e0e8a63b4d45cb27b6"], "message": "[dv] Add test glitching register file read data\n\nThis commit addresses the integrity checking part of #1756 by verifying\nthat a glitch on the data read from the register file raises a major\nalert by the core (if the data read from the register file is used by\nthe core).\n\nSigned-off-by: Andreas Kurth <adk@lowrisc.org>"}], "resolved_issues": [1873, 1756, 1879]}
+{"org": "lowRISC", "repo": "ibex", "number": 2063, "state": "closed", "title": "[ci] Consolidate Verible linting workflow into one stage", "body": "Demo PR on my local fork: https://github.com/jwnrt/ibex/pull/1\r\n\r\n## Problem\r\n\r\nThe current GitHub Actions (for Verible linting) have some dependencies on actions that use Node.js v12 (`actions/checkout@v2` and `actions/github-script@v3.1.0`) which [will be dropped on 2023-08-14](https://github.blog/changelog/2023-07-17-github-actions-removal-of-node12-from-the-actions-runner/).\r\n\r\nThese deprecated actions have newer versions that use Node.js 16, but `github-script` is a non-trivial update since our usage includes some actual Node.js code that needs porting.\r\n\r\n## Suggested fix\r\n\r\nThe docs for the Verible linter action [have been updated](https://github.com/chipsalliance/verible-linter-action/pull/31) to suggest using a single workflow, avoiding the need for `github-script`.\r\n\r\nThis PR updates to using this workflow, allowing us to update from deprecated dependencies.\r\n\r\nWe've been using this consolidated version of the linting workflow in [lowRISC/opentitan](https://github.com/lowRISC/opentitan/pull/18910) for a couple of weeks ([example](https://github.com/lowRISC/opentitan/pull/19207)). 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248, "license": {"key": "apache-2.0", "name": "Apache License 2.0", "spdx_id": "Apache-2.0", "url": "https://api.github.com/licenses/apache-2.0", "node_id": "MDc6TGljZW5zZTI="}, "allow_forking": true, "is_template": false, "web_commit_signoff_required": false, "has_pull_requests": true, "pull_request_creation_policy": "all", "topics": ["cpucore", "hardware", "risc-v", "rv32"], "visibility": "public", "forks": 749, "open_issues": 248, "watchers": 1920, "default_branch": "master"}}, "commits": [{"sha": "6711a42e624a99f57d05d2af398a278a72be3f06", "parents": ["06df66452feb8b607ba605431a77045017a5ac01"], "message": "[ci] Consolidate Verible linting workflow into one stage\n\nRunning the verible linter and adding review comments to the pull\nrequest previously had to be done in two stages:\n\n1. Triggered on the pull request - prepare config and waiver files as\n   artifacts.\n2. Running on the repo's HEAD - run Verible and add review comments.\n\nThis was required because Actions running in the context of the pull\nrequest did not have write permissions to add comments to pull requests.\n\nThis is now possible with the `pull_request_target` event, which\ntriggers when pull requests change, but runs in the context of the\nrepo's HEAD and has the permissions to create comments.\n\nSee lowRISC/ibex#1427 and\nchipsalliance/verible-linter-action#31 for details.\n\nSigned-off-by: James Wainwright <james.wainwright@lowrisc.org>"}], "resolved_issues": [1427, 31]}
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https://github.com/google/riscv-\ndv to revision 68e3bcac7293ac79067f0d8196bb973bd7c889cf\n\n* [pmp] Remove restriction on using NAPOT when granularity = 0 (Marno\n  van der Maas)\n* [pmp] Add PMP entries for data in case of MML or MMWP (Marno van der\n  Maas)\n* [pmp] Add already_configured flag to skip address in PMP routine\n  (Marno van der Maas)\n* [pmp] Fix constraint and CSR write test in MML mode (Marno van der\n  Maas)\n* [pmp] Use random address instead of offset for full random test\n  (Marno van der Maas)\n* [pmp] Allow specifying address zero in `+pmp_region_%0d` (Marno van\n  der Maas)\n* [pmp] Randomizing entry for instructions for PMP randomization\n  (Marno van der Maas)\n* [lint] Remove trailing whitespace (Marno van der Maas)\n* Tweak CSR constraints for more even read/write distribution (Greg\n  Chadwick)\n* [lint] Replace tabs with spaces (Marno van der Maas)\n* [pmp] No PMP exception handler when no PMP support (Greg Chadwick)\n* Expand CSR instruction constraint functionality (Greg Chadwick)\n* Refactor CSR instruction into their own class (Greg Chadwick)\n\nSigned-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>"}, {"sha": "0ac206878ef9785f70c132c892a700886086ad2f", "parents": ["fb528e52dbd0295963e5d776818019ca9145965e"], "message": "[dv,pmp] Minor fixes to PMP full random test\n\n- Increase iterations to 20 because double faults are less likely.\n- Remove restriction on MPRV randomization.\n\nSigned-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>"}], "resolved_issues": [1777]}
+{"org": "lowRISC", "repo": "ibex", "number": 1801, "state": "closed", "title": "[dv,debug] Add new uvm test to hit hardware breakpoints coverpoints", "body": "Overrides some riscv-dv classes to create a custom debug_rom for this test\r\nspecifically, which is used to setup the breakpoint registers.\r\nIt is difficult to get stimulus of this hardware feature without a more directed test.\r\n\r\n~~This test currently sets `+disable_cosim=1` because there is a cosimulation bug around setting the trigger address correctly.\r\nThat bug will be solved separately.~~\r\n\r\n~~Also, the coverpoint `cp_insn_trigger_exception` does not get hit yet because that coverpoint is not possible to hit. It's implementation needs to be rethought, though I believe the stimulus here does trigger the intended behaviour for this coverpoint.~~ Coverpoint was broken, removed & replaced with a new coverpoint in #1872 \r\n\r\nTo test:\r\n```bash\r\nmake TEST=riscv_debug_triggers_test\r\n```\r\n\r\nGoes towards #1701 ", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/1801", "id": 1043490166, "node_id": "PR_kwDOBfEjEc4-MmV2", "html_url": "https://github.com/lowRISC/ibex/pull/1801", "diff_url": "https://github.com/lowRISC/ibex/pull/1801.diff", "patch_url": "https://github.com/lowRISC/ibex/pull/1801.patch", "issue_url": "https://api.github.com/repos/lowRISC/ibex/issues/1801", "created_at": "2022-09-01T09:59:07+00:00", "updated_at": "2022-10-31T16:07:01+00:00", "closed_at": "2022-10-31T16:06:58+00:00", "merged_at": "2022-10-31T16:06:57+00:00", "merge_commit_sha": "36d0d3089d444fbe5dec72e774a7ff471f58e41c", "labels": ["Component:DV"], "draft": false, "commits_url": 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the option of jumping directly to these label. Previously, ECALL was\nused to provide a single path to this code."}, {"sha": "3e34c669ba64099174f135794852df6947b338d1", "parents": ["bee0de6aa8325b5ddc26a01ba3a077bc95c0d737"], "message": "Redefine ECALL handler to no-longer jump to 'write_tohost:'\n\nThis prevents the simulation from entering an infinite loop which it can no\nlonger detect and terminate from."}, {"sha": "3cfa5f8cd0609590e573890bd1cbb357d26378c9", "parents": ["3e34c669ba64099174f135794852df6947b338d1"], "message": "Add new uvm test to hit hardware breakpoints coverpoints\n\nOverrides some riscv-dv classes to create a custom debug_rom for this test,\nwhich is used to setup the breakpoint registers.\nI have found it difficult to get stimulus of this hardware feature without\na more directed test. Improvements or ideas are welcome here.\n\nTest-specific timeout of 5min within which I see >90% pass rate."}, {"sha": "d54858f11aa0df252976ec94e7ee723130cd3551", "parents": ["3cfa5f8cd0609590e573890bd1cbb357d26378c9"], "message": "Change defaults for bad_intg on uninit accesses for Dmem/Imem\n\nImem : never create bad_intg on uninit access\nDmem : by default, enable bad_intg on uninit access. Plusarg to change behaviour."}, {"sha": "dbcf9ed5b7854f91148a0987d575dc70831e3d79", "parents": ["d54858f11aa0df252976ec94e7ee723130cd3551"], "message": "Bump up timeout for irq_stimulus to accomodate fetch_enable changes\n\nThe recent change to add the fetch_enable sequence in to every regression\ncan very-rarely cause the 3000 cycle timeout for the irq_stimulus check to fail.\nThis only happens with a large randomized length of the fetch being disabled,\nand long latency for memory accesses.\nIncrease this timeout."}], "resolved_issues": [1872, 1701]}
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+{"org": "lowRISC", "repo": "ibex", "number": 1737, "state": "closed", "title": "[rtl] Deny no-match X access in M-Mode while MML=1", "body": "In ePMP spec, it specifies as:\r\n\r\n```\r\nExecuting code with Machine mode privileges is only possible from memory\r\nregions with a matching Mmode-only rule or a locked Shared-Region rule\r\nwith executable privileges. Executing code from a region without a\r\nmatching rule or with a matching S/U-mode-only rule is denied.\r\n```\r\n\r\nThis change provides that.\r\n\r\nResolves #1736 \r\n\r\nSigned-off-by: Canberk Topal <ctopal@lowrisc.org>", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/1737", "id": 1013836534, "node_id": "PR_kwDOBfEjEc48ber2", "html_url": "https://github.com/lowRISC/ibex/pull/1737", "diff_url": "https://github.com/lowRISC/ibex/pull/1737.diff", "patch_url": "https://github.com/lowRISC/ibex/pull/1737.patch", "issue_url": "https://api.github.com/repos/lowRISC/ibex/issues/1737", "created_at": "2022-08-01T13:05:33+00:00", "updated_at": "2022-08-03T09:59:41+00:00", "closed_at": "2022-08-03T09:59:41+00:00", "merged_at": "2022-08-03T09:59:41+00:00", "merge_commit_sha": "e242ef07ad3757c5064a89facbce4b0f690e8e50", "labels": ["Type:Bug", "Component:RTL"], "draft": false, "commits_url": "https://api.github.com/repos/lowRISC/ibex/pulls/1737/commits", "review_comments_url": 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Shared-Region rule\nwith executable privileges. Executing code from a region without a\nmatching rule or with a matching S/U-mode-only rule is denied.\n```\n\nThis change provides that.\n\nSigned-off-by: Canberk Topal <ctopal@lowrisc.org>"}], "resolved_issues": [1736]}
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["4975c7fa4bea96ad3000f1b1e3fdc508f7905d20"], "message": "Change test_done mechanism to use riscvdv handshake, not ecall\n\nUse the address (signature_addr - 0x4) for a TEST_PASS handshake.\nCreate new mem_seq_item subscriber port for test_done functionality.\n\nBy creating a new, distinct port and subscribing to all incoming memory items,\nthe existing wait_for_mem_txn() can be used with minor modifications to be\nable to choose the port to wait on as an argument to the task.\n\nBecause the wait_for_mem_txn() implementation currently uses get() to pop the\nlatest item from the item_collected queue, having two different forked processes\nthat both await on this queue is not possible. The simplest solution is to\ncreate a new, seperate port which also subscribes to the sequence_items\nbroadcast by the mem_if monitor.\n\nSigned-off-by: Harry Callahan <hcallahan@lowrisc.org>"}, {"sha": "efe6a37c7e36e0daaf2b34dc387d7e7ffc4675c2", "parents": ["24661ea5d825298cdb95592ef8855aa75de22bcb"], "message": "Add special-case signature for test_done in riscv_csr_test\n\nThis test is generated differently to all the others, as it exclusively uses a\npython script.\nThe easiest way to make this work with the new test_done signature address is to\ndetect it as a special case and pass it the new address. The handshaking is only\nused for ending the test, so the original address does not matter."}], "resolved_issues": [1718]}
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I think this should probably be upstreamed.\r\n\r\nGoes towards #1701 ", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/1763", "id": 1023603604, "node_id": "PR_kwDOBfEjEc49AvOU", "html_url": "https://github.com/lowRISC/ibex/pull/1763", "diff_url": "https://github.com/lowRISC/ibex/pull/1763.diff", "patch_url": "https://github.com/lowRISC/ibex/pull/1763.patch", "issue_url": "https://api.github.com/repos/lowRISC/ibex/issues/1763", "created_at": "2022-08-11T08:55:00+00:00", "updated_at": "2022-10-06T16:56:15+00:00", "closed_at": "2022-10-06T16:52:37+00:00", "merged_at": "2022-10-06T16:52:36+00:00", "merge_commit_sha": "3c11ef10b98a73c06345bd0f2fcb8d94226b4f31", "labels": [], "draft": false, "commits_url": "https://api.github.com/repos/lowRISC/ibex/pulls/1763/commits", "review_comments_url": "https://api.github.com/repos/lowRISC/ibex/pulls/1763/comments", "review_comment_url": "https://api.github.com/repos/lowRISC/ibex/pulls/comments{/number}", "comments_url": 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illegal instructions, csr instructions, ebreak, etc. which the previous\nbrittle checking paradigms could not handle."}, {"sha": "f6f09177baa35d61209723fed09be1c8291295a0", "parents": ["b66af050444676170567d3abcb3102cbdd68e6b9"], "message": "single_step test : only drive debug_req_i after stepping finishes\n\nThis addresses a current testbench issue where asserting debug_req_i close to\nwhen single_stepping over an instruction causes an incorrect 'cause' to be\nrecorded within DCSR."}], "resolved_issues": [1701]}
+{"org": "lowRISC", "repo": "ibex", "number": 1875, "state": "closed", "title": "Nested interrupt test fixes", "body": "> After [removing the integrity-errors generated](https://github.com/lowRISC/ibex/pull/1874/files) from uninit memory accesses, the nested_interrupt test was still failing reliably.\r\n> I think I found the reason why this test was accessing uninit memory in the first place, and propose a solution in this PR.\r\n> \r\n> Note that I am making this PR with changes directly to the vendored RISCV-DV code, with a view to upstream shortly.\r\n\r\nUpstream PR merged [here](https://github.com/google/riscv-dv/pull/906), now vendored into Ibex [here](https://github.com/lowRISC/ibex/pull/1880).\r\n\r\n> \r\n> The problem with this test currently is that riscv-dv has routines to push and pop the GPR's to the kernel-stack upon entering and exiting an interrupt handler, storing the pointer to this effective stack-frame in MSCRATCH. However, the code that allows for nested interrupts by setting xSTATUS.xIE inside the ISR also makes use of MSCRATCH to hold a temporary value that stops the program from entering more than one level of nesting. By overwriting our original pointer to the GPR's, we could not restore them when going back to our original program, hence the program state was corrupted and we would access uninit memory.\r\n> \r\n> These changes fix the problem by storing the pointer to the saved state also on the kernel mode stack, and not in the MSCRATCH csr.\r\n> This PR also raises the value of `vseq.irq_raise_seq_h.max_delay = 5000;`, which allows more instructions to be executed between our applied IRQ stimulus. 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(Michael\n  Schaffner)\n* [prim_onehot_check] Add option for permissive en_i checks (Michael\n  Schaffner)\n* [tools/dv] updated UNR flow to support xcelium/jg (Rasmus Madsen)\n* [prim] Add dv_macros missing dependency (Timothy Chen)\n* [top, dv] Fix ext clk plusarg (Weicai Yang)\n* [dv/build_seed] Fix build_seed (Cindy Chen)\n* [clkmgr] Correct the disable condition (Timothy Chen)\n* [flash, dv] Fix RMA test backdoor symbol overwrite (Weicai Yang)\n* [top, dv] Fix rom backdoor symbol overwrite (Weicai Yang)\n* [flash_ctrl] Add checks for unexpected acks (Timothy Chen)\n* [prim_present] Add Verilator lint waiver (Michael Schaffner)\n* [xcelium] Pass cov_merge_db_dir through to cov_report.tcl (Rupert\n  Swarbrick)\n* [dv/build_seed] Fix build seed errors (Cindy Chen)\n* [prim_mubi] Add assertion to check that the values are complementary\n  (Michael Schaffner)\n\nSigned-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>"}, {"sha": "782fce2ed66ee2792b53c5e5204f47600d771837", "parents": ["3def54ea57503043921086562ea7004c846faa2b"], "message": "[dv,prim] Fix build and assert errors for vendored prim changes\n\nAfter vendoring the new changes to the prim IP:\n- Reorder `ibex_dv.f` to reflect the dependency on `prim_assert.sv`\n- Disable assertion for register file prim onehot check.\n\nSigned-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>"}], "resolved_issues": [12761, 12236, 12319]}
+{"org": "lowRISC", "repo": "ibex", "number": 1668, "state": "closed", "title": "Update google_riscv-dv to google/riscv-dv@cc4b870", "body": "Update code from upstream repository https://github.com/google/riscv-\r\ndv to revision cc4b87057cb38c91cb0c2ecb065e38281df7aa97\r\n\r\n* Fix google/riscv-dv#857 (aneels3)\r\n* [euvm] Fixed a typo in the README file (Puneet Goel)\r\n* [euvm] updated the README file (Puneet Goel)\r\n* [euvm] Moved euvm specific README to euvm folder (Puneet Goel)\r\n* [euvm] ported some SV updates (Puneet Goel)\r\n* [euvm] Fixed generated ASM code indentation (Puneet Goel)\r\n* Add support for RV64IMC instr coverage (aneels3)\r\n* Add register definitions for privilege spec 1.12 and debug spec\r\n  1.0.0 (Henrik Fegran)\r\n* Updated README note for EUVM (Puneet Goel)\r\n* Use current date in output folder name (Puneet Goel)\r\n* Try to create output file folder if it does not exist (Puneet Goel)\r\n* Added a readme for EUVM port (Puneet Goel)\r\n* Allow providing a randomization seed from command line (Puneet Goel)\r\n* Make merging of directed instruction streams scalable (Puneet Goel)\r\n* Create and use new class riscv_prog_instr_stream (Puneet Goel)\r\n* Added and used append and prepend functions for instr_list (Puneet\r\n  Goel)\r\n* Added new targets and tests (Puneet Goel)\r\n* Expose riscv instruction classes in the riscv gen package (Puneet\r\n  Goel)\r\n* Use mixin templates to create RISCV instruction classes (Puneet\r\n  Goel)\r\n* Fix a bug in asm section tag generation (Puneet Goel)\r\n* EUVM upgrade for bitmanip (Puneet Goel)\r\n* Use new clog2 implemented in esdl.data.bvec module (Puneet Goel)\r\n* Add debug and clean targets to Makefile (Puneet Goel)\r\n* Use Queue functions in place of array concatenation (Puneet Goel)\r\n* Misc fixes after review (Puneet Goel)\r\n* Fix broken run.py script (Puneet Goel)\r\n* Use more verbose naming in main function in the test (Puneet Goel)\r\n* Removed some redundant code comments (Puneet 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Goel)\r\n* Use variable for setting rand_mode (Puneet Goel)\r\n* Use false in place of '0' for bools (Puneet Goel)\r\n* Added build makefile (Puneet Goel)\r\n* misc fixes (Puneet Goel)\r\n* Added riscv instruction definitions (Puneet Goel)\r\n* Added euvm module riscv_instr_registry (Puneet Goel)\r\n* Added euvm module riscv_data_page_gen (Puneet Goel)\r\n* Added euvm module riscv_privileged_common_seq (Puneet Goel)\r\n* Added euvm module riscv_debug_rom_gen (Puneet Goel)\r\n* Use urandom!bool in place of inappropriately named function toss\r\n  (Puneet Goel)\r\n* Added euvm module riscv_illegal_instr (Puneet Goel)\r\n* Added euvm module riscv_asm_program_gen (Puneet Goel)\r\n* Use esdl.rand: toss instead os uniform(0, 2) (Puneet Goel)\r\n* Fixed randomization of avail_regs in euvm module riscv_instr_stream\r\n  (Puneet Goel)\r\n* Use esdl.rand: shuffle instead of randomShuffle (Puneet Goel)\r\n* Added euvm module riscv_directed_instr_lib (Puneet Goel)\r\n* added euvm module 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command to to run a test (Puneet Goel)\n* Cast return value from ceil to integer (Puneet Goel)\n* Miscelleneous fixes (Puneet Goel)\n* Fixed some issues in riscv_loop_instr (Puneet Goel)\n* Use variable for setting rand_mode (Puneet Goel)\n* Use false in place of '0' for bools (Puneet Goel)\n* Added build makefile (Puneet Goel)\n* misc fixes (Puneet Goel)\n* Added riscv instruction definitions (Puneet Goel)\n* Added euvm module riscv_instr_registry (Puneet Goel)\n* Added euvm module riscv_data_page_gen (Puneet Goel)\n* Added euvm module riscv_privileged_common_seq (Puneet Goel)\n* Added euvm module riscv_debug_rom_gen (Puneet Goel)\n* Use urandom!bool in place of inappropriately named function toss\n  (Puneet Goel)\n* Added euvm module riscv_illegal_instr (Puneet Goel)\n* Added euvm module riscv_asm_program_gen (Puneet Goel)\n* Use esdl.rand: toss instead os uniform(0, 2) (Puneet Goel)\n* Fixed randomization of avail_regs in euvm module riscv_instr_stream\n  (Puneet Goel)\n* Use esdl.rand: shuffle instead of randomShuffle (Puneet Goel)\n* Added euvm module riscv_directed_instr_lib (Puneet Goel)\n* added euvm module riscv_load_store_instr_lib (Puneet Goel)\n* urandom has moved to package esdl.rand (Puneet Goel)\n* Added euvm module riscv_instr_sequence (Puneet Goel)\n* Added euvm module riscv_amo_instr_lib (Puneet Goel)\n* Added euvm module riscv_instr_stream (Puneet Goel)\n* A small fix in riscv_pmp_cfg module (Puneet Goel)\n* Added euvm module riscv_loop_instr (Puneet Goel)\n* Added euvm module riscv_pseudo_instr (Puneet Goel)\n* Added euvm module riscv_vector_instr (Puneet Goel)\n* Added euvm module riscv_floating_point_instr (Puneet Goel)\n* Added euvm module riscv_b_instr (Puneet Goel)\n* Added euvm module isa/riscv_compressed_instr (Puneet Goel)\n* Added euvm module isa/riscv_amo_instr (Puneet Goel)\n* Added euvm module isa/riscv_instr (Puneet Goel)\n* Added euvm module riscv_callstack_gen (Puneet Goel)\n* Added euvm module riscv_page_table_list (Puneet Goel)\n* Used ranged switch case statements where required (Puneet Goel)\n* Added euvm module riscv_privil_reg (Puneet Goel)\n* Add @UVM_DEFAULT uda on the class members where required (Puneet\n  Goel)\n* Added euvm module riscv_reg (Puneet Goel)\n* Added euvm module riscv_pmp_cfg (Puneet Goel)\n* Added euvm module riscv_vector_cfg (Puneet Goel)\n* Added euvm module riscv_page_table_exception_cfg (Puneet Goel)\n* Added euvm module riscv_page_table_entry (Puneet Goel)\n* Added euvm module riscv_page_table (Puneet Goel)\n* Added riscv_core_setting module (Puneet Goel)\n* Added new file riscv_instr_gen_config (Puneet Goel)\n* Fixed some module imports (Puneet Goel)\n* Added new file riscv_signature_pkg (Puneet Goel)\n* Added D port of riscv_instr_pkg (Puneet Goel)\n\nSigned-off-by: Pirmin Vogel <vogelpi@lowrisc.org>"}], "resolved_issues": [857]}
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instantiate the ibex_icache module. For verilator\nsimulations, the module is then discarded entirely, which means that\nits two DPI functions are not defined. That's unfortunate because\nwe're also compiling the code in scrambled_ecc32_mem_area.cc, which\nexpects the functions to be defined.\n\nThe obvious solution (don't include scrambled_ecc32_mem_area.cc if you\ndon't have an icache) isn't easy to do, because FuseSoc doesn't\ncurrently allow us to use parameters to configure its dependency\ntree (see fusesoc issue 438 for a discussion).\n\nThe super-clever solution that I came up with before(!) was to declare\nthese symbols as weak in the C++ code. That way, we can do a runtime\ncheck to make sure that no-one is silly enough to call them without an\nicache, but everything will still build properly either way.\n\nUnfortunately, that doesn't work well with xcelium simulations.\nXcelium turns out to compile all the C++ code into one .so library and\ngenerate functions for exported DPI functions in another. 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for all regwen CSRs (Weicai Yang)\r\n* [dvsim] Add support for tags in testplan (Srikrishna Iyer)\r\n* [dv] Enable xcelium to include X for toggle coverage (Weicai Yang)\r\n* [dv] Clean up mem_bkdr_util__sram (Weicai Yang)\r\n* [util, testplan] Allow relative testplan imports (Srikrishna Iyer)\r\n* [prim] Add phase output to shadow register primitive (Pirmin Vogel)\r\n* [dv] Add assertion to check double_lfsr err triggers an alert\r\n  (Weicai Yang)\r\n* [dv] Fix foundary failure (Weicai Yang)\r\n* [prim] update prim_count comment (Timothy Chen)\r\n* [prim_flop_2sync] Make the prim a standard non-generated prim\r\n  (Michael Schaffner)\r\n* [dv/prim_max_tree] Fix xcelium compile error (Cindy Chen)\r\n* [dv] Fixes to enable foundry database pwrmgr_smoketest (Timothy\r\n  Chen)\r\n* [dv] Add countermeasure verification for double_lfsr (Weicai Yang)\r\n* [dv] Update countermeasure verification (Weicai Yang)\r\n* [doc] Update V2S items (Weicai Yang)\r\n* [prim_max_tree] Remove dedicated FPV TB since all SVAs are embedded\r\n  (Michael Schaffner)\r\n* [prim_max_tree/fpv] Add a simple formal testbench (Michael\r\n  Schaffner)\r\n* [prim_max_tree] Create a primitive that calculates maxima (Michael\r\n  Schaffner)\r\n* [dv] CSR / RAL model fixes (Srikrishna Iyer)\r\n* [uvmdvgen] bug fix (Srikrishna Iyer)\r\n* [dv] Fix some Xcelium warnings (Srikrishna Iyer)\r\n* [dv] Disable some benign warnings (Srikrishna Iyer)\r\n* [prim_mubi*_sender] Add option to omit sender flops (Michael\r\n  Schaffner)\r\n* [dv, mem_bkdr_util] Fix ECC-computed backdoor WRs (Srikrishna Iyer)\r\n* [keymgr] sparsify the data control fsm (Timothy Chen)\r\n* [prim_lc_sender] Add AsyncOn parameter (Michael Schaffner)\r\n* [prim] Update behavior of prim_count (Timothy Chen)\r\n* [flash_ctrl] Minor fixes to flash foundry failure (Timothy Chen)\r\n* [sw,tests,pwrmgr] Improve synchronization (Guillermo Maturana)\r\n* [sw,tests] SRAM execution test DV integration (Dave Williams)\r\n* [dv] Update common_cov_excl to exclude d_user.rsp_intg[6] (Weicai\r\n  Yang)\r\n* [otbn, dv] Added otbn_passthru_mem_tl_intg_err testcase (Prajwala\r\n  Puttappa)\r\n* [rom_ctrl, dv] Fixes regression failures in\r\n  rom_ctrl_passthru_mem_tl_intg_err (Prajwala Puttappa)\r\n* [dv/chip] Add jtag_csr_rw seq (Cindy Chen)\r\n* [chip dv] Remove xcelium build opt (Srikrishna Iyer)\r\n* [doc] Reorder D2S checklist items (Michael Schaffner)\r\n* [reggen] Add support for validation of RTL CM annotation (Michael\r\n  Schaffner)\r\n* [all] various simple lint fixes (Timothy Chen)\r\n* [mem_bkdr,dv] Add missing type to otp_write_lc_partition_cnt (Rupert\r\n  Swarbrick)\r\n* [dv/csr_utils_pkg] Clone ral map with top-level submaps (Cindy Chen)\r\n* [clkmgr] various spec and parameter updates (Timothy Chen)\r\n* [dv] Add ASSERT_NET to check net value (Weicai Yang)\r\n* [dv] revert lowRISC/opentitan#9050 and lowRISC/opentitan#9934\r\n  (Weicai Yang)\r\n* [primgen] Update AscentLint waiver in generated abstract prim\r\n  wrappers (Pirmin Vogel)\r\n* [prim_generic] Fix lint errors (Pirmin Vogel)\r\n* [prim_count] Fix lint warnings (Pirmin Vogel)\r\n* [prim_alert_receiver] Fix ping during init sequence bug (Michael\r\n  Schaffner)\r\n* [rom_ctrl, dv] Added passthru mem test (Prajwala Puttappa)\r\n* [prim_assert,dv] Use if condition in assert_init (Srikrishna Iyer)\r\n* [prim_filter_cnt] Make threshold runtime programmable (Michael\r\n  Schaffner)\r\n* [prim_filter*] Optionally instantiate a 2-stage sync in prim_filter*\r\n  (Michael Schaffner)\r\n* [dv] intg_err test cleanup and change passthru_mem_tl_intg_err to\r\n  V2S (Weicai Yang)\r\n* [prim_xilinx] Replace KEEP with DONT_TOUCH attributes (Pirmin Vogel)\r\n* [sram/dv] Enable the integrity test for passthru (Weicai Yang)\r\n* [dv] Add integrity test for passthru mem (Weicai Yang)\r\n* [dv/tools] Fix alert ping exclusion (Cindy Chen)\r\n* [dv/mem_bkdr_util] added backdoor write of LC counter into LC\r\n  partition in OTP (Dror Kabely)\r\n* [prim_pad_wrapper] Add dual pad wrapper for USB (Michael Schaffner)\r\n* [prim_clock_mux] Model generic mux with boolean ops (Michael\r\n  Schaffner)\r\n* [prim_buf] Ensure generic primitives contain a logic cell (Michael\r\n  Schaffner)\r\n* [prim_count] improved documentation and style (Michael Tempelmeier)\r\n* Revert \"[dv] Replace fileset_partner flag with fileset_ast flag\"\r\n  (Michael Schaffner)\r\n* [dv] Replace fileset_partner flag with fileset_ast flag (Sharon\r\n  Topaz)\r\n* [dv] Pass data_intg_passthru to dv_base_mem (Weicai Yang)\r\n* [dv/prim_alert] Add V3 item to testplan (Cindy Chen)\r\n* [dv/prim_count] Add an assertion to check max count stable (Cindy\r\n  Chen)\r\n* [dv] Fix typo in uvmdvgen comment (Rupert Swarbrick)\r\n* [mem_bkdr_util] Use inverted integrity in rom_encrypt_write32_integ\r\n  (Rupert Swarbrick)\r\n* [doc/checklist] Template fix (Cindy Chen)\r\n* [mem_bkdr_util,rom_ctrl] Fix how we call encrypt_sram_data (Rupert\r\n  Swarbrick)\r\n* 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memutil_dpi_scrambled even without\n  prim_ram_1p_scr\" (Rupert Swarbrick)\n* [dv] Fix some signed/unsigned comparison warnings (Rupert Swarbrick)\n* [dv] Make an implicit up-conversion explicit (Rupert Swarbrick)\n* [dv] Remove an unused array variable in prince_ref.h (Rupert\n  Swarbrick)\n* [prim/security] Improve the code for prim_sparse_fsm security check\n  (Cindy Chen)\n* [dv] Apply VCS option `-xprop=mmsopt` only when wave dump is off\n  (Weicai Yang)\n* [all] variety of minor lint fixes (Timothy Chen)\n* [dv] Add options to improve VCS runtime (Weicai Yang)\n* [rv_dm] CSR test fixes (Srikrishna Iyer)\n* [dvsim] Fix pass/fail status for synthesis regression (Michael\n  Schaffner)\n* [prim] Minor lint fixes for unused clocks / resets (Timothy Chen)\n* [dv] Flag illegal ENUMASSIGN warnings as errors (Michael Schaffner)\n* [flash_ctrl] Correct erase suspend interface behavior (Timothy Chen)\n* [rstmgr] Address several d2s review items (Timothy Chen)\n* [fpv/sec] Add some workaround logic for $cast keyword (Cindy Chen)\n* [dv] CSR seq lib - support for adapter-less RAL (Srikrishna Iyer)\n* [dv] Prepare codebase for UVM REG changes (Srikrishna Iyer)\n* [dv] Print computed CSR stuff in RAL (Srikrishna Iyer)\n* [dv] Allow CSR tests to run on custom RALs (Srikrishna Iyer)\n* [fpv/rom_ctrl] Check connectivity for alerts in rom_ctrl (Cindy\n  Chen)\n* [prim] Add prim_and2 primitive (Pirmin Vogel)\n* [prim_dom_and_2share] Remove EnNegedge parameter (Pirmin Vogel)\n* [prim_dom_and_2share] Use prim_xor2 and prim_flop_en primitives\n  (Pirmin Vogel)\n* [prim_dom_and_2share] Switch to single randomness input (Pirmin\n  Vogel)\n* [util/dvsim] Fix confusing error message (Guillermo Maturana)\n* [dvsim] Minor changes to SynCfg results reporting (Michael\n  Schaffner)\n* [fpv] V2S formal support (Cindy Chen)\n* [tools/xcelium] updated common coverage exclusions to exclude single\n  bit correctly (Rasmus Madsen)\n* [dv] Clean up enable_reg_testplan (Weicai Yang)\n* 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[dv/shadow_reg] Move shadow_reg to V2S (Cindy Chen)\n* [prim_count] Updated comments to reflect all changes in\n  lowRISC/opentitan#10378 (Michael Tempelmeier)\n* [dv] Teach ECC32 flavours of mem_area to write with integrity bits\n  (Rupert Swarbrick)\n* [dv/shadow_reg] update milestone for shadow reg tests (Cindy Chen)\n* [checklists] Update V2S checklists (Srikrishna Iyer)\n* [tools/xcelium] updated xcelium flow to vcs for coverage test\n  grading (Rasmus Madsen)\n* [prim] Add stub flops to remove lint warnings (Timothy Chen)\n* [dv] Add automatic covergroup for all regwen CSRs (Weicai Yang)\n* [dvsim] Add support for tags in testplan (Srikrishna Iyer)\n* [dv] Enable xcelium to include X for toggle coverage (Weicai Yang)\n* [dv] Clean up mem_bkdr_util__sram (Weicai Yang)\n* [util, testplan] Allow relative testplan imports (Srikrishna Iyer)\n* [prim] Add phase output to shadow register primitive (Pirmin Vogel)\n* [dv] Add assertion to check double_lfsr err triggers an alert\n  (Weicai Yang)\n* [dv] Fix foundary failure (Weicai Yang)\n* [prim] update prim_count comment (Timothy Chen)\n* [prim_flop_2sync] Make the prim a standard non-generated prim\n  (Michael Schaffner)\n* [dv/prim_max_tree] Fix xcelium compile error (Cindy Chen)\n* [dv] Fixes to enable foundry database pwrmgr_smoketest (Timothy\n  Chen)\n* [dv] Add countermeasure verification for double_lfsr (Weicai Yang)\n* [dv] Update countermeasure verification (Weicai Yang)\n* [doc] Update V2S items (Weicai Yang)\n* [prim_max_tree] Remove dedicated FPV TB since all SVAs are embedded\n  (Michael Schaffner)\n* [prim_max_tree/fpv] Add a simple formal testbench (Michael\n  Schaffner)\n* [prim_max_tree] Create a primitive that calculates maxima (Michael\n  Schaffner)\n* [dv] CSR / RAL model fixes (Srikrishna Iyer)\n* [uvmdvgen] bug fix (Srikrishna Iyer)\n* [dv] Fix some Xcelium warnings (Srikrishna Iyer)\n* [dv] Disable some benign warnings (Srikrishna Iyer)\n* [prim_mubi*_sender] Add option to omit sender flops (Michael\n  Schaffner)\n* [dv, mem_bkdr_util] Fix ECC-computed backdoor WRs (Srikrishna Iyer)\n* [keymgr] sparsify the data control fsm (Timothy Chen)\n* [prim_lc_sender] Add AsyncOn parameter (Michael Schaffner)\n* [prim] Update behavior of prim_count (Timothy Chen)\n* [flash_ctrl] Minor fixes to flash foundry failure (Timothy Chen)\n* [sw,tests,pwrmgr] Improve synchronization (Guillermo Maturana)\n* [sw,tests] SRAM execution test DV integration (Dave Williams)\n* [dv] Update common_cov_excl to exclude d_user.rsp_intg[6] (Weicai\n  Yang)\n* [otbn, dv] Added otbn_passthru_mem_tl_intg_err testcase (Prajwala\n  Puttappa)\n* [rom_ctrl, dv] Fixes regression failures in\n  rom_ctrl_passthru_mem_tl_intg_err (Prajwala Puttappa)\n* [dv/chip] Add jtag_csr_rw seq (Cindy Chen)\n* [chip dv] Remove xcelium build opt (Srikrishna Iyer)\n* [doc] Reorder D2S checklist items (Michael Schaffner)\n* [reggen] Add support for validation of RTL CM annotation (Michael\n  Schaffner)\n* [all] various simple lint fixes (Timothy Chen)\n* [mem_bkdr,dv] Add missing type to otp_write_lc_partition_cnt (Rupert\n  Swarbrick)\n* [dv/csr_utils_pkg] Clone ral map with top-level submaps (Cindy Chen)\n* [clkmgr] various spec and parameter updates (Timothy Chen)\n* [dv] Add ASSERT_NET to check net value (Weicai Yang)\n* [dv] revert lowRISC/opentitan#9050 and lowRISC/opentitan#9934\n  (Weicai Yang)\n* [primgen] Update AscentLint waiver in generated abstract prim\n  wrappers (Pirmin Vogel)\n* [prim_generic] Fix lint errors (Pirmin Vogel)\n* [prim_count] Fix lint warnings (Pirmin Vogel)\n* [prim_alert_receiver] Fix ping during init sequence bug (Michael\n  Schaffner)\n* [rom_ctrl, dv] Added passthru mem test (Prajwala Puttappa)\n* [prim_assert,dv] Use if condition in assert_init (Srikrishna Iyer)\n* [prim_filter_cnt] Make threshold runtime programmable (Michael\n  Schaffner)\n* [prim_filter*] Optionally instantiate a 2-stage sync in prim_filter*\n  (Michael Schaffner)\n* [dv] intg_err test cleanup and change passthru_mem_tl_intg_err to\n  V2S (Weicai Yang)\n* [prim_xilinx] Replace KEEP with DONT_TOUCH attributes (Pirmin Vogel)\n* [sram/dv] Enable the integrity test for passthru (Weicai Yang)\n* [dv] Add integrity test for passthru mem (Weicai Yang)\n* [dv/tools] Fix alert ping exclusion (Cindy Chen)\n* [dv/mem_bkdr_util] added backdoor write of LC counter into LC\n  partition in OTP (Dror Kabely)\n* [prim_pad_wrapper] Add dual pad wrapper for USB (Michael Schaffner)\n* [prim_clock_mux] Model generic mux with boolean ops (Michael\n  Schaffner)\n* [prim_buf] Ensure generic primitives contain a logic cell (Michael\n  Schaffner)\n* [prim_count] improved documentation and style (Michael Tempelmeier)\n* Revert \"[dv] Replace fileset_partner flag with fileset_ast flag\"\n  (Michael Schaffner)\n* [dv] Replace fileset_partner flag with fileset_ast flag (Sharon\n  Topaz)\n* [dv] Pass data_intg_passthru to dv_base_mem (Weicai Yang)\n* [dv/prim_alert] Add V3 item to testplan (Cindy Chen)\n* [dv/prim_count] Add an assertion to check max count stable (Cindy\n  Chen)\n* [dv] Fix typo in uvmdvgen comment (Rupert Swarbrick)\n* [mem_bkdr_util] Use inverted integrity in rom_encrypt_write32_integ\n  (Rupert Swarbrick)\n* [doc/checklist] Template fix (Cindy Chen)\n* [mem_bkdr_util,rom_ctrl] Fix how we call encrypt_sram_data (Rupert\n  Swarbrick)\n* [rom/ram/xbar/otbn] Switch end-end bus integrity to inverted ECC\n  codes (Michael Schaffner)\n* [dv/prim_alert_tb] Modify the seq to ensure alert always sends\n  (Cindy Chen)\n* [dv,xcelium] Fix lowRISC/opentitan#4230: Xcelium compile error.\n  (Timothy Trippel)\n* [dv/prim_alert] Add randomization in ping request sequence (Cindy\n  Chen)\n* [prim_alert_receiver] Only check for ping requests after\n  initialization (Michael Schaffner)\n* [doc] Update D2S checklist template and description (Michael\n  Schaffner)\n* [prim_esc_receiver] Switch to standardized prim_count (Michael\n  Schaffner)\n* [prim_count] Add option to disable the connection SVA (Michael\n  Schaffner)\n* [otbn, rtl] Lint fixes (Greg Chadwick)\n* [sram/dv] Better support partial write in scb (Weicai Yang)\n* [dv/mem_bkdr_util] Fix ECC width error in OTP foundary test (Cindy\n  Chen)\n* [secded/lint] Fix lint errors (Michael Schaffner)\n* [dv/prim_esc] Add more stimulus to reach coverage goal (Cindy Chen)\n* [alert_handler] Switch to sparse fsm primitive (Michael Schaffner)\n* [prim_sparse_fsm_flop] Add a parameter to disable SVA (Michael\n  Schaffner)\n\nSigned-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>"}], "resolved_issues": [10378, 4230, 9050, 9934]}
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Jonnalagadda)\n* [sram_ctrl] Update docs (Michael Schaffner)\n* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)\n* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)\n* [dv/dvsim] Add \"testfile\" grading option (Guillermo Maturana)\n* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)\n* [dv/utils] added 6MHz to clk_freq_mhz_e (Dror Kabely)\n* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael\n  Schaffner)\n* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)\n* Fix the testplan link in dvsim code (Srikrishna Iyer)\n* [dv/dsim] Add dsim workaround for issue 242 (Guillermo Maturana)\n* [util, reggen] Support standardized cdc handling for regfile\n  (Timothy Chen)\n* [dv/shadow_reg] Align shadow_reg field update behavior (Cindy Chen)\n* [dvsim] Fix publish report summary typo (Cindy Chen)\n* [rtl/prim_alert_sender] Allow ping_req to stay high without error\n  (Cindy Chen)\n* [dvsim] Separate publish report from dvsim flow [PART3] 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The proper fix is to clear them\nfrom the environment in the dvsim command: we'll do that on the\nOpenTitan side[1] and can revert this patch once that change is vendored\nin.\n\n[1] https://github.com/lowRISC/opentitan/pull/4325"}, {"sha": "8305e5ad8cadedcdc48632b23d332508fe678387", "parents": ["4352c897c9c55906e80182a3767b7ae2689ca1b0"], "message": "Update lowrisc_ip to lowRISC/opentitan@e619fc60\n\nThis updates the vendored code from OpenTitan and fixes up patches as\nwe go. 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(Eunchan Kim)\n* [prim_lfsr] Update prim_lfsr and testbench to use correct perm width\n  (Michael Schaffner)\n* [prim_lfsr] Add script to generate seed and perm constants (Michael\n  Schaffner)\n* [dv/common] Upgrade some VCS warnings to errors (Weicai Yang)\n* [dvsim] Document and slightly improve subst_wildcards in utils.py\n  (Rupert Swarbrick)\n* [csrng/dv] Initial dv environment (Steve Nelson)\n* [sparse-fsm-encode] Update template to prevent JG compile error\n  (Michael Schaffner)\n* Gracefully shut down Verilator when software test fails (Philipp\n  Wagner)\n* [otp] fix FPV compile error (Cindy Chen)\n* [dvsim] Kill subprocesses more gracefully (Rupert Swarbrick)\n* [prim] Fix Verilator lint warnings (Pirmin Vogel)\n* [memutil] Allocate the right number of bytes in StagedMem::GetFlat()\n  (Rupert Swarbrick)\n* [memutil] Load ELF files via a staging area (Rupert Swarbrick)\n* [memutil] Add iterator and merging insertion interfaces to RangedMap\n  (Rupert Swarbrick)\n* [memutil] Factor out \"ranged map\" implementation from dpi_memutil\n  (Rupert Swarbrick)\n* [alert_handler] update alert hander ports (Timothy Chen)\n* [otp_ctrl] Update OTP output data mapping (Michael Schaffner)\n* [otp_ctrl] Split partition metadata into separate package (Michael\n  Schaffner)\n* [prim_otp] Add TL-UL regfile for testing (sim only) (Michael\n  Schaffner)\n* [memutil] Split out the non-verilator part of verilator_memutil\n  (Rupert Swarbrick)\n* [dv/common] Update DV_CHECK_* macros (Weicai Yang)\n* [dv/common] Fix testplan path (Weicai Yang)\n* [prim_assert] Fixed non-UVM part of `ASSERT_ERROR (Srikrishna Iyer)\n* [otp_ctrl] Simplify and consolidate OTP error codes (Michael\n  Schaffner)\n* [kmac] Fix critical syntax errors. (Eunchan Kim)\n* [dv/common] Move testplan from tools directory to data (Weicai Yang)\n* [dvsim] Rename verbosity wildcards to something more informative\n  (Rupert Swarbrick)\n* [dv/lfsr] Update prim_lfsr_sim_cfg.hjson and add coverage (Udi\n  Jonnalagadda)\n* [dv common] Added string check macros (Srikrishna Iyer)\n* [rtl] Use platform-agnostic log macros prim_assert (Srikrishna Iyer)\n* [dv] Minor fixups to dv_Utils_pkg (Srikrishna Iyer)\n* [dv] Fix platform-agnostic log macros (Srikrishna Iyer)\n* [checklist] Upgrade wording for D1 milestone (Scott Johnson)\n* [entropy_src/rtl] fix for dv sanity test (Mark Branstad)\n* [lint] Add option to bail out on first invalid Tcl cmd (Michael\n  Schaffner)\n* [sram_ctrl] Add first cut implementation (Michael Schaffner)\n* [prim] Fix AscentLint waiver that made the tool crash (Michael\n  Schaffner)\n* [checklists] Clean up and align HW and SW checklists (Michael\n  Schaffner)\n* [prim] Update signal name in lint waiver rule (Pirmin Vogel)\n* [flash_ctrl] Switch to new keyschedule in PRINCE (Michael Schaffner)\n* [lint] fix the waiver format (Eunchan Kim)\n* [dv] Waive lint warnings in dv_macros.svh (Srikrishna Iyer)\n* [dv common] Add platform-agnostic log macros (Srikrishna Iyer)\n* [util] Add Rust Enum Support to sparse-fsm-encode.py (Sam Elliott)\n* [util] Add C Enum Support to sparse-fsm-encode.py (Sam Elliott)\n* [sparse-fsm-encode] Expand error and help messages (Michael\n  Schaffner)\n* [dv/common] TLUL agent function coverage (Weicai Yang)\n* [dv/shadow_reg] support alert handshake checking (Cindy Chen)\n* [prim_present/otp_ctrl] Add round index state IOs to primitive\n  (Michael Schaffner)\n* [dv] Fix 2 regression failures (Weicai Yang)\n* [prim_multibit_sync] Add multibit synchronizer with consistency\n  check (Michael Schaffner)\n* [prim] Fix Lint warning for prim_slicer (Eunchan Kim)\n* [prim_generic_otp] Add TL-UL test interface stub for DV (Michael\n  Schaffner)\n* [doc] Improve documentation for common_ifs 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Enhance `DV_CHECK_MEMBER_RANDOMIZE_*` (Srikrishna Iyer)\n* [otbn] Use relative scope names for OTBN scopes (Rupert Swarbrick)\n* [verilator simutil] Add support for relative scope names to SVScoped\n  (Rupert Swarbrick)\n* [fpv/prim_packer] remove assumption (Cindy Chen)\n* [fpv/csr_assert] support all modules for CSR assert (Cindy Chen)\n* [memutil] Teach verilator_memutil to load multi-segment ELF files\n  (Rupert Swarbrick)\n* [memutil] Simplify how we read ELF files in verilator_memutil.cc\n  (Rupert Swarbrick)\n* [memutil] Add a \"verbose\" flag to detail memory loads (Rupert\n  Swarbrick)\n* [memutil] Parse all arguments before loading anything (Rupert\n  Swarbrick)\n* [memutil] Use override keyword, not virtual for overridden method\n  (Rupert Swarbrick)\n* [memutil] Use exceptions to simplify error handling (Rupert\n  Swarbrick)\n* [memutil] Store the width of memory areas in bytes, not bits (Rupert\n  Swarbrick)\n* [memutil] Allow memory locations to have associated LMAs (Rupert\n  Swarbrick)\n* [memutil] Improve type of ElfFileToBinary in verilator_memutil.cc\n  (Rupert Swarbrick)\n* [verilator simutil] Move SVScoped class into dv/verilator/cpp\n  (Rupert Swarbrick)\n* [memutil] Move static functions out of VerilatorMemUtil class\n  (Rupert Swarbrick)\n* [memutil] Run clang-format on verilator_memutil.* (Rupert Swarbrick)\n* [dv:entropy_src] Initial rng_agent and integrated into entropy_src\n  env (Steve Nelson)\n* [prim_ram_adv/fpv] fix assertion (Cindy Chen)\n* [prim_ram_1p_scr] Simplify nonce input and align to multiples of 64b\n  (Michael Schaffner)\n* [fpv/csr_assert] add csr support for regwen (Cindy Chen)\n* [prim*] Various lint fixes in the prims (Michael Schaffner)\n* [prim] remove FPV related assertions (Eunchan Kim)\n* [prim_lfsr] Add option to supply custom output permutation (Michael\n  Schaffner)\n* [dv/common] calculate addr map size in RAL (Weicai Yang)\n* [flash_ctrl] Add ECC to program / erase datapaths (Timothy Chen)\n* [otp_ctrl] First cut implementation of the OTP controller (Michael\n  Schaffner)\n* Fix invalid read in verilator_memutil (Rupert Swarbrick)\n* [doc] Don't strip markdown headings from HW checklist (Philipp\n  Wagner)\n* [site] Set lint title (Tobias Wölfel)\n* [dv/prim] add basic PRINCE testbench (Udi Jonnalagadda)\n* [flash_ctrl] Support the notion of a 'program-repair'. (Timothy\n  Chen)\n* [prim/tlul] Various small lint fixes (Michael Schaffner)\n* [dv/uvmdvgen] update dvsim and remove Makefile (Cindy Chen)\n* [util] Add script for generating sparse FSM encodings (Michael\n  Schaffner)\n* [prim] Add option to register output for interrupts (Timothy Chen)\n* [prim_otp] First cut implementation of FPGA emulation (Michael\n  Schaffner)\n* [prim_ram_1p_adv] Add 16bit ECC mode (Michael Schaffner)\n* [chip dv] Fix for failing GPIO test (Srikrishna Iyer)\n* [RTl] Generic pad wrapper default behavior fix (Srikrishna Iyer)\n* [slicer] Select partial from bitstream (Eunchan Kim)\n* [util] Don't hack __repr__ in FlowCfg (Rupert Swarbrick)\n* [util] Fix lint in dvsim.py (Rupert Swarbrick)\n* [fpv/prim_packer] Add a FPV TB (Cindy Chen)\n* [Keccak] Keccak_f implementation (Eunchan Kim)\n* [dv/csr] add common task for csr_or_field_rd_check (Cindy Chen)\n* [keccak] Add valid signal to random value (Eunchan Kim)\n* [prim] Add primitive clock divider (Timothy Chen)\n* [dv/shadow_reg] update sequence for storage error (Cindy Chen)\n* [dv/lib] clear csr_outstanding_access after reset (Cindy Chen)\n* [sw] Ensure Headers are Correctly Ordered (Sam Elliott)\n* [dv] Fix csr_rd check during reset (Weicai Yang)\n* Adding the first update to coverage methodology (Rasmus Madsen)\n* [dv] TL agent supports no clock reset (Weicai Yang)\n* [tlul/dv] Update test plan for tl errors (Weicai Yang)\n* [fpv/alert] update namings for FPV tb (Cindy Chen)\n* [keccak] Masked/Unmasked Keccak single round (Eunchan Kim)\n* [lint/prim*] Waive STAR_PORT_CONN_USE errors in generated prims\n  (Michael Schaffner)\n* [prim_usb_diff_rx] Carry over wrapper for USB diff receiver (Michael\n  Schaffner)\n\nSigned-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>"}, {"sha": "469936f66195c74f1fe91dd2f6a834c6da4fa6c1", "parents": ["8305e5ad8cadedcdc48632b23d332508fe678387"], "message": "Avoid use of the term \"sanity test\" in icache UVM testbench"}], "resolved_issues": [985, 4325]}
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It's probably better to\ndo this than to directly vendor in OpenTitan's top_pkg, because the\nlatter has information about e.g. flash memory layout, which doesn't\nreally have any meaning for Ibex."}, {"sha": "3581c01fd0a3fe5538468541da4b095d4b08c3da", "parents": ["2583edf83e151237369e6cfb8fabedcf7215a870"], "message": "Remove duplicated files from dv/uvm/core_ibex/common/utils\n\nWe now have a clock/reset interface and the dv_utils stuff vendored\nfrom OpenTitan so can delete the duplicates and point the file list at\nthe vendored files.\n\nThe only difficulty is that the clock interfaces are slightly\ndifferent, so there are a couple of minor changes to the core_ibex\ntest lib, renaming \"clk_if\" to \"clk_rst_if\" and changing how we apply\nresets.\n\nNote that the testbench (core_ibex_tb_top.sv) starts the clock and\nresets the DUT at the start of time. This is different from how other\nOpenTitan VIP does things (where the reset happens in the sequence),\nbut this is the smallest change I could make from how it worked\nbefore (where the reset happened in the clock interface itself)."}], "resolved_issues": [985]}
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+{"org": "lowRISC", "repo": "ibex", "number": 994, "state": "closed", "title": "A Yosys-based formal flow (currently targetting the ICache)", "body": "This is finally in a working shape. To use it, you need [an edalize patch](https://github.com/olofk/edalize/pull/173), but I wanted to push the work sooner rather than later. If nothing else, this might serve as proof for Olof that the edalize stuff works!\r\n\r\nIn order, the patches are:\r\n\r\n1. c39627c2 Move riscv-formal code into formal/riscv-formal\r\n\r\n   Moving some other stuff down a level so that we can put our new code in the formal/ directory.\r\n\r\n1. c1755210 A simple formal flow for the ICache based on SymbiYosys\r\n\r\n   An initial working flow, proving something reasonably trivial. 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Later\npatches will add more.\n\nThere are currently some rough edges to this flow:\n\n  (1) We use a hacky pre_build hook to run sv2v and edit the files in\n      the work tree. Among other problems, this means that the any\n      failure messages that come out of sby have bogus line numbers.\n\n  (2) Since we haven't yet got bind support in Yosys, we have to\n      include a fragment from the design itself."}, {"sha": "5183bb1b8df77100e64876de9d4a59562a38931d", "parents": ["683467b092e0083297ac81e05f0c47bd5a112799"], "message": "Formal protocol checking for icache <-> core interface\n\nThis turns out to be quite complicated, because the icache has a lot\nof different counters that all track addresses or fill buffer state.\nFor an inductive proof to go through, you need to make the relations\nbetween them explicit, which takes lots of assertions.\n\nAll of the signals defined in the formal_tb are prefixed with 'f_'.\nThis isn't strictly necessary, but it makes it much easier to see what\ncame from the design (since we are \"bound in\", our ports don't have _o\nor _i suffixes).\n\nWe add a couple of protocol assumptions:\n\nICache <-> Core:\n\n  - Branch target addresses are half-word aligned\n  - The branch_spec signal is driven if branch is\n\nICache <-> Memory:\n\n  - The bus doesn't respond unless there is an outstanding request\n  - The bus doesn't grant more than 4 billion outstanding requests(!)\n\nThere's also some protocol state tracking:\n\n  - f_addr_valid tracks whether the ICache currently has an\n    architectural address. It goes high with branch_i (which gives the\n    cache an address) and goes low when the cache completes a\n    transaction with err_o set (since the data is bad, there's no\n    notion of a \"next address\").\n\n  - f_reqs_on_bus tracks the number of requests currently outstanding\n    on the bus. This is used for the ICache <-> Memory assumptions\n    above. We have some internal assertions that check this equals the\n    sum of the \"ext\" counters minus the sum of the \"rvd\" counters.\n\nWith these assumptions, we can prove:\n\n  - Once asserted, valid_o stays high until a transaction is completed\n    by ready_i or until branch_i is asserted (which cancels the\n    transaction).\n\n  - While the transaction is pending, addr_o remains stable.\n\n  - While the transaction is pending, err_o remains stable and, if\n    err_o is asserted, so does err_plus2_o.\n\n  - While the transaction is pending, if err_o and err_plus2_o are\n    high then bottom 16 bits of the returned instruction data imply an\n    uncompressed instruction.\n\n  - While the transaction is pending, if err_o is low then the bottom\n    16 bits of the returned instruction remain stable.\n\n  - While the transaction is pending, if err_o is low and the bottom\n    16 bits of the returned instruction imply an uncompressed\n    instruction then the top 16 bits of the returned instruction\n    remain stable."}, {"sha": "7e015e73da5f34c91e49dc296cc670ee48d27f75", "parents": ["5183bb1b8df77100e64876de9d4a59562a38931d"], "message": "Add an ICacheECC parameter to ICache formal flow\n\nSatisfyingly the formal checks go through with no changes."}, {"sha": "aa4ec52f43ea39c3210530b06988295fd74df3fa", "parents": ["7e015e73da5f34c91e49dc296cc670ee48d27f75"], "message": "Add some formal cover properties for ICache\n\nAlso (and probably more interestingly) put in the tooling framework to\ndrive sby in the two different modes."}], "resolved_issues": [173]}
+{"org": "lowRISC", "repo": "ibex", "number": 1034, "state": "closed", "title": "[rtl] remove lsu_req_in_id signal", "body": "This signal aimed to ensure loads/stores completed succesfully when an\r\ninterrupt or debug request appeared at the same time they were being\r\nexecuted when the writeback stage is present. However other stall logic\r\nsuffices for this purpose (debug/interrupt will wait for instruction to\r\nunstall in ID/EX which only happens once request has been sent out, then\r\nfirst instruction of debug/interrupt handler will stall until load/store\r\nresponse has been seen based on the generic stall logic for lsu requests\r\nin the writeback stage).\r\n\r\nWith this signal in place debug single stepping was broken around loads\r\nand stores.\r\n\r\nFixes #1029\r\n\r\nThis half undoes the fix from this PR: https://github.com/lowRISC/ibex/pull/928 which was in response to this OT issue: https://github.com/lowRISC/opentitan/issues/2405\r\n\r\nI'm happy to accept this is not the correct fix but I did have a play with interrupts appearing the same cycle as a load in simple system with various delays on gnt/rvalid and it all seems to work fine. The DV interrupt tests all looked fine. The test in OT that found the original bug was broken on main yesterday (chip_uart_tx_rx) but looking at the latest nightly it seems to be fixed, so I'll have another play with that. Also realised there's some other timing scenarios I can check out with simple system.\r\n", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/1034", "id": 449384911, "node_id": "MDExOlB1bGxSZXF1ZXN0NDQ5Mzg0OTEx", "html_url": "https://github.com/lowRISC/ibex/pull/1034", "diff_url": "https://github.com/lowRISC/ibex/pull/1034.diff", "patch_url": "https://github.com/lowRISC/ibex/pull/1034.patch", "issue_url": "https://api.github.com/repos/lowRISC/ibex/issues/1034", "created_at": "2020-07-15T10:14:59+00:00", "updated_at": "2020-08-11T13:12:09+00:00", "closed_at": "2020-08-11T13:12:09+00:00", "merged_at": "2020-08-11T13:12:09+00:00", "merge_commit_sha": "21ad662418b6c4b4f3916003e9926e057bf3b2c3", "labels": [], "draft": false, "commits_url": "https://api.github.com/repos/lowRISC/ibex/pulls/1034/commits", "review_comments_url": "https://api.github.com/repos/lowRISC/ibex/pulls/1034/comments", "review_comment_url": "https://api.github.com/repos/lowRISC/ibex/pulls/comments{/number}", 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+{"org": "lowRISC", "repo": "ibex", "number": 987, "state": "closed", "title": "[dv/ibex] Add two new interrupt/debug tests", "body": "As a result of lowRISC/opentitan#2405 and lowRISC/ibex#928, this PR adds some new\r\ndirected interrupt and debug tests to check that the core behaves\r\nproperly during execution of each supported instruction when some\r\nexternal irq/debug stimulus comes in.\r\n\r\nTo do this, we use the two new functions `decode_instr(...)` and\r\n`decode_compressed_instr(...)` in `core_ibex_test_list.sv` to \"decode\"\r\nevery instruction that the `core_ibex_instr_monitor_if` sees in the ID\r\nstage of the pipeline. Once the testbench decodes an instruction that\r\nwe have not seen before, it can then drive interrupt or debug stimulus\r\ninto the core.\r\n\r\nOnce any given instruction has been detected by the testbench (and\r\nstimulus driven), it will no longer drive stimulus if this instruction\r\nis seen in the decode pipeline (e.g. if we have previously detected a\r\n`c.addi` instruction in the ID stage and have driven irq/debug stimulus,\r\nwe will no longer drive stimulus if we see another `c.addi` instruction,\r\nno matter the operands). This is to avoid driving irq/debug stimulus\r\nafter every single instruction as this will add a huge amount\r\nof simulation latency.\r\n\r\nA few notes:\r\n\r\n- From a reviewer standpoint, the actual decoding logic is a bit esoteric,\r\n  but simply just adheres to the encoding scheme defined by the official\r\n  RISC-V specification\r\n- We drive irq/debug stimulus into the core every time we see a\r\n  `wfi` instruction, as otherwise we will timeout as the core waits\r\n  infinitely for some stimulus from the outside world.\r\n- We ignore some system-level instructions (ebreak/mret/dret) and illegal\r\n  instructions for now, as driving stimulus during these instructions will\r\n  result in a nested trap, which requires special handling.\r\n- The interrupt agent was modified slightly to drive stimulus by\r\n  default on the falling edge of the clock, so this way we can \"catch\"\r\n  instructions that are in the ID pipeline for only a single cycle.\r\n- The interrupt agent was additionally modified to add a control knob \r\n  to turn off 'fast' interrupts, as there is no guarantee that a 'fast' interrupt\r\n  into Ibex will be taken, as `mie` is completely randomized.\r\n- The duration for which the testbench raises `debug_req_i` for the core\r\n  is also increased to avoid edge cases where we lower the debug line\r\n  too early (e.g. while long multicycle instructions like `div` are\r\n  executing in the ID stage).", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/987", "id": 438881253, "node_id": "MDExOlB1bGxSZXF1ZXN0NDM4ODgxMjUz", "html_url": "https://github.com/lowRISC/ibex/pull/987", "diff_url": "https://github.com/lowRISC/ibex/pull/987.diff", "patch_url": "https://github.com/lowRISC/ibex/pull/987.patch", "issue_url": "https://api.github.com/repos/lowRISC/ibex/issues/987", "created_at": "2020-06-23T23:49:02+00:00", "updated_at": "2020-07-07T00:51:01+00:00", "closed_at": "2020-07-07T00:51:00+00:00", "merged_at": "2020-07-07T00:51:00+00:00", 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["414ff7eeb0d8d227df0ed131441d08d4a8c0ad44"], "message": "[dv/ibex] Add two new interrupt/debug tests\n\nAs a result of lowRISC/opentitan#2405 and lowRISC/ibex#928 (reporting\nthat interrupts that came in while a load instruction was in the ID\nstage caused some incorrect behavior in Ibex), this PR adds some new\ndirected interrupt and debug tests to check that the core behaves\nproperly during execution of each supported instruction when some\nexternal irq/debug stimulus comes in.\n\nTo do this, we use the two new functions `decode_instr(...)` and\n`decode_compressed_instr(...)` in `core_ibex_test_list.sv` to \"decode\"\nevery instruction that the `core_ibex_instr_monitor_if` sees in the ID\nstage of the pipeline. Once the testbench decodes an instruction that\nwe have not seen before, it can then drive interrupt or debug stimulus\ninto the core.\n\nOnce any given instruction has been detected by the testbench (and\nstimulus driven), it will no longer drive stimulus if this instruction\nis seen in the decode pipeline (e.g. if we have previously detected a\n`c.addi` instruction in the ID stage and have driven irq/debug stimulus,\nwe will no longer drive stimulus if we see another `c.addi` instruction,\nno matter the operands). This is to avoid driving irq/debug stimulus\nafter every single instruction as this will add a huge unwanted amount\nof simulation latency.\n\nA few notes:\n\n- We drive irq/debug stimulus into the core every time we see a\n  `wfi` instruction, as otherwise we will timeout as the core waits\n  infinitely for some stimulus from the outside world.\n- We ignore some system-level instructions (ebreak/mret/dret) and\n  illegal instructionsfor now, as driving stimulus during these\n  instructions will result in a nested trap, which requires special\n  handling.\n- The interrupt agent was modified slightly to drive stimulus by\n  default on the falling edge of the clock, so this way we can \"catch\"\n  instructions that are in the ID pipeline for only a single cycle.\n- The duration for which the testbench raises `debug_req_i` for the core\n  is also increased to avoid edge cases where we lower the debug line\n  too early (e.g. while long multicycle instructions like `div` are\n  executing in the ID stage)."}], "resolved_issues": [928, 2405]}
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Only these unqualified signals are used to control data muxes in the EX stage.\r\n- The qualified `mult_en` and `div_en` siganls are dervied from `mult_sel` and `div_sel` and qualified as before. They are no longer used for controlling data muxes.\r\n- The regular decoder is only responsible for detecting illegal instructions related to `multdiv`. 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+{"org": "lowRISC", "repo": "ibex", "number": 894, "state": "closed", "title": "Use vendored-in primitives from OpenTitan", "body": "Instead of using copies of primitives from OpenTitan, vendor the files\nin directly from OpenTitan, and use them.\n\nBenefits:\n\n- Less potential for diverging code between OpenTitan and Ibex, causing\n  problems when importing Ibex into OT.\n\n- Use of the abstract primitives instead of the generic ones. The\n  abstract primitives are replaced during synthesis time with\n  target-dependent implementations. For simulation, nothing changes. For\n  synthesis for a given target technology (e.g. a specific ASIC or FPGA\n  technology), the primitives system can be instructed to choose\n  optimized versions (if available).\n\n  This is most relevant for the icache, which hard-coded the generic\n  SRAM primitive before. This primitive is always implemented as\n  registers. By using the abstract primitive (prim_ram_1p) instead, the\n  RAMs can be replaced with memory-compiler-generated ones if necessary.\n\nThere are no real draw-backs, but a couple points to be aware of:\n\n- Our ram_1p and ram_2p implementations are kept as wrapper around the\n  primitives, since their interface deviates slightly from the one in\n  prim_ram*. This also includes a rather unfortunate naming confusion\n  around rvalid, which means \"read data valid\" in the OpenTitan advanced\n  RAM primitives (prim_ram_1p_adv for example), but means \"ack\" in\n  PULP-derived IP and in our bus implementation.\n\n- The core_ibex UVM DV doesn't use FuseSoC to generate its file list,\n  but uses a hard-coded list in `ibex_files.f` instead. Since the\n  dynamic primitives system requires the use of FuseSoC we need to\n  provide a stop-gap until this file is removed. Issue #893 tracks\n  progress on that.\n\n- Dynamic primitives depend no a not-yet-merged feature of FuseSoC\n  (https://github.com/olofk/fusesoc/pull/391). We depend on the same\n  functionality in OpenTitan and have instructed users to use a patched\n  branch of FuseSoC for a long time through `python-requirements.txt`,\n  so no action is needed for users which are either successfully\n  interacting with the OpenTitan source code, or have followed our\n  instructions. All other users will see a reasonably descriptive error\n  message during a FuseSoC run.\n\n- This commit is massive, but there are no good ways to split it into\n  bisectable, yet small, chunks. I'm sorry. Reviewers can safely ignore\n  all code in `vendor/lowrisc_ip`, it's an import from OpenTitan.\n\n- The check_tool_requirements tooling isn't easily vendor-able from\n  OpenTitan at the moment. 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For\n  synthesis for a given target technology (e.g. a specific ASIC or FPGA\n  technology), the primitives system can be instructed to choose\n  optimized versions (if available).\n\n  This is most relevant for the icache, which hard-coded the generic\n  SRAM primitive before. This primitive is always implemented as\n  registers. By using the abstract primitive (prim_ram_1p) instead, the\n  RAMs can be replaced with memory-compiler-generated ones if necessary.\n\nThere are no real draw-backs, but a couple points to be aware of:\n\n- Our ram_1p and ram_2p implementations are kept as wrapper around the\n  primitives, since their interface deviates slightly from the one in\n  prim_ram*. This also includes a rather unfortunate naming confusion\n  around rvalid, which means \"read data valid\" in the OpenTitan advanced\n  RAM primitives (prim_ram_1p_adv for example), but means \"ack\" in\n  PULP-derived IP and in our bus implementation.\n\n- The core_ibex UVM DV doesn't use FuseSoC to generate its file list,\n  but uses a hard-coded list in `ibex_files.f` instead. Since the\n  dynamic primitives system requires the use of FuseSoC we need to\n  provide a stop-gap until this file is removed. Issue #893 tracks\n  progress on that.\n\n- Dynamic primitives depend no a not-yet-merged feature of FuseSoC\n  (https://github.com/olofk/fusesoc/pull/391). We depend on the same\n  functionality in OpenTitan and have instructed users to use a patched\n  branch of FuseSoC for a long time through `python-requirements.txt`,\n  so no action is needed for users which are either successfully\n  interacting with the OpenTitan source code, or have followed our\n  instructions. All other users will see a reasonably descriptive error\n  message during a FuseSoC run.\n\n- This commit is massive, but there are no good ways to split it into\n  bisectable, yet small, chunks. I'm sorry. Reviewers can safely ignore\n  all code in `vendor/lowrisc_ip`, it's an import from OpenTitan.\n\n- The check_tool_requirements tooling isn't easily vendor-able from\n  OpenTitan at the moment. I've filed\n  https://github.com/lowRISC/opentitan/issues/2309 to get that sorted.\n\n- The LFSR primitive doesn't have a own core file, forcing us to include\n  the catch-all `lowrisc:prim:all` core. I've filed\n  https://github.com/lowRISC/opentitan/issues/2310 to get that sorted."}], "resolved_issues": [2309, 844, 893, 2310]}
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"6384d5b3c07c8e715d3376559edc3481a4a8b2ed", "parents": ["1a9ac95715dd54ea697cb7edc32df53d187fcd8a"], "message": "Check for supported tool versions\n\nDefine supported tool versions in tool_requirements.py, and check them\nin a fusesoc run. If an unsupported tool version is found, fusesoc\noutputs an error like this:\n\n```\n$ fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core\nINFO: Preparing lowrisc:ibex:check_tool_requirements:0.1\nINFO: Preparing lowrisc:prim:assert:0.1\nINFO: Preparing lowrisc:ibex:sim_shared:0\nINFO: Preparing lowrisc:ibex:ibex_core:0.1\nINFO: Setting up project\n\nINFO: Running pre_build script check_tool_requirements\nERROR: verilator is too old: found version 4.010, need at least 4.028\nERROR: Tool requirements not fulfilled. Please update the tools and retry.\nERROR: Failed to build lowrisc:ibex:ibex_core:0.1 : pre_build script 'check_tool_requirements' exited with error code 1\n```\n\nThe only version checked at this point is Verilator, which is set\nsomewhat arbitrarily to the version used by me (and I know it works). CI\nuses a slightly newer version. As we are about to merge changes soon\nwhich require a newer Verilator version, there's not much point in\nfinding the oldest supported version right now."}, {"sha": "2a4523dffba92e193560e9b762a7c90e82b9fa20", "parents": ["6384d5b3c07c8e715d3376559edc3481a4a8b2ed"], "message": "Doc: Documented supported tool versions\n\nAdd a section on supported tools to the Ibex documentation. Populate it\nwith my knowledge about tools we've tried. That's a starting point: we\nneed to add more version numbers and other information as we collect\nmore data points.\n\nThe Verilator version is taken from the new tool_requirements.py file\nand inserted into Sphinx."}, {"sha": "64cd80b7b3f374d91084c39b8939ca556dd63ea6", "parents": ["2a4523dffba92e193560e9b762a7c90e82b9fa20"], "message": "Doc: Fix broken table in integration docs"}], "resolved_issues": [603]}
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This commits makes\n  the core wait until both transactions have completed.\n- This prevents strange behaviour caused by the lsu and controller\n  being out of sync (fixes #374)."}], "resolved_issues": [374]}
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The trace\ninformation is coming from the RVFI signals, as specified at\nhttps://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md.\n\nThe existing implementation was tailored for use in ModelSim and other\ncommercial simulators, and used SystemVerilog features which are not\nsupported in Verilator or Icarus Verilog, such as classes, queues and\nnon-standard format specifiers (e.g. the `-` specifier for right-aligned\noutput). Being unable to see an execution trace when using Verilator\nsignificantly reduced productivity and its usefulness.\n\nThis commit refactors the tracer to only use SystemVerilog constructs\nwhich are supported in Verilator. While doing so, multiple improvements\nwere made for correctness and style.\n\nMajor changes:\n\n- Improve compatibility with Verilator. Remove many non-synthesizable\n  SystemVerilog constructs, such as classes and queues.\n  Use casez instead of casex for better Verilator support (Verilator\n  doesn't support X).\n- Make the decoded output of the tracer match objdump from binutils\n  exactly. Doing so is beneficial for two reasons: we can easily\n  cross-check the decoded output from the tracer against the disassembly\n  produced by objdump (and we did that), and users don't need to get\n  used to another slighly different disassembly format.\n- A plusarg \"+ibex_tracer_file_base=ibex_my_trace\" can be used to set a\n  different basename for the trace log file.\n\nSmaller cleanups:\n\n- Remove decoding of reg-reg loads, which were leftover from a PULP\n  extension.\n- Make better use of the data available on the RVFI. Pass all of RVFI\n  to the tracer, and use the provided data instead of manually\n  recreating it, e.g. to get register data or the jump target.\n- Rename all \"instr\" abbreviations to \"insn\". \"insn\" is what RVFI uses\n  (and we cannot change that), so for consistency we now always use this\n  abbreviation across the file.\n\nAll CSR names have been imported from binutils' riscv-opc.h file, available at\nhttps://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=include/opcode/riscv-opc.h\nusing this small C program:\n\n  #include <stdio.h>\n\n  #define STR(s) #s\n\n  int main(int argc, char **argv) {\n    printf(\"unique case (csr_addr)\\n\");\n  #define DECLARE_CSR(name, csraddr) \\\n    printf(\"  12'd%d: return \\\"%s\\\";\\n\", csraddr, STR(name));\n  #include \"riscv-opc.h\"\n    printf(\"  default: return $sformatf(\\\"0x%%x\\\", csr_addr);\\n\");\n    printf(\"endcase\\n\");\n    return 0;\n  }\n\nThe RISC-V compliance test suite for the RV32 I, M, and C extensions has\nbeen executed and traced. The disassembly of all traces have been\ncompared against traces produced by objdump to ensure identical output.\n\nThis PR is based on work by Rahul Behl <raulbehl@gmail.com> in #280.\nThank you Rahul for providing a great starting point for this work!"}, {"sha": "2035583daf25e27994079b04eb1964209e4afa69", "parents": ["754c88d179c80d93460102f40f64e59df305ca1c"], "message": "Document new tracer implementation"}, {"sha": "abb377673e348d4d0420ca6154145ca4151eb56e", "parents": ["2035583daf25e27994079b04eb1964209e4afa69"], "message": "Update gitignore to include trace log file"}, {"sha": "0365408ad5096043742d5c6245e3f9e762ace162", "parents": ["abb377673e348d4d0420ca6154145ca4151eb56e"], "message": "Lint: Enable lint for ibex_core_tracing\n\nAdd fusesoc description for core with tracing enabled, implicitly\nlinting the ibex_tracer as well.\n\nRun with\n\n$ fusesoc --cores-root=. run --target=lint lowrisc:ibex:ibex_core_tracing"}, {"sha": "c6b231254a9868c89de81299abd35dc7e032acaf", "parents": ["0365408ad5096043742d5c6245e3f9e762ace162"], "message": "CI: Also check tracer in lint\n\nBy linting ibex_core_tracing, we lint all submodules as well: ibex_core\nand ibex_tracer."}], "resolved_issues": [280]}
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I've done some basic tests to ensure exceptions continue to function but if you had something more in-depth to try out that would be useful.", "url": "https://api.github.com/repos/lowRISC/ibex/pulls/335", "id": 319200287, "node_id": "MDExOlB1bGxSZXF1ZXN0MzE5MjAwMjg3", "html_url": "https://github.com/lowRISC/ibex/pull/335", "diff_url": "https://github.com/lowRISC/ibex/pull/335.diff", "patch_url": "https://github.com/lowRISC/ibex/pull/335.patch", "issue_url": "https://api.github.com/repos/lowRISC/ibex/issues/335", "created_at": "2019-09-19T10:14:34+00:00", "updated_at": "2020-05-04T13:51:33+00:00", "closed_at": "2019-10-02T14:46:28+00:00", "merged_at": "2019-10-02T14:46:27+00:00", "merge_commit_sha": "2a947c5e7fa79ea951dabcf68a566cd147d853a3", "labels": [], "draft": false, "commits_url": "https://api.github.com/repos/lowRISC/ibex/pulls/335/commits", "review_comments_url": "https://api.github.com/repos/lowRISC/ibex/pulls/335/comments", "review_comment_url": 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Thus, the handler must read the `mip` register\nto find out whether the interrupt routine has been entered because of\nthe software interrupt or the legacy interrupt.\n\nEventually, the number of legacy interrupts will be reduced to avoid\nthis overlapping, and they will be connected to the `mie` and `mip`\nCSRs directly."}, {"sha": "e426e97cfda44d8d1e3af964b32ee83f23e1e5a9", "parents": ["331694533f9fc02524846e3db60c5edc2447d4c2"], "message": "Add local fast interrupts, remove legacy interrupts\n\nThis commit adds 15 local fast interrupt lines managed through\nthe `mie` and `mip` CSRs directly, and removes the old legacy\ninterrupts including the internal controller."}, {"sha": "b168d64939d61809516406d44553ac0f9b6c3ed0", "parents": ["e426e97cfda44d8d1e3af964b32ee83f23e1e5a9"], "message": "Add non-maskeable interrupt (NMI)"}, {"sha": "a9af165cd9b8aeffce1253ab5d04b791a40f6530", "parents": ["b168d64939d61809516406d44553ac0f9b6c3ed0"], "message": "Add `mstack` CSRs for recoverable NMIs\n\nTo enable recoverable non-maskeable interrupts (NMIs), an additional\nset of registers is needed to backup `mstatus.MPP/MPIE` as well as\n`mepc` and `mcause`. This is currently not part of the RISC-V Priv\nSpec (v1.11). This commit adds these registers called `mstack` CSRs\naccording to the following proposal:\nhttps://github.com/riscv/riscv-isa-manual/issues/261\n\nThese CSRs are only accessed by the hardware and not accessible to\nsoftware running on the core."}, {"sha": "7ff5b3b4c72297c344e412431b74fe4f40a91983", "parents": ["a9af165cd9b8aeffce1253ab5d04b791a40f6530"], "message": "Update documentation of interrupt framework"}], "resolved_issues": [261]}
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The LSU valid signal is not needed inside\nthe EX block and can thus be fed directly to the ID stage."}, {"sha": "0f38d6a14594450ab34c8b7563c368d953896161", "parents": ["4243b3746df11c2863d1e7c933a9483c5b540ed2"], "message": "Multdiv: rename state signals"}, {"sha": "0e4716a397d842202dceb3bd7f691153f1df3dda", "parents": ["0f38d6a14594450ab34c8b7563c368d953896161"], "message": "Remove decoder MUX signals for jump and branch\n\nThese signals do not need to be generated by the WB FSM inside the ID\nstage and be fed back into the decoder. They simply depend on whether\nthe instruction is new (we execute for the first cycle) or not."}, {"sha": "7f31a5b5c44da7a29be2bf52665b9a7d51c4d382", "parents": ["0e4716a397d842202dceb3bd7f691153f1df3dda"], "message": "Move `jump_set` generation from WB FSM into decoder"}, {"sha": "320078a66e438b03bad1e22afac6d04fc4e1fe70", "parents": ["7f31a5b5c44da7a29be2bf52665b9a7d51c4d382"], "message": "Rework register file write data mux"}, {"sha": "bea831e52917ecfaf85ff126900bbb84896e81dc", "parents": ["320078a66e438b03bad1e22afac6d04fc4e1fe70"], "message": "Rework WB FSM in ID stage, remove combinational loop"}, {"sha": "d9be220903db2421ca163ef1e6053c9fc4307fad", "parents": ["bea831e52917ecfaf85ff126900bbb84896e81dc"], "message": "Rework ID stage and decoder\n\nThis commit moves logic directly related to the decoder from the ID\nstage into the decoder. This logic includes:\n- Generation of immediates and decoder-based mux selectors\n- Generation of register file addresses\n- CSR operand check and manipulation depending on value in `rs1`\n- Register file address check for RV32E (still disabled)\n\nThe muxes themselves stay in the ID stage as their control signals also\ndepend also on other, non-decoder-based signals (LSU, EX, WB FSM)."}, {"sha": "c98359a783a4d7280a6ce8144a0dbb4bc4af4dbc", "parents": ["d9be220903db2421ca163ef1e6053c9fc4307fad"], "message": "Cleanup CSR-related signals"}], "resolved_issues": [103]}
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If a misalgned transaction creates an error during the first\n   part of the transaction, the second part is not pushed out and\n   the transaction is aborted. Previously, the LSU tried to output\n   also the second part but did not adhere to the defined\n   protocol.\n\n2. Misaligned operations are again working correctly. Previously,\n   the generation of the byte enable and the alignment of read\n   data was broken as these operations rely on the updated\n   address from the AGU to have the same alignment as the\n   original address.\n\nThis partially resolves #121."}, {"sha": "b3ea5c72dec4a88e38b41e1aa8a06668fcd35486", "parents": ["60fc44ccba97f03c396b85f9e44418a02c2a3650"], "message": "Fix linting errors"}], "resolved_issues": [121]}
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This commit replaces\nthese masks with offsets and instead masks the input address\nbefore comparison.\n\nTo enable the synthesizer optimizing away unused counters,\nthe masks for these counters are set to zero."}, {"sha": "08a0eada23bdef78984bf4dab8df80822adcddfe", "parents": ["bdadde2e49d9eba8dd0a0c984e5a7fdb0d0892d1"], "message": "Correct performance counter increment\n\nPrior to this commit, the next counter value was not based on the\ncurrent value."}], "resolved_issues": [80]}
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values in registers rd and rs2 and writes the result to\nregister rd. C.ADD expands into add rd, rd, rs2. C.ADD is only valid\nwhen rs2̸=x0; the code points with rs2=x0 correspond to the C.JALR and\nC.EBREAK instructions. The code points with rs2̸=x0 and rd=x0 are HINTs.\n\nThis essentially says: rs2 == x0 takes precedence when decoding, that's\ninstr[6:2]. The current code was written with the assumption of\ninstr[11:7] taking precedence, thus incorrectly decoding a C.ADD HINT.\n\nFixes lowrisc/ibex#64"}, {"sha": "efa93b27945fe8b2e3dae24c674db28377f25361", "parents": ["af8ae94da0c5d96fbcfeb931bad52657c4a34973"], "message": "Fix handling of C.MV and C.JR\n\n- Decoding must give precedence to rs2 (i.e. instr_i[6:2]) to\n  switch between C.MV and C.JR.\n  \"C.MV is only valid when rs2̸=x0; the code points with rs2=x0\n   correspond to the C.JR instruction. The code points with rs2̸=x0\n   and rd=x0 are HINTs.\"\n\n- C.JR is only valid with rs1==x0. Throw an illegal instruction\n  exception if that's not the case.\n  \"C.JR is only valid when rs1̸=x0; the code point with rs1=x0\n   is reserved.\" RV32 Spec, p103\n\nAll spec references based on RISC-V Unprivileged ISA\nV20190305-Base-Ratification"}], "resolved_issues": [64, 46]}
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to revision d23da3862f95954e6374aaec787e0fb0c1878a16\n\n* fix matched_list and directed_list size comparisons (Udi\n  Jonnalagadda)\n* Add run_cmd_output for reporting all debug command lines\n  (google/riscv-dv#436) (Hai Hoang Dang)\n*  Resolve: missing pass gcc_opts from YAML for GCC compile command\n  (google/riscv-dv#435) (Hai Hoang Dang)\n* Sphinx: Add generating pdf file (google/riscv-dv#431) (Hai Hoang\n  Dang)\n* integrate directed asm_tests with yaml flow (Udi Jonnalagadda)\n* Fix running cov without arguments (google/riscv-dv#433) (Hai Hoang\n  Dang)\n* Add setup Travis CI for tracking build docs, and install\n  (google/riscv-dv#430) (Hai Hoang Dang)\n* Add handling KeyboardInterrupt for run_cmd and run_parallel_cmd\n  (google/riscv-dv#424) (Hai Hoang Dang)\n* Sphinx: add basic page for structure of the document (google/riscv-\n  dv#428) (Hai Hoang Dang)\n* README.md: Update the information relating to usage (google/riscv-\n  dv#426) (Hai Hoang Dang)\n* Add initial Sphinx docs (google/riscv-dv#427) (Hai Hoang Dang)\n* Fix typo in the testlist (google/riscv-dv#423) (taoliug)\n* Add try-except for handling KeyboardInterrupt (google/riscv-dv#421)\n  (Hai Hoang Dang)\n* Update information about instruction for running scripts\n  (google/riscv-dv#420) (Hai Hoang Dang)\n* Add vector permutation, reduction, mask instructions (google/riscv-\n  dv#422) (taoliug)\n* Python package (google/riscv-dv#419) (Hai Hoang Dang)\n* Refactor the code for cov.py (google/riscv-dv#416) (Hai Hoang Dang)\n* Update ovpsim config for vector extesion (google/riscv-dv#415)\n  (taoliug)\n* Fix coverage flow issue (google/riscv-dv#414) (taoliug)\n* Add missing license header (google/riscv-dv#412) (taoliug)\n* Fix typo in cov_test (google/riscv-dv#410) (taoliug)\n* Add vector floating point instructions (google/riscv-dv#409)\n  (taoliug)\n* Add fixed point arithmetic vector instruction (google/riscv-dv#408)\n  (taoliug)\n* cov.py: Generate error when it cannot find spike_sim directory\n  (google/riscv-dv#407) (Hai Hoang Dang)\n* Add vector CSR initialization routine (google/riscv-dv#405)\n  (taoliug)\n* Create vector extension target, add basic enums (google/riscv-\n  dv#404) (taoliug)\n* Fix qrun sim warning (google/riscv-dv#402) (taoliug)\n* Try fix qrun constraint solver issue (google/riscv-dv#401) (taoliug)\n* Fix simulation warning (google/riscv-dv#400) (taoliug)\n* run.py: Generate error for gcc compile when it cannot find assembly\n  files (google/riscv-dv#398) (Hai Hoang Dang)\n* Add numeric corner case test, misc coverage fixes (google/riscv-\n  dv#396) (taoliug)\n* Switch to new CSV format (google/riscv-dv#395) (taoliug)\n* misc fixes for the coverage model (google/riscv-dv#394) (taoliug)\n* Fix new CSV coverage flow issue (google/riscv-dv#392) (taoliug)\n* Integrate new trace CSV format with coverage flow (google/riscv-\n  dv#390) (taoliug)\n* Add experimental script for the new CSV format (google/riscv-dv#389)\n  (taoliug)\n* Support flexible running directed assembly tests (google/riscv-\n  dv#386) (Hai Hoang Dang)\n* run.py: Enhance passing argument for gen function (google/riscv-\n  dv#382) (Hai Hoang Dang)\n* Fix qrun issue, take 2 (google/riscv-dv#384) (taoliug)\n* Attempt to fix qrun issue (google/riscv-dv#383) (taoliug)\n* Fix (google/riscv-dv#381) (taoliug)\n* Fix typo (google/riscv-dv#380) (taoliug)\n* Fix qrun simulation issue (google/riscv-dv#379) (taoliug)\n* Cleaning the output directory by default. Using exist output\n  directory (google/riscv-dv#377) (Hai Hoang Dang)\n* Fix ius compilation error temporarily (google/riscv-dv#378)\n  (taoliug)\n* Functional coverage improvement (google/riscv-dv#376) (taoliug)\n* Add unaligned jump instruction support (google/riscv-dv#375)\n  (taoliug)\n* move handcoded asm_test generation into separate output directory\n  (Udi Jonnalagadda)\n* Ignore return code for ovpsim sim (google/riscv-dv#371) (taoliug)\n* Fix mie compare mismatch (google/riscv-dv#370) (taoliug)\n* Fix directory/file name for assembly test flow (google/riscv-dv#369)\n  (taoliug)\n* Fix error in README (google/riscv-dv#368) (taoliug)\n* Add sample rv32imc test (google/riscv-dv#367) (taoliug)\n* Fix typo (google/riscv-dv#366) (taoliug)\n* Support running regression with hand-coded assembly tests\n  (google/riscv-dv#365) (taoliug)\n\nSigned-off-by: Udi <udij@google.com>"}], "resolved_issues": [384, 386, 389, 390, 392, 394, 395, 396, 398, 400, 401, 402, 404, 405, 407, 408, 409, 410, 412, 414, 415, 416, 419, 420, 421, 422, 423, 424, 426, 427, 428, 430, 431, 433, 435, 436, 365, 366, 367, 368, 369, 370, 371, 375, 376, 377, 378, 379, 380, 381, 382, 383]}