[
  {
    "id": "fveval_3_2_0",
    "project_family": "temporal_delay",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "If both sig_G and sig_C are high and sig_A is high, then sig_I must not be high 5 clock cycles later.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) (sig_G && (sig_C && sig_A)) |-> ##5 (sig_I !== 1'b1)"
  },
  {
    "id": "fveval_3_3_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "It is never the case that sig_C is equal to the logical AND of sig_A and sig_H.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) ((sig_C === (sig_A && sig_H)) !== 1'b1)"
  },
  {
    "id": "fveval_3_4_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "sig_H being equal to sig_F must differ from the value of sig_J.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) ((sig_H === sig_F) !== sig_J)"
  },
  {
    "id": "fveval_3_6_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "sig_F must not be equal to 1'b1.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) (sig_F !== 1'b1)"
  },
  {
    "id": "fveval_3_9_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "If sig_C is not 1, then sig_F should be true.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) ((sig_C !== 1'b1) || sig_F)"
  },
  {
    "id": "fveval_3_10_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "Either sig_J is equal to sig_E or sig_C is true.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) ((sig_J === sig_E) || sig_C)"
  },
  {
    "id": "fveval_3_12_0",
    "project_family": "temporal_delay",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "If sig_B is less than sig_A or sig_E is true, then one cycle later, sig_F must be equal to sig_A.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) ((sig_B < sig_A) || sig_E) |-> ##1 (sig_F === sig_A)"
  },
  {
    "id": "fveval_3_14_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "Whenever sig_I is not equal to sig_G and sig_C is not 1, this holds true.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) ((sig_I !== sig_G) && (sig_C !== 1'b1))"
  },
  {
    "id": "fveval_3_15_0",
    "project_family": "temporal_delay",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "If sig_C is true, then after three clock cycles, sig_B must not be equal to 1'b1.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) sig_C |-> ##3 (~sig_B !== 1'b1)"
  },
  {
    "id": "fveval_3_18_0",
    "project_family": "temporal_delay",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "If sig_G is not equal to 1'b1, then four cycles later, sig_J must be true.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) (sig_G !== 1'b1) |-> ##4 sig_J"
  },
  {
    "id": "fveval_3_21_0",
    "project_family": "next_cycle",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "If sig_C is high or sig_D is low, then sig_J must be different from sig_E in the next cycle.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) (sig_C || !sig_D) |=> (sig_J ^ sig_E)"
  },
  {
    "id": "fveval_3_24_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "sig_G and sig_E must both be high.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) (sig_G && sig_E)"
  },
  {
    "id": "fveval_3_26_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "If sig_C is high or the exclusive OR between sig_G not equal to sig_D and sig_E is true, the property holds.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) (sig_C || ((sig_G !== sig_D) ^ sig_E))"
  },
  {
    "id": "fveval_3_27_0",
    "project_family": "boolean_relation",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "sig_H is high and the logical AND of sig_I and sig_F is equal to sig_B.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) (sig_H && ((sig_I && sig_F) === sig_B))"
  },
  {
    "id": "fveval_3_29_0",
    "project_family": "next_cycle",
    "module": "fveval_scalar_context",
    "rtl": "module fveval_scalar_context(input logic clk, input logic sig_A, sig_B, sig_C, sig_D, sig_E, sig_F, sig_G, sig_H, sig_I, sig_J); endmodule",
    "requirements": "When sig_D is true, sig_F must be true on the following clock cycle.",
    "allowed_signals": ["clk", "sig_A", "sig_B", "sig_C", "sig_D", "sig_E", "sig_F", "sig_G", "sig_H", "sig_I", "sig_J"],
    "clock": "clk",
    "reference_property": "@(posedge clk) sig_D |=> sig_F"
  }
]