{"family_id": "arbiter_0008", "category": "arbiter", "description": "Three-client fixed-priority arbiter with one-cycle grants.", "rtl_variant": "canonical_case.sv", "rtl": "module arbiter_0008_canonical_case (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire req2,\n output reg grant0,\n output reg grant1,\n output reg grant2\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] G0 = 2'd1;\n localparam [1:0] G1 = 2'd2;\n localparam [1:0] G2 = 2'd3;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n IDLE: next_state = (req0) ? G0 : ((!req0 && req1) ? G1 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE))));\n G0: next_state = IDLE;\n G1: next_state = IDLE;\n G2: next_state = IDLE;\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n grant2 = 1'b0;\n case (state)\n IDLE: begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n grant2 = 1'b0;\n end\n G0: begin\n grant0 = 1'b1;\n grant1 = 1'b0;\n grant2 = 1'b0;\n end\n G1: begin\n grant0 = 1'b0;\n grant1 = 1'b1;\n grant2 = 1'b0;\n end\n G2: begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n grant2 = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"arbiter_0008\",\n \"category\": \"arbiter\",\n \"template\": \"three_client_fixed\",\n \"description\": \"Three-client fixed-priority arbiter with one-cycle grants.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req0\",\n \"req1\",\n \"req2\"\n ],\n \"outputs\": [\n \"grant0\",\n \"grant1\",\n \"grant2\"\n ],\n \"states\": [\n \"IDLE\",\n \"G0\",\n \"G1\",\n \"G2\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"grant0\": 0,\n \"grant1\": 0,\n \"grant2\": 0\n },\n \"G0\": {\n \"grant0\": 1,\n \"grant1\": 0,\n \"grant2\": 0\n },\n \"G1\": {\n \"grant0\": 0,\n \"grant1\": 1,\n \"grant2\": 0\n },\n \"G2\": {\n \"grant0\": 0,\n \"grant1\": 0,\n \"grant2\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1 && req2\",\n \"to\": \"G2\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1 && !req2\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G2\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1, grant2})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (req0)\",\n \"consequent\": \"grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G2 when !req0 && !req1 && req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)\",\n \"consequent\": \"!grant0 && !grant1 && grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1 && !req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when true\",\n \"antecedent\": \"grant0 && !grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G2 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && !grant1 && grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req0\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && req1\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && !req1 && req2\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: arbiter_0008\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({grant0, grant1, grant2}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!grant0 && !grant1 && !grant2));\n\n// P3_T1: IDLE transitions to G0 when req0.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (req0)) |=> (grant0 && !grant1 && !grant2));\n\n// P4_T2: IDLE transitions to G1 when !req0 && req1.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && req1)) |=> (!grant0 && grant1 && !grant2));\n\n// P5_T3: IDLE transitions to G2 when !req0 && !req1 && req2.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)) |=> (!grant0 && !grant1 && grant2));\n\n// P6_T4: IDLE transitions to IDLE when !req0 && !req1 && !req2.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)) |=> (!grant0 && !grant1 && !grant2));\n\n// P7_T5: G0 transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (grant0 && !grant1 && !grant2) |=> (!grant0 && !grant1 && !grant2));\n\n// P8_T6: G1 transitions to IDLE when true.\np_t6: assert property (@(posedge clk) disable iff (rst)\n (!grant0 && grant1 && !grant2) |=> (!grant0 && !grant1 && !grant2));\n\n// P9_T7: G2 transitions to IDLE when true.\np_t7: assert property (@(posedge clk) disable iff (rst)\n (!grant0 && !grant1 && grant2) |=> (!grant0 && !grant1 && !grant2));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1, grant2})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (req0)\",\n \"consequent\": \"grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G2 when !req0 && !req1 && req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)\",\n \"consequent\": \"!grant0 && !grant1 && grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1 && !req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when true\",\n \"antecedent\": \"grant0 && !grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G2 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && !grant1 && grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module arbiter_0008_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req0 && req1) ? G1 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module arbiter_0008_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module arbiter_0008_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && req1) ? G1 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "arbiter_0008", "category": "arbiter", "description": "Three-client fixed-priority arbiter with one-cycle grants.", "rtl_variant": "onehot_case.sv", "rtl": "module arbiter_0008_onehot_case (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire req2,\n output reg grant0,\n output reg grant1,\n output reg grant2\n);\n localparam [3:0] IDLE = 4'b0001;\n localparam [3:0] G0 = 4'b0010;\n localparam [3:0] G1 = 4'b0100;\n localparam [3:0] G2 = 4'b1000;\n\n reg [3:0] state, next_state;\n\n always @* begin\n next_state = IDLE;\n case (state)\n IDLE: next_state = (req0) ? G0 : ((!req0 && req1) ? G1 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE))));\n G0: next_state = IDLE;\n G1: next_state = IDLE;\n G2: next_state = IDLE;\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n grant0 = (state == G0);\n grant1 = (state == G1);\n grant2 = (state == G2);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"arbiter_0008\",\n \"category\": \"arbiter\",\n \"template\": \"three_client_fixed\",\n \"description\": \"Three-client fixed-priority arbiter with one-cycle grants.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req0\",\n \"req1\",\n \"req2\"\n ],\n \"outputs\": [\n \"grant0\",\n \"grant1\",\n \"grant2\"\n ],\n \"states\": [\n \"IDLE\",\n \"G0\",\n \"G1\",\n \"G2\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"grant0\": 0,\n \"grant1\": 0,\n \"grant2\": 0\n },\n \"G0\": {\n \"grant0\": 1,\n \"grant1\": 0,\n \"grant2\": 0\n },\n \"G1\": {\n \"grant0\": 0,\n \"grant1\": 1,\n \"grant2\": 0\n },\n \"G2\": {\n \"grant0\": 0,\n \"grant1\": 0,\n \"grant2\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1 && req2\",\n \"to\": \"G2\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1 && !req2\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G2\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1, grant2})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (req0)\",\n \"consequent\": \"grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G2 when !req0 && !req1 && req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)\",\n \"consequent\": \"!grant0 && !grant1 && grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1 && !req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when true\",\n \"antecedent\": \"grant0 && !grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G2 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && !grant1 && grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req0\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && req1\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && !req1 && req2\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: arbiter_0008\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({grant0, grant1, grant2}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!grant0 && !grant1 && !grant2));\n\n// P3_T1: IDLE transitions to G0 when req0.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (req0)) |=> (grant0 && !grant1 && !grant2));\n\n// P4_T2: IDLE transitions to G1 when !req0 && req1.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && req1)) |=> (!grant0 && grant1 && !grant2));\n\n// P5_T3: IDLE transitions to G2 when !req0 && !req1 && req2.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)) |=> (!grant0 && !grant1 && grant2));\n\n// P6_T4: IDLE transitions to IDLE when !req0 && !req1 && !req2.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)) |=> (!grant0 && !grant1 && !grant2));\n\n// P7_T5: G0 transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (grant0 && !grant1 && !grant2) |=> (!grant0 && !grant1 && !grant2));\n\n// P8_T6: G1 transitions to IDLE when true.\np_t6: assert property (@(posedge clk) disable iff (rst)\n (!grant0 && grant1 && !grant2) |=> (!grant0 && !grant1 && !grant2));\n\n// P9_T7: G2 transitions to IDLE when true.\np_t7: assert property (@(posedge clk) disable iff (rst)\n (!grant0 && !grant1 && grant2) |=> (!grant0 && !grant1 && !grant2));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1, grant2})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (req0)\",\n \"consequent\": \"grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G2 when !req0 && !req1 && req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)\",\n \"consequent\": \"!grant0 && !grant1 && grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1 && !req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when true\",\n \"antecedent\": \"grant0 && !grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G2 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && !grant1 && grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module arbiter_0008_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req0 && req1) ? G1 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module arbiter_0008_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module arbiter_0008_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && req1) ? G1 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "arbiter_0008", "category": "arbiter", "description": "Three-client fixed-priority arbiter with one-cycle grants.", "rtl_variant": "nested_if.sv", "rtl": "module arbiter_0008_nested_if (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire req2,\n output wire grant0,\n output wire grant1,\n output wire grant2\n);\n localparam [1:0] S_IDLE = 2'd0;\n localparam [1:0] S_G0 = 2'd1;\n localparam [1:0] S_G1 = 2'd2;\n localparam [1:0] S_G2 = 2'd3;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_IDLE;\n end else begin\n if (state == S_IDLE) begin\n state <= (req0) ? S_G0 : ((!req0 && req1) ? S_G1 : ((!req0 && !req1 && req2) ? S_G2 : ((!req0 && !req1 && !req2) ? S_IDLE : (S_IDLE))));\n end\n else if (state == S_G0) begin\n state <= S_IDLE;\n end\n else if (state == S_G1) begin\n state <= S_IDLE;\n end\n else if (state == S_G2) begin\n state <= S_IDLE;\n end\n else begin\n state <= S_IDLE;\n end\n end\n end\n\n assign grant0 = (state == S_G0);\n assign grant1 = (state == S_G1);\n assign grant2 = (state == S_G2);\nendmodule\n", "spec_json": "{\n \"design_id\": \"arbiter_0008\",\n \"category\": \"arbiter\",\n \"template\": \"three_client_fixed\",\n \"description\": \"Three-client fixed-priority arbiter with one-cycle grants.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req0\",\n \"req1\",\n \"req2\"\n ],\n \"outputs\": [\n \"grant0\",\n \"grant1\",\n \"grant2\"\n ],\n \"states\": [\n \"IDLE\",\n \"G0\",\n \"G1\",\n \"G2\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"grant0\": 0,\n \"grant1\": 0,\n \"grant2\": 0\n },\n \"G0\": {\n \"grant0\": 1,\n \"grant1\": 0,\n \"grant2\": 0\n },\n \"G1\": {\n \"grant0\": 0,\n \"grant1\": 1,\n \"grant2\": 0\n },\n \"G2\": {\n \"grant0\": 0,\n \"grant1\": 0,\n \"grant2\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1 && req2\",\n \"to\": \"G2\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1 && !req2\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G2\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1, grant2})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (req0)\",\n \"consequent\": \"grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G2 when !req0 && !req1 && req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)\",\n \"consequent\": \"!grant0 && !grant1 && grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1 && !req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when true\",\n \"antecedent\": \"grant0 && !grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G2 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && !grant1 && grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req0\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && req1\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && !req1 && req2\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: arbiter_0008\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({grant0, grant1, grant2}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!grant0 && !grant1 && !grant2));\n\n// P3_T1: IDLE transitions to G0 when req0.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (req0)) |=> (grant0 && !grant1 && !grant2));\n\n// P4_T2: IDLE transitions to G1 when !req0 && req1.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && req1)) |=> (!grant0 && grant1 && !grant2));\n\n// P5_T3: IDLE transitions to G2 when !req0 && !req1 && req2.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)) |=> (!grant0 && !grant1 && grant2));\n\n// P6_T4: IDLE transitions to IDLE when !req0 && !req1 && !req2.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)) |=> (!grant0 && !grant1 && !grant2));\n\n// P7_T5: G0 transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (grant0 && !grant1 && !grant2) |=> (!grant0 && !grant1 && !grant2));\n\n// P8_T6: G1 transitions to IDLE when true.\np_t6: assert property (@(posedge clk) disable iff (rst)\n (!grant0 && grant1 && !grant2) |=> (!grant0 && !grant1 && !grant2));\n\n// P9_T7: G2 transitions to IDLE when true.\np_t7: assert property (@(posedge clk) disable iff (rst)\n (!grant0 && !grant1 && grant2) |=> (!grant0 && !grant1 && !grant2));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1, grant2})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (req0)\",\n \"consequent\": \"grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G2 when !req0 && !req1 && req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)\",\n \"consequent\": \"!grant0 && !grant1 && grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1 && !req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when true\",\n \"antecedent\": \"grant0 && !grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G2 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && !grant1 && grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module arbiter_0008_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req0 && req1) ? G1 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module arbiter_0008_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module arbiter_0008_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && req1) ? G1 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "arbiter_0008", "category": "arbiter", "description": "Three-client fixed-priority arbiter with one-cycle grants.", "rtl_variant": "factored_flags.sv", "rtl": "module arbiter_0008_factored_flags (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire req2,\n output reg grant0,\n output reg grant1,\n output reg grant2\n);\n localparam [1:0] F_IDLE = 2'd0;\n localparam [1:0] F_G0 = 2'd1;\n localparam [1:0] F_G1 = 2'd2;\n localparam [1:0] F_G2 = 2'd3;\n\n reg [1:0] state, next_state;\n\n wire guard_idle_0 = (req0);\n wire guard_idle_1 = (!req0 && req1);\n wire guard_idle_2 = (!req0 && !req1 && req2);\n wire guard_idle_3 = (!req0 && !req1 && !req2);\n\n always @* begin\n next_state = state;\n case (state)\n F_IDLE: begin\n if (guard_idle_0)\n next_state = F_G0;\n else if (guard_idle_1)\n next_state = F_G1;\n else if (guard_idle_2)\n next_state = F_G2;\n else if (guard_idle_3)\n next_state = F_IDLE;\n end\n F_G0: begin\n next_state = F_IDLE;\n end\n F_G1: begin\n next_state = F_IDLE;\n end\n F_G2: begin\n next_state = F_IDLE;\n end\n default: next_state = F_IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n grant2 = 1'b0;\n case (state)\n F_IDLE: begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n grant2 = 1'b0;\n end\n F_G0: begin\n grant0 = 1'b1;\n grant1 = 1'b0;\n grant2 = 1'b0;\n end\n F_G1: begin\n grant0 = 1'b0;\n grant1 = 1'b1;\n grant2 = 1'b0;\n end\n F_G2: begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n grant2 = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"arbiter_0008\",\n \"category\": \"arbiter\",\n \"template\": \"three_client_fixed\",\n \"description\": \"Three-client fixed-priority arbiter with one-cycle grants.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req0\",\n \"req1\",\n \"req2\"\n ],\n \"outputs\": [\n \"grant0\",\n \"grant1\",\n \"grant2\"\n ],\n \"states\": [\n \"IDLE\",\n \"G0\",\n \"G1\",\n \"G2\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"grant0\": 0,\n \"grant1\": 0,\n \"grant2\": 0\n },\n \"G0\": {\n \"grant0\": 1,\n \"grant1\": 0,\n \"grant2\": 0\n },\n \"G1\": {\n \"grant0\": 0,\n \"grant1\": 1,\n \"grant2\": 0\n },\n \"G2\": {\n \"grant0\": 0,\n \"grant1\": 0,\n \"grant2\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1 && req2\",\n \"to\": \"G2\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1 && !req2\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G2\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1, grant2})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (req0)\",\n \"consequent\": \"grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G2 when !req0 && !req1 && req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)\",\n \"consequent\": \"!grant0 && !grant1 && grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1 && !req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when true\",\n \"antecedent\": \"grant0 && !grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G2 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && !grant1 && grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req0\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && req1\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && !req1 && req2\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: arbiter_0008\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({grant0, grant1, grant2}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!grant0 && !grant1 && !grant2));\n\n// P3_T1: IDLE transitions to G0 when req0.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (req0)) |=> (grant0 && !grant1 && !grant2));\n\n// P4_T2: IDLE transitions to G1 when !req0 && req1.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && req1)) |=> (!grant0 && grant1 && !grant2));\n\n// P5_T3: IDLE transitions to G2 when !req0 && !req1 && req2.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)) |=> (!grant0 && !grant1 && grant2));\n\n// P6_T4: IDLE transitions to IDLE when !req0 && !req1 && !req2.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)) |=> (!grant0 && !grant1 && !grant2));\n\n// P7_T5: G0 transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (grant0 && !grant1 && !grant2) |=> (!grant0 && !grant1 && !grant2));\n\n// P8_T6: G1 transitions to IDLE when true.\np_t6: assert property (@(posedge clk) disable iff (rst)\n (!grant0 && grant1 && !grant2) |=> (!grant0 && !grant1 && !grant2));\n\n// P9_T7: G2 transitions to IDLE when true.\np_t7: assert property (@(posedge clk) disable iff (rst)\n (!grant0 && !grant1 && grant2) |=> (!grant0 && !grant1 && !grant2));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1, grant2})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (req0)\",\n \"consequent\": \"grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G2 when !req0 && !req1 && req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && req2)\",\n \"consequent\": \"!grant0 && !grant1 && grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1 && !req2\",\n \"antecedent\": \"(!grant0 && !grant1 && !grant2) && (!req0 && !req1 && !req2)\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when true\",\n \"antecedent\": \"grant0 && !grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && grant1 && !grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G2 transitions to IDLE when true\",\n \"antecedent\": \"!grant0 && !grant1 && grant2\",\n \"consequent\": \"!grant0 && !grant1 && !grant2\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module arbiter_0008_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req0 && req1) ? G1 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module arbiter_0008_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && !req1 && req2) ? G2 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module arbiter_0008_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire req2,\\n output reg grant0,\\n output reg grant1,\\n output reg grant2\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n localparam [1:0] G2 = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && req1) ? G1 : ((!req0 && !req1 && !req2) ? IDLE : (IDLE)));\\n G0: next_state = IDLE;\\n G1: next_state = IDLE;\\n G2: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n grant2 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n grant2 = 1'b0;\\n end\\n G2: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n grant2 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "arbiter_0007", "category": "arbiter", "description": "Two-client arbiter gives req0 priority after idle and req1 priority after serving req0.", "rtl_variant": "canonical_case.sv", "rtl": "module arbiter_0007_canonical_case (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire done,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] G0 = 2'd1;\n localparam [1:0] G1 = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n IDLE: next_state = (req0) ? G0 : ((!req0 && req1) ? G1 : ((!req0 && !req1) ? IDLE : (IDLE)));\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n case (state)\n IDLE: begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n end\n G0: begin\n grant0 = 1'b1;\n grant1 = 1'b0;\n end\n G1: begin\n grant0 = 1'b0;\n grant1 = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"arbiter_0007\",\n \"category\": \"arbiter\",\n \"template\": \"grant0_then_grant1\",\n \"description\": \"Two-client arbiter gives req0 priority after idle and req1 priority after serving req0.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req0\",\n \"req1\",\n \"done\"\n ],\n \"outputs\": [\n \"grant0\",\n \"grant1\"\n ],\n \"states\": [\n \"IDLE\",\n \"G0\",\n \"G1\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"grant0\": 0,\n \"grant1\": 0\n },\n \"G0\": {\n \"grant0\": 1,\n \"grant1\": 0\n },\n \"G1\": {\n \"grant0\": 0,\n \"grant1\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"done && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"done && !req1\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"!done\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"done && req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"done && !req0\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"!done\",\n \"to\": \"G1\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1) && (req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G1 when done && req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when done && !req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G0 when !done\",\n \"antecedent\": \"(grant0 && !grant1) && (!done)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G0 when done && req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when done && !req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && !req0)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G1 when !done\",\n \"antecedent\": \"(!grant0 && grant1) && (!done)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req0\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && req1\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"G0\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: arbiter_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({grant0, grant1}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!grant0 && !grant1));\n\n// P3_T1: IDLE transitions to G0 when req0.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (req0)) |=> (grant0 && !grant1));\n\n// P4_T2: IDLE transitions to G1 when !req0 && req1.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (!req0 && req1)) |=> (!grant0 && grant1));\n\n// P5_T3: IDLE transitions to IDLE when !req0 && !req1.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (!req0 && !req1)) |=> (!grant0 && !grant1));\n\n// P6_T4: G0 transitions to G1 when done && req1.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (done && req1)) |=> (!grant0 && grant1));\n\n// P7_T5: G0 transitions to IDLE when done && !req1.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (done && !req1)) |=> (!grant0 && !grant1));\n\n// P8_T6: G0 transitions to G0 when !done.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (!done)) |=> (grant0 && !grant1));\n\n// P9_T7: G1 transitions to G0 when done && req0.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (done && req0)) |=> (grant0 && !grant1));\n\n// P10_T8: G1 transitions to IDLE when done && !req0.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (done && !req0)) |=> (!grant0 && !grant1));\n\n// P11_T9: G1 transitions to G1 when !done.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (!done)) |=> (!grant0 && grant1));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1) && (req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G1 when done && req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when done && !req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G0 when !done\",\n \"antecedent\": \"(grant0 && !grant1) && (!done)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G0 when done && req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when done && !req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && !req0)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G1 when !done\",\n \"antecedent\": \"(!grant0 && grant1) && (!done)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module arbiter_0007_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req0 && req1) ? G1 : ((!req0 && !req1) ? IDLE : (IDLE));\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module arbiter_0007_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && !req1) ? IDLE : (IDLE));\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module arbiter_0007_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = G0;\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "arbiter_0007", "category": "arbiter", "description": "Two-client arbiter gives req0 priority after idle and req1 priority after serving req0.", "rtl_variant": "onehot_case.sv", "rtl": "module arbiter_0007_onehot_case (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire done,\n output reg grant0,\n output reg grant1\n);\n localparam [2:0] IDLE = 3'b001;\n localparam [2:0] G0 = 3'b010;\n localparam [2:0] G1 = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = IDLE;\n case (state)\n IDLE: next_state = (req0) ? G0 : ((!req0 && req1) ? G1 : ((!req0 && !req1) ? IDLE : (IDLE)));\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n grant0 = (state == G0);\n grant1 = (state == G1);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"arbiter_0007\",\n \"category\": \"arbiter\",\n \"template\": \"grant0_then_grant1\",\n \"description\": \"Two-client arbiter gives req0 priority after idle and req1 priority after serving req0.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req0\",\n \"req1\",\n \"done\"\n ],\n \"outputs\": [\n \"grant0\",\n \"grant1\"\n ],\n \"states\": [\n \"IDLE\",\n \"G0\",\n \"G1\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"grant0\": 0,\n \"grant1\": 0\n },\n \"G0\": {\n \"grant0\": 1,\n \"grant1\": 0\n },\n \"G1\": {\n \"grant0\": 0,\n \"grant1\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"done && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"done && !req1\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"!done\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"done && req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"done && !req0\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"!done\",\n \"to\": \"G1\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1) && (req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G1 when done && req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when done && !req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G0 when !done\",\n \"antecedent\": \"(grant0 && !grant1) && (!done)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G0 when done && req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when done && !req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && !req0)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G1 when !done\",\n \"antecedent\": \"(!grant0 && grant1) && (!done)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req0\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && req1\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"G0\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: arbiter_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({grant0, grant1}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!grant0 && !grant1));\n\n// P3_T1: IDLE transitions to G0 when req0.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (req0)) |=> (grant0 && !grant1));\n\n// P4_T2: IDLE transitions to G1 when !req0 && req1.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (!req0 && req1)) |=> (!grant0 && grant1));\n\n// P5_T3: IDLE transitions to IDLE when !req0 && !req1.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (!req0 && !req1)) |=> (!grant0 && !grant1));\n\n// P6_T4: G0 transitions to G1 when done && req1.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (done && req1)) |=> (!grant0 && grant1));\n\n// P7_T5: G0 transitions to IDLE when done && !req1.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (done && !req1)) |=> (!grant0 && !grant1));\n\n// P8_T6: G0 transitions to G0 when !done.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (!done)) |=> (grant0 && !grant1));\n\n// P9_T7: G1 transitions to G0 when done && req0.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (done && req0)) |=> (grant0 && !grant1));\n\n// P10_T8: G1 transitions to IDLE when done && !req0.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (done && !req0)) |=> (!grant0 && !grant1));\n\n// P11_T9: G1 transitions to G1 when !done.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (!done)) |=> (!grant0 && grant1));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1) && (req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G1 when done && req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when done && !req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G0 when !done\",\n \"antecedent\": \"(grant0 && !grant1) && (!done)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G0 when done && req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when done && !req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && !req0)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G1 when !done\",\n \"antecedent\": \"(!grant0 && grant1) && (!done)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module arbiter_0007_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req0 && req1) ? G1 : ((!req0 && !req1) ? IDLE : (IDLE));\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module arbiter_0007_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && !req1) ? IDLE : (IDLE));\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module arbiter_0007_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = G0;\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "arbiter_0007", "category": "arbiter", "description": "Two-client arbiter gives req0 priority after idle and req1 priority after serving req0.", "rtl_variant": "nested_if.sv", "rtl": "module arbiter_0007_nested_if (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire done,\n output wire grant0,\n output wire grant1\n);\n localparam [1:0] S_IDLE = 2'd0;\n localparam [1:0] S_G0 = 2'd1;\n localparam [1:0] S_G1 = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_IDLE;\n end else begin\n if (state == S_IDLE) begin\n state <= (req0) ? S_G0 : ((!req0 && req1) ? S_G1 : ((!req0 && !req1) ? S_IDLE : (S_IDLE)));\n end\n else if (state == S_G0) begin\n state <= (done && req1) ? S_G1 : ((done && !req1) ? S_IDLE : ((!done) ? S_G0 : (S_G0)));\n end\n else if (state == S_G1) begin\n state <= (done && req0) ? S_G0 : ((done && !req0) ? S_IDLE : ((!done) ? S_G1 : (S_G1)));\n end\n else begin\n state <= S_IDLE;\n end\n end\n end\n\n assign grant0 = (state == S_G0);\n assign grant1 = (state == S_G1);\nendmodule\n", "spec_json": "{\n \"design_id\": \"arbiter_0007\",\n \"category\": \"arbiter\",\n \"template\": \"grant0_then_grant1\",\n \"description\": \"Two-client arbiter gives req0 priority after idle and req1 priority after serving req0.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req0\",\n \"req1\",\n \"done\"\n ],\n \"outputs\": [\n \"grant0\",\n \"grant1\"\n ],\n \"states\": [\n \"IDLE\",\n \"G0\",\n \"G1\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"grant0\": 0,\n \"grant1\": 0\n },\n \"G0\": {\n \"grant0\": 1,\n \"grant1\": 0\n },\n \"G1\": {\n \"grant0\": 0,\n \"grant1\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"done && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"done && !req1\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"!done\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"done && req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"done && !req0\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"!done\",\n \"to\": \"G1\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1) && (req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G1 when done && req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when done && !req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G0 when !done\",\n \"antecedent\": \"(grant0 && !grant1) && (!done)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G0 when done && req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when done && !req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && !req0)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G1 when !done\",\n \"antecedent\": \"(!grant0 && grant1) && (!done)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req0\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && req1\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"G0\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: arbiter_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({grant0, grant1}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!grant0 && !grant1));\n\n// P3_T1: IDLE transitions to G0 when req0.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (req0)) |=> (grant0 && !grant1));\n\n// P4_T2: IDLE transitions to G1 when !req0 && req1.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (!req0 && req1)) |=> (!grant0 && grant1));\n\n// P5_T3: IDLE transitions to IDLE when !req0 && !req1.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (!req0 && !req1)) |=> (!grant0 && !grant1));\n\n// P6_T4: G0 transitions to G1 when done && req1.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (done && req1)) |=> (!grant0 && grant1));\n\n// P7_T5: G0 transitions to IDLE when done && !req1.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (done && !req1)) |=> (!grant0 && !grant1));\n\n// P8_T6: G0 transitions to G0 when !done.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (!done)) |=> (grant0 && !grant1));\n\n// P9_T7: G1 transitions to G0 when done && req0.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (done && req0)) |=> (grant0 && !grant1));\n\n// P10_T8: G1 transitions to IDLE when done && !req0.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (done && !req0)) |=> (!grant0 && !grant1));\n\n// P11_T9: G1 transitions to G1 when !done.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (!done)) |=> (!grant0 && grant1));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1) && (req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G1 when done && req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when done && !req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G0 when !done\",\n \"antecedent\": \"(grant0 && !grant1) && (!done)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G0 when done && req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when done && !req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && !req0)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G1 when !done\",\n \"antecedent\": \"(!grant0 && grant1) && (!done)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module arbiter_0007_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req0 && req1) ? G1 : ((!req0 && !req1) ? IDLE : (IDLE));\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module arbiter_0007_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && !req1) ? IDLE : (IDLE));\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module arbiter_0007_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = G0;\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "arbiter_0007", "category": "arbiter", "description": "Two-client arbiter gives req0 priority after idle and req1 priority after serving req0.", "rtl_variant": "factored_flags.sv", "rtl": "module arbiter_0007_factored_flags (\n input wire clk,\n input wire rst,\n input wire req0,\n input wire req1,\n input wire done,\n output reg grant0,\n output reg grant1\n);\n localparam [1:0] F_IDLE = 2'd0;\n localparam [1:0] F_G0 = 2'd1;\n localparam [1:0] F_G1 = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_idle_0 = (req0);\n wire guard_idle_1 = (!req0 && req1);\n wire guard_idle_2 = (!req0 && !req1);\n wire guard_g0_0 = (done && req1);\n wire guard_g0_1 = (done && !req1);\n wire guard_g0_2 = (!done);\n wire guard_g1_0 = (done && req0);\n wire guard_g1_1 = (done && !req0);\n wire guard_g1_2 = (!done);\n\n always @* begin\n next_state = state;\n case (state)\n F_IDLE: begin\n if (guard_idle_0)\n next_state = F_G0;\n else if (guard_idle_1)\n next_state = F_G1;\n else if (guard_idle_2)\n next_state = F_IDLE;\n end\n F_G0: begin\n if (guard_g0_0)\n next_state = F_G1;\n else if (guard_g0_1)\n next_state = F_IDLE;\n else if (guard_g0_2)\n next_state = F_G0;\n end\n F_G1: begin\n if (guard_g1_0)\n next_state = F_G0;\n else if (guard_g1_1)\n next_state = F_IDLE;\n else if (guard_g1_2)\n next_state = F_G1;\n end\n default: next_state = F_IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n case (state)\n F_IDLE: begin\n grant0 = 1'b0;\n grant1 = 1'b0;\n end\n F_G0: begin\n grant0 = 1'b1;\n grant1 = 1'b0;\n end\n F_G1: begin\n grant0 = 1'b0;\n grant1 = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"arbiter_0007\",\n \"category\": \"arbiter\",\n \"template\": \"grant0_then_grant1\",\n \"description\": \"Two-client arbiter gives req0 priority after idle and req1 priority after serving req0.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req0\",\n \"req1\",\n \"done\"\n ],\n \"outputs\": [\n \"grant0\",\n \"grant1\"\n ],\n \"states\": [\n \"IDLE\",\n \"G0\",\n \"G1\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"grant0\": 0,\n \"grant1\": 0\n },\n \"G0\": {\n \"grant0\": 1,\n \"grant1\": 0\n },\n \"G1\": {\n \"grant0\": 0,\n \"grant1\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req0 && !req1\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"done && req1\",\n \"to\": \"G1\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"done && !req1\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G0\",\n \"when\": \"!done\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"done && req0\",\n \"to\": \"G0\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"done && !req0\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"G1\",\n \"when\": \"!done\",\n \"to\": \"G1\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1) && (req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G1 when done && req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when done && !req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G0 when !done\",\n \"antecedent\": \"(grant0 && !grant1) && (!done)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G0 when done && req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when done && !req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && !req0)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G1 when !done\",\n \"antecedent\": \"(!grant0 && grant1) && (!done)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req0\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"!req0 && req1\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"G0\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: arbiter_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({grant0, grant1}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!grant0 && !grant1));\n\n// P3_T1: IDLE transitions to G0 when req0.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (req0)) |=> (grant0 && !grant1));\n\n// P4_T2: IDLE transitions to G1 when !req0 && req1.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (!req0 && req1)) |=> (!grant0 && grant1));\n\n// P5_T3: IDLE transitions to IDLE when !req0 && !req1.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && !grant1) && (!req0 && !req1)) |=> (!grant0 && !grant1));\n\n// P6_T4: G0 transitions to G1 when done && req1.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (done && req1)) |=> (!grant0 && grant1));\n\n// P7_T5: G0 transitions to IDLE when done && !req1.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (done && !req1)) |=> (!grant0 && !grant1));\n\n// P8_T6: G0 transitions to G0 when !done.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((grant0 && !grant1) && (!done)) |=> (grant0 && !grant1));\n\n// P9_T7: G1 transitions to G0 when done && req0.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (done && req0)) |=> (grant0 && !grant1));\n\n// P10_T8: G1 transitions to IDLE when done && !req0.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (done && !req0)) |=> (!grant0 && !grant1));\n\n// P11_T9: G1 transitions to G1 when !done.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!grant0 && grant1) && (!done)) |=> (!grant0 && grant1));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({grant0, grant1})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G0 when req0\",\n \"antecedent\": \"(!grant0 && !grant1) && (req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to G1 when !req0 && req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req0 && !req1\",\n \"antecedent\": \"(!grant0 && !grant1) && (!req0 && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G1 when done && req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && req1)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to IDLE when done && !req1\",\n \"antecedent\": \"(grant0 && !grant1) && (done && !req1)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G0 transitions to G0 when !done\",\n \"antecedent\": \"(grant0 && !grant1) && (!done)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G0 when done && req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && req0)\",\n \"consequent\": \"grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to IDLE when done && !req0\",\n \"antecedent\": \"(!grant0 && grant1) && (done && !req0)\",\n \"consequent\": \"!grant0 && !grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"G1 transitions to G1 when !done\",\n \"antecedent\": \"(!grant0 && grant1) && (!done)\",\n \"consequent\": \"!grant0 && grant1\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module arbiter_0007_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req0 && req1) ? G1 : ((!req0 && !req1) ? IDLE : (IDLE));\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module arbiter_0007_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req0) ? G0 : ((!req0 && !req1) ? IDLE : (IDLE));\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module arbiter_0007_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req0,\\n input wire req1,\\n input wire done,\\n output reg grant0,\\n output reg grant1\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] G0 = 2'd1;\\n localparam [1:0] G1 = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = G0;\\n G0: next_state = (done && req1) ? G1 : ((done && !req1) ? IDLE : ((!done) ? G0 : (G0)));\\n G1: next_state = (done && req0) ? G0 : ((done && !req0) ? IDLE : ((!done) ? G1 : (G1)));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n case (state)\\n IDLE: begin\\n grant0 = 1'b0;\\n grant1 = 1'b0;\\n end\\n G0: begin\\n grant0 = 1'b1;\\n grant1 = 1'b0;\\n end\\n G1: begin\\n grant0 = 1'b0;\\n grant1 = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "counter_0007", "category": "counter", "description": "Saturating down-counter starting from seven.", "rtl_variant": "canonical_next.sv", "rtl": "module counter_0007_canonical_next (\n input wire clk,\n input wire rst,\n input wire reload,\n input wire enable,\n output reg [2:0] count,\n output wire at_zero\n);\n\n reg [2:0] next_count;\n\n always @* begin\n if (reload) next_count = 3'd7;\n else if (!reload && enable && (count > 3'd0)) next_count = count - 3'd1;\n else next_count = count;\n end\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd7;\n else\n count <= next_count;\n end\n\n assign at_zero = count == 3'd0;\nendmodule\n", "spec_json": "{\n \"design_id\": \"counter_0007\",\n \"category\": \"counter\",\n \"model_type\": \"register_rules\",\n \"template\": \"saturating_down_counter\",\n \"description\": \"Saturating down-counter starting from seven.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"reload\",\n \"enable\"\n ],\n \"outputs\": [\n \"count\",\n \"at_zero\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd7\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_zero\": \"count == 3'd0\"\n },\n \"update_rules\": [\n {\n \"when\": \"reload\",\n \"value\": \"3'd7\"\n },\n {\n \"when\": \"!reload && enable && (count > 3'd0)\",\n \"value\": \"count - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule reload produces the specified next value\",\n \"antecedent\": \"reload\",\n \"consequent\": \"count == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !reload && enable && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"!reload && enable && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(reload) && !(!reload && enable && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_reload\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"reload\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_enable\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!reload && enable && (count > 3'd0)\",\n \"new\": \"!reload && (count > 3'd0)\"\n },\n {\n \"name\": \"never_decrement\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!reload && enable && (count > 3'd0)\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for counter_0007\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd7);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_ZERO: at_zero is consistent with the observable register value\nproperty p_at_zero;\n @(posedge clk) disable iff (rst) (at_zero == (count == 3'd0));\nendproperty\nassert property (p_at_zero);\n\n// P3_RULE: update rule reload produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (reload) |=> (count == (3'd7));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !reload && enable && (count > 3'd0) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!reload && enable && (count > 3'd0)) |=> (count == ($past(count) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(reload) && !(!reload && enable && (count > 3'd0))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule reload produces the specified next value\",\n \"antecedent\": \"reload\",\n \"consequent\": \"count == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !reload && enable && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"!reload && enable && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(reload) && !(!reload && enable && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_enable.sv\": \"module counter_0007_mutant_ignore_enable (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (reload) count <= 3'd7;\\n else if (!reload && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\", \"ignore_reload.sv\": \"module counter_0007_mutant_ignore_reload (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (!reload && enable && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\", \"never_decrement.sv\": \"module counter_0007_mutant_never_decrement (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (reload) count <= 3'd7;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\"}"} {"family_id": "counter_0007", "category": "counter", "description": "Saturating down-counter starting from seven.", "rtl_variant": "sequential_priority.sv", "rtl": "module counter_0007_sequential_priority (\n input wire clk,\n input wire rst,\n input wire reload,\n input wire enable,\n output reg [2:0] count,\n output wire at_zero\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 3'd7;\n end\n else begin\n if (reload) count <= 3'd7;\n else if (!reload && enable && (count > 3'd0)) count <= count - 3'd1;\n else count <= count;\n end\n end\n\n assign at_zero = count == 3'd0;\nendmodule\n", "spec_json": "{\n \"design_id\": \"counter_0007\",\n \"category\": \"counter\",\n \"model_type\": \"register_rules\",\n \"template\": \"saturating_down_counter\",\n \"description\": \"Saturating down-counter starting from seven.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"reload\",\n \"enable\"\n ],\n \"outputs\": [\n \"count\",\n \"at_zero\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd7\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_zero\": \"count == 3'd0\"\n },\n \"update_rules\": [\n {\n \"when\": \"reload\",\n \"value\": \"3'd7\"\n },\n {\n \"when\": \"!reload && enable && (count > 3'd0)\",\n \"value\": \"count - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule reload produces the specified next value\",\n \"antecedent\": \"reload\",\n \"consequent\": \"count == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !reload && enable && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"!reload && enable && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(reload) && !(!reload && enable && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_reload\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"reload\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_enable\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!reload && enable && (count > 3'd0)\",\n \"new\": \"!reload && (count > 3'd0)\"\n },\n {\n \"name\": \"never_decrement\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!reload && enable && (count > 3'd0)\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for counter_0007\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd7);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_ZERO: at_zero is consistent with the observable register value\nproperty p_at_zero;\n @(posedge clk) disable iff (rst) (at_zero == (count == 3'd0));\nendproperty\nassert property (p_at_zero);\n\n// P3_RULE: update rule reload produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (reload) |=> (count == (3'd7));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !reload && enable && (count > 3'd0) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!reload && enable && (count > 3'd0)) |=> (count == ($past(count) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(reload) && !(!reload && enable && (count > 3'd0))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule reload produces the specified next value\",\n \"antecedent\": \"reload\",\n \"consequent\": \"count == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !reload && enable && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"!reload && enable && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(reload) && !(!reload && enable && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_enable.sv\": \"module counter_0007_mutant_ignore_enable (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (reload) count <= 3'd7;\\n else if (!reload && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\", \"ignore_reload.sv\": \"module counter_0007_mutant_ignore_reload (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (!reload && enable && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\", \"never_decrement.sv\": \"module counter_0007_mutant_never_decrement (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (reload) count <= 3'd7;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\"}"} {"family_id": "counter_0007", "category": "counter", "description": "Saturating down-counter starting from seven.", "rtl_variant": "ternary_next.sv", "rtl": "module counter_0007_ternary_next (\n input wire clk,\n input wire rst,\n input wire reload,\n input wire enable,\n output reg [2:0] count,\n output wire at_zero\n);\n\n wire [2:0] next_count;\n\n assign next_count = (reload) ? (3'd7) : ((!reload && enable && (count > 3'd0)) ? (count - 3'd1) : (count));\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd7;\n else\n count <= next_count;\n end\n\n assign at_zero = count == 3'd0;\nendmodule\n", "spec_json": "{\n \"design_id\": \"counter_0007\",\n \"category\": \"counter\",\n \"model_type\": \"register_rules\",\n \"template\": \"saturating_down_counter\",\n \"description\": \"Saturating down-counter starting from seven.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"reload\",\n \"enable\"\n ],\n \"outputs\": [\n \"count\",\n \"at_zero\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd7\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_zero\": \"count == 3'd0\"\n },\n \"update_rules\": [\n {\n \"when\": \"reload\",\n \"value\": \"3'd7\"\n },\n {\n \"when\": \"!reload && enable && (count > 3'd0)\",\n \"value\": \"count - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule reload produces the specified next value\",\n \"antecedent\": \"reload\",\n \"consequent\": \"count == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !reload && enable && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"!reload && enable && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(reload) && !(!reload && enable && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_reload\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"reload\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_enable\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!reload && enable && (count > 3'd0)\",\n \"new\": \"!reload && (count > 3'd0)\"\n },\n {\n \"name\": \"never_decrement\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!reload && enable && (count > 3'd0)\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for counter_0007\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd7);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_ZERO: at_zero is consistent with the observable register value\nproperty p_at_zero;\n @(posedge clk) disable iff (rst) (at_zero == (count == 3'd0));\nendproperty\nassert property (p_at_zero);\n\n// P3_RULE: update rule reload produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (reload) |=> (count == (3'd7));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !reload && enable && (count > 3'd0) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!reload && enable && (count > 3'd0)) |=> (count == ($past(count) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(reload) && !(!reload && enable && (count > 3'd0))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule reload produces the specified next value\",\n \"antecedent\": \"reload\",\n \"consequent\": \"count == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !reload && enable && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"!reload && enable && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(reload) && !(!reload && enable && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_enable.sv\": \"module counter_0007_mutant_ignore_enable (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (reload) count <= 3'd7;\\n else if (!reload && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\", \"ignore_reload.sv\": \"module counter_0007_mutant_ignore_reload (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (!reload && enable && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\", \"never_decrement.sv\": \"module counter_0007_mutant_never_decrement (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (reload) count <= 3'd7;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\"}"} {"family_id": "counter_0007", "category": "counter", "description": "Saturating down-counter starting from seven.", "rtl_variant": "function_update.sv", "rtl": "module counter_0007_function_update (\n input wire clk,\n input wire rst,\n input wire reload,\n input wire enable,\n output reg [2:0] count,\n output wire at_zero\n);\n\n function automatic [2:0] compute_next_count;\n input [2:0] current;\n input reload;\n input enable;\n begin\n if (reload) compute_next_count = 3'd7;\n else if (!reload && enable && (current > 3'd0)) compute_next_count = current - 3'd1;\n else compute_next_count = current;\n end\n endfunction\n\n wire [2:0] next_count;\n\n assign next_count = compute_next_count(count, reload, enable);\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd7;\n else\n count <= next_count;\n end\n\n assign at_zero = count == 3'd0;\nendmodule\n", "spec_json": "{\n \"design_id\": \"counter_0007\",\n \"category\": \"counter\",\n \"model_type\": \"register_rules\",\n \"template\": \"saturating_down_counter\",\n \"description\": \"Saturating down-counter starting from seven.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"reload\",\n \"enable\"\n ],\n \"outputs\": [\n \"count\",\n \"at_zero\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd7\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_zero\": \"count == 3'd0\"\n },\n \"update_rules\": [\n {\n \"when\": \"reload\",\n \"value\": \"3'd7\"\n },\n {\n \"when\": \"!reload && enable && (count > 3'd0)\",\n \"value\": \"count - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule reload produces the specified next value\",\n \"antecedent\": \"reload\",\n \"consequent\": \"count == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !reload && enable && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"!reload && enable && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(reload) && !(!reload && enable && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_reload\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"reload\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_enable\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!reload && enable && (count > 3'd0)\",\n \"new\": \"!reload && (count > 3'd0)\"\n },\n {\n \"name\": \"never_decrement\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!reload && enable && (count > 3'd0)\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for counter_0007\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd7);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_ZERO: at_zero is consistent with the observable register value\nproperty p_at_zero;\n @(posedge clk) disable iff (rst) (at_zero == (count == 3'd0));\nendproperty\nassert property (p_at_zero);\n\n// P3_RULE: update rule reload produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (reload) |=> (count == (3'd7));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !reload && enable && (count > 3'd0) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!reload && enable && (count > 3'd0)) |=> (count == ($past(count) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(reload) && !(!reload && enable && (count > 3'd0))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule reload produces the specified next value\",\n \"antecedent\": \"reload\",\n \"consequent\": \"count == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !reload && enable && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"!reload && enable && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(reload) && !(!reload && enable && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_enable.sv\": \"module counter_0007_mutant_ignore_enable (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (reload) count <= 3'd7;\\n else if (!reload && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\", \"ignore_reload.sv\": \"module counter_0007_mutant_ignore_reload (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (!reload && enable && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\", \"never_decrement.sv\": \"module counter_0007_mutant_never_decrement (\\n input wire clk,\\n input wire rst,\\n input wire reload,\\n input wire enable,\\n output reg [2:0] count,\\n output wire at_zero\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd7;\\n end\\n else begin\\n if (reload) count <= 3'd7;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\nendmodule\\n\"}"} {"family_id": "counter_0009", "category": "counter", "description": "Three-bit up/down counter bounded at zero and seven.", "rtl_variant": "canonical_next.sv", "rtl": "module counter_0009_canonical_next (\n input wire clk,\n input wire rst,\n input wire up,\n input wire down,\n output reg [2:0] count,\n output wire at_zero,\n output wire at_max\n);\n\n reg [2:0] next_count;\n\n always @* begin\n if (up && !down && (count < 3'd7)) next_count = count + 3'd1;\n else if (down && !up && (count > 3'd0)) next_count = count - 3'd1;\n else next_count = count;\n end\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd0;\n else\n count <= next_count;\n end\n\n assign at_zero = count == 3'd0;\n assign at_max = count == 3'd7;\nendmodule\n", "spec_json": "{\n \"design_id\": \"counter_0009\",\n \"category\": \"counter\",\n \"model_type\": \"register_rules\",\n \"template\": \"bounded_up_down_counter\",\n \"description\": \"Three-bit up/down counter bounded at zero and seven.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"up\",\n \"down\"\n ],\n \"outputs\": [\n \"count\",\n \"at_zero\",\n \"at_max\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_zero\": \"count == 3'd0\",\n \"at_max\": \"count == 3'd7\"\n },\n \"update_rules\": [\n {\n \"when\": \"up && !down && (count < 3'd7)\",\n \"value\": \"count + 3'd1\"\n },\n {\n \"when\": \"down && !up && (count > 3'd0)\",\n \"value\": \"count - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_AT_MAX\",\n \"sva_name\": \"p_at_max\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_max is consistent with the observable register value\",\n \"expression\": \"at_max == (count == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule up && !down && (count < 3'd7) produces the specified next value\",\n \"antecedent\": \"up && !down && (count < 3'd7)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_RULE\",\n \"sva_name\": \"p_rule_5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule down && !up && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"down && !up && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_up\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"up && !down && (count < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_down\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"down && !up && (count > 3'd0)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"up_when_both\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"up && !down && (count < 3'd7)\",\n \"new\": \"up && (count < 3'd7)\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for counter_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_ZERO: at_zero is consistent with the observable register value\nproperty p_at_zero;\n @(posedge clk) disable iff (rst) (at_zero == (count == 3'd0));\nendproperty\nassert property (p_at_zero);\n\n// P3_AT_MAX: at_max is consistent with the observable register value\nproperty p_at_max;\n @(posedge clk) disable iff (rst) (at_max == (count == 3'd7));\nendproperty\nassert property (p_at_max);\n\n// P4_RULE: update rule up && !down && (count < 3'd7) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (up && !down && (count < 3'd7)) |=> (count == ($past(count) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_RULE: update rule down && !up && (count > 3'd0) produces the specified next value\nproperty p_rule_5;\n @(posedge clk) disable iff (rst) (down && !up && (count > 3'd0)) |=> (count == ($past(count) - 3'd1));\nendproperty\nassert property (p_rule_5);\n\n// P6_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_AT_MAX\",\n \"sva_name\": \"p_at_max\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_max is consistent with the observable register value\",\n \"expression\": \"at_max == (count == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule up && !down && (count < 3'd7) produces the specified next value\",\n \"antecedent\": \"up && !down && (count < 3'd7)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_RULE\",\n \"sva_name\": \"p_rule_5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule down && !up && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"down && !up && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_down.sv\": \"module counter_0009_mutant_ignore_down (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (up && !down && (count < 3'd7)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\", \"ignore_up.sv\": \"module counter_0009_mutant_ignore_up (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (down && !up && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\", \"up_when_both.sv\": \"module counter_0009_mutant_up_when_both (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (up && (count < 3'd7)) count <= count + 3'd1;\\n else if (down && !up && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\"}"} {"family_id": "counter_0009", "category": "counter", "description": "Three-bit up/down counter bounded at zero and seven.", "rtl_variant": "sequential_priority.sv", "rtl": "module counter_0009_sequential_priority (\n input wire clk,\n input wire rst,\n input wire up,\n input wire down,\n output reg [2:0] count,\n output wire at_zero,\n output wire at_max\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 3'd0;\n end\n else begin\n if (up && !down && (count < 3'd7)) count <= count + 3'd1;\n else if (down && !up && (count > 3'd0)) count <= count - 3'd1;\n else count <= count;\n end\n end\n\n assign at_zero = count == 3'd0;\n assign at_max = count == 3'd7;\nendmodule\n", "spec_json": "{\n \"design_id\": \"counter_0009\",\n \"category\": \"counter\",\n \"model_type\": \"register_rules\",\n \"template\": \"bounded_up_down_counter\",\n \"description\": \"Three-bit up/down counter bounded at zero and seven.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"up\",\n \"down\"\n ],\n \"outputs\": [\n \"count\",\n \"at_zero\",\n \"at_max\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_zero\": \"count == 3'd0\",\n \"at_max\": \"count == 3'd7\"\n },\n \"update_rules\": [\n {\n \"when\": \"up && !down && (count < 3'd7)\",\n \"value\": \"count + 3'd1\"\n },\n {\n \"when\": \"down && !up && (count > 3'd0)\",\n \"value\": \"count - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_AT_MAX\",\n \"sva_name\": \"p_at_max\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_max is consistent with the observable register value\",\n \"expression\": \"at_max == (count == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule up && !down && (count < 3'd7) produces the specified next value\",\n \"antecedent\": \"up && !down && (count < 3'd7)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_RULE\",\n \"sva_name\": \"p_rule_5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule down && !up && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"down && !up && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_up\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"up && !down && (count < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_down\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"down && !up && (count > 3'd0)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"up_when_both\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"up && !down && (count < 3'd7)\",\n \"new\": \"up && (count < 3'd7)\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for counter_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_ZERO: at_zero is consistent with the observable register value\nproperty p_at_zero;\n @(posedge clk) disable iff (rst) (at_zero == (count == 3'd0));\nendproperty\nassert property (p_at_zero);\n\n// P3_AT_MAX: at_max is consistent with the observable register value\nproperty p_at_max;\n @(posedge clk) disable iff (rst) (at_max == (count == 3'd7));\nendproperty\nassert property (p_at_max);\n\n// P4_RULE: update rule up && !down && (count < 3'd7) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (up && !down && (count < 3'd7)) |=> (count == ($past(count) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_RULE: update rule down && !up && (count > 3'd0) produces the specified next value\nproperty p_rule_5;\n @(posedge clk) disable iff (rst) (down && !up && (count > 3'd0)) |=> (count == ($past(count) - 3'd1));\nendproperty\nassert property (p_rule_5);\n\n// P6_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_AT_MAX\",\n \"sva_name\": \"p_at_max\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_max is consistent with the observable register value\",\n \"expression\": \"at_max == (count == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule up && !down && (count < 3'd7) produces the specified next value\",\n \"antecedent\": \"up && !down && (count < 3'd7)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_RULE\",\n \"sva_name\": \"p_rule_5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule down && !up && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"down && !up && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_down.sv\": \"module counter_0009_mutant_ignore_down (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (up && !down && (count < 3'd7)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\", \"ignore_up.sv\": \"module counter_0009_mutant_ignore_up (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (down && !up && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\", \"up_when_both.sv\": \"module counter_0009_mutant_up_when_both (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (up && (count < 3'd7)) count <= count + 3'd1;\\n else if (down && !up && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\"}"} {"family_id": "counter_0009", "category": "counter", "description": "Three-bit up/down counter bounded at zero and seven.", "rtl_variant": "ternary_next.sv", "rtl": "module counter_0009_ternary_next (\n input wire clk,\n input wire rst,\n input wire up,\n input wire down,\n output reg [2:0] count,\n output wire at_zero,\n output wire at_max\n);\n\n wire [2:0] next_count;\n\n assign next_count = (up && !down && (count < 3'd7)) ? (count + 3'd1) : ((down && !up && (count > 3'd0)) ? (count - 3'd1) : (count));\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd0;\n else\n count <= next_count;\n end\n\n assign at_zero = count == 3'd0;\n assign at_max = count == 3'd7;\nendmodule\n", "spec_json": "{\n \"design_id\": \"counter_0009\",\n \"category\": \"counter\",\n \"model_type\": \"register_rules\",\n \"template\": \"bounded_up_down_counter\",\n \"description\": \"Three-bit up/down counter bounded at zero and seven.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"up\",\n \"down\"\n ],\n \"outputs\": [\n \"count\",\n \"at_zero\",\n \"at_max\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_zero\": \"count == 3'd0\",\n \"at_max\": \"count == 3'd7\"\n },\n \"update_rules\": [\n {\n \"when\": \"up && !down && (count < 3'd7)\",\n \"value\": \"count + 3'd1\"\n },\n {\n \"when\": \"down && !up && (count > 3'd0)\",\n \"value\": \"count - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_AT_MAX\",\n \"sva_name\": \"p_at_max\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_max is consistent with the observable register value\",\n \"expression\": \"at_max == (count == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule up && !down && (count < 3'd7) produces the specified next value\",\n \"antecedent\": \"up && !down && (count < 3'd7)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_RULE\",\n \"sva_name\": \"p_rule_5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule down && !up && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"down && !up && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_up\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"up && !down && (count < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_down\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"down && !up && (count > 3'd0)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"up_when_both\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"up && !down && (count < 3'd7)\",\n \"new\": \"up && (count < 3'd7)\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for counter_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_ZERO: at_zero is consistent with the observable register value\nproperty p_at_zero;\n @(posedge clk) disable iff (rst) (at_zero == (count == 3'd0));\nendproperty\nassert property (p_at_zero);\n\n// P3_AT_MAX: at_max is consistent with the observable register value\nproperty p_at_max;\n @(posedge clk) disable iff (rst) (at_max == (count == 3'd7));\nendproperty\nassert property (p_at_max);\n\n// P4_RULE: update rule up && !down && (count < 3'd7) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (up && !down && (count < 3'd7)) |=> (count == ($past(count) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_RULE: update rule down && !up && (count > 3'd0) produces the specified next value\nproperty p_rule_5;\n @(posedge clk) disable iff (rst) (down && !up && (count > 3'd0)) |=> (count == ($past(count) - 3'd1));\nendproperty\nassert property (p_rule_5);\n\n// P6_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_AT_MAX\",\n \"sva_name\": \"p_at_max\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_max is consistent with the observable register value\",\n \"expression\": \"at_max == (count == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule up && !down && (count < 3'd7) produces the specified next value\",\n \"antecedent\": \"up && !down && (count < 3'd7)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_RULE\",\n \"sva_name\": \"p_rule_5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule down && !up && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"down && !up && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_down.sv\": \"module counter_0009_mutant_ignore_down (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (up && !down && (count < 3'd7)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\", \"ignore_up.sv\": \"module counter_0009_mutant_ignore_up (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (down && !up && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\", \"up_when_both.sv\": \"module counter_0009_mutant_up_when_both (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (up && (count < 3'd7)) count <= count + 3'd1;\\n else if (down && !up && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\"}"} {"family_id": "counter_0009", "category": "counter", "description": "Three-bit up/down counter bounded at zero and seven.", "rtl_variant": "function_update.sv", "rtl": "module counter_0009_function_update (\n input wire clk,\n input wire rst,\n input wire up,\n input wire down,\n output reg [2:0] count,\n output wire at_zero,\n output wire at_max\n);\n\n function automatic [2:0] compute_next_count;\n input [2:0] current;\n input up;\n input down;\n begin\n if (up && !down && (current < 3'd7)) compute_next_count = current + 3'd1;\n else if (down && !up && (current > 3'd0)) compute_next_count = current - 3'd1;\n else compute_next_count = current;\n end\n endfunction\n\n wire [2:0] next_count;\n\n assign next_count = compute_next_count(count, up, down);\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd0;\n else\n count <= next_count;\n end\n\n assign at_zero = count == 3'd0;\n assign at_max = count == 3'd7;\nendmodule\n", "spec_json": "{\n \"design_id\": \"counter_0009\",\n \"category\": \"counter\",\n \"model_type\": \"register_rules\",\n \"template\": \"bounded_up_down_counter\",\n \"description\": \"Three-bit up/down counter bounded at zero and seven.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"up\",\n \"down\"\n ],\n \"outputs\": [\n \"count\",\n \"at_zero\",\n \"at_max\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_zero\": \"count == 3'd0\",\n \"at_max\": \"count == 3'd7\"\n },\n \"update_rules\": [\n {\n \"when\": \"up && !down && (count < 3'd7)\",\n \"value\": \"count + 3'd1\"\n },\n {\n \"when\": \"down && !up && (count > 3'd0)\",\n \"value\": \"count - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_AT_MAX\",\n \"sva_name\": \"p_at_max\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_max is consistent with the observable register value\",\n \"expression\": \"at_max == (count == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule up && !down && (count < 3'd7) produces the specified next value\",\n \"antecedent\": \"up && !down && (count < 3'd7)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_RULE\",\n \"sva_name\": \"p_rule_5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule down && !up && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"down && !up && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_up\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"up && !down && (count < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_down\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"down && !up && (count > 3'd0)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"up_when_both\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"up && !down && (count < 3'd7)\",\n \"new\": \"up && (count < 3'd7)\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for counter_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_ZERO: at_zero is consistent with the observable register value\nproperty p_at_zero;\n @(posedge clk) disable iff (rst) (at_zero == (count == 3'd0));\nendproperty\nassert property (p_at_zero);\n\n// P3_AT_MAX: at_max is consistent with the observable register value\nproperty p_at_max;\n @(posedge clk) disable iff (rst) (at_max == (count == 3'd7));\nendproperty\nassert property (p_at_max);\n\n// P4_RULE: update rule up && !down && (count < 3'd7) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (up && !down && (count < 3'd7)) |=> (count == ($past(count) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_RULE: update rule down && !up && (count > 3'd0) produces the specified next value\nproperty p_rule_5;\n @(posedge clk) disable iff (rst) (down && !up && (count > 3'd0)) |=> (count == ($past(count) - 3'd1));\nendproperty\nassert property (p_rule_5);\n\n// P6_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_ZERO\",\n \"sva_name\": \"p_at_zero\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_zero is consistent with the observable register value\",\n \"expression\": \"at_zero == (count == 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_AT_MAX\",\n \"sva_name\": \"p_at_max\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_max is consistent with the observable register value\",\n \"expression\": \"at_max == (count == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule up && !down && (count < 3'd7) produces the specified next value\",\n \"antecedent\": \"up && !down && (count < 3'd7)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_RULE\",\n \"sva_name\": \"p_rule_5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule down && !up && (count > 3'd0) produces the specified next value\",\n \"antecedent\": \"down && !up && (count > 3'd0)\",\n \"consequent\": \"count == ($past(count) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(up && !down && (count < 3'd7)) && !(down && !up && (count > 3'd0))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_down.sv\": \"module counter_0009_mutant_ignore_down (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (up && !down && (count < 3'd7)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\", \"ignore_up.sv\": \"module counter_0009_mutant_ignore_up (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (down && !up && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\", \"up_when_both.sv\": \"module counter_0009_mutant_up_when_both (\\n input wire clk,\\n input wire rst,\\n input wire up,\\n input wire down,\\n output reg [2:0] count,\\n output wire at_zero,\\n output wire at_max\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (up && (count < 3'd7)) count <= count + 3'd1;\\n else if (down && !up && (count > 3'd0)) count <= count - 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign at_zero = count == 3'd0;\\n assign at_max = count == 3'd7;\\nendmodule\\n\"}"} {"family_id": "fifo_0007", "category": "fifo_control", "description": "Two-slot FIFO occupancy controller exposing empty, one-entry, and full states.", "rtl_variant": "canonical_case.sv", "rtl": "module fifo_0007_canonical_case (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n output reg empty,\n output reg one,\n output reg full\n);\n localparam [1:0] EMPTY = 2'd0;\n localparam [1:0] ONE = 2'd1;\n localparam [1:0] FULL = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\n default: next_state = EMPTY;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= EMPTY;\n else\n state <= next_state;\n end\n\n always @* begin\n empty = 1'b0;\n one = 1'b0;\n full = 1'b0;\n case (state)\n EMPTY: begin\n empty = 1'b1;\n one = 1'b0;\n full = 1'b0;\n end\n ONE: begin\n empty = 1'b0;\n one = 1'b1;\n full = 1'b0;\n end\n FULL: begin\n empty = 1'b0;\n one = 1'b0;\n full = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"fifo_0007\",\n \"category\": \"fifo_control\",\n \"template\": \"two_slot_occupancy_fsm\",\n \"description\": \"Two-slot FIFO occupancy controller exposing empty, one-entry, and full states.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"EMPTY\"\n },\n \"inputs\": [\n \"push\",\n \"pop\"\n ],\n \"outputs\": [\n \"empty\",\n \"one\",\n \"full\"\n ],\n \"states\": [\n \"EMPTY\",\n \"ONE\",\n \"FULL\"\n ],\n \"state_outputs\": {\n \"EMPTY\": {\n \"empty\": 1,\n \"one\": 0,\n \"full\": 0\n },\n \"ONE\": {\n \"empty\": 0,\n \"one\": 1,\n \"full\": 0\n },\n \"FULL\": {\n \"empty\": 0,\n \"one\": 0,\n \"full\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"EMPTY\",\n \"when\": \"push\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"EMPTY\",\n \"when\": \"!push\",\n \"to\": \"EMPTY\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"push && !pop\",\n \"to\": \"FULL\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"pop && !push\",\n \"to\": \"EMPTY\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"(push && pop) || (!push && !pop)\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"FULL\",\n \"when\": \"pop\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"FULL\",\n \"when\": \"!pop\",\n \"to\": \"FULL\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"exactly one occupancy state is visible\",\n \"expression\": \"$onehot({empty, one, full})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the FIFO\",\n \"antecedent\": \"rst\",\n \"consequent\": \"empty\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_EMPTY_PUSH\",\n \"sva_name\": \"p_empty_push\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pushing an empty FIFO creates one entry\",\n \"antecedent\": \"empty && push\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ONE_PUSH\",\n \"sva_name\": \"p_one_push\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push without pop fills a one-entry FIFO\",\n \"antecedent\": \"one && push && !pop\",\n \"consequent\": \"full\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_ONE_POP\",\n \"sva_name\": \"p_one_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without push empties a one-entry FIFO\",\n \"antecedent\": \"one && pop && !push\",\n \"consequent\": \"empty\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_SIMULTANEOUS\",\n \"sva_name\": \"p_simultaneous\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous push and pop preserves one-entry occupancy\",\n \"antecedent\": \"one && push && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_FULL_POP\",\n \"sva_name\": \"p_full_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"popping a full FIFO leaves one entry\",\n \"antecedent\": \"full && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"empty_ignores_push\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"EMPTY\",\n \"old\": \"push\",\n \"new\": \"false\"\n },\n {\n \"name\": \"one_never_fills\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ONE\",\n \"old\": \"push && !pop\",\n \"new\": \"false\"\n },\n {\n \"name\": \"full_ignores_pop\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"FULL\",\n \"old\": \"pop\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: fifo_0007\n\n// P1_ONEHOT: exactly one occupancy state is visible.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({empty, one, full}));\n\n// P2_RESET: reset empties the FIFO.\np_reset: assert property (@(posedge clk)\n (rst) |=> (empty));\n\n// P3_EMPTY_PUSH: pushing an empty FIFO creates one entry.\np_empty_push: assert property (@(posedge clk) disable iff (rst)\n (empty && push) |=> (one));\n\n// P4_ONE_PUSH: push without pop fills a one-entry FIFO.\np_one_push: assert property (@(posedge clk) disable iff (rst)\n (one && push && !pop) |=> (full));\n\n// P5_ONE_POP: pop without push empties a one-entry FIFO.\np_one_pop: assert property (@(posedge clk) disable iff (rst)\n (one && pop && !push) |=> (empty));\n\n// P6_SIMULTANEOUS: simultaneous push and pop preserves one-entry occupancy.\np_simultaneous: assert property (@(posedge clk) disable iff (rst)\n (one && push && pop) |=> (one));\n\n// P7_FULL_POP: popping a full FIFO leaves one entry.\np_full_pop: assert property (@(posedge clk) disable iff (rst)\n (full && pop) |=> (one));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"exactly one occupancy state is visible\",\n \"expression\": \"$onehot({empty, one, full})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the FIFO\",\n \"antecedent\": \"rst\",\n \"consequent\": \"empty\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_EMPTY_PUSH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pushing an empty FIFO creates one entry\",\n \"antecedent\": \"empty && push\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ONE_PUSH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push without pop fills a one-entry FIFO\",\n \"antecedent\": \"one && push && !pop\",\n \"consequent\": \"full\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_ONE_POP\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without push empties a one-entry FIFO\",\n \"antecedent\": \"one && pop && !push\",\n \"consequent\": \"empty\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_SIMULTANEOUS\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous push and pop preserves one-entry occupancy\",\n \"antecedent\": \"one && push && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_FULL_POP\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"popping a full FIFO leaves one entry\",\n \"antecedent\": \"full && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"empty_ignores_push.sv\": \"module fifo_0007_mutant_empty_ignores_push (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (!push) ? EMPTY : (EMPTY);\\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"full_ignores_pop.sv\": \"module fifo_0007_mutant_full_ignores_pop (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\\n FULL: next_state = (!pop) ? FULL : (FULL);\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"one_never_fills.sv\": \"module fifo_0007_mutant_one_never_fills (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\\n ONE: next_state = (pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE));\\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "fifo_0007", "category": "fifo_control", "description": "Two-slot FIFO occupancy controller exposing empty, one-entry, and full states.", "rtl_variant": "onehot_case.sv", "rtl": "module fifo_0007_onehot_case (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n output reg empty,\n output reg one,\n output reg full\n);\n localparam [2:0] EMPTY = 3'b001;\n localparam [2:0] ONE = 3'b010;\n localparam [2:0] FULL = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = EMPTY;\n case (state)\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\n default: next_state = EMPTY;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= EMPTY;\n else\n state <= next_state;\n end\n\n always @* begin\n empty = (state == EMPTY);\n one = (state == ONE);\n full = (state == FULL);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"fifo_0007\",\n \"category\": \"fifo_control\",\n \"template\": \"two_slot_occupancy_fsm\",\n \"description\": \"Two-slot FIFO occupancy controller exposing empty, one-entry, and full states.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"EMPTY\"\n },\n \"inputs\": [\n \"push\",\n \"pop\"\n ],\n \"outputs\": [\n \"empty\",\n \"one\",\n \"full\"\n ],\n \"states\": [\n \"EMPTY\",\n \"ONE\",\n \"FULL\"\n ],\n \"state_outputs\": {\n \"EMPTY\": {\n \"empty\": 1,\n \"one\": 0,\n \"full\": 0\n },\n \"ONE\": {\n \"empty\": 0,\n \"one\": 1,\n \"full\": 0\n },\n \"FULL\": {\n \"empty\": 0,\n \"one\": 0,\n \"full\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"EMPTY\",\n \"when\": \"push\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"EMPTY\",\n \"when\": \"!push\",\n \"to\": \"EMPTY\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"push && !pop\",\n \"to\": \"FULL\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"pop && !push\",\n \"to\": \"EMPTY\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"(push && pop) || (!push && !pop)\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"FULL\",\n \"when\": \"pop\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"FULL\",\n \"when\": \"!pop\",\n \"to\": \"FULL\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"exactly one occupancy state is visible\",\n \"expression\": \"$onehot({empty, one, full})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the FIFO\",\n \"antecedent\": \"rst\",\n \"consequent\": \"empty\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_EMPTY_PUSH\",\n \"sva_name\": \"p_empty_push\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pushing an empty FIFO creates one entry\",\n \"antecedent\": \"empty && push\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ONE_PUSH\",\n \"sva_name\": \"p_one_push\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push without pop fills a one-entry FIFO\",\n \"antecedent\": \"one && push && !pop\",\n \"consequent\": \"full\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_ONE_POP\",\n \"sva_name\": \"p_one_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without push empties a one-entry FIFO\",\n \"antecedent\": \"one && pop && !push\",\n \"consequent\": \"empty\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_SIMULTANEOUS\",\n \"sva_name\": \"p_simultaneous\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous push and pop preserves one-entry occupancy\",\n \"antecedent\": \"one && push && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_FULL_POP\",\n \"sva_name\": \"p_full_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"popping a full FIFO leaves one entry\",\n \"antecedent\": \"full && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"empty_ignores_push\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"EMPTY\",\n \"old\": \"push\",\n \"new\": \"false\"\n },\n {\n \"name\": \"one_never_fills\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ONE\",\n \"old\": \"push && !pop\",\n \"new\": \"false\"\n },\n {\n \"name\": \"full_ignores_pop\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"FULL\",\n \"old\": \"pop\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: fifo_0007\n\n// P1_ONEHOT: exactly one occupancy state is visible.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({empty, one, full}));\n\n// P2_RESET: reset empties the FIFO.\np_reset: assert property (@(posedge clk)\n (rst) |=> (empty));\n\n// P3_EMPTY_PUSH: pushing an empty FIFO creates one entry.\np_empty_push: assert property (@(posedge clk) disable iff (rst)\n (empty && push) |=> (one));\n\n// P4_ONE_PUSH: push without pop fills a one-entry FIFO.\np_one_push: assert property (@(posedge clk) disable iff (rst)\n (one && push && !pop) |=> (full));\n\n// P5_ONE_POP: pop without push empties a one-entry FIFO.\np_one_pop: assert property (@(posedge clk) disable iff (rst)\n (one && pop && !push) |=> (empty));\n\n// P6_SIMULTANEOUS: simultaneous push and pop preserves one-entry occupancy.\np_simultaneous: assert property (@(posedge clk) disable iff (rst)\n (one && push && pop) |=> (one));\n\n// P7_FULL_POP: popping a full FIFO leaves one entry.\np_full_pop: assert property (@(posedge clk) disable iff (rst)\n (full && pop) |=> (one));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"exactly one occupancy state is visible\",\n \"expression\": \"$onehot({empty, one, full})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the FIFO\",\n \"antecedent\": \"rst\",\n \"consequent\": \"empty\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_EMPTY_PUSH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pushing an empty FIFO creates one entry\",\n \"antecedent\": \"empty && push\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ONE_PUSH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push without pop fills a one-entry FIFO\",\n \"antecedent\": \"one && push && !pop\",\n \"consequent\": \"full\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_ONE_POP\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without push empties a one-entry FIFO\",\n \"antecedent\": \"one && pop && !push\",\n \"consequent\": \"empty\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_SIMULTANEOUS\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous push and pop preserves one-entry occupancy\",\n \"antecedent\": \"one && push && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_FULL_POP\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"popping a full FIFO leaves one entry\",\n \"antecedent\": \"full && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"empty_ignores_push.sv\": \"module fifo_0007_mutant_empty_ignores_push (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (!push) ? EMPTY : (EMPTY);\\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"full_ignores_pop.sv\": \"module fifo_0007_mutant_full_ignores_pop (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\\n FULL: next_state = (!pop) ? FULL : (FULL);\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"one_never_fills.sv\": \"module fifo_0007_mutant_one_never_fills (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\\n ONE: next_state = (pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE));\\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "fifo_0007", "category": "fifo_control", "description": "Two-slot FIFO occupancy controller exposing empty, one-entry, and full states.", "rtl_variant": "nested_if.sv", "rtl": "module fifo_0007_nested_if (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n output wire empty,\n output wire one,\n output wire full\n);\n localparam [1:0] S_EMPTY = 2'd0;\n localparam [1:0] S_ONE = 2'd1;\n localparam [1:0] S_FULL = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_EMPTY;\n end else begin\n if (state == S_EMPTY) begin\n state <= (push) ? S_ONE : ((!push) ? S_EMPTY : (S_EMPTY));\n end\n else if (state == S_ONE) begin\n state <= (push && !pop) ? S_FULL : ((pop && !push) ? S_EMPTY : (((push && pop) || (!push && !pop)) ? S_ONE : (S_ONE)));\n end\n else if (state == S_FULL) begin\n state <= (pop) ? S_ONE : ((!pop) ? S_FULL : (S_FULL));\n end\n else begin\n state <= S_EMPTY;\n end\n end\n end\n\n assign empty = (state == S_EMPTY);\n assign one = (state == S_ONE);\n assign full = (state == S_FULL);\nendmodule\n", "spec_json": "{\n \"design_id\": \"fifo_0007\",\n \"category\": \"fifo_control\",\n \"template\": \"two_slot_occupancy_fsm\",\n \"description\": \"Two-slot FIFO occupancy controller exposing empty, one-entry, and full states.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"EMPTY\"\n },\n \"inputs\": [\n \"push\",\n \"pop\"\n ],\n \"outputs\": [\n \"empty\",\n \"one\",\n \"full\"\n ],\n \"states\": [\n \"EMPTY\",\n \"ONE\",\n \"FULL\"\n ],\n \"state_outputs\": {\n \"EMPTY\": {\n \"empty\": 1,\n \"one\": 0,\n \"full\": 0\n },\n \"ONE\": {\n \"empty\": 0,\n \"one\": 1,\n \"full\": 0\n },\n \"FULL\": {\n \"empty\": 0,\n \"one\": 0,\n \"full\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"EMPTY\",\n \"when\": \"push\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"EMPTY\",\n \"when\": \"!push\",\n \"to\": \"EMPTY\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"push && !pop\",\n \"to\": \"FULL\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"pop && !push\",\n \"to\": \"EMPTY\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"(push && pop) || (!push && !pop)\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"FULL\",\n \"when\": \"pop\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"FULL\",\n \"when\": \"!pop\",\n \"to\": \"FULL\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"exactly one occupancy state is visible\",\n \"expression\": \"$onehot({empty, one, full})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the FIFO\",\n \"antecedent\": \"rst\",\n \"consequent\": \"empty\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_EMPTY_PUSH\",\n \"sva_name\": \"p_empty_push\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pushing an empty FIFO creates one entry\",\n \"antecedent\": \"empty && push\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ONE_PUSH\",\n \"sva_name\": \"p_one_push\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push without pop fills a one-entry FIFO\",\n \"antecedent\": \"one && push && !pop\",\n \"consequent\": \"full\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_ONE_POP\",\n \"sva_name\": \"p_one_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without push empties a one-entry FIFO\",\n \"antecedent\": \"one && pop && !push\",\n \"consequent\": \"empty\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_SIMULTANEOUS\",\n \"sva_name\": \"p_simultaneous\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous push and pop preserves one-entry occupancy\",\n \"antecedent\": \"one && push && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_FULL_POP\",\n \"sva_name\": \"p_full_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"popping a full FIFO leaves one entry\",\n \"antecedent\": \"full && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"empty_ignores_push\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"EMPTY\",\n \"old\": \"push\",\n \"new\": \"false\"\n },\n {\n \"name\": \"one_never_fills\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ONE\",\n \"old\": \"push && !pop\",\n \"new\": \"false\"\n },\n {\n \"name\": \"full_ignores_pop\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"FULL\",\n \"old\": \"pop\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: fifo_0007\n\n// P1_ONEHOT: exactly one occupancy state is visible.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({empty, one, full}));\n\n// P2_RESET: reset empties the FIFO.\np_reset: assert property (@(posedge clk)\n (rst) |=> (empty));\n\n// P3_EMPTY_PUSH: pushing an empty FIFO creates one entry.\np_empty_push: assert property (@(posedge clk) disable iff (rst)\n (empty && push) |=> (one));\n\n// P4_ONE_PUSH: push without pop fills a one-entry FIFO.\np_one_push: assert property (@(posedge clk) disable iff (rst)\n (one && push && !pop) |=> (full));\n\n// P5_ONE_POP: pop without push empties a one-entry FIFO.\np_one_pop: assert property (@(posedge clk) disable iff (rst)\n (one && pop && !push) |=> (empty));\n\n// P6_SIMULTANEOUS: simultaneous push and pop preserves one-entry occupancy.\np_simultaneous: assert property (@(posedge clk) disable iff (rst)\n (one && push && pop) |=> (one));\n\n// P7_FULL_POP: popping a full FIFO leaves one entry.\np_full_pop: assert property (@(posedge clk) disable iff (rst)\n (full && pop) |=> (one));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"exactly one occupancy state is visible\",\n \"expression\": \"$onehot({empty, one, full})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the FIFO\",\n \"antecedent\": \"rst\",\n \"consequent\": \"empty\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_EMPTY_PUSH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pushing an empty FIFO creates one entry\",\n \"antecedent\": \"empty && push\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ONE_PUSH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push without pop fills a one-entry FIFO\",\n \"antecedent\": \"one && push && !pop\",\n \"consequent\": \"full\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_ONE_POP\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without push empties a one-entry FIFO\",\n \"antecedent\": \"one && pop && !push\",\n \"consequent\": \"empty\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_SIMULTANEOUS\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous push and pop preserves one-entry occupancy\",\n \"antecedent\": \"one && push && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_FULL_POP\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"popping a full FIFO leaves one entry\",\n \"antecedent\": \"full && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"empty_ignores_push.sv\": \"module fifo_0007_mutant_empty_ignores_push (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (!push) ? EMPTY : (EMPTY);\\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"full_ignores_pop.sv\": \"module fifo_0007_mutant_full_ignores_pop (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\\n FULL: next_state = (!pop) ? FULL : (FULL);\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"one_never_fills.sv\": \"module fifo_0007_mutant_one_never_fills (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\\n ONE: next_state = (pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE));\\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "fifo_0007", "category": "fifo_control", "description": "Two-slot FIFO occupancy controller exposing empty, one-entry, and full states.", "rtl_variant": "factored_flags.sv", "rtl": "module fifo_0007_factored_flags (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n output reg empty,\n output reg one,\n output reg full\n);\n localparam [1:0] F_EMPTY = 2'd0;\n localparam [1:0] F_ONE = 2'd1;\n localparam [1:0] F_FULL = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_empty_0 = (push);\n wire guard_empty_1 = (!push);\n wire guard_one_0 = (push && !pop);\n wire guard_one_1 = (pop && !push);\n wire guard_one_2 = ((push && pop) || (!push && !pop));\n wire guard_full_0 = (pop);\n wire guard_full_1 = (!pop);\n\n always @* begin\n next_state = state;\n case (state)\n F_EMPTY: begin\n if (guard_empty_0)\n next_state = F_ONE;\n else if (guard_empty_1)\n next_state = F_EMPTY;\n end\n F_ONE: begin\n if (guard_one_0)\n next_state = F_FULL;\n else if (guard_one_1)\n next_state = F_EMPTY;\n else if (guard_one_2)\n next_state = F_ONE;\n end\n F_FULL: begin\n if (guard_full_0)\n next_state = F_ONE;\n else if (guard_full_1)\n next_state = F_FULL;\n end\n default: next_state = F_EMPTY;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_EMPTY;\n else\n state <= next_state;\n end\n\n always @* begin\n empty = 1'b0;\n one = 1'b0;\n full = 1'b0;\n case (state)\n F_EMPTY: begin\n empty = 1'b1;\n one = 1'b0;\n full = 1'b0;\n end\n F_ONE: begin\n empty = 1'b0;\n one = 1'b1;\n full = 1'b0;\n end\n F_FULL: begin\n empty = 1'b0;\n one = 1'b0;\n full = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"fifo_0007\",\n \"category\": \"fifo_control\",\n \"template\": \"two_slot_occupancy_fsm\",\n \"description\": \"Two-slot FIFO occupancy controller exposing empty, one-entry, and full states.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"EMPTY\"\n },\n \"inputs\": [\n \"push\",\n \"pop\"\n ],\n \"outputs\": [\n \"empty\",\n \"one\",\n \"full\"\n ],\n \"states\": [\n \"EMPTY\",\n \"ONE\",\n \"FULL\"\n ],\n \"state_outputs\": {\n \"EMPTY\": {\n \"empty\": 1,\n \"one\": 0,\n \"full\": 0\n },\n \"ONE\": {\n \"empty\": 0,\n \"one\": 1,\n \"full\": 0\n },\n \"FULL\": {\n \"empty\": 0,\n \"one\": 0,\n \"full\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"EMPTY\",\n \"when\": \"push\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"EMPTY\",\n \"when\": \"!push\",\n \"to\": \"EMPTY\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"push && !pop\",\n \"to\": \"FULL\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"pop && !push\",\n \"to\": \"EMPTY\"\n },\n {\n \"from\": \"ONE\",\n \"when\": \"(push && pop) || (!push && !pop)\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"FULL\",\n \"when\": \"pop\",\n \"to\": \"ONE\"\n },\n {\n \"from\": \"FULL\",\n \"when\": \"!pop\",\n \"to\": \"FULL\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"exactly one occupancy state is visible\",\n \"expression\": \"$onehot({empty, one, full})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the FIFO\",\n \"antecedent\": \"rst\",\n \"consequent\": \"empty\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_EMPTY_PUSH\",\n \"sva_name\": \"p_empty_push\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pushing an empty FIFO creates one entry\",\n \"antecedent\": \"empty && push\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ONE_PUSH\",\n \"sva_name\": \"p_one_push\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push without pop fills a one-entry FIFO\",\n \"antecedent\": \"one && push && !pop\",\n \"consequent\": \"full\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_ONE_POP\",\n \"sva_name\": \"p_one_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without push empties a one-entry FIFO\",\n \"antecedent\": \"one && pop && !push\",\n \"consequent\": \"empty\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_SIMULTANEOUS\",\n \"sva_name\": \"p_simultaneous\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous push and pop preserves one-entry occupancy\",\n \"antecedent\": \"one && push && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_FULL_POP\",\n \"sva_name\": \"p_full_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"popping a full FIFO leaves one entry\",\n \"antecedent\": \"full && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"empty_ignores_push\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"EMPTY\",\n \"old\": \"push\",\n \"new\": \"false\"\n },\n {\n \"name\": \"one_never_fills\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ONE\",\n \"old\": \"push && !pop\",\n \"new\": \"false\"\n },\n {\n \"name\": \"full_ignores_pop\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"FULL\",\n \"old\": \"pop\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: fifo_0007\n\n// P1_ONEHOT: exactly one occupancy state is visible.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({empty, one, full}));\n\n// P2_RESET: reset empties the FIFO.\np_reset: assert property (@(posedge clk)\n (rst) |=> (empty));\n\n// P3_EMPTY_PUSH: pushing an empty FIFO creates one entry.\np_empty_push: assert property (@(posedge clk) disable iff (rst)\n (empty && push) |=> (one));\n\n// P4_ONE_PUSH: push without pop fills a one-entry FIFO.\np_one_push: assert property (@(posedge clk) disable iff (rst)\n (one && push && !pop) |=> (full));\n\n// P5_ONE_POP: pop without push empties a one-entry FIFO.\np_one_pop: assert property (@(posedge clk) disable iff (rst)\n (one && pop && !push) |=> (empty));\n\n// P6_SIMULTANEOUS: simultaneous push and pop preserves one-entry occupancy.\np_simultaneous: assert property (@(posedge clk) disable iff (rst)\n (one && push && pop) |=> (one));\n\n// P7_FULL_POP: popping a full FIFO leaves one entry.\np_full_pop: assert property (@(posedge clk) disable iff (rst)\n (full && pop) |=> (one));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"exactly one occupancy state is visible\",\n \"expression\": \"$onehot({empty, one, full})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the FIFO\",\n \"antecedent\": \"rst\",\n \"consequent\": \"empty\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_EMPTY_PUSH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pushing an empty FIFO creates one entry\",\n \"antecedent\": \"empty && push\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ONE_PUSH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push without pop fills a one-entry FIFO\",\n \"antecedent\": \"one && push && !pop\",\n \"consequent\": \"full\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_ONE_POP\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without push empties a one-entry FIFO\",\n \"antecedent\": \"one && pop && !push\",\n \"consequent\": \"empty\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_SIMULTANEOUS\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous push and pop preserves one-entry occupancy\",\n \"antecedent\": \"one && push && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_FULL_POP\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"popping a full FIFO leaves one entry\",\n \"antecedent\": \"full && pop\",\n \"consequent\": \"one\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"empty_ignores_push.sv\": \"module fifo_0007_mutant_empty_ignores_push (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (!push) ? EMPTY : (EMPTY);\\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"full_ignores_pop.sv\": \"module fifo_0007_mutant_full_ignores_pop (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\\n ONE: next_state = (push && !pop) ? FULL : ((pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE)));\\n FULL: next_state = (!pop) ? FULL : (FULL);\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"one_never_fills.sv\": \"module fifo_0007_mutant_one_never_fills (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n output reg empty,\\n output reg one,\\n output reg full\\n);\\n localparam [1:0] EMPTY = 2'd0;\\n localparam [1:0] ONE = 2'd1;\\n localparam [1:0] FULL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n EMPTY: next_state = (push) ? ONE : ((!push) ? EMPTY : (EMPTY));\\n ONE: next_state = (pop && !push) ? EMPTY : (((push && pop) || (!push && !pop)) ? ONE : (ONE));\\n FULL: next_state = (pop) ? ONE : ((!pop) ? FULL : (FULL));\\n default: next_state = EMPTY;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= EMPTY;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b0;\\n case (state)\\n EMPTY: begin\\n empty = 1'b1;\\n one = 1'b0;\\n full = 1'b0;\\n end\\n ONE: begin\\n empty = 1'b0;\\n one = 1'b1;\\n full = 1'b0;\\n end\\n FULL: begin\\n empty = 1'b0;\\n one = 1'b0;\\n full = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "fifo_0006", "category": "fifo_control", "description": "Elastic one-entry queue with same-cycle pop-and-replace.", "rtl_variant": "canonical_next.sv", "rtl": "module fifo_0006_canonical_next (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [2:0] din,\n output wire [2:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [2:0] data_reg;\n reg valid_reg;\n\n reg [2:0] next_data_reg;\n reg next_valid_reg;\n\n always @* begin\n if (push && (!valid_reg || pop)) next_data_reg = din;\n else next_data_reg = data_reg;\n if (push && (!valid_reg || pop)) next_valid_reg = 1'b1;\n else if (pop && valid_reg) next_valid_reg = 1'b0;\n else next_valid_reg = valid_reg;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n data_reg <= 3'd0;\n valid_reg <= 1'b0;\n end\n else begin\n data_reg <= next_data_reg;\n valid_reg <= next_valid_reg;\n end\n end\n\n assign dout = data_reg;\n assign valid = valid_reg;\n assign ready = !valid_reg || pop;\nendmodule\n", "spec_json": "{\n \"design_id\": \"fifo_0006\",\n \"category\": \"fifo_control\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"elastic_mailbox\",\n \"description\": \"Elastic one-entry queue with same-cycle pop-and-replace.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"push\",\n \"pop\",\n \"din\"\n ],\n \"outputs\": [\n \"dout\",\n \"valid\",\n \"ready\"\n ],\n \"signal_widths\": {\n \"dout\": 3,\n \"din\": 3\n },\n \"registers\": [\n {\n \"name\": \"data_reg\",\n \"width\": 3,\n \"reset_value\": \"3'd0\"\n },\n {\n \"name\": \"valid_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"dout\": \"data_reg\",\n \"valid\": \"valid_reg\",\n \"ready\": \"!valid_reg || pop\"\n },\n \"update_rules\": {\n \"data_reg\": [\n {\n \"when\": \"push && (!valid_reg || pop)\",\n \"value\": \"din\"\n },\n {\n \"when\": \"true\",\n \"value\": \"data_reg\"\n }\n ],\n \"valid_reg\": [\n {\n \"when\": \"push && (!valid_reg || pop)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"pop && valid_reg\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"true\",\n \"value\": \"valid_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_READY\",\n \"sva_name\": \"p_ready\",\n \"type\": \"invariant\",\n \"natural_language\": \"ready reflects elastic acceptance\",\n \"expression\": \"ready == (!valid || pop)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the queue\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_PUSH_EMPTY\",\n \"sva_name\": \"p_push_empty\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push into empty captures data\",\n \"antecedent\": \"!valid && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HOLD_FULL\",\n \"sva_name\": \"p_hold_full\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"full queue without pop holds data\",\n \"antecedent\": \"valid && !pop\",\n \"consequent\": \"valid && (dout == $past(dout))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_POP\",\n \"sva_name\": \"p_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without replacement empties queue\",\n \"antecedent\": \"valid && pop && !push\",\n \"consequent\": \"!valid\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REPLACE\",\n \"sva_name\": \"p_replace\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous pop and push replaces item\",\n \"antecedent\": \"valid && pop && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_pop\",\n \"register\": \"valid_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"pop && valid_reg\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_replacement\",\n \"register\": \"valid_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"push && (!valid_reg || pop)\",\n \"new\": \"push && !valid_reg\"\n },\n {\n \"name\": \"overwrite_without_accept\",\n \"register\": \"data_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"push && (!valid_reg || pop)\",\n \"new\": \"push\"\n }\n ]\n}\n", "properties_sva": "// P1_READY: ready reflects elastic acceptance\nproperty p_ready;\n @(posedge clk) disable iff (rst) (ready == (!valid || pop));\nendproperty\nassert property (p_ready);\n\n// P2_RESET: reset empties the queue\nproperty p_reset;\n @(posedge clk) (rst) |=> (!valid);\nendproperty\nassert property (p_reset);\n\n// P3_PUSH_EMPTY: push into empty captures data\nproperty p_push_empty;\n @(posedge clk) disable iff (rst) (!valid && push) |=> (valid && (dout == $past(din)));\nendproperty\nassert property (p_push_empty);\n\n// P4_HOLD_FULL: full queue without pop holds data\nproperty p_hold_full;\n @(posedge clk) disable iff (rst) (valid && !pop) |=> (valid && (dout == $past(dout)));\nendproperty\nassert property (p_hold_full);\n\n// P5_POP: pop without replacement empties queue\nproperty p_pop;\n @(posedge clk) disable iff (rst) (valid && pop && !push) |=> (!valid);\nendproperty\nassert property (p_pop);\n\n// P6_REPLACE: simultaneous pop and push replaces item\nproperty p_replace;\n @(posedge clk) disable iff (rst) (valid && pop && push) |=> (valid && (dout == $past(din)));\nendproperty\nassert property (p_replace);\n", "properties_json": "[\n {\n \"id\": \"P1_READY\",\n \"sva_name\": \"p_ready\",\n \"type\": \"invariant\",\n \"natural_language\": \"ready reflects elastic acceptance\",\n \"expression\": \"ready == (!valid || pop)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the queue\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_PUSH_EMPTY\",\n \"sva_name\": \"p_push_empty\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push into empty captures data\",\n \"antecedent\": \"!valid && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HOLD_FULL\",\n \"sva_name\": \"p_hold_full\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"full queue without pop holds data\",\n \"antecedent\": \"valid && !pop\",\n \"consequent\": \"valid && (dout == $past(dout))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_POP\",\n \"sva_name\": \"p_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without replacement empties queue\",\n \"antecedent\": \"valid && pop && !push\",\n \"consequent\": \"!valid\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REPLACE\",\n \"sva_name\": \"p_replace\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous pop and push replaces item\",\n \"antecedent\": \"valid && pop && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_replacement.sv\": \"module fifo_0006_mutant_drop_replacement (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push && (!valid_reg || pop)) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && !valid_reg) valid_reg <= 1'b1;\\n else if (pop && valid_reg) valid_reg <= 1'b0;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\", \"ignore_pop.sv\": \"module fifo_0006_mutant_ignore_pop (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push && (!valid_reg || pop)) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\", \"overwrite_without_accept.sv\": \"module fifo_0006_mutant_overwrite_without_accept (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\\n else if (pop && valid_reg) valid_reg <= 1'b0;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\"}"} {"family_id": "fifo_0006", "category": "fifo_control", "description": "Elastic one-entry queue with same-cycle pop-and-replace.", "rtl_variant": "sequential_priority.sv", "rtl": "module fifo_0006_sequential_priority (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [2:0] din,\n output wire [2:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [2:0] data_reg;\n reg valid_reg;\n\n always @(posedge clk) begin\n if (rst) begin\n data_reg <= 3'd0;\n valid_reg <= 1'b0;\n end\n else begin\n if (push && (!valid_reg || pop)) data_reg <= din;\n else data_reg <= data_reg;\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\n else if (pop && valid_reg) valid_reg <= 1'b0;\n else valid_reg <= valid_reg;\n end\n end\n\n assign dout = data_reg;\n assign valid = valid_reg;\n assign ready = !valid_reg || pop;\nendmodule\n", "spec_json": "{\n \"design_id\": \"fifo_0006\",\n \"category\": \"fifo_control\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"elastic_mailbox\",\n \"description\": \"Elastic one-entry queue with same-cycle pop-and-replace.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"push\",\n \"pop\",\n \"din\"\n ],\n \"outputs\": [\n \"dout\",\n \"valid\",\n \"ready\"\n ],\n \"signal_widths\": {\n \"dout\": 3,\n \"din\": 3\n },\n \"registers\": [\n {\n \"name\": \"data_reg\",\n \"width\": 3,\n \"reset_value\": \"3'd0\"\n },\n {\n \"name\": \"valid_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"dout\": \"data_reg\",\n \"valid\": \"valid_reg\",\n \"ready\": \"!valid_reg || pop\"\n },\n \"update_rules\": {\n \"data_reg\": [\n {\n \"when\": \"push && (!valid_reg || pop)\",\n \"value\": \"din\"\n },\n {\n \"when\": \"true\",\n \"value\": \"data_reg\"\n }\n ],\n \"valid_reg\": [\n {\n \"when\": \"push && (!valid_reg || pop)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"pop && valid_reg\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"true\",\n \"value\": \"valid_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_READY\",\n \"sva_name\": \"p_ready\",\n \"type\": \"invariant\",\n \"natural_language\": \"ready reflects elastic acceptance\",\n \"expression\": \"ready == (!valid || pop)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the queue\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_PUSH_EMPTY\",\n \"sva_name\": \"p_push_empty\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push into empty captures data\",\n \"antecedent\": \"!valid && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HOLD_FULL\",\n \"sva_name\": \"p_hold_full\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"full queue without pop holds data\",\n \"antecedent\": \"valid && !pop\",\n \"consequent\": \"valid && (dout == $past(dout))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_POP\",\n \"sva_name\": \"p_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without replacement empties queue\",\n \"antecedent\": \"valid && pop && !push\",\n \"consequent\": \"!valid\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REPLACE\",\n \"sva_name\": \"p_replace\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous pop and push replaces item\",\n \"antecedent\": \"valid && pop && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_pop\",\n \"register\": \"valid_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"pop && valid_reg\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_replacement\",\n \"register\": \"valid_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"push && (!valid_reg || pop)\",\n \"new\": \"push && !valid_reg\"\n },\n {\n \"name\": \"overwrite_without_accept\",\n \"register\": \"data_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"push && (!valid_reg || pop)\",\n \"new\": \"push\"\n }\n ]\n}\n", "properties_sva": "// P1_READY: ready reflects elastic acceptance\nproperty p_ready;\n @(posedge clk) disable iff (rst) (ready == (!valid || pop));\nendproperty\nassert property (p_ready);\n\n// P2_RESET: reset empties the queue\nproperty p_reset;\n @(posedge clk) (rst) |=> (!valid);\nendproperty\nassert property (p_reset);\n\n// P3_PUSH_EMPTY: push into empty captures data\nproperty p_push_empty;\n @(posedge clk) disable iff (rst) (!valid && push) |=> (valid && (dout == $past(din)));\nendproperty\nassert property (p_push_empty);\n\n// P4_HOLD_FULL: full queue without pop holds data\nproperty p_hold_full;\n @(posedge clk) disable iff (rst) (valid && !pop) |=> (valid && (dout == $past(dout)));\nendproperty\nassert property (p_hold_full);\n\n// P5_POP: pop without replacement empties queue\nproperty p_pop;\n @(posedge clk) disable iff (rst) (valid && pop && !push) |=> (!valid);\nendproperty\nassert property (p_pop);\n\n// P6_REPLACE: simultaneous pop and push replaces item\nproperty p_replace;\n @(posedge clk) disable iff (rst) (valid && pop && push) |=> (valid && (dout == $past(din)));\nendproperty\nassert property (p_replace);\n", "properties_json": "[\n {\n \"id\": \"P1_READY\",\n \"sva_name\": \"p_ready\",\n \"type\": \"invariant\",\n \"natural_language\": \"ready reflects elastic acceptance\",\n \"expression\": \"ready == (!valid || pop)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the queue\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_PUSH_EMPTY\",\n \"sva_name\": \"p_push_empty\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push into empty captures data\",\n \"antecedent\": \"!valid && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HOLD_FULL\",\n \"sva_name\": \"p_hold_full\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"full queue without pop holds data\",\n \"antecedent\": \"valid && !pop\",\n \"consequent\": \"valid && (dout == $past(dout))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_POP\",\n \"sva_name\": \"p_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without replacement empties queue\",\n \"antecedent\": \"valid && pop && !push\",\n \"consequent\": \"!valid\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REPLACE\",\n \"sva_name\": \"p_replace\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous pop and push replaces item\",\n \"antecedent\": \"valid && pop && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_replacement.sv\": \"module fifo_0006_mutant_drop_replacement (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push && (!valid_reg || pop)) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && !valid_reg) valid_reg <= 1'b1;\\n else if (pop && valid_reg) valid_reg <= 1'b0;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\", \"ignore_pop.sv\": \"module fifo_0006_mutant_ignore_pop (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push && (!valid_reg || pop)) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\", \"overwrite_without_accept.sv\": \"module fifo_0006_mutant_overwrite_without_accept (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\\n else if (pop && valid_reg) valid_reg <= 1'b0;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\"}"} {"family_id": "fifo_0006", "category": "fifo_control", "description": "Elastic one-entry queue with same-cycle pop-and-replace.", "rtl_variant": "ternary_next.sv", "rtl": "module fifo_0006_ternary_next (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [2:0] din,\n output wire [2:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [2:0] data_reg;\n reg valid_reg;\n\n wire [2:0] next_data_reg;\n wire next_valid_reg;\n\n assign next_data_reg = (push && (!valid_reg || pop)) ? (din) : (data_reg);\n assign next_valid_reg = (push && (!valid_reg || pop)) ? (1'b1) : ((pop && valid_reg) ? (1'b0) : (valid_reg));\n\n always @(posedge clk) begin\n if (rst) begin\n data_reg <= 3'd0;\n valid_reg <= 1'b0;\n end\n else begin\n data_reg <= next_data_reg;\n valid_reg <= next_valid_reg;\n end\n end\n\n assign dout = data_reg;\n assign valid = valid_reg;\n assign ready = !valid_reg || pop;\nendmodule\n", "spec_json": "{\n \"design_id\": \"fifo_0006\",\n \"category\": \"fifo_control\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"elastic_mailbox\",\n \"description\": \"Elastic one-entry queue with same-cycle pop-and-replace.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"push\",\n \"pop\",\n \"din\"\n ],\n \"outputs\": [\n \"dout\",\n \"valid\",\n \"ready\"\n ],\n \"signal_widths\": {\n \"dout\": 3,\n \"din\": 3\n },\n \"registers\": [\n {\n \"name\": \"data_reg\",\n \"width\": 3,\n \"reset_value\": \"3'd0\"\n },\n {\n \"name\": \"valid_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"dout\": \"data_reg\",\n \"valid\": \"valid_reg\",\n \"ready\": \"!valid_reg || pop\"\n },\n \"update_rules\": {\n \"data_reg\": [\n {\n \"when\": \"push && (!valid_reg || pop)\",\n \"value\": \"din\"\n },\n {\n \"when\": \"true\",\n \"value\": \"data_reg\"\n }\n ],\n \"valid_reg\": [\n {\n \"when\": \"push && (!valid_reg || pop)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"pop && valid_reg\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"true\",\n \"value\": \"valid_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_READY\",\n \"sva_name\": \"p_ready\",\n \"type\": \"invariant\",\n \"natural_language\": \"ready reflects elastic acceptance\",\n \"expression\": \"ready == (!valid || pop)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the queue\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_PUSH_EMPTY\",\n \"sva_name\": \"p_push_empty\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push into empty captures data\",\n \"antecedent\": \"!valid && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HOLD_FULL\",\n \"sva_name\": \"p_hold_full\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"full queue without pop holds data\",\n \"antecedent\": \"valid && !pop\",\n \"consequent\": \"valid && (dout == $past(dout))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_POP\",\n \"sva_name\": \"p_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without replacement empties queue\",\n \"antecedent\": \"valid && pop && !push\",\n \"consequent\": \"!valid\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REPLACE\",\n \"sva_name\": \"p_replace\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous pop and push replaces item\",\n \"antecedent\": \"valid && pop && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_pop\",\n \"register\": \"valid_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"pop && valid_reg\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_replacement\",\n \"register\": \"valid_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"push && (!valid_reg || pop)\",\n \"new\": \"push && !valid_reg\"\n },\n {\n \"name\": \"overwrite_without_accept\",\n \"register\": \"data_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"push && (!valid_reg || pop)\",\n \"new\": \"push\"\n }\n ]\n}\n", "properties_sva": "// P1_READY: ready reflects elastic acceptance\nproperty p_ready;\n @(posedge clk) disable iff (rst) (ready == (!valid || pop));\nendproperty\nassert property (p_ready);\n\n// P2_RESET: reset empties the queue\nproperty p_reset;\n @(posedge clk) (rst) |=> (!valid);\nendproperty\nassert property (p_reset);\n\n// P3_PUSH_EMPTY: push into empty captures data\nproperty p_push_empty;\n @(posedge clk) disable iff (rst) (!valid && push) |=> (valid && (dout == $past(din)));\nendproperty\nassert property (p_push_empty);\n\n// P4_HOLD_FULL: full queue without pop holds data\nproperty p_hold_full;\n @(posedge clk) disable iff (rst) (valid && !pop) |=> (valid && (dout == $past(dout)));\nendproperty\nassert property (p_hold_full);\n\n// P5_POP: pop without replacement empties queue\nproperty p_pop;\n @(posedge clk) disable iff (rst) (valid && pop && !push) |=> (!valid);\nendproperty\nassert property (p_pop);\n\n// P6_REPLACE: simultaneous pop and push replaces item\nproperty p_replace;\n @(posedge clk) disable iff (rst) (valid && pop && push) |=> (valid && (dout == $past(din)));\nendproperty\nassert property (p_replace);\n", "properties_json": "[\n {\n \"id\": \"P1_READY\",\n \"sva_name\": \"p_ready\",\n \"type\": \"invariant\",\n \"natural_language\": \"ready reflects elastic acceptance\",\n \"expression\": \"ready == (!valid || pop)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the queue\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_PUSH_EMPTY\",\n \"sva_name\": \"p_push_empty\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push into empty captures data\",\n \"antecedent\": \"!valid && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HOLD_FULL\",\n \"sva_name\": \"p_hold_full\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"full queue without pop holds data\",\n \"antecedent\": \"valid && !pop\",\n \"consequent\": \"valid && (dout == $past(dout))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_POP\",\n \"sva_name\": \"p_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without replacement empties queue\",\n \"antecedent\": \"valid && pop && !push\",\n \"consequent\": \"!valid\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REPLACE\",\n \"sva_name\": \"p_replace\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous pop and push replaces item\",\n \"antecedent\": \"valid && pop && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_replacement.sv\": \"module fifo_0006_mutant_drop_replacement (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push && (!valid_reg || pop)) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && !valid_reg) valid_reg <= 1'b1;\\n else if (pop && valid_reg) valid_reg <= 1'b0;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\", \"ignore_pop.sv\": \"module fifo_0006_mutant_ignore_pop (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push && (!valid_reg || pop)) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\", \"overwrite_without_accept.sv\": \"module fifo_0006_mutant_overwrite_without_accept (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\\n else if (pop && valid_reg) valid_reg <= 1'b0;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\"}"} {"family_id": "fifo_0006", "category": "fifo_control", "description": "Elastic one-entry queue with same-cycle pop-and-replace.", "rtl_variant": "function_update.sv", "rtl": "module fifo_0006_function_update (\n input wire clk,\n input wire rst,\n input wire push,\n input wire pop,\n input wire [2:0] din,\n output wire [2:0] dout,\n output wire valid,\n output wire ready\n);\n\n reg [2:0] data_reg;\n reg valid_reg;\n\n function automatic [2:0] compute_next_data_reg;\n input [2:0] current_data_reg;\n input current_valid_reg;\n input push;\n input pop;\n input [2:0] din;\n begin\n if (push && (!current_valid_reg || pop)) compute_next_data_reg = din;\n else compute_next_data_reg = current_data_reg;\n end\n endfunction\n\n function automatic compute_next_valid_reg;\n input [2:0] current_data_reg;\n input current_valid_reg;\n input push;\n input pop;\n input [2:0] din;\n begin\n if (push && (!current_valid_reg || pop)) compute_next_valid_reg = 1'b1;\n else if (pop && current_valid_reg) compute_next_valid_reg = 1'b0;\n else compute_next_valid_reg = current_valid_reg;\n end\n endfunction\n\n wire [2:0] next_data_reg;\n wire next_valid_reg;\n\n assign next_data_reg = compute_next_data_reg(data_reg, valid_reg, push, pop, din);\n assign next_valid_reg = compute_next_valid_reg(data_reg, valid_reg, push, pop, din);\n\n always @(posedge clk) begin\n if (rst) begin\n data_reg <= 3'd0;\n valid_reg <= 1'b0;\n end\n else begin\n data_reg <= next_data_reg;\n valid_reg <= next_valid_reg;\n end\n end\n\n assign dout = data_reg;\n assign valid = valid_reg;\n assign ready = !valid_reg || pop;\nendmodule\n", "spec_json": "{\n \"design_id\": \"fifo_0006\",\n \"category\": \"fifo_control\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"elastic_mailbox\",\n \"description\": \"Elastic one-entry queue with same-cycle pop-and-replace.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"push\",\n \"pop\",\n \"din\"\n ],\n \"outputs\": [\n \"dout\",\n \"valid\",\n \"ready\"\n ],\n \"signal_widths\": {\n \"dout\": 3,\n \"din\": 3\n },\n \"registers\": [\n {\n \"name\": \"data_reg\",\n \"width\": 3,\n \"reset_value\": \"3'd0\"\n },\n {\n \"name\": \"valid_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"dout\": \"data_reg\",\n \"valid\": \"valid_reg\",\n \"ready\": \"!valid_reg || pop\"\n },\n \"update_rules\": {\n \"data_reg\": [\n {\n \"when\": \"push && (!valid_reg || pop)\",\n \"value\": \"din\"\n },\n {\n \"when\": \"true\",\n \"value\": \"data_reg\"\n }\n ],\n \"valid_reg\": [\n {\n \"when\": \"push && (!valid_reg || pop)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"pop && valid_reg\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"true\",\n \"value\": \"valid_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_READY\",\n \"sva_name\": \"p_ready\",\n \"type\": \"invariant\",\n \"natural_language\": \"ready reflects elastic acceptance\",\n \"expression\": \"ready == (!valid || pop)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the queue\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_PUSH_EMPTY\",\n \"sva_name\": \"p_push_empty\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push into empty captures data\",\n \"antecedent\": \"!valid && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HOLD_FULL\",\n \"sva_name\": \"p_hold_full\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"full queue without pop holds data\",\n \"antecedent\": \"valid && !pop\",\n \"consequent\": \"valid && (dout == $past(dout))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_POP\",\n \"sva_name\": \"p_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without replacement empties queue\",\n \"antecedent\": \"valid && pop && !push\",\n \"consequent\": \"!valid\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REPLACE\",\n \"sva_name\": \"p_replace\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous pop and push replaces item\",\n \"antecedent\": \"valid && pop && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_pop\",\n \"register\": \"valid_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"pop && valid_reg\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_replacement\",\n \"register\": \"valid_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"push && (!valid_reg || pop)\",\n \"new\": \"push && !valid_reg\"\n },\n {\n \"name\": \"overwrite_without_accept\",\n \"register\": \"data_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"push && (!valid_reg || pop)\",\n \"new\": \"push\"\n }\n ]\n}\n", "properties_sva": "// P1_READY: ready reflects elastic acceptance\nproperty p_ready;\n @(posedge clk) disable iff (rst) (ready == (!valid || pop));\nendproperty\nassert property (p_ready);\n\n// P2_RESET: reset empties the queue\nproperty p_reset;\n @(posedge clk) (rst) |=> (!valid);\nendproperty\nassert property (p_reset);\n\n// P3_PUSH_EMPTY: push into empty captures data\nproperty p_push_empty;\n @(posedge clk) disable iff (rst) (!valid && push) |=> (valid && (dout == $past(din)));\nendproperty\nassert property (p_push_empty);\n\n// P4_HOLD_FULL: full queue without pop holds data\nproperty p_hold_full;\n @(posedge clk) disable iff (rst) (valid && !pop) |=> (valid && (dout == $past(dout)));\nendproperty\nassert property (p_hold_full);\n\n// P5_POP: pop without replacement empties queue\nproperty p_pop;\n @(posedge clk) disable iff (rst) (valid && pop && !push) |=> (!valid);\nendproperty\nassert property (p_pop);\n\n// P6_REPLACE: simultaneous pop and push replaces item\nproperty p_replace;\n @(posedge clk) disable iff (rst) (valid && pop && push) |=> (valid && (dout == $past(din)));\nendproperty\nassert property (p_replace);\n", "properties_json": "[\n {\n \"id\": \"P1_READY\",\n \"sva_name\": \"p_ready\",\n \"type\": \"invariant\",\n \"natural_language\": \"ready reflects elastic acceptance\",\n \"expression\": \"ready == (!valid || pop)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset empties the queue\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_PUSH_EMPTY\",\n \"sva_name\": \"p_push_empty\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"push into empty captures data\",\n \"antecedent\": \"!valid && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HOLD_FULL\",\n \"sva_name\": \"p_hold_full\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"full queue without pop holds data\",\n \"antecedent\": \"valid && !pop\",\n \"consequent\": \"valid && (dout == $past(dout))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_POP\",\n \"sva_name\": \"p_pop\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"pop without replacement empties queue\",\n \"antecedent\": \"valid && pop && !push\",\n \"consequent\": \"!valid\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REPLACE\",\n \"sva_name\": \"p_replace\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"simultaneous pop and push replaces item\",\n \"antecedent\": \"valid && pop && push\",\n \"consequent\": \"valid && (dout == $past(din))\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_replacement.sv\": \"module fifo_0006_mutant_drop_replacement (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push && (!valid_reg || pop)) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && !valid_reg) valid_reg <= 1'b1;\\n else if (pop && valid_reg) valid_reg <= 1'b0;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\", \"ignore_pop.sv\": \"module fifo_0006_mutant_ignore_pop (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push && (!valid_reg || pop)) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\", \"overwrite_without_accept.sv\": \"module fifo_0006_mutant_overwrite_without_accept (\\n input wire clk,\\n input wire rst,\\n input wire push,\\n input wire pop,\\n input wire [2:0] din,\\n output wire [2:0] dout,\\n output wire valid,\\n output wire ready\\n);\\n\\n reg [2:0] data_reg;\\n reg valid_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n data_reg <= 3'd0;\\n valid_reg <= 1'b0;\\n end\\n else begin\\n if (push) data_reg <= din;\\n else data_reg <= data_reg;\\n if (push && (!valid_reg || pop)) valid_reg <= 1'b1;\\n else if (pop && valid_reg) valid_reg <= 1'b0;\\n else valid_reg <= valid_reg;\\n end\\n end\\n\\n assign dout = data_reg;\\n assign valid = valid_reg;\\n assign ready = !valid_reg || pop;\\nendmodule\\n\"}"} {"family_id": "handshake_0007", "category": "handshake", "description": "Producer raises valid, waits for ready, then emits a completion state.", "rtl_variant": "canonical_case.sv", "rtl": "module handshake_0007_canonical_case (\n input wire clk,\n input wire rst,\n input wire produce,\n input wire ready,\n output reg valid,\n output reg done\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] VALID = 2'd1;\n localparam [1:0] DONE = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n IDLE: next_state = (produce) ? VALID : ((!produce) ? IDLE : (IDLE));\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\n DONE: next_state = IDLE;\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n valid = 1'b0;\n done = 1'b0;\n case (state)\n IDLE: begin\n valid = 1'b0;\n done = 1'b0;\n end\n VALID: begin\n valid = 1'b1;\n done = 1'b0;\n end\n DONE: begin\n valid = 1'b0;\n done = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"handshake_0007\",\n \"category\": \"handshake\",\n \"template\": \"valid_ready_completion\",\n \"description\": \"Producer raises valid, waits for ready, then emits a completion state.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"produce\",\n \"ready\"\n ],\n \"outputs\": [\n \"valid\",\n \"done\"\n ],\n \"states\": [\n \"IDLE\",\n \"VALID\",\n \"DONE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"valid\": 0,\n \"done\": 0\n },\n \"VALID\": {\n \"valid\": 1,\n \"done\": 0\n },\n \"DONE\": {\n \"valid\": 0,\n \"done\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"produce\",\n \"to\": \"VALID\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!produce\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"VALID\",\n \"when\": \"ready\",\n \"to\": \"DONE\"\n },\n {\n \"from\": \"VALID\",\n \"when\": \"!ready\",\n \"to\": \"VALID\"\n },\n {\n \"from\": \"DONE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({valid, done})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to VALID when produce\",\n \"antecedent\": \"(!valid && !done) && (produce)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !produce\",\n \"antecedent\": \"(!valid && !done) && (!produce)\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to DONE when ready\",\n \"antecedent\": \"(valid && !done) && (ready)\",\n \"consequent\": \"!valid && done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to VALID when !ready\",\n \"antecedent\": \"(valid && !done) && (!ready)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"DONE transitions to IDLE when true\",\n \"antecedent\": \"!valid && done\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"produce\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"VALID\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"VALID\",\n \"old\": \"ready\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: handshake_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({valid, done}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!valid && !done));\n\n// P3_T1: IDLE transitions to VALID when produce.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!valid && !done) && (produce)) |=> (valid && !done));\n\n// P4_T2: IDLE transitions to IDLE when !produce.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!valid && !done) && (!produce)) |=> (!valid && !done));\n\n// P5_T3: VALID transitions to DONE when ready.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((valid && !done) && (ready)) |=> (!valid && done));\n\n// P6_T4: VALID transitions to VALID when !ready.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((valid && !done) && (!ready)) |=> (valid && !done));\n\n// P7_T5: DONE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!valid && done) |=> (!valid && !done));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({valid, done})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to VALID when produce\",\n \"antecedent\": \"(!valid && !done) && (produce)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !produce\",\n \"antecedent\": \"(!valid && !done) && (!produce)\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to DONE when ready\",\n \"antecedent\": \"(valid && !done) && (ready)\",\n \"consequent\": \"!valid && done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to VALID when !ready\",\n \"antecedent\": \"(valid && !done) && (!ready)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"DONE transitions to IDLE when true\",\n \"antecedent\": \"!valid && done\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module handshake_0007_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!produce) ? IDLE : (IDLE);\\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module handshake_0007_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (produce) ? VALID : ((!produce) ? IDLE : (IDLE));\\n VALID: next_state = (!ready) ? VALID : (VALID);\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module handshake_0007_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = VALID;\\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "handshake_0007", "category": "handshake", "description": "Producer raises valid, waits for ready, then emits a completion state.", "rtl_variant": "onehot_case.sv", "rtl": "module handshake_0007_onehot_case (\n input wire clk,\n input wire rst,\n input wire produce,\n input wire ready,\n output reg valid,\n output reg done\n);\n localparam [2:0] IDLE = 3'b001;\n localparam [2:0] VALID = 3'b010;\n localparam [2:0] DONE = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = IDLE;\n case (state)\n IDLE: next_state = (produce) ? VALID : ((!produce) ? IDLE : (IDLE));\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\n DONE: next_state = IDLE;\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n valid = (state == VALID);\n done = (state == DONE);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"handshake_0007\",\n \"category\": \"handshake\",\n \"template\": \"valid_ready_completion\",\n \"description\": \"Producer raises valid, waits for ready, then emits a completion state.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"produce\",\n \"ready\"\n ],\n \"outputs\": [\n \"valid\",\n \"done\"\n ],\n \"states\": [\n \"IDLE\",\n \"VALID\",\n \"DONE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"valid\": 0,\n \"done\": 0\n },\n \"VALID\": {\n \"valid\": 1,\n \"done\": 0\n },\n \"DONE\": {\n \"valid\": 0,\n \"done\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"produce\",\n \"to\": \"VALID\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!produce\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"VALID\",\n \"when\": \"ready\",\n \"to\": \"DONE\"\n },\n {\n \"from\": \"VALID\",\n \"when\": \"!ready\",\n \"to\": \"VALID\"\n },\n {\n \"from\": \"DONE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({valid, done})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to VALID when produce\",\n \"antecedent\": \"(!valid && !done) && (produce)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !produce\",\n \"antecedent\": \"(!valid && !done) && (!produce)\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to DONE when ready\",\n \"antecedent\": \"(valid && !done) && (ready)\",\n \"consequent\": \"!valid && done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to VALID when !ready\",\n \"antecedent\": \"(valid && !done) && (!ready)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"DONE transitions to IDLE when true\",\n \"antecedent\": \"!valid && done\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"produce\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"VALID\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"VALID\",\n \"old\": \"ready\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: handshake_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({valid, done}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!valid && !done));\n\n// P3_T1: IDLE transitions to VALID when produce.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!valid && !done) && (produce)) |=> (valid && !done));\n\n// P4_T2: IDLE transitions to IDLE when !produce.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!valid && !done) && (!produce)) |=> (!valid && !done));\n\n// P5_T3: VALID transitions to DONE when ready.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((valid && !done) && (ready)) |=> (!valid && done));\n\n// P6_T4: VALID transitions to VALID when !ready.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((valid && !done) && (!ready)) |=> (valid && !done));\n\n// P7_T5: DONE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!valid && done) |=> (!valid && !done));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({valid, done})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to VALID when produce\",\n \"antecedent\": \"(!valid && !done) && (produce)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !produce\",\n \"antecedent\": \"(!valid && !done) && (!produce)\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to DONE when ready\",\n \"antecedent\": \"(valid && !done) && (ready)\",\n \"consequent\": \"!valid && done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to VALID when !ready\",\n \"antecedent\": \"(valid && !done) && (!ready)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"DONE transitions to IDLE when true\",\n \"antecedent\": \"!valid && done\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module handshake_0007_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!produce) ? IDLE : (IDLE);\\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module handshake_0007_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (produce) ? VALID : ((!produce) ? IDLE : (IDLE));\\n VALID: next_state = (!ready) ? VALID : (VALID);\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module handshake_0007_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = VALID;\\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "handshake_0007", "category": "handshake", "description": "Producer raises valid, waits for ready, then emits a completion state.", "rtl_variant": "nested_if.sv", "rtl": "module handshake_0007_nested_if (\n input wire clk,\n input wire rst,\n input wire produce,\n input wire ready,\n output wire valid,\n output wire done\n);\n localparam [1:0] S_IDLE = 2'd0;\n localparam [1:0] S_VALID = 2'd1;\n localparam [1:0] S_DONE = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_IDLE;\n end else begin\n if (state == S_IDLE) begin\n state <= (produce) ? S_VALID : ((!produce) ? S_IDLE : (S_IDLE));\n end\n else if (state == S_VALID) begin\n state <= (ready) ? S_DONE : ((!ready) ? S_VALID : (S_VALID));\n end\n else if (state == S_DONE) begin\n state <= S_IDLE;\n end\n else begin\n state <= S_IDLE;\n end\n end\n end\n\n assign valid = (state == S_VALID);\n assign done = (state == S_DONE);\nendmodule\n", "spec_json": "{\n \"design_id\": \"handshake_0007\",\n \"category\": \"handshake\",\n \"template\": \"valid_ready_completion\",\n \"description\": \"Producer raises valid, waits for ready, then emits a completion state.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"produce\",\n \"ready\"\n ],\n \"outputs\": [\n \"valid\",\n \"done\"\n ],\n \"states\": [\n \"IDLE\",\n \"VALID\",\n \"DONE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"valid\": 0,\n \"done\": 0\n },\n \"VALID\": {\n \"valid\": 1,\n \"done\": 0\n },\n \"DONE\": {\n \"valid\": 0,\n \"done\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"produce\",\n \"to\": \"VALID\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!produce\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"VALID\",\n \"when\": \"ready\",\n \"to\": \"DONE\"\n },\n {\n \"from\": \"VALID\",\n \"when\": \"!ready\",\n \"to\": \"VALID\"\n },\n {\n \"from\": \"DONE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({valid, done})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to VALID when produce\",\n \"antecedent\": \"(!valid && !done) && (produce)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !produce\",\n \"antecedent\": \"(!valid && !done) && (!produce)\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to DONE when ready\",\n \"antecedent\": \"(valid && !done) && (ready)\",\n \"consequent\": \"!valid && done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to VALID when !ready\",\n \"antecedent\": \"(valid && !done) && (!ready)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"DONE transitions to IDLE when true\",\n \"antecedent\": \"!valid && done\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"produce\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"VALID\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"VALID\",\n \"old\": \"ready\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: handshake_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({valid, done}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!valid && !done));\n\n// P3_T1: IDLE transitions to VALID when produce.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!valid && !done) && (produce)) |=> (valid && !done));\n\n// P4_T2: IDLE transitions to IDLE when !produce.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!valid && !done) && (!produce)) |=> (!valid && !done));\n\n// P5_T3: VALID transitions to DONE when ready.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((valid && !done) && (ready)) |=> (!valid && done));\n\n// P6_T4: VALID transitions to VALID when !ready.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((valid && !done) && (!ready)) |=> (valid && !done));\n\n// P7_T5: DONE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!valid && done) |=> (!valid && !done));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({valid, done})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to VALID when produce\",\n \"antecedent\": \"(!valid && !done) && (produce)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !produce\",\n \"antecedent\": \"(!valid && !done) && (!produce)\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to DONE when ready\",\n \"antecedent\": \"(valid && !done) && (ready)\",\n \"consequent\": \"!valid && done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to VALID when !ready\",\n \"antecedent\": \"(valid && !done) && (!ready)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"DONE transitions to IDLE when true\",\n \"antecedent\": \"!valid && done\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module handshake_0007_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!produce) ? IDLE : (IDLE);\\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module handshake_0007_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (produce) ? VALID : ((!produce) ? IDLE : (IDLE));\\n VALID: next_state = (!ready) ? VALID : (VALID);\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module handshake_0007_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = VALID;\\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "handshake_0007", "category": "handshake", "description": "Producer raises valid, waits for ready, then emits a completion state.", "rtl_variant": "factored_flags.sv", "rtl": "module handshake_0007_factored_flags (\n input wire clk,\n input wire rst,\n input wire produce,\n input wire ready,\n output reg valid,\n output reg done\n);\n localparam [1:0] F_IDLE = 2'd0;\n localparam [1:0] F_VALID = 2'd1;\n localparam [1:0] F_DONE = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_idle_0 = (produce);\n wire guard_idle_1 = (!produce);\n wire guard_valid_0 = (ready);\n wire guard_valid_1 = (!ready);\n\n always @* begin\n next_state = state;\n case (state)\n F_IDLE: begin\n if (guard_idle_0)\n next_state = F_VALID;\n else if (guard_idle_1)\n next_state = F_IDLE;\n end\n F_VALID: begin\n if (guard_valid_0)\n next_state = F_DONE;\n else if (guard_valid_1)\n next_state = F_VALID;\n end\n F_DONE: begin\n next_state = F_IDLE;\n end\n default: next_state = F_IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n valid = 1'b0;\n done = 1'b0;\n case (state)\n F_IDLE: begin\n valid = 1'b0;\n done = 1'b0;\n end\n F_VALID: begin\n valid = 1'b1;\n done = 1'b0;\n end\n F_DONE: begin\n valid = 1'b0;\n done = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"handshake_0007\",\n \"category\": \"handshake\",\n \"template\": \"valid_ready_completion\",\n \"description\": \"Producer raises valid, waits for ready, then emits a completion state.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"produce\",\n \"ready\"\n ],\n \"outputs\": [\n \"valid\",\n \"done\"\n ],\n \"states\": [\n \"IDLE\",\n \"VALID\",\n \"DONE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"valid\": 0,\n \"done\": 0\n },\n \"VALID\": {\n \"valid\": 1,\n \"done\": 0\n },\n \"DONE\": {\n \"valid\": 0,\n \"done\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"produce\",\n \"to\": \"VALID\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!produce\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"VALID\",\n \"when\": \"ready\",\n \"to\": \"DONE\"\n },\n {\n \"from\": \"VALID\",\n \"when\": \"!ready\",\n \"to\": \"VALID\"\n },\n {\n \"from\": \"DONE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({valid, done})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to VALID when produce\",\n \"antecedent\": \"(!valid && !done) && (produce)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !produce\",\n \"antecedent\": \"(!valid && !done) && (!produce)\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to DONE when ready\",\n \"antecedent\": \"(valid && !done) && (ready)\",\n \"consequent\": \"!valid && done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to VALID when !ready\",\n \"antecedent\": \"(valid && !done) && (!ready)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"DONE transitions to IDLE when true\",\n \"antecedent\": \"!valid && done\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"produce\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"VALID\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"VALID\",\n \"old\": \"ready\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: handshake_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({valid, done}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!valid && !done));\n\n// P3_T1: IDLE transitions to VALID when produce.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!valid && !done) && (produce)) |=> (valid && !done));\n\n// P4_T2: IDLE transitions to IDLE when !produce.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!valid && !done) && (!produce)) |=> (!valid && !done));\n\n// P5_T3: VALID transitions to DONE when ready.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((valid && !done) && (ready)) |=> (!valid && done));\n\n// P6_T4: VALID transitions to VALID when !ready.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((valid && !done) && (!ready)) |=> (valid && !done));\n\n// P7_T5: DONE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!valid && done) |=> (!valid && !done));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({valid, done})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to VALID when produce\",\n \"antecedent\": \"(!valid && !done) && (produce)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !produce\",\n \"antecedent\": \"(!valid && !done) && (!produce)\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to DONE when ready\",\n \"antecedent\": \"(valid && !done) && (ready)\",\n \"consequent\": \"!valid && done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"VALID transitions to VALID when !ready\",\n \"antecedent\": \"(valid && !done) && (!ready)\",\n \"consequent\": \"valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"DONE transitions to IDLE when true\",\n \"antecedent\": \"!valid && done\",\n \"consequent\": \"!valid && !done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module handshake_0007_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!produce) ? IDLE : (IDLE);\\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module handshake_0007_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (produce) ? VALID : ((!produce) ? IDLE : (IDLE));\\n VALID: next_state = (!ready) ? VALID : (VALID);\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module handshake_0007_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire produce,\\n input wire ready,\\n output reg valid,\\n output reg done\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] VALID = 2'd1;\\n localparam [1:0] DONE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = VALID;\\n VALID: next_state = (ready) ? DONE : ((!ready) ? VALID : (VALID));\\n DONE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n valid = 1'b0;\\n done = 1'b0;\\n case (state)\\n IDLE: begin\\n valid = 1'b0;\\n done = 1'b0;\\n end\\n VALID: begin\\n valid = 1'b1;\\n done = 1'b0;\\n end\\n DONE: begin\\n valid = 1'b0;\\n done = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "handshake_0006", "category": "handshake", "description": "Request remains active until acknowledge, then waits for request release.", "rtl_variant": "canonical_case.sv", "rtl": "module handshake_0006_canonical_case (\n input wire clk,\n input wire rst,\n input wire req,\n input wire accept,\n output reg busy,\n output reg ack\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] ACK = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n IDLE: next_state = (req) ? WAIT : ((!req) ? IDLE : (IDLE));\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n busy = 1'b0;\n ack = 1'b0;\n case (state)\n IDLE: begin\n busy = 1'b0;\n ack = 1'b0;\n end\n WAIT: begin\n busy = 1'b1;\n ack = 1'b0;\n end\n ACK: begin\n busy = 1'b0;\n ack = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"handshake_0006\",\n \"category\": \"handshake\",\n \"template\": \"held_request_ack\",\n \"description\": \"Request remains active until acknowledge, then waits for request release.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req\",\n \"accept\"\n ],\n \"outputs\": [\n \"busy\",\n \"ack\"\n ],\n \"states\": [\n \"IDLE\",\n \"WAIT\",\n \"ACK\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"busy\": 0,\n \"ack\": 0\n },\n \"WAIT\": {\n \"busy\": 1,\n \"ack\": 0\n },\n \"ACK\": {\n \"busy\": 0,\n \"ack\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"accept\",\n \"to\": \"ACK\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"!accept\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"ACK\",\n \"when\": \"req\",\n \"to\": \"ACK\"\n },\n {\n \"from\": \"ACK\",\n \"when\": \"!req\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({busy, ack})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when req\",\n \"antecedent\": \"(!busy && !ack) && (req)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && !ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to ACK when accept\",\n \"antecedent\": \"(busy && !ack) && (accept)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !accept\",\n \"antecedent\": \"(busy && !ack) && (!accept)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to ACK when req\",\n \"antecedent\": \"(!busy && ack) && (req)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"WAIT\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"WAIT\",\n \"old\": \"accept\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: handshake_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({busy, ack}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!busy && !ack));\n\n// P3_T1: IDLE transitions to WAIT when req.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!busy && !ack) && (req)) |=> (busy && !ack));\n\n// P4_T2: IDLE transitions to IDLE when !req.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!busy && !ack) && (!req)) |=> (!busy && !ack));\n\n// P5_T3: WAIT transitions to ACK when accept.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((busy && !ack) && (accept)) |=> (!busy && ack));\n\n// P6_T4: WAIT transitions to WAIT when !accept.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((busy && !ack) && (!accept)) |=> (busy && !ack));\n\n// P7_T5: ACK transitions to ACK when req.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!busy && ack) && (req)) |=> (!busy && ack));\n\n// P8_T6: ACK transitions to IDLE when !req.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!busy && ack) && (!req)) |=> (!busy && !ack));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({busy, ack})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when req\",\n \"antecedent\": \"(!busy && !ack) && (req)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && !ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to ACK when accept\",\n \"antecedent\": \"(busy && !ack) && (accept)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !accept\",\n \"antecedent\": \"(busy && !ack) && (!accept)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to ACK when req\",\n \"antecedent\": \"(!busy && ack) && (req)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module handshake_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req) ? IDLE : (IDLE);\\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module handshake_0006_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req) ? WAIT : ((!req) ? IDLE : (IDLE));\\n WAIT: next_state = (!accept) ? WAIT : (WAIT);\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module handshake_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = WAIT;\\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "handshake_0006", "category": "handshake", "description": "Request remains active until acknowledge, then waits for request release.", "rtl_variant": "onehot_case.sv", "rtl": "module handshake_0006_onehot_case (\n input wire clk,\n input wire rst,\n input wire req,\n input wire accept,\n output reg busy,\n output reg ack\n);\n localparam [2:0] IDLE = 3'b001;\n localparam [2:0] WAIT = 3'b010;\n localparam [2:0] ACK = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = IDLE;\n case (state)\n IDLE: next_state = (req) ? WAIT : ((!req) ? IDLE : (IDLE));\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n busy = (state == WAIT);\n ack = (state == ACK);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"handshake_0006\",\n \"category\": \"handshake\",\n \"template\": \"held_request_ack\",\n \"description\": \"Request remains active until acknowledge, then waits for request release.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req\",\n \"accept\"\n ],\n \"outputs\": [\n \"busy\",\n \"ack\"\n ],\n \"states\": [\n \"IDLE\",\n \"WAIT\",\n \"ACK\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"busy\": 0,\n \"ack\": 0\n },\n \"WAIT\": {\n \"busy\": 1,\n \"ack\": 0\n },\n \"ACK\": {\n \"busy\": 0,\n \"ack\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"accept\",\n \"to\": \"ACK\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"!accept\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"ACK\",\n \"when\": \"req\",\n \"to\": \"ACK\"\n },\n {\n \"from\": \"ACK\",\n \"when\": \"!req\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({busy, ack})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when req\",\n \"antecedent\": \"(!busy && !ack) && (req)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && !ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to ACK when accept\",\n \"antecedent\": \"(busy && !ack) && (accept)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !accept\",\n \"antecedent\": \"(busy && !ack) && (!accept)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to ACK when req\",\n \"antecedent\": \"(!busy && ack) && (req)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"WAIT\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"WAIT\",\n \"old\": \"accept\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: handshake_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({busy, ack}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!busy && !ack));\n\n// P3_T1: IDLE transitions to WAIT when req.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!busy && !ack) && (req)) |=> (busy && !ack));\n\n// P4_T2: IDLE transitions to IDLE when !req.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!busy && !ack) && (!req)) |=> (!busy && !ack));\n\n// P5_T3: WAIT transitions to ACK when accept.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((busy && !ack) && (accept)) |=> (!busy && ack));\n\n// P6_T4: WAIT transitions to WAIT when !accept.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((busy && !ack) && (!accept)) |=> (busy && !ack));\n\n// P7_T5: ACK transitions to ACK when req.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!busy && ack) && (req)) |=> (!busy && ack));\n\n// P8_T6: ACK transitions to IDLE when !req.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!busy && ack) && (!req)) |=> (!busy && !ack));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({busy, ack})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when req\",\n \"antecedent\": \"(!busy && !ack) && (req)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && !ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to ACK when accept\",\n \"antecedent\": \"(busy && !ack) && (accept)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !accept\",\n \"antecedent\": \"(busy && !ack) && (!accept)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to ACK when req\",\n \"antecedent\": \"(!busy && ack) && (req)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module handshake_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req) ? IDLE : (IDLE);\\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module handshake_0006_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req) ? WAIT : ((!req) ? IDLE : (IDLE));\\n WAIT: next_state = (!accept) ? WAIT : (WAIT);\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module handshake_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = WAIT;\\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "handshake_0006", "category": "handshake", "description": "Request remains active until acknowledge, then waits for request release.", "rtl_variant": "nested_if.sv", "rtl": "module handshake_0006_nested_if (\n input wire clk,\n input wire rst,\n input wire req,\n input wire accept,\n output wire busy,\n output wire ack\n);\n localparam [1:0] S_IDLE = 2'd0;\n localparam [1:0] S_WAIT = 2'd1;\n localparam [1:0] S_ACK = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_IDLE;\n end else begin\n if (state == S_IDLE) begin\n state <= (req) ? S_WAIT : ((!req) ? S_IDLE : (S_IDLE));\n end\n else if (state == S_WAIT) begin\n state <= (accept) ? S_ACK : ((!accept) ? S_WAIT : (S_WAIT));\n end\n else if (state == S_ACK) begin\n state <= (req) ? S_ACK : ((!req) ? S_IDLE : (S_ACK));\n end\n else begin\n state <= S_IDLE;\n end\n end\n end\n\n assign busy = (state == S_WAIT);\n assign ack = (state == S_ACK);\nendmodule\n", "spec_json": "{\n \"design_id\": \"handshake_0006\",\n \"category\": \"handshake\",\n \"template\": \"held_request_ack\",\n \"description\": \"Request remains active until acknowledge, then waits for request release.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req\",\n \"accept\"\n ],\n \"outputs\": [\n \"busy\",\n \"ack\"\n ],\n \"states\": [\n \"IDLE\",\n \"WAIT\",\n \"ACK\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"busy\": 0,\n \"ack\": 0\n },\n \"WAIT\": {\n \"busy\": 1,\n \"ack\": 0\n },\n \"ACK\": {\n \"busy\": 0,\n \"ack\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"accept\",\n \"to\": \"ACK\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"!accept\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"ACK\",\n \"when\": \"req\",\n \"to\": \"ACK\"\n },\n {\n \"from\": \"ACK\",\n \"when\": \"!req\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({busy, ack})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when req\",\n \"antecedent\": \"(!busy && !ack) && (req)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && !ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to ACK when accept\",\n \"antecedent\": \"(busy && !ack) && (accept)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !accept\",\n \"antecedent\": \"(busy && !ack) && (!accept)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to ACK when req\",\n \"antecedent\": \"(!busy && ack) && (req)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"WAIT\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"WAIT\",\n \"old\": \"accept\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: handshake_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({busy, ack}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!busy && !ack));\n\n// P3_T1: IDLE transitions to WAIT when req.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!busy && !ack) && (req)) |=> (busy && !ack));\n\n// P4_T2: IDLE transitions to IDLE when !req.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!busy && !ack) && (!req)) |=> (!busy && !ack));\n\n// P5_T3: WAIT transitions to ACK when accept.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((busy && !ack) && (accept)) |=> (!busy && ack));\n\n// P6_T4: WAIT transitions to WAIT when !accept.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((busy && !ack) && (!accept)) |=> (busy && !ack));\n\n// P7_T5: ACK transitions to ACK when req.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!busy && ack) && (req)) |=> (!busy && ack));\n\n// P8_T6: ACK transitions to IDLE when !req.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!busy && ack) && (!req)) |=> (!busy && !ack));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({busy, ack})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when req\",\n \"antecedent\": \"(!busy && !ack) && (req)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && !ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to ACK when accept\",\n \"antecedent\": \"(busy && !ack) && (accept)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !accept\",\n \"antecedent\": \"(busy && !ack) && (!accept)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to ACK when req\",\n \"antecedent\": \"(!busy && ack) && (req)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module handshake_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req) ? IDLE : (IDLE);\\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module handshake_0006_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req) ? WAIT : ((!req) ? IDLE : (IDLE));\\n WAIT: next_state = (!accept) ? WAIT : (WAIT);\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module handshake_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = WAIT;\\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "handshake_0006", "category": "handshake", "description": "Request remains active until acknowledge, then waits for request release.", "rtl_variant": "factored_flags.sv", "rtl": "module handshake_0006_factored_flags (\n input wire clk,\n input wire rst,\n input wire req,\n input wire accept,\n output reg busy,\n output reg ack\n);\n localparam [1:0] F_IDLE = 2'd0;\n localparam [1:0] F_WAIT = 2'd1;\n localparam [1:0] F_ACK = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_idle_0 = (req);\n wire guard_idle_1 = (!req);\n wire guard_wait_0 = (accept);\n wire guard_wait_1 = (!accept);\n wire guard_ack_0 = (req);\n wire guard_ack_1 = (!req);\n\n always @* begin\n next_state = state;\n case (state)\n F_IDLE: begin\n if (guard_idle_0)\n next_state = F_WAIT;\n else if (guard_idle_1)\n next_state = F_IDLE;\n end\n F_WAIT: begin\n if (guard_wait_0)\n next_state = F_ACK;\n else if (guard_wait_1)\n next_state = F_WAIT;\n end\n F_ACK: begin\n if (guard_ack_0)\n next_state = F_ACK;\n else if (guard_ack_1)\n next_state = F_IDLE;\n end\n default: next_state = F_IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n busy = 1'b0;\n ack = 1'b0;\n case (state)\n F_IDLE: begin\n busy = 1'b0;\n ack = 1'b0;\n end\n F_WAIT: begin\n busy = 1'b1;\n ack = 1'b0;\n end\n F_ACK: begin\n busy = 1'b0;\n ack = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"handshake_0006\",\n \"category\": \"handshake\",\n \"template\": \"held_request_ack\",\n \"description\": \"Request remains active until acknowledge, then waits for request release.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"req\",\n \"accept\"\n ],\n \"outputs\": [\n \"busy\",\n \"ack\"\n ],\n \"states\": [\n \"IDLE\",\n \"WAIT\",\n \"ACK\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"busy\": 0,\n \"ack\": 0\n },\n \"WAIT\": {\n \"busy\": 1,\n \"ack\": 0\n },\n \"ACK\": {\n \"busy\": 0,\n \"ack\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"req\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!req\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"accept\",\n \"to\": \"ACK\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"!accept\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"ACK\",\n \"when\": \"req\",\n \"to\": \"ACK\"\n },\n {\n \"from\": \"ACK\",\n \"when\": \"!req\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({busy, ack})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when req\",\n \"antecedent\": \"(!busy && !ack) && (req)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && !ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to ACK when accept\",\n \"antecedent\": \"(busy && !ack) && (accept)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !accept\",\n \"antecedent\": \"(busy && !ack) && (!accept)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to ACK when req\",\n \"antecedent\": \"(!busy && ack) && (req)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"req\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"WAIT\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"WAIT\",\n \"old\": \"accept\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: handshake_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({busy, ack}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!busy && !ack));\n\n// P3_T1: IDLE transitions to WAIT when req.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!busy && !ack) && (req)) |=> (busy && !ack));\n\n// P4_T2: IDLE transitions to IDLE when !req.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!busy && !ack) && (!req)) |=> (!busy && !ack));\n\n// P5_T3: WAIT transitions to ACK when accept.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((busy && !ack) && (accept)) |=> (!busy && ack));\n\n// P6_T4: WAIT transitions to WAIT when !accept.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((busy && !ack) && (!accept)) |=> (busy && !ack));\n\n// P7_T5: ACK transitions to ACK when req.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!busy && ack) && (req)) |=> (!busy && ack));\n\n// P8_T6: ACK transitions to IDLE when !req.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!busy && ack) && (!req)) |=> (!busy && !ack));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({busy, ack})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when req\",\n \"antecedent\": \"(!busy && !ack) && (req)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && !ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to ACK when accept\",\n \"antecedent\": \"(busy && !ack) && (accept)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !accept\",\n \"antecedent\": \"(busy && !ack) && (!accept)\",\n \"consequent\": \"busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to ACK when req\",\n \"antecedent\": \"(!busy && ack) && (req)\",\n \"consequent\": \"!busy && ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ACK transitions to IDLE when !req\",\n \"antecedent\": \"(!busy && ack) && (!req)\",\n \"consequent\": \"!busy && !ack\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module handshake_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!req) ? IDLE : (IDLE);\\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module handshake_0006_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (req) ? WAIT : ((!req) ? IDLE : (IDLE));\\n WAIT: next_state = (!accept) ? WAIT : (WAIT);\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module handshake_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire req,\\n input wire accept,\\n output reg busy,\\n output reg ack\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] ACK = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = WAIT;\\n WAIT: next_state = (accept) ? ACK : ((!accept) ? WAIT : (WAIT));\\n ACK: next_state = (req) ? ACK : ((!req) ? IDLE : (ACK));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n busy = 1'b0;\\n ack = 1'b0;\\n case (state)\\n IDLE: begin\\n busy = 1'b0;\\n ack = 1'b0;\\n end\\n WAIT: begin\\n busy = 1'b1;\\n ack = 1'b0;\\n end\\n ACK: begin\\n busy = 1'b0;\\n ack = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "interrupt_0006", "category": "interrupt_control", "description": "Masked interrupt is latched when enabled and cleared by acknowledge.", "rtl_variant": "canonical_case.sv", "rtl": "module interrupt_0006_canonical_case (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire mask,\n input wire ack,\n output reg pending,\n output reg servicing\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] PENDING = 2'd1;\n localparam [1:0] SERVICE = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n IDLE: next_state = (irq && !mask) ? PENDING : ((!(irq && !mask)) ? IDLE : (IDLE));\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\n SERVICE: next_state = IDLE;\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n pending = 1'b0;\n servicing = 1'b0;\n case (state)\n IDLE: begin\n pending = 1'b0;\n servicing = 1'b0;\n end\n PENDING: begin\n pending = 1'b1;\n servicing = 1'b0;\n end\n SERVICE: begin\n pending = 1'b0;\n servicing = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"interrupt_0006\",\n \"category\": \"interrupt_control\",\n \"template\": \"masked_latched_irq\",\n \"description\": \"Masked interrupt is latched when enabled and cleared by acknowledge.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"irq\",\n \"mask\",\n \"ack\"\n ],\n \"outputs\": [\n \"pending\",\n \"servicing\"\n ],\n \"states\": [\n \"IDLE\",\n \"PENDING\",\n \"SERVICE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"pending\": 0,\n \"servicing\": 0\n },\n \"PENDING\": {\n \"pending\": 1,\n \"servicing\": 0\n },\n \"SERVICE\": {\n \"pending\": 0,\n \"servicing\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"irq && !mask\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!(irq && !mask)\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"ack\",\n \"to\": \"SERVICE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"!ack\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"SERVICE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({pending, servicing})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to PENDING when irq && !mask\",\n \"antecedent\": \"(!pending && !servicing) && (irq && !mask)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !(irq && !mask)\",\n \"antecedent\": \"(!pending && !servicing) && (!(irq && !mask))\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to SERVICE when ack\",\n \"antecedent\": \"(pending && !servicing) && (ack)\",\n \"consequent\": \"!pending && servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to PENDING when !ack\",\n \"antecedent\": \"(pending && !servicing) && (!ack)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"SERVICE transitions to IDLE when true\",\n \"antecedent\": \"!pending && servicing\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"irq && !mask\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"PENDING\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PENDING\",\n \"old\": \"ack\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: interrupt_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({pending, servicing}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!pending && !servicing));\n\n// P3_T1: IDLE transitions to PENDING when irq && !mask.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!pending && !servicing) && (irq && !mask)) |=> (pending && !servicing));\n\n// P4_T2: IDLE transitions to IDLE when !(irq && !mask).\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!pending && !servicing) && (!(irq && !mask))) |=> (!pending && !servicing));\n\n// P5_T3: PENDING transitions to SERVICE when ack.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((pending && !servicing) && (ack)) |=> (!pending && servicing));\n\n// P6_T4: PENDING transitions to PENDING when !ack.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((pending && !servicing) && (!ack)) |=> (pending && !servicing));\n\n// P7_T5: SERVICE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!pending && servicing) |=> (!pending && !servicing));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({pending, servicing})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to PENDING when irq && !mask\",\n \"antecedent\": \"(!pending && !servicing) && (irq && !mask)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !(irq && !mask)\",\n \"antecedent\": \"(!pending && !servicing) && (!(irq && !mask))\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to SERVICE when ack\",\n \"antecedent\": \"(pending && !servicing) && (ack)\",\n \"consequent\": \"!pending && servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to PENDING when !ack\",\n \"antecedent\": \"(pending && !servicing) && (!ack)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"SERVICE transitions to IDLE when true\",\n \"antecedent\": \"!pending && servicing\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module interrupt_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!(irq && !mask)) ? IDLE : (IDLE);\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module interrupt_0006_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (irq && !mask) ? PENDING : ((!(irq && !mask)) ? IDLE : (IDLE));\\n PENDING: next_state = (!ack) ? PENDING : (PENDING);\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module interrupt_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = PENDING;\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "interrupt_0006", "category": "interrupt_control", "description": "Masked interrupt is latched when enabled and cleared by acknowledge.", "rtl_variant": "onehot_case.sv", "rtl": "module interrupt_0006_onehot_case (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire mask,\n input wire ack,\n output reg pending,\n output reg servicing\n);\n localparam [2:0] IDLE = 3'b001;\n localparam [2:0] PENDING = 3'b010;\n localparam [2:0] SERVICE = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = IDLE;\n case (state)\n IDLE: next_state = (irq && !mask) ? PENDING : ((!(irq && !mask)) ? IDLE : (IDLE));\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\n SERVICE: next_state = IDLE;\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n pending = (state == PENDING);\n servicing = (state == SERVICE);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"interrupt_0006\",\n \"category\": \"interrupt_control\",\n \"template\": \"masked_latched_irq\",\n \"description\": \"Masked interrupt is latched when enabled and cleared by acknowledge.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"irq\",\n \"mask\",\n \"ack\"\n ],\n \"outputs\": [\n \"pending\",\n \"servicing\"\n ],\n \"states\": [\n \"IDLE\",\n \"PENDING\",\n \"SERVICE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"pending\": 0,\n \"servicing\": 0\n },\n \"PENDING\": {\n \"pending\": 1,\n \"servicing\": 0\n },\n \"SERVICE\": {\n \"pending\": 0,\n \"servicing\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"irq && !mask\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!(irq && !mask)\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"ack\",\n \"to\": \"SERVICE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"!ack\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"SERVICE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({pending, servicing})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to PENDING when irq && !mask\",\n \"antecedent\": \"(!pending && !servicing) && (irq && !mask)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !(irq && !mask)\",\n \"antecedent\": \"(!pending && !servicing) && (!(irq && !mask))\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to SERVICE when ack\",\n \"antecedent\": \"(pending && !servicing) && (ack)\",\n \"consequent\": \"!pending && servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to PENDING when !ack\",\n \"antecedent\": \"(pending && !servicing) && (!ack)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"SERVICE transitions to IDLE when true\",\n \"antecedent\": \"!pending && servicing\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"irq && !mask\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"PENDING\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PENDING\",\n \"old\": \"ack\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: interrupt_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({pending, servicing}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!pending && !servicing));\n\n// P3_T1: IDLE transitions to PENDING when irq && !mask.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!pending && !servicing) && (irq && !mask)) |=> (pending && !servicing));\n\n// P4_T2: IDLE transitions to IDLE when !(irq && !mask).\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!pending && !servicing) && (!(irq && !mask))) |=> (!pending && !servicing));\n\n// P5_T3: PENDING transitions to SERVICE when ack.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((pending && !servicing) && (ack)) |=> (!pending && servicing));\n\n// P6_T4: PENDING transitions to PENDING when !ack.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((pending && !servicing) && (!ack)) |=> (pending && !servicing));\n\n// P7_T5: SERVICE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!pending && servicing) |=> (!pending && !servicing));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({pending, servicing})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to PENDING when irq && !mask\",\n \"antecedent\": \"(!pending && !servicing) && (irq && !mask)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !(irq && !mask)\",\n \"antecedent\": \"(!pending && !servicing) && (!(irq && !mask))\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to SERVICE when ack\",\n \"antecedent\": \"(pending && !servicing) && (ack)\",\n \"consequent\": \"!pending && servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to PENDING when !ack\",\n \"antecedent\": \"(pending && !servicing) && (!ack)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"SERVICE transitions to IDLE when true\",\n \"antecedent\": \"!pending && servicing\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module interrupt_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!(irq && !mask)) ? IDLE : (IDLE);\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module interrupt_0006_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (irq && !mask) ? PENDING : ((!(irq && !mask)) ? IDLE : (IDLE));\\n PENDING: next_state = (!ack) ? PENDING : (PENDING);\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module interrupt_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = PENDING;\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "interrupt_0006", "category": "interrupt_control", "description": "Masked interrupt is latched when enabled and cleared by acknowledge.", "rtl_variant": "nested_if.sv", "rtl": "module interrupt_0006_nested_if (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire mask,\n input wire ack,\n output wire pending,\n output wire servicing\n);\n localparam [1:0] S_IDLE = 2'd0;\n localparam [1:0] S_PENDING = 2'd1;\n localparam [1:0] S_SERVICE = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_IDLE;\n end else begin\n if (state == S_IDLE) begin\n state <= (irq && !mask) ? S_PENDING : ((!(irq && !mask)) ? S_IDLE : (S_IDLE));\n end\n else if (state == S_PENDING) begin\n state <= (ack) ? S_SERVICE : ((!ack) ? S_PENDING : (S_PENDING));\n end\n else if (state == S_SERVICE) begin\n state <= S_IDLE;\n end\n else begin\n state <= S_IDLE;\n end\n end\n end\n\n assign pending = (state == S_PENDING);\n assign servicing = (state == S_SERVICE);\nendmodule\n", "spec_json": "{\n \"design_id\": \"interrupt_0006\",\n \"category\": \"interrupt_control\",\n \"template\": \"masked_latched_irq\",\n \"description\": \"Masked interrupt is latched when enabled and cleared by acknowledge.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"irq\",\n \"mask\",\n \"ack\"\n ],\n \"outputs\": [\n \"pending\",\n \"servicing\"\n ],\n \"states\": [\n \"IDLE\",\n \"PENDING\",\n \"SERVICE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"pending\": 0,\n \"servicing\": 0\n },\n \"PENDING\": {\n \"pending\": 1,\n \"servicing\": 0\n },\n \"SERVICE\": {\n \"pending\": 0,\n \"servicing\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"irq && !mask\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!(irq && !mask)\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"ack\",\n \"to\": \"SERVICE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"!ack\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"SERVICE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({pending, servicing})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to PENDING when irq && !mask\",\n \"antecedent\": \"(!pending && !servicing) && (irq && !mask)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !(irq && !mask)\",\n \"antecedent\": \"(!pending && !servicing) && (!(irq && !mask))\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to SERVICE when ack\",\n \"antecedent\": \"(pending && !servicing) && (ack)\",\n \"consequent\": \"!pending && servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to PENDING when !ack\",\n \"antecedent\": \"(pending && !servicing) && (!ack)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"SERVICE transitions to IDLE when true\",\n \"antecedent\": \"!pending && servicing\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"irq && !mask\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"PENDING\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PENDING\",\n \"old\": \"ack\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: interrupt_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({pending, servicing}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!pending && !servicing));\n\n// P3_T1: IDLE transitions to PENDING when irq && !mask.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!pending && !servicing) && (irq && !mask)) |=> (pending && !servicing));\n\n// P4_T2: IDLE transitions to IDLE when !(irq && !mask).\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!pending && !servicing) && (!(irq && !mask))) |=> (!pending && !servicing));\n\n// P5_T3: PENDING transitions to SERVICE when ack.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((pending && !servicing) && (ack)) |=> (!pending && servicing));\n\n// P6_T4: PENDING transitions to PENDING when !ack.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((pending && !servicing) && (!ack)) |=> (pending && !servicing));\n\n// P7_T5: SERVICE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!pending && servicing) |=> (!pending && !servicing));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({pending, servicing})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to PENDING when irq && !mask\",\n \"antecedent\": \"(!pending && !servicing) && (irq && !mask)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !(irq && !mask)\",\n \"antecedent\": \"(!pending && !servicing) && (!(irq && !mask))\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to SERVICE when ack\",\n \"antecedent\": \"(pending && !servicing) && (ack)\",\n \"consequent\": \"!pending && servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to PENDING when !ack\",\n \"antecedent\": \"(pending && !servicing) && (!ack)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"SERVICE transitions to IDLE when true\",\n \"antecedent\": \"!pending && servicing\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module interrupt_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!(irq && !mask)) ? IDLE : (IDLE);\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module interrupt_0006_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (irq && !mask) ? PENDING : ((!(irq && !mask)) ? IDLE : (IDLE));\\n PENDING: next_state = (!ack) ? PENDING : (PENDING);\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module interrupt_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = PENDING;\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "interrupt_0006", "category": "interrupt_control", "description": "Masked interrupt is latched when enabled and cleared by acknowledge.", "rtl_variant": "factored_flags.sv", "rtl": "module interrupt_0006_factored_flags (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire mask,\n input wire ack,\n output reg pending,\n output reg servicing\n);\n localparam [1:0] F_IDLE = 2'd0;\n localparam [1:0] F_PENDING = 2'd1;\n localparam [1:0] F_SERVICE = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_idle_0 = (irq && !mask);\n wire guard_idle_1 = (!(irq && !mask));\n wire guard_pending_0 = (ack);\n wire guard_pending_1 = (!ack);\n\n always @* begin\n next_state = state;\n case (state)\n F_IDLE: begin\n if (guard_idle_0)\n next_state = F_PENDING;\n else if (guard_idle_1)\n next_state = F_IDLE;\n end\n F_PENDING: begin\n if (guard_pending_0)\n next_state = F_SERVICE;\n else if (guard_pending_1)\n next_state = F_PENDING;\n end\n F_SERVICE: begin\n next_state = F_IDLE;\n end\n default: next_state = F_IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n pending = 1'b0;\n servicing = 1'b0;\n case (state)\n F_IDLE: begin\n pending = 1'b0;\n servicing = 1'b0;\n end\n F_PENDING: begin\n pending = 1'b1;\n servicing = 1'b0;\n end\n F_SERVICE: begin\n pending = 1'b0;\n servicing = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"interrupt_0006\",\n \"category\": \"interrupt_control\",\n \"template\": \"masked_latched_irq\",\n \"description\": \"Masked interrupt is latched when enabled and cleared by acknowledge.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"irq\",\n \"mask\",\n \"ack\"\n ],\n \"outputs\": [\n \"pending\",\n \"servicing\"\n ],\n \"states\": [\n \"IDLE\",\n \"PENDING\",\n \"SERVICE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"pending\": 0,\n \"servicing\": 0\n },\n \"PENDING\": {\n \"pending\": 1,\n \"servicing\": 0\n },\n \"SERVICE\": {\n \"pending\": 0,\n \"servicing\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"irq && !mask\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!(irq && !mask)\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"ack\",\n \"to\": \"SERVICE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"!ack\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"SERVICE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({pending, servicing})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to PENDING when irq && !mask\",\n \"antecedent\": \"(!pending && !servicing) && (irq && !mask)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !(irq && !mask)\",\n \"antecedent\": \"(!pending && !servicing) && (!(irq && !mask))\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to SERVICE when ack\",\n \"antecedent\": \"(pending && !servicing) && (ack)\",\n \"consequent\": \"!pending && servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to PENDING when !ack\",\n \"antecedent\": \"(pending && !servicing) && (!ack)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"SERVICE transitions to IDLE when true\",\n \"antecedent\": \"!pending && servicing\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"irq && !mask\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"PENDING\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PENDING\",\n \"old\": \"ack\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: interrupt_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({pending, servicing}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!pending && !servicing));\n\n// P3_T1: IDLE transitions to PENDING when irq && !mask.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!pending && !servicing) && (irq && !mask)) |=> (pending && !servicing));\n\n// P4_T2: IDLE transitions to IDLE when !(irq && !mask).\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!pending && !servicing) && (!(irq && !mask))) |=> (!pending && !servicing));\n\n// P5_T3: PENDING transitions to SERVICE when ack.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((pending && !servicing) && (ack)) |=> (!pending && servicing));\n\n// P6_T4: PENDING transitions to PENDING when !ack.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((pending && !servicing) && (!ack)) |=> (pending && !servicing));\n\n// P7_T5: SERVICE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!pending && servicing) |=> (!pending && !servicing));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({pending, servicing})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to PENDING when irq && !mask\",\n \"antecedent\": \"(!pending && !servicing) && (irq && !mask)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !(irq && !mask)\",\n \"antecedent\": \"(!pending && !servicing) && (!(irq && !mask))\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to SERVICE when ack\",\n \"antecedent\": \"(pending && !servicing) && (ack)\",\n \"consequent\": \"!pending && servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PENDING transitions to PENDING when !ack\",\n \"antecedent\": \"(pending && !servicing) && (!ack)\",\n \"consequent\": \"pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"SERVICE transitions to IDLE when true\",\n \"antecedent\": \"!pending && servicing\",\n \"consequent\": \"!pending && !servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module interrupt_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!(irq && !mask)) ? IDLE : (IDLE);\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module interrupt_0006_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (irq && !mask) ? PENDING : ((!(irq && !mask)) ? IDLE : (IDLE));\\n PENDING: next_state = (!ack) ? PENDING : (PENDING);\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module interrupt_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire mask,\\n input wire ack,\\n output reg pending,\\n output reg servicing\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = PENDING;\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n case (state)\\n IDLE: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "interrupt_0009", "category": "interrupt_control", "description": "Interrupt service waits for irq to deassert before rearming.", "rtl_variant": "canonical_case.sv", "rtl": "module interrupt_0009_canonical_case (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire ack,\n output reg pending,\n output reg servicing,\n output reg wait_low,\n output reg armed\n);\n localparam [1:0] ARMED = 2'd0;\n localparam [1:0] PENDING = 2'd1;\n localparam [1:0] SERVICE = 2'd2;\n localparam [1:0] WAIT_LOW = 2'd3;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\n SERVICE: next_state = WAIT_LOW;\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\n default: next_state = ARMED;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= ARMED;\n else\n state <= next_state;\n end\n\n always @* begin\n pending = 1'b0;\n servicing = 1'b0;\n wait_low = 1'b0;\n armed = 1'b0;\n case (state)\n ARMED: begin\n pending = 1'b0;\n servicing = 1'b0;\n wait_low = 1'b0;\n armed = 1'b1;\n end\n PENDING: begin\n pending = 1'b1;\n servicing = 1'b0;\n wait_low = 1'b0;\n armed = 1'b0;\n end\n SERVICE: begin\n pending = 1'b0;\n servicing = 1'b1;\n wait_low = 1'b0;\n armed = 1'b0;\n end\n WAIT_LOW: begin\n pending = 1'b0;\n servicing = 1'b0;\n wait_low = 1'b1;\n armed = 1'b0;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"interrupt_0009\",\n \"category\": \"interrupt_control\",\n \"template\": \"service_then_rearm_low\",\n \"description\": \"Interrupt service waits for irq to deassert before rearming.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"ARMED\"\n },\n \"inputs\": [\n \"irq\",\n \"ack\"\n ],\n \"outputs\": [\n \"pending\",\n \"servicing\",\n \"wait_low\",\n \"armed\"\n ],\n \"states\": [\n \"ARMED\",\n \"PENDING\",\n \"SERVICE\",\n \"WAIT_LOW\"\n ],\n \"state_outputs\": {\n \"ARMED\": {\n \"pending\": 0,\n \"servicing\": 0,\n \"wait_low\": 0,\n \"armed\": 1\n },\n \"PENDING\": {\n \"pending\": 1,\n \"servicing\": 0,\n \"wait_low\": 0,\n \"armed\": 0\n },\n \"SERVICE\": {\n \"pending\": 0,\n \"servicing\": 1,\n \"wait_low\": 0,\n \"armed\": 0\n },\n \"WAIT_LOW\": {\n \"pending\": 0,\n \"servicing\": 0,\n \"wait_low\": 1,\n \"armed\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"ARMED\",\n \"when\": \"irq\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"!irq\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"ack\",\n \"to\": \"SERVICE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"!ack\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"SERVICE\",\n \"when\": \"true\",\n \"to\": \"WAIT_LOW\"\n },\n {\n \"from\": \"WAIT_LOW\",\n \"when\": \"irq\",\n \"to\": \"WAIT_LOW\"\n },\n {\n \"from\": \"WAIT_LOW\",\n \"when\": \"!irq\",\n \"to\": \"ARMED\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"interrupt phases are mutually exclusive\",\n \"expression\": \"$onehot({pending, servicing, wait_low, armed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset arms interrupt capture\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_IRQ\",\n \"sva_name\": \"p_irq\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq while armed becomes pending\",\n \"antecedent\": \"armed && irq\",\n \"consequent\": \"pending\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ACK\",\n \"sva_name\": \"p_ack\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"acknowledge services a pending interrupt\",\n \"antecedent\": \"pending && ack\",\n \"consequent\": \"servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_WAIT_LOW\",\n \"sva_name\": \"p_wait_low\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"service completion waits for irq deassertion\",\n \"antecedent\": \"servicing\",\n \"consequent\": \"wait_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REARM\",\n \"sva_name\": \"p_rearm\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq deassertion rearms capture\",\n \"antecedent\": \"wait_low && !irq\",\n \"consequent\": \"armed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_irq\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"irq\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_ack\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PENDING\",\n \"old\": \"ack\",\n \"new\": \"false\"\n },\n {\n \"name\": \"premature_rearm\",\n \"kind\": \"force_transition\",\n \"from\": \"SERVICE\",\n \"to\": \"ARMED\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: interrupt_0009\n\n// P1_ONEHOT: interrupt phases are mutually exclusive.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({pending, servicing, wait_low, armed}));\n\n// P2_RESET: reset arms interrupt capture.\np_reset: assert property (@(posedge clk)\n (rst) |=> (armed));\n\n// P3_IRQ: irq while armed becomes pending.\np_irq: assert property (@(posedge clk) disable iff (rst)\n (armed && irq) |=> (pending));\n\n// P4_ACK: acknowledge services a pending interrupt.\np_ack: assert property (@(posedge clk) disable iff (rst)\n (pending && ack) |=> (servicing));\n\n// P5_WAIT_LOW: service completion waits for irq deassertion.\np_wait_low: assert property (@(posedge clk) disable iff (rst)\n (servicing) |=> (wait_low));\n\n// P6_REARM: irq deassertion rearms capture.\np_rearm: assert property (@(posedge clk) disable iff (rst)\n (wait_low && !irq) |=> (armed));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"interrupt phases are mutually exclusive\",\n \"expression\": \"$onehot({pending, servicing, wait_low, armed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset arms interrupt capture\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_IRQ\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq while armed becomes pending\",\n \"antecedent\": \"armed && irq\",\n \"consequent\": \"pending\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ACK\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"acknowledge services a pending interrupt\",\n \"antecedent\": \"pending && ack\",\n \"consequent\": \"servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_WAIT_LOW\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"service completion waits for irq deassertion\",\n \"antecedent\": \"servicing\",\n \"consequent\": \"wait_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REARM\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq deassertion rearms capture\",\n \"antecedent\": \"wait_low && !irq\",\n \"consequent\": \"armed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_ack.sv\": \"module interrupt_0009_mutant_ignore_ack (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\\n PENDING: next_state = (!ack) ? PENDING : (PENDING);\\n SERVICE: next_state = WAIT_LOW;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_irq.sv\": \"module interrupt_0009_mutant_ignore_irq (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (!irq) ? ARMED : (ARMED);\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = WAIT_LOW;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"premature_rearm.sv\": \"module interrupt_0009_mutant_premature_rearm (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = ARMED;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "interrupt_0009", "category": "interrupt_control", "description": "Interrupt service waits for irq to deassert before rearming.", "rtl_variant": "onehot_case.sv", "rtl": "module interrupt_0009_onehot_case (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire ack,\n output reg pending,\n output reg servicing,\n output reg wait_low,\n output reg armed\n);\n localparam [3:0] ARMED = 4'b0001;\n localparam [3:0] PENDING = 4'b0010;\n localparam [3:0] SERVICE = 4'b0100;\n localparam [3:0] WAIT_LOW = 4'b1000;\n\n reg [3:0] state, next_state;\n\n always @* begin\n next_state = ARMED;\n case (state)\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\n SERVICE: next_state = WAIT_LOW;\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\n default: next_state = ARMED;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= ARMED;\n else\n state <= next_state;\n end\n\n always @* begin\n pending = (state == PENDING);\n servicing = (state == SERVICE);\n wait_low = (state == WAIT_LOW);\n armed = (state == ARMED);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"interrupt_0009\",\n \"category\": \"interrupt_control\",\n \"template\": \"service_then_rearm_low\",\n \"description\": \"Interrupt service waits for irq to deassert before rearming.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"ARMED\"\n },\n \"inputs\": [\n \"irq\",\n \"ack\"\n ],\n \"outputs\": [\n \"pending\",\n \"servicing\",\n \"wait_low\",\n \"armed\"\n ],\n \"states\": [\n \"ARMED\",\n \"PENDING\",\n \"SERVICE\",\n \"WAIT_LOW\"\n ],\n \"state_outputs\": {\n \"ARMED\": {\n \"pending\": 0,\n \"servicing\": 0,\n \"wait_low\": 0,\n \"armed\": 1\n },\n \"PENDING\": {\n \"pending\": 1,\n \"servicing\": 0,\n \"wait_low\": 0,\n \"armed\": 0\n },\n \"SERVICE\": {\n \"pending\": 0,\n \"servicing\": 1,\n \"wait_low\": 0,\n \"armed\": 0\n },\n \"WAIT_LOW\": {\n \"pending\": 0,\n \"servicing\": 0,\n \"wait_low\": 1,\n \"armed\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"ARMED\",\n \"when\": \"irq\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"!irq\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"ack\",\n \"to\": \"SERVICE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"!ack\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"SERVICE\",\n \"when\": \"true\",\n \"to\": \"WAIT_LOW\"\n },\n {\n \"from\": \"WAIT_LOW\",\n \"when\": \"irq\",\n \"to\": \"WAIT_LOW\"\n },\n {\n \"from\": \"WAIT_LOW\",\n \"when\": \"!irq\",\n \"to\": \"ARMED\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"interrupt phases are mutually exclusive\",\n \"expression\": \"$onehot({pending, servicing, wait_low, armed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset arms interrupt capture\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_IRQ\",\n \"sva_name\": \"p_irq\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq while armed becomes pending\",\n \"antecedent\": \"armed && irq\",\n \"consequent\": \"pending\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ACK\",\n \"sva_name\": \"p_ack\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"acknowledge services a pending interrupt\",\n \"antecedent\": \"pending && ack\",\n \"consequent\": \"servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_WAIT_LOW\",\n \"sva_name\": \"p_wait_low\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"service completion waits for irq deassertion\",\n \"antecedent\": \"servicing\",\n \"consequent\": \"wait_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REARM\",\n \"sva_name\": \"p_rearm\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq deassertion rearms capture\",\n \"antecedent\": \"wait_low && !irq\",\n \"consequent\": \"armed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_irq\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"irq\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_ack\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PENDING\",\n \"old\": \"ack\",\n \"new\": \"false\"\n },\n {\n \"name\": \"premature_rearm\",\n \"kind\": \"force_transition\",\n \"from\": \"SERVICE\",\n \"to\": \"ARMED\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: interrupt_0009\n\n// P1_ONEHOT: interrupt phases are mutually exclusive.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({pending, servicing, wait_low, armed}));\n\n// P2_RESET: reset arms interrupt capture.\np_reset: assert property (@(posedge clk)\n (rst) |=> (armed));\n\n// P3_IRQ: irq while armed becomes pending.\np_irq: assert property (@(posedge clk) disable iff (rst)\n (armed && irq) |=> (pending));\n\n// P4_ACK: acknowledge services a pending interrupt.\np_ack: assert property (@(posedge clk) disable iff (rst)\n (pending && ack) |=> (servicing));\n\n// P5_WAIT_LOW: service completion waits for irq deassertion.\np_wait_low: assert property (@(posedge clk) disable iff (rst)\n (servicing) |=> (wait_low));\n\n// P6_REARM: irq deassertion rearms capture.\np_rearm: assert property (@(posedge clk) disable iff (rst)\n (wait_low && !irq) |=> (armed));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"interrupt phases are mutually exclusive\",\n \"expression\": \"$onehot({pending, servicing, wait_low, armed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset arms interrupt capture\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_IRQ\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq while armed becomes pending\",\n \"antecedent\": \"armed && irq\",\n \"consequent\": \"pending\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ACK\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"acknowledge services a pending interrupt\",\n \"antecedent\": \"pending && ack\",\n \"consequent\": \"servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_WAIT_LOW\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"service completion waits for irq deassertion\",\n \"antecedent\": \"servicing\",\n \"consequent\": \"wait_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REARM\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq deassertion rearms capture\",\n \"antecedent\": \"wait_low && !irq\",\n \"consequent\": \"armed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_ack.sv\": \"module interrupt_0009_mutant_ignore_ack (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\\n PENDING: next_state = (!ack) ? PENDING : (PENDING);\\n SERVICE: next_state = WAIT_LOW;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_irq.sv\": \"module interrupt_0009_mutant_ignore_irq (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (!irq) ? ARMED : (ARMED);\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = WAIT_LOW;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"premature_rearm.sv\": \"module interrupt_0009_mutant_premature_rearm (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = ARMED;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "interrupt_0009", "category": "interrupt_control", "description": "Interrupt service waits for irq to deassert before rearming.", "rtl_variant": "nested_if.sv", "rtl": "module interrupt_0009_nested_if (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire ack,\n output wire pending,\n output wire servicing,\n output wire wait_low,\n output wire armed\n);\n localparam [1:0] S_ARMED = 2'd0;\n localparam [1:0] S_PENDING = 2'd1;\n localparam [1:0] S_SERVICE = 2'd2;\n localparam [1:0] S_WAIT_LOW = 2'd3;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_ARMED;\n end else begin\n if (state == S_ARMED) begin\n state <= (irq) ? S_PENDING : ((!irq) ? S_ARMED : (S_ARMED));\n end\n else if (state == S_PENDING) begin\n state <= (ack) ? S_SERVICE : ((!ack) ? S_PENDING : (S_PENDING));\n end\n else if (state == S_SERVICE) begin\n state <= S_WAIT_LOW;\n end\n else if (state == S_WAIT_LOW) begin\n state <= (irq) ? S_WAIT_LOW : ((!irq) ? S_ARMED : (S_WAIT_LOW));\n end\n else begin\n state <= S_ARMED;\n end\n end\n end\n\n assign pending = (state == S_PENDING);\n assign servicing = (state == S_SERVICE);\n assign wait_low = (state == S_WAIT_LOW);\n assign armed = (state == S_ARMED);\nendmodule\n", "spec_json": "{\n \"design_id\": \"interrupt_0009\",\n \"category\": \"interrupt_control\",\n \"template\": \"service_then_rearm_low\",\n \"description\": \"Interrupt service waits for irq to deassert before rearming.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"ARMED\"\n },\n \"inputs\": [\n \"irq\",\n \"ack\"\n ],\n \"outputs\": [\n \"pending\",\n \"servicing\",\n \"wait_low\",\n \"armed\"\n ],\n \"states\": [\n \"ARMED\",\n \"PENDING\",\n \"SERVICE\",\n \"WAIT_LOW\"\n ],\n \"state_outputs\": {\n \"ARMED\": {\n \"pending\": 0,\n \"servicing\": 0,\n \"wait_low\": 0,\n \"armed\": 1\n },\n \"PENDING\": {\n \"pending\": 1,\n \"servicing\": 0,\n \"wait_low\": 0,\n \"armed\": 0\n },\n \"SERVICE\": {\n \"pending\": 0,\n \"servicing\": 1,\n \"wait_low\": 0,\n \"armed\": 0\n },\n \"WAIT_LOW\": {\n \"pending\": 0,\n \"servicing\": 0,\n \"wait_low\": 1,\n \"armed\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"ARMED\",\n \"when\": \"irq\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"!irq\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"ack\",\n \"to\": \"SERVICE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"!ack\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"SERVICE\",\n \"when\": \"true\",\n \"to\": \"WAIT_LOW\"\n },\n {\n \"from\": \"WAIT_LOW\",\n \"when\": \"irq\",\n \"to\": \"WAIT_LOW\"\n },\n {\n \"from\": \"WAIT_LOW\",\n \"when\": \"!irq\",\n \"to\": \"ARMED\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"interrupt phases are mutually exclusive\",\n \"expression\": \"$onehot({pending, servicing, wait_low, armed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset arms interrupt capture\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_IRQ\",\n \"sva_name\": \"p_irq\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq while armed becomes pending\",\n \"antecedent\": \"armed && irq\",\n \"consequent\": \"pending\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ACK\",\n \"sva_name\": \"p_ack\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"acknowledge services a pending interrupt\",\n \"antecedent\": \"pending && ack\",\n \"consequent\": \"servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_WAIT_LOW\",\n \"sva_name\": \"p_wait_low\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"service completion waits for irq deassertion\",\n \"antecedent\": \"servicing\",\n \"consequent\": \"wait_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REARM\",\n \"sva_name\": \"p_rearm\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq deassertion rearms capture\",\n \"antecedent\": \"wait_low && !irq\",\n \"consequent\": \"armed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_irq\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"irq\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_ack\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PENDING\",\n \"old\": \"ack\",\n \"new\": \"false\"\n },\n {\n \"name\": \"premature_rearm\",\n \"kind\": \"force_transition\",\n \"from\": \"SERVICE\",\n \"to\": \"ARMED\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: interrupt_0009\n\n// P1_ONEHOT: interrupt phases are mutually exclusive.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({pending, servicing, wait_low, armed}));\n\n// P2_RESET: reset arms interrupt capture.\np_reset: assert property (@(posedge clk)\n (rst) |=> (armed));\n\n// P3_IRQ: irq while armed becomes pending.\np_irq: assert property (@(posedge clk) disable iff (rst)\n (armed && irq) |=> (pending));\n\n// P4_ACK: acknowledge services a pending interrupt.\np_ack: assert property (@(posedge clk) disable iff (rst)\n (pending && ack) |=> (servicing));\n\n// P5_WAIT_LOW: service completion waits for irq deassertion.\np_wait_low: assert property (@(posedge clk) disable iff (rst)\n (servicing) |=> (wait_low));\n\n// P6_REARM: irq deassertion rearms capture.\np_rearm: assert property (@(posedge clk) disable iff (rst)\n (wait_low && !irq) |=> (armed));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"interrupt phases are mutually exclusive\",\n \"expression\": \"$onehot({pending, servicing, wait_low, armed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset arms interrupt capture\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_IRQ\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq while armed becomes pending\",\n \"antecedent\": \"armed && irq\",\n \"consequent\": \"pending\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ACK\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"acknowledge services a pending interrupt\",\n \"antecedent\": \"pending && ack\",\n \"consequent\": \"servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_WAIT_LOW\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"service completion waits for irq deassertion\",\n \"antecedent\": \"servicing\",\n \"consequent\": \"wait_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REARM\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq deassertion rearms capture\",\n \"antecedent\": \"wait_low && !irq\",\n \"consequent\": \"armed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_ack.sv\": \"module interrupt_0009_mutant_ignore_ack (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\\n PENDING: next_state = (!ack) ? PENDING : (PENDING);\\n SERVICE: next_state = WAIT_LOW;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_irq.sv\": \"module interrupt_0009_mutant_ignore_irq (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (!irq) ? ARMED : (ARMED);\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = WAIT_LOW;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"premature_rearm.sv\": \"module interrupt_0009_mutant_premature_rearm (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = ARMED;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "interrupt_0009", "category": "interrupt_control", "description": "Interrupt service waits for irq to deassert before rearming.", "rtl_variant": "factored_flags.sv", "rtl": "module interrupt_0009_factored_flags (\n input wire clk,\n input wire rst,\n input wire irq,\n input wire ack,\n output reg pending,\n output reg servicing,\n output reg wait_low,\n output reg armed\n);\n localparam [1:0] F_ARMED = 2'd0;\n localparam [1:0] F_PENDING = 2'd1;\n localparam [1:0] F_SERVICE = 2'd2;\n localparam [1:0] F_WAIT_LOW = 2'd3;\n\n reg [1:0] state, next_state;\n\n wire guard_armed_0 = (irq);\n wire guard_armed_1 = (!irq);\n wire guard_pending_0 = (ack);\n wire guard_pending_1 = (!ack);\n wire guard_wait_low_0 = (irq);\n wire guard_wait_low_1 = (!irq);\n\n always @* begin\n next_state = state;\n case (state)\n F_ARMED: begin\n if (guard_armed_0)\n next_state = F_PENDING;\n else if (guard_armed_1)\n next_state = F_ARMED;\n end\n F_PENDING: begin\n if (guard_pending_0)\n next_state = F_SERVICE;\n else if (guard_pending_1)\n next_state = F_PENDING;\n end\n F_SERVICE: begin\n next_state = F_WAIT_LOW;\n end\n F_WAIT_LOW: begin\n if (guard_wait_low_0)\n next_state = F_WAIT_LOW;\n else if (guard_wait_low_1)\n next_state = F_ARMED;\n end\n default: next_state = F_ARMED;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_ARMED;\n else\n state <= next_state;\n end\n\n always @* begin\n pending = 1'b0;\n servicing = 1'b0;\n wait_low = 1'b0;\n armed = 1'b0;\n case (state)\n F_ARMED: begin\n pending = 1'b0;\n servicing = 1'b0;\n wait_low = 1'b0;\n armed = 1'b1;\n end\n F_PENDING: begin\n pending = 1'b1;\n servicing = 1'b0;\n wait_low = 1'b0;\n armed = 1'b0;\n end\n F_SERVICE: begin\n pending = 1'b0;\n servicing = 1'b1;\n wait_low = 1'b0;\n armed = 1'b0;\n end\n F_WAIT_LOW: begin\n pending = 1'b0;\n servicing = 1'b0;\n wait_low = 1'b1;\n armed = 1'b0;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"interrupt_0009\",\n \"category\": \"interrupt_control\",\n \"template\": \"service_then_rearm_low\",\n \"description\": \"Interrupt service waits for irq to deassert before rearming.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"ARMED\"\n },\n \"inputs\": [\n \"irq\",\n \"ack\"\n ],\n \"outputs\": [\n \"pending\",\n \"servicing\",\n \"wait_low\",\n \"armed\"\n ],\n \"states\": [\n \"ARMED\",\n \"PENDING\",\n \"SERVICE\",\n \"WAIT_LOW\"\n ],\n \"state_outputs\": {\n \"ARMED\": {\n \"pending\": 0,\n \"servicing\": 0,\n \"wait_low\": 0,\n \"armed\": 1\n },\n \"PENDING\": {\n \"pending\": 1,\n \"servicing\": 0,\n \"wait_low\": 0,\n \"armed\": 0\n },\n \"SERVICE\": {\n \"pending\": 0,\n \"servicing\": 1,\n \"wait_low\": 0,\n \"armed\": 0\n },\n \"WAIT_LOW\": {\n \"pending\": 0,\n \"servicing\": 0,\n \"wait_low\": 1,\n \"armed\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"ARMED\",\n \"when\": \"irq\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"!irq\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"ack\",\n \"to\": \"SERVICE\"\n },\n {\n \"from\": \"PENDING\",\n \"when\": \"!ack\",\n \"to\": \"PENDING\"\n },\n {\n \"from\": \"SERVICE\",\n \"when\": \"true\",\n \"to\": \"WAIT_LOW\"\n },\n {\n \"from\": \"WAIT_LOW\",\n \"when\": \"irq\",\n \"to\": \"WAIT_LOW\"\n },\n {\n \"from\": \"WAIT_LOW\",\n \"when\": \"!irq\",\n \"to\": \"ARMED\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"interrupt phases are mutually exclusive\",\n \"expression\": \"$onehot({pending, servicing, wait_low, armed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset arms interrupt capture\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_IRQ\",\n \"sva_name\": \"p_irq\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq while armed becomes pending\",\n \"antecedent\": \"armed && irq\",\n \"consequent\": \"pending\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ACK\",\n \"sva_name\": \"p_ack\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"acknowledge services a pending interrupt\",\n \"antecedent\": \"pending && ack\",\n \"consequent\": \"servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_WAIT_LOW\",\n \"sva_name\": \"p_wait_low\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"service completion waits for irq deassertion\",\n \"antecedent\": \"servicing\",\n \"consequent\": \"wait_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REARM\",\n \"sva_name\": \"p_rearm\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq deassertion rearms capture\",\n \"antecedent\": \"wait_low && !irq\",\n \"consequent\": \"armed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_irq\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"irq\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_ack\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PENDING\",\n \"old\": \"ack\",\n \"new\": \"false\"\n },\n {\n \"name\": \"premature_rearm\",\n \"kind\": \"force_transition\",\n \"from\": \"SERVICE\",\n \"to\": \"ARMED\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: interrupt_0009\n\n// P1_ONEHOT: interrupt phases are mutually exclusive.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({pending, servicing, wait_low, armed}));\n\n// P2_RESET: reset arms interrupt capture.\np_reset: assert property (@(posedge clk)\n (rst) |=> (armed));\n\n// P3_IRQ: irq while armed becomes pending.\np_irq: assert property (@(posedge clk) disable iff (rst)\n (armed && irq) |=> (pending));\n\n// P4_ACK: acknowledge services a pending interrupt.\np_ack: assert property (@(posedge clk) disable iff (rst)\n (pending && ack) |=> (servicing));\n\n// P5_WAIT_LOW: service completion waits for irq deassertion.\np_wait_low: assert property (@(posedge clk) disable iff (rst)\n (servicing) |=> (wait_low));\n\n// P6_REARM: irq deassertion rearms capture.\np_rearm: assert property (@(posedge clk) disable iff (rst)\n (wait_low && !irq) |=> (armed));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"interrupt phases are mutually exclusive\",\n \"expression\": \"$onehot({pending, servicing, wait_low, armed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset arms interrupt capture\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_IRQ\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq while armed becomes pending\",\n \"antecedent\": \"armed && irq\",\n \"consequent\": \"pending\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_ACK\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"acknowledge services a pending interrupt\",\n \"antecedent\": \"pending && ack\",\n \"consequent\": \"servicing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_WAIT_LOW\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"service completion waits for irq deassertion\",\n \"antecedent\": \"servicing\",\n \"consequent\": \"wait_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_REARM\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"irq deassertion rearms capture\",\n \"antecedent\": \"wait_low && !irq\",\n \"consequent\": \"armed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_ack.sv\": \"module interrupt_0009_mutant_ignore_ack (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\\n PENDING: next_state = (!ack) ? PENDING : (PENDING);\\n SERVICE: next_state = WAIT_LOW;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_irq.sv\": \"module interrupt_0009_mutant_ignore_irq (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (!irq) ? ARMED : (ARMED);\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = WAIT_LOW;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"premature_rearm.sv\": \"module interrupt_0009_mutant_premature_rearm (\\n input wire clk,\\n input wire rst,\\n input wire irq,\\n input wire ack,\\n output reg pending,\\n output reg servicing,\\n output reg wait_low,\\n output reg armed\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PENDING = 2'd1;\\n localparam [1:0] SERVICE = 2'd2;\\n localparam [1:0] WAIT_LOW = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (irq) ? PENDING : ((!irq) ? ARMED : (ARMED));\\n PENDING: next_state = (ack) ? SERVICE : ((!ack) ? PENDING : (PENDING));\\n SERVICE: next_state = ARMED;\\n WAIT_LOW: next_state = (irq) ? WAIT_LOW : ((!irq) ? ARMED : (WAIT_LOW));\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n case (state)\\n ARMED: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b1;\\n end\\n PENDING: begin\\n pending = 1'b1;\\n servicing = 1'b0;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n SERVICE: begin\\n pending = 1'b0;\\n servicing = 1'b1;\\n wait_low = 1'b0;\\n armed = 1'b0;\\n end\\n WAIT_LOW: begin\\n pending = 1'b0;\\n servicing = 1'b0;\\n wait_low = 1'b1;\\n armed = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "mode_controller_0009", "category": "mode_controller", "description": "Mode controller implementing primary backup behavior.", "rtl_variant": "canonical_case.sv", "rtl": "module mode_controller_0009_canonical_case (\n input wire clk,\n input wire rst,\n input wire enable,\n input wire fail,\n input wire recover,\n output reg primary,\n output reg backup,\n output reg off\n);\n localparam [1:0] OFF = 2'd0;\n localparam [1:0] PRIMARY = 2'd1;\n localparam [1:0] BACKUP = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n OFF: next_state = (enable) ? PRIMARY : ((!enable) ? OFF : (OFF));\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\n default: next_state = OFF;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= OFF;\n else\n state <= next_state;\n end\n\n always @* begin\n primary = 1'b0;\n backup = 1'b0;\n off = 1'b0;\n case (state)\n OFF: begin\n primary = 1'b0;\n backup = 1'b0;\n off = 1'b1;\n end\n PRIMARY: begin\n primary = 1'b1;\n backup = 1'b0;\n off = 1'b0;\n end\n BACKUP: begin\n primary = 1'b0;\n backup = 1'b1;\n off = 1'b0;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"mode_controller_0009\",\n \"category\": \"mode_controller\",\n \"template\": \"primary_backup\",\n \"description\": \"Mode controller implementing primary backup behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"OFF\"\n },\n \"inputs\": [\n \"enable\",\n \"fail\",\n \"recover\"\n ],\n \"outputs\": [\n \"primary\",\n \"backup\",\n \"off\"\n ],\n \"states\": [\n \"OFF\",\n \"PRIMARY\",\n \"BACKUP\"\n ],\n \"state_outputs\": {\n \"OFF\": {\n \"primary\": 0,\n \"backup\": 0,\n \"off\": 1\n },\n \"PRIMARY\": {\n \"primary\": 1,\n \"backup\": 0,\n \"off\": 0\n },\n \"BACKUP\": {\n \"primary\": 0,\n \"backup\": 1,\n \"off\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"OFF\",\n \"when\": \"enable\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"OFF\",\n \"when\": \"!enable\",\n \"to\": \"OFF\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"fail\",\n \"to\": \"BACKUP\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"!fail && enable\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"!fail && !enable\",\n \"to\": \"OFF\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"recover\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"!recover && enable\",\n \"to\": \"BACKUP\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"!recover && !enable\",\n \"to\": \"OFF\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({primary, backup, off})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to PRIMARY when enable\",\n \"antecedent\": \"(!primary && !backup && off) && (enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to OFF when !enable\",\n \"antecedent\": \"(!primary && !backup && off) && (!enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to BACKUP when fail\",\n \"antecedent\": \"(primary && !backup && !off) && (fail)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to PRIMARY when !fail && enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to OFF when !fail && !enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to PRIMARY when recover\",\n \"antecedent\": \"(!primary && backup && !off) && (recover)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to BACKUP when !recover && enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && enable)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to OFF when !recover && !enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"OFF\",\n \"old\": \"enable\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"OFF\",\n \"to\": \"PRIMARY\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PRIMARY\",\n \"old\": \"fail\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: mode_controller_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({primary, backup, off}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!primary && !backup && off));\n\n// P3_T1: OFF transitions to PRIMARY when enable.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!primary && !backup && off) && (enable)) |=> (primary && !backup && !off));\n\n// P4_T2: OFF transitions to OFF when !enable.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!primary && !backup && off) && (!enable)) |=> (!primary && !backup && off));\n\n// P5_T3: PRIMARY transitions to BACKUP when fail.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (fail)) |=> (!primary && backup && !off));\n\n// P6_T4: PRIMARY transitions to PRIMARY when !fail && enable.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (!fail && enable)) |=> (primary && !backup && !off));\n\n// P7_T5: PRIMARY transitions to OFF when !fail && !enable.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (!fail && !enable)) |=> (!primary && !backup && off));\n\n// P8_T6: BACKUP transitions to PRIMARY when recover.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (recover)) |=> (primary && !backup && !off));\n\n// P9_T7: BACKUP transitions to BACKUP when !recover && enable.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (!recover && enable)) |=> (!primary && backup && !off));\n\n// P10_T8: BACKUP transitions to OFF when !recover && !enable.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (!recover && !enable)) |=> (!primary && !backup && off));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({primary, backup, off})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to PRIMARY when enable\",\n \"antecedent\": \"(!primary && !backup && off) && (enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to OFF when !enable\",\n \"antecedent\": \"(!primary && !backup && off) && (!enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to BACKUP when fail\",\n \"antecedent\": \"(primary && !backup && !off) && (fail)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to PRIMARY when !fail && enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to OFF when !fail && !enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to PRIMARY when recover\",\n \"antecedent\": \"(!primary && backup && !off) && (recover)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to BACKUP when !recover && enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && enable)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to OFF when !recover && !enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module mode_controller_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = (!enable) ? OFF : (OFF);\\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module mode_controller_0009_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = (enable) ? PRIMARY : ((!enable) ? OFF : (OFF));\\n PRIMARY: next_state = (!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module mode_controller_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = PRIMARY;\\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "mode_controller_0009", "category": "mode_controller", "description": "Mode controller implementing primary backup behavior.", "rtl_variant": "onehot_case.sv", "rtl": "module mode_controller_0009_onehot_case (\n input wire clk,\n input wire rst,\n input wire enable,\n input wire fail,\n input wire recover,\n output reg primary,\n output reg backup,\n output reg off\n);\n localparam [2:0] OFF = 3'b001;\n localparam [2:0] PRIMARY = 3'b010;\n localparam [2:0] BACKUP = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = OFF;\n case (state)\n OFF: next_state = (enable) ? PRIMARY : ((!enable) ? OFF : (OFF));\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\n default: next_state = OFF;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= OFF;\n else\n state <= next_state;\n end\n\n always @* begin\n primary = (state == PRIMARY);\n backup = (state == BACKUP);\n off = (state == OFF);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"mode_controller_0009\",\n \"category\": \"mode_controller\",\n \"template\": \"primary_backup\",\n \"description\": \"Mode controller implementing primary backup behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"OFF\"\n },\n \"inputs\": [\n \"enable\",\n \"fail\",\n \"recover\"\n ],\n \"outputs\": [\n \"primary\",\n \"backup\",\n \"off\"\n ],\n \"states\": [\n \"OFF\",\n \"PRIMARY\",\n \"BACKUP\"\n ],\n \"state_outputs\": {\n \"OFF\": {\n \"primary\": 0,\n \"backup\": 0,\n \"off\": 1\n },\n \"PRIMARY\": {\n \"primary\": 1,\n \"backup\": 0,\n \"off\": 0\n },\n \"BACKUP\": {\n \"primary\": 0,\n \"backup\": 1,\n \"off\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"OFF\",\n \"when\": \"enable\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"OFF\",\n \"when\": \"!enable\",\n \"to\": \"OFF\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"fail\",\n \"to\": \"BACKUP\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"!fail && enable\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"!fail && !enable\",\n \"to\": \"OFF\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"recover\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"!recover && enable\",\n \"to\": \"BACKUP\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"!recover && !enable\",\n \"to\": \"OFF\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({primary, backup, off})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to PRIMARY when enable\",\n \"antecedent\": \"(!primary && !backup && off) && (enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to OFF when !enable\",\n \"antecedent\": \"(!primary && !backup && off) && (!enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to BACKUP when fail\",\n \"antecedent\": \"(primary && !backup && !off) && (fail)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to PRIMARY when !fail && enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to OFF when !fail && !enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to PRIMARY when recover\",\n \"antecedent\": \"(!primary && backup && !off) && (recover)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to BACKUP when !recover && enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && enable)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to OFF when !recover && !enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"OFF\",\n \"old\": \"enable\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"OFF\",\n \"to\": \"PRIMARY\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PRIMARY\",\n \"old\": \"fail\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: mode_controller_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({primary, backup, off}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!primary && !backup && off));\n\n// P3_T1: OFF transitions to PRIMARY when enable.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!primary && !backup && off) && (enable)) |=> (primary && !backup && !off));\n\n// P4_T2: OFF transitions to OFF when !enable.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!primary && !backup && off) && (!enable)) |=> (!primary && !backup && off));\n\n// P5_T3: PRIMARY transitions to BACKUP when fail.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (fail)) |=> (!primary && backup && !off));\n\n// P6_T4: PRIMARY transitions to PRIMARY when !fail && enable.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (!fail && enable)) |=> (primary && !backup && !off));\n\n// P7_T5: PRIMARY transitions to OFF when !fail && !enable.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (!fail && !enable)) |=> (!primary && !backup && off));\n\n// P8_T6: BACKUP transitions to PRIMARY when recover.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (recover)) |=> (primary && !backup && !off));\n\n// P9_T7: BACKUP transitions to BACKUP when !recover && enable.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (!recover && enable)) |=> (!primary && backup && !off));\n\n// P10_T8: BACKUP transitions to OFF when !recover && !enable.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (!recover && !enable)) |=> (!primary && !backup && off));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({primary, backup, off})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to PRIMARY when enable\",\n \"antecedent\": \"(!primary && !backup && off) && (enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to OFF when !enable\",\n \"antecedent\": \"(!primary && !backup && off) && (!enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to BACKUP when fail\",\n \"antecedent\": \"(primary && !backup && !off) && (fail)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to PRIMARY when !fail && enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to OFF when !fail && !enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to PRIMARY when recover\",\n \"antecedent\": \"(!primary && backup && !off) && (recover)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to BACKUP when !recover && enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && enable)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to OFF when !recover && !enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module mode_controller_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = (!enable) ? OFF : (OFF);\\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module mode_controller_0009_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = (enable) ? PRIMARY : ((!enable) ? OFF : (OFF));\\n PRIMARY: next_state = (!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module mode_controller_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = PRIMARY;\\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "mode_controller_0009", "category": "mode_controller", "description": "Mode controller implementing primary backup behavior.", "rtl_variant": "nested_if.sv", "rtl": "module mode_controller_0009_nested_if (\n input wire clk,\n input wire rst,\n input wire enable,\n input wire fail,\n input wire recover,\n output wire primary,\n output wire backup,\n output wire off\n);\n localparam [1:0] S_OFF = 2'd0;\n localparam [1:0] S_PRIMARY = 2'd1;\n localparam [1:0] S_BACKUP = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_OFF;\n end else begin\n if (state == S_OFF) begin\n state <= (enable) ? S_PRIMARY : ((!enable) ? S_OFF : (S_OFF));\n end\n else if (state == S_PRIMARY) begin\n state <= (fail) ? S_BACKUP : ((!fail && enable) ? S_PRIMARY : ((!fail && !enable) ? S_OFF : (S_PRIMARY)));\n end\n else if (state == S_BACKUP) begin\n state <= (recover) ? S_PRIMARY : ((!recover && enable) ? S_BACKUP : ((!recover && !enable) ? S_OFF : (S_BACKUP)));\n end\n else begin\n state <= S_OFF;\n end\n end\n end\n\n assign primary = (state == S_PRIMARY);\n assign backup = (state == S_BACKUP);\n assign off = (state == S_OFF);\nendmodule\n", "spec_json": "{\n \"design_id\": \"mode_controller_0009\",\n \"category\": \"mode_controller\",\n \"template\": \"primary_backup\",\n \"description\": \"Mode controller implementing primary backup behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"OFF\"\n },\n \"inputs\": [\n \"enable\",\n \"fail\",\n \"recover\"\n ],\n \"outputs\": [\n \"primary\",\n \"backup\",\n \"off\"\n ],\n \"states\": [\n \"OFF\",\n \"PRIMARY\",\n \"BACKUP\"\n ],\n \"state_outputs\": {\n \"OFF\": {\n \"primary\": 0,\n \"backup\": 0,\n \"off\": 1\n },\n \"PRIMARY\": {\n \"primary\": 1,\n \"backup\": 0,\n \"off\": 0\n },\n \"BACKUP\": {\n \"primary\": 0,\n \"backup\": 1,\n \"off\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"OFF\",\n \"when\": \"enable\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"OFF\",\n \"when\": \"!enable\",\n \"to\": \"OFF\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"fail\",\n \"to\": \"BACKUP\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"!fail && enable\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"!fail && !enable\",\n \"to\": \"OFF\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"recover\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"!recover && enable\",\n \"to\": \"BACKUP\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"!recover && !enable\",\n \"to\": \"OFF\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({primary, backup, off})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to PRIMARY when enable\",\n \"antecedent\": \"(!primary && !backup && off) && (enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to OFF when !enable\",\n \"antecedent\": \"(!primary && !backup && off) && (!enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to BACKUP when fail\",\n \"antecedent\": \"(primary && !backup && !off) && (fail)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to PRIMARY when !fail && enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to OFF when !fail && !enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to PRIMARY when recover\",\n \"antecedent\": \"(!primary && backup && !off) && (recover)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to BACKUP when !recover && enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && enable)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to OFF when !recover && !enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"OFF\",\n \"old\": \"enable\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"OFF\",\n \"to\": \"PRIMARY\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PRIMARY\",\n \"old\": \"fail\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: mode_controller_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({primary, backup, off}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!primary && !backup && off));\n\n// P3_T1: OFF transitions to PRIMARY when enable.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!primary && !backup && off) && (enable)) |=> (primary && !backup && !off));\n\n// P4_T2: OFF transitions to OFF when !enable.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!primary && !backup && off) && (!enable)) |=> (!primary && !backup && off));\n\n// P5_T3: PRIMARY transitions to BACKUP when fail.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (fail)) |=> (!primary && backup && !off));\n\n// P6_T4: PRIMARY transitions to PRIMARY when !fail && enable.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (!fail && enable)) |=> (primary && !backup && !off));\n\n// P7_T5: PRIMARY transitions to OFF when !fail && !enable.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (!fail && !enable)) |=> (!primary && !backup && off));\n\n// P8_T6: BACKUP transitions to PRIMARY when recover.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (recover)) |=> (primary && !backup && !off));\n\n// P9_T7: BACKUP transitions to BACKUP when !recover && enable.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (!recover && enable)) |=> (!primary && backup && !off));\n\n// P10_T8: BACKUP transitions to OFF when !recover && !enable.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (!recover && !enable)) |=> (!primary && !backup && off));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({primary, backup, off})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to PRIMARY when enable\",\n \"antecedent\": \"(!primary && !backup && off) && (enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to OFF when !enable\",\n \"antecedent\": \"(!primary && !backup && off) && (!enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to BACKUP when fail\",\n \"antecedent\": \"(primary && !backup && !off) && (fail)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to PRIMARY when !fail && enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to OFF when !fail && !enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to PRIMARY when recover\",\n \"antecedent\": \"(!primary && backup && !off) && (recover)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to BACKUP when !recover && enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && enable)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to OFF when !recover && !enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module mode_controller_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = (!enable) ? OFF : (OFF);\\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module mode_controller_0009_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = (enable) ? PRIMARY : ((!enable) ? OFF : (OFF));\\n PRIMARY: next_state = (!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module mode_controller_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = PRIMARY;\\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "mode_controller_0009", "category": "mode_controller", "description": "Mode controller implementing primary backup behavior.", "rtl_variant": "factored_flags.sv", "rtl": "module mode_controller_0009_factored_flags (\n input wire clk,\n input wire rst,\n input wire enable,\n input wire fail,\n input wire recover,\n output reg primary,\n output reg backup,\n output reg off\n);\n localparam [1:0] F_OFF = 2'd0;\n localparam [1:0] F_PRIMARY = 2'd1;\n localparam [1:0] F_BACKUP = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_off_0 = (enable);\n wire guard_off_1 = (!enable);\n wire guard_primary_0 = (fail);\n wire guard_primary_1 = (!fail && enable);\n wire guard_primary_2 = (!fail && !enable);\n wire guard_backup_0 = (recover);\n wire guard_backup_1 = (!recover && enable);\n wire guard_backup_2 = (!recover && !enable);\n\n always @* begin\n next_state = state;\n case (state)\n F_OFF: begin\n if (guard_off_0)\n next_state = F_PRIMARY;\n else if (guard_off_1)\n next_state = F_OFF;\n end\n F_PRIMARY: begin\n if (guard_primary_0)\n next_state = F_BACKUP;\n else if (guard_primary_1)\n next_state = F_PRIMARY;\n else if (guard_primary_2)\n next_state = F_OFF;\n end\n F_BACKUP: begin\n if (guard_backup_0)\n next_state = F_PRIMARY;\n else if (guard_backup_1)\n next_state = F_BACKUP;\n else if (guard_backup_2)\n next_state = F_OFF;\n end\n default: next_state = F_OFF;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_OFF;\n else\n state <= next_state;\n end\n\n always @* begin\n primary = 1'b0;\n backup = 1'b0;\n off = 1'b0;\n case (state)\n F_OFF: begin\n primary = 1'b0;\n backup = 1'b0;\n off = 1'b1;\n end\n F_PRIMARY: begin\n primary = 1'b1;\n backup = 1'b0;\n off = 1'b0;\n end\n F_BACKUP: begin\n primary = 1'b0;\n backup = 1'b1;\n off = 1'b0;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"mode_controller_0009\",\n \"category\": \"mode_controller\",\n \"template\": \"primary_backup\",\n \"description\": \"Mode controller implementing primary backup behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"OFF\"\n },\n \"inputs\": [\n \"enable\",\n \"fail\",\n \"recover\"\n ],\n \"outputs\": [\n \"primary\",\n \"backup\",\n \"off\"\n ],\n \"states\": [\n \"OFF\",\n \"PRIMARY\",\n \"BACKUP\"\n ],\n \"state_outputs\": {\n \"OFF\": {\n \"primary\": 0,\n \"backup\": 0,\n \"off\": 1\n },\n \"PRIMARY\": {\n \"primary\": 1,\n \"backup\": 0,\n \"off\": 0\n },\n \"BACKUP\": {\n \"primary\": 0,\n \"backup\": 1,\n \"off\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"OFF\",\n \"when\": \"enable\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"OFF\",\n \"when\": \"!enable\",\n \"to\": \"OFF\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"fail\",\n \"to\": \"BACKUP\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"!fail && enable\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"PRIMARY\",\n \"when\": \"!fail && !enable\",\n \"to\": \"OFF\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"recover\",\n \"to\": \"PRIMARY\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"!recover && enable\",\n \"to\": \"BACKUP\"\n },\n {\n \"from\": \"BACKUP\",\n \"when\": \"!recover && !enable\",\n \"to\": \"OFF\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({primary, backup, off})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to PRIMARY when enable\",\n \"antecedent\": \"(!primary && !backup && off) && (enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to OFF when !enable\",\n \"antecedent\": \"(!primary && !backup && off) && (!enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to BACKUP when fail\",\n \"antecedent\": \"(primary && !backup && !off) && (fail)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to PRIMARY when !fail && enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to OFF when !fail && !enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to PRIMARY when recover\",\n \"antecedent\": \"(!primary && backup && !off) && (recover)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to BACKUP when !recover && enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && enable)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to OFF when !recover && !enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"OFF\",\n \"old\": \"enable\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"OFF\",\n \"to\": \"PRIMARY\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"PRIMARY\",\n \"old\": \"fail\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: mode_controller_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({primary, backup, off}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!primary && !backup && off));\n\n// P3_T1: OFF transitions to PRIMARY when enable.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!primary && !backup && off) && (enable)) |=> (primary && !backup && !off));\n\n// P4_T2: OFF transitions to OFF when !enable.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!primary && !backup && off) && (!enable)) |=> (!primary && !backup && off));\n\n// P5_T3: PRIMARY transitions to BACKUP when fail.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (fail)) |=> (!primary && backup && !off));\n\n// P6_T4: PRIMARY transitions to PRIMARY when !fail && enable.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (!fail && enable)) |=> (primary && !backup && !off));\n\n// P7_T5: PRIMARY transitions to OFF when !fail && !enable.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((primary && !backup && !off) && (!fail && !enable)) |=> (!primary && !backup && off));\n\n// P8_T6: BACKUP transitions to PRIMARY when recover.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (recover)) |=> (primary && !backup && !off));\n\n// P9_T7: BACKUP transitions to BACKUP when !recover && enable.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (!recover && enable)) |=> (!primary && backup && !off));\n\n// P10_T8: BACKUP transitions to OFF when !recover && !enable.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!primary && backup && !off) && (!recover && !enable)) |=> (!primary && !backup && off));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({primary, backup, off})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to PRIMARY when enable\",\n \"antecedent\": \"(!primary && !backup && off) && (enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OFF transitions to OFF when !enable\",\n \"antecedent\": \"(!primary && !backup && off) && (!enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to BACKUP when fail\",\n \"antecedent\": \"(primary && !backup && !off) && (fail)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to PRIMARY when !fail && enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && enable)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PRIMARY transitions to OFF when !fail && !enable\",\n \"antecedent\": \"(primary && !backup && !off) && (!fail && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to PRIMARY when recover\",\n \"antecedent\": \"(!primary && backup && !off) && (recover)\",\n \"consequent\": \"primary && !backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to BACKUP when !recover && enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && enable)\",\n \"consequent\": \"!primary && backup && !off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BACKUP transitions to OFF when !recover && !enable\",\n \"antecedent\": \"(!primary && backup && !off) && (!recover && !enable)\",\n \"consequent\": \"!primary && !backup && off\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module mode_controller_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = (!enable) ? OFF : (OFF);\\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module mode_controller_0009_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = (enable) ? PRIMARY : ((!enable) ? OFF : (OFF));\\n PRIMARY: next_state = (!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module mode_controller_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire enable,\\n input wire fail,\\n input wire recover,\\n output reg primary,\\n output reg backup,\\n output reg off\\n);\\n localparam [1:0] OFF = 2'd0;\\n localparam [1:0] PRIMARY = 2'd1;\\n localparam [1:0] BACKUP = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OFF: next_state = PRIMARY;\\n PRIMARY: next_state = (fail) ? BACKUP : ((!fail && enable) ? PRIMARY : ((!fail && !enable) ? OFF : (PRIMARY)));\\n BACKUP: next_state = (recover) ? PRIMARY : ((!recover && enable) ? BACKUP : ((!recover && !enable) ? OFF : (BACKUP)));\\n default: next_state = OFF;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OFF;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b0;\\n case (state)\\n OFF: begin\\n primary = 1'b0;\\n backup = 1'b0;\\n off = 1'b1;\\n end\\n PRIMARY: begin\\n primary = 1'b1;\\n backup = 1'b0;\\n off = 1'b0;\\n end\\n BACKUP: begin\\n primary = 1'b0;\\n backup = 1'b1;\\n off = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "mode_controller_0008", "category": "mode_controller", "description": "Mode controller implementing boot ready run behavior.", "rtl_variant": "canonical_case.sv", "rtl": "module mode_controller_0008_canonical_case (\n input wire clk,\n input wire rst,\n input wire boot_ok,\n input wire start,\n input wire stop,\n output reg booting,\n output reg ready,\n output reg running\n);\n localparam [1:0] BOOT = 2'd0;\n localparam [1:0] READY = 2'd1;\n localparam [1:0] RUN = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n BOOT: next_state = (boot_ok) ? READY : ((!boot_ok) ? BOOT : (BOOT));\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\n default: next_state = BOOT;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= BOOT;\n else\n state <= next_state;\n end\n\n always @* begin\n booting = 1'b0;\n ready = 1'b0;\n running = 1'b0;\n case (state)\n BOOT: begin\n booting = 1'b1;\n ready = 1'b0;\n running = 1'b0;\n end\n READY: begin\n booting = 1'b0;\n ready = 1'b1;\n running = 1'b0;\n end\n RUN: begin\n booting = 1'b0;\n ready = 1'b0;\n running = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"mode_controller_0008\",\n \"category\": \"mode_controller\",\n \"template\": \"boot_ready_run\",\n \"description\": \"Mode controller implementing boot ready run behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"BOOT\"\n },\n \"inputs\": [\n \"boot_ok\",\n \"start\",\n \"stop\"\n ],\n \"outputs\": [\n \"booting\",\n \"ready\",\n \"running\"\n ],\n \"states\": [\n \"BOOT\",\n \"READY\",\n \"RUN\"\n ],\n \"state_outputs\": {\n \"BOOT\": {\n \"booting\": 1,\n \"ready\": 0,\n \"running\": 0\n },\n \"READY\": {\n \"booting\": 0,\n \"ready\": 1,\n \"running\": 0\n },\n \"RUN\": {\n \"booting\": 0,\n \"ready\": 0,\n \"running\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"BOOT\",\n \"when\": \"boot_ok\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"BOOT\",\n \"when\": \"!boot_ok\",\n \"to\": \"BOOT\"\n },\n {\n \"from\": \"READY\",\n \"when\": \"start\",\n \"to\": \"RUN\"\n },\n {\n \"from\": \"READY\",\n \"when\": \"!start\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"RUN\",\n \"when\": \"stop\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"RUN\",\n \"when\": \"!stop\",\n \"to\": \"RUN\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({booting, ready, running})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to READY when boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (boot_ok)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to BOOT when !boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (!boot_ok)\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to RUN when start\",\n \"antecedent\": \"(!booting && ready && !running) && (start)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to READY when !start\",\n \"antecedent\": \"(!booting && ready && !running) && (!start)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to READY when stop\",\n \"antecedent\": \"(!booting && !ready && running) && (stop)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to RUN when !stop\",\n \"antecedent\": \"(!booting && !ready && running) && (!stop)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"BOOT\",\n \"old\": \"boot_ok\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"BOOT\",\n \"to\": \"READY\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"READY\",\n \"old\": \"start\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: mode_controller_0008\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({booting, ready, running}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (booting && !ready && !running));\n\n// P3_T1: BOOT transitions to READY when boot_ok.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((booting && !ready && !running) && (boot_ok)) |=> (!booting && ready && !running));\n\n// P4_T2: BOOT transitions to BOOT when !boot_ok.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((booting && !ready && !running) && (!boot_ok)) |=> (booting && !ready && !running));\n\n// P5_T3: READY transitions to RUN when start.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!booting && ready && !running) && (start)) |=> (!booting && !ready && running));\n\n// P6_T4: READY transitions to READY when !start.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!booting && ready && !running) && (!start)) |=> (!booting && ready && !running));\n\n// P7_T5: RUN transitions to READY when stop.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!booting && !ready && running) && (stop)) |=> (!booting && ready && !running));\n\n// P8_T6: RUN transitions to RUN when !stop.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!booting && !ready && running) && (!stop)) |=> (!booting && !ready && running));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({booting, ready, running})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to READY when boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (boot_ok)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to BOOT when !boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (!boot_ok)\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to RUN when start\",\n \"antecedent\": \"(!booting && ready && !running) && (start)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to READY when !start\",\n \"antecedent\": \"(!booting && ready && !running) && (!start)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to READY when stop\",\n \"antecedent\": \"(!booting && !ready && running) && (stop)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to RUN when !stop\",\n \"antecedent\": \"(!booting && !ready && running) && (!stop)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module mode_controller_0008_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = (!boot_ok) ? BOOT : (BOOT);\\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module mode_controller_0008_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = (boot_ok) ? READY : ((!boot_ok) ? BOOT : (BOOT));\\n READY: next_state = (!start) ? READY : (READY);\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module mode_controller_0008_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = READY;\\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "mode_controller_0008", "category": "mode_controller", "description": "Mode controller implementing boot ready run behavior.", "rtl_variant": "onehot_case.sv", "rtl": "module mode_controller_0008_onehot_case (\n input wire clk,\n input wire rst,\n input wire boot_ok,\n input wire start,\n input wire stop,\n output reg booting,\n output reg ready,\n output reg running\n);\n localparam [2:0] BOOT = 3'b001;\n localparam [2:0] READY = 3'b010;\n localparam [2:0] RUN = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = BOOT;\n case (state)\n BOOT: next_state = (boot_ok) ? READY : ((!boot_ok) ? BOOT : (BOOT));\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\n default: next_state = BOOT;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= BOOT;\n else\n state <= next_state;\n end\n\n always @* begin\n booting = (state == BOOT);\n ready = (state == READY);\n running = (state == RUN);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"mode_controller_0008\",\n \"category\": \"mode_controller\",\n \"template\": \"boot_ready_run\",\n \"description\": \"Mode controller implementing boot ready run behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"BOOT\"\n },\n \"inputs\": [\n \"boot_ok\",\n \"start\",\n \"stop\"\n ],\n \"outputs\": [\n \"booting\",\n \"ready\",\n \"running\"\n ],\n \"states\": [\n \"BOOT\",\n \"READY\",\n \"RUN\"\n ],\n \"state_outputs\": {\n \"BOOT\": {\n \"booting\": 1,\n \"ready\": 0,\n \"running\": 0\n },\n \"READY\": {\n \"booting\": 0,\n \"ready\": 1,\n \"running\": 0\n },\n \"RUN\": {\n \"booting\": 0,\n \"ready\": 0,\n \"running\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"BOOT\",\n \"when\": \"boot_ok\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"BOOT\",\n \"when\": \"!boot_ok\",\n \"to\": \"BOOT\"\n },\n {\n \"from\": \"READY\",\n \"when\": \"start\",\n \"to\": \"RUN\"\n },\n {\n \"from\": \"READY\",\n \"when\": \"!start\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"RUN\",\n \"when\": \"stop\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"RUN\",\n \"when\": \"!stop\",\n \"to\": \"RUN\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({booting, ready, running})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to READY when boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (boot_ok)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to BOOT when !boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (!boot_ok)\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to RUN when start\",\n \"antecedent\": \"(!booting && ready && !running) && (start)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to READY when !start\",\n \"antecedent\": \"(!booting && ready && !running) && (!start)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to READY when stop\",\n \"antecedent\": \"(!booting && !ready && running) && (stop)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to RUN when !stop\",\n \"antecedent\": \"(!booting && !ready && running) && (!stop)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"BOOT\",\n \"old\": \"boot_ok\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"BOOT\",\n \"to\": \"READY\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"READY\",\n \"old\": \"start\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: mode_controller_0008\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({booting, ready, running}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (booting && !ready && !running));\n\n// P3_T1: BOOT transitions to READY when boot_ok.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((booting && !ready && !running) && (boot_ok)) |=> (!booting && ready && !running));\n\n// P4_T2: BOOT transitions to BOOT when !boot_ok.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((booting && !ready && !running) && (!boot_ok)) |=> (booting && !ready && !running));\n\n// P5_T3: READY transitions to RUN when start.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!booting && ready && !running) && (start)) |=> (!booting && !ready && running));\n\n// P6_T4: READY transitions to READY when !start.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!booting && ready && !running) && (!start)) |=> (!booting && ready && !running));\n\n// P7_T5: RUN transitions to READY when stop.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!booting && !ready && running) && (stop)) |=> (!booting && ready && !running));\n\n// P8_T6: RUN transitions to RUN when !stop.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!booting && !ready && running) && (!stop)) |=> (!booting && !ready && running));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({booting, ready, running})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to READY when boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (boot_ok)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to BOOT when !boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (!boot_ok)\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to RUN when start\",\n \"antecedent\": \"(!booting && ready && !running) && (start)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to READY when !start\",\n \"antecedent\": \"(!booting && ready && !running) && (!start)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to READY when stop\",\n \"antecedent\": \"(!booting && !ready && running) && (stop)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to RUN when !stop\",\n \"antecedent\": \"(!booting && !ready && running) && (!stop)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module mode_controller_0008_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = (!boot_ok) ? BOOT : (BOOT);\\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module mode_controller_0008_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = (boot_ok) ? READY : ((!boot_ok) ? BOOT : (BOOT));\\n READY: next_state = (!start) ? READY : (READY);\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module mode_controller_0008_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = READY;\\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "mode_controller_0008", "category": "mode_controller", "description": "Mode controller implementing boot ready run behavior.", "rtl_variant": "nested_if.sv", "rtl": "module mode_controller_0008_nested_if (\n input wire clk,\n input wire rst,\n input wire boot_ok,\n input wire start,\n input wire stop,\n output wire booting,\n output wire ready,\n output wire running\n);\n localparam [1:0] S_BOOT = 2'd0;\n localparam [1:0] S_READY = 2'd1;\n localparam [1:0] S_RUN = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_BOOT;\n end else begin\n if (state == S_BOOT) begin\n state <= (boot_ok) ? S_READY : ((!boot_ok) ? S_BOOT : (S_BOOT));\n end\n else if (state == S_READY) begin\n state <= (start) ? S_RUN : ((!start) ? S_READY : (S_READY));\n end\n else if (state == S_RUN) begin\n state <= (stop) ? S_READY : ((!stop) ? S_RUN : (S_RUN));\n end\n else begin\n state <= S_BOOT;\n end\n end\n end\n\n assign booting = (state == S_BOOT);\n assign ready = (state == S_READY);\n assign running = (state == S_RUN);\nendmodule\n", "spec_json": "{\n \"design_id\": \"mode_controller_0008\",\n \"category\": \"mode_controller\",\n \"template\": \"boot_ready_run\",\n \"description\": \"Mode controller implementing boot ready run behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"BOOT\"\n },\n \"inputs\": [\n \"boot_ok\",\n \"start\",\n \"stop\"\n ],\n \"outputs\": [\n \"booting\",\n \"ready\",\n \"running\"\n ],\n \"states\": [\n \"BOOT\",\n \"READY\",\n \"RUN\"\n ],\n \"state_outputs\": {\n \"BOOT\": {\n \"booting\": 1,\n \"ready\": 0,\n \"running\": 0\n },\n \"READY\": {\n \"booting\": 0,\n \"ready\": 1,\n \"running\": 0\n },\n \"RUN\": {\n \"booting\": 0,\n \"ready\": 0,\n \"running\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"BOOT\",\n \"when\": \"boot_ok\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"BOOT\",\n \"when\": \"!boot_ok\",\n \"to\": \"BOOT\"\n },\n {\n \"from\": \"READY\",\n \"when\": \"start\",\n \"to\": \"RUN\"\n },\n {\n \"from\": \"READY\",\n \"when\": \"!start\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"RUN\",\n \"when\": \"stop\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"RUN\",\n \"when\": \"!stop\",\n \"to\": \"RUN\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({booting, ready, running})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to READY when boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (boot_ok)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to BOOT when !boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (!boot_ok)\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to RUN when start\",\n \"antecedent\": \"(!booting && ready && !running) && (start)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to READY when !start\",\n \"antecedent\": \"(!booting && ready && !running) && (!start)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to READY when stop\",\n \"antecedent\": \"(!booting && !ready && running) && (stop)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to RUN when !stop\",\n \"antecedent\": \"(!booting && !ready && running) && (!stop)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"BOOT\",\n \"old\": \"boot_ok\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"BOOT\",\n \"to\": \"READY\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"READY\",\n \"old\": \"start\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: mode_controller_0008\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({booting, ready, running}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (booting && !ready && !running));\n\n// P3_T1: BOOT transitions to READY when boot_ok.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((booting && !ready && !running) && (boot_ok)) |=> (!booting && ready && !running));\n\n// P4_T2: BOOT transitions to BOOT when !boot_ok.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((booting && !ready && !running) && (!boot_ok)) |=> (booting && !ready && !running));\n\n// P5_T3: READY transitions to RUN when start.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!booting && ready && !running) && (start)) |=> (!booting && !ready && running));\n\n// P6_T4: READY transitions to READY when !start.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!booting && ready && !running) && (!start)) |=> (!booting && ready && !running));\n\n// P7_T5: RUN transitions to READY when stop.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!booting && !ready && running) && (stop)) |=> (!booting && ready && !running));\n\n// P8_T6: RUN transitions to RUN when !stop.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!booting && !ready && running) && (!stop)) |=> (!booting && !ready && running));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({booting, ready, running})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to READY when boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (boot_ok)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to BOOT when !boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (!boot_ok)\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to RUN when start\",\n \"antecedent\": \"(!booting && ready && !running) && (start)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to READY when !start\",\n \"antecedent\": \"(!booting && ready && !running) && (!start)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to READY when stop\",\n \"antecedent\": \"(!booting && !ready && running) && (stop)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to RUN when !stop\",\n \"antecedent\": \"(!booting && !ready && running) && (!stop)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module mode_controller_0008_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = (!boot_ok) ? BOOT : (BOOT);\\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module mode_controller_0008_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = (boot_ok) ? READY : ((!boot_ok) ? BOOT : (BOOT));\\n READY: next_state = (!start) ? READY : (READY);\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module mode_controller_0008_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = READY;\\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "mode_controller_0008", "category": "mode_controller", "description": "Mode controller implementing boot ready run behavior.", "rtl_variant": "factored_flags.sv", "rtl": "module mode_controller_0008_factored_flags (\n input wire clk,\n input wire rst,\n input wire boot_ok,\n input wire start,\n input wire stop,\n output reg booting,\n output reg ready,\n output reg running\n);\n localparam [1:0] F_BOOT = 2'd0;\n localparam [1:0] F_READY = 2'd1;\n localparam [1:0] F_RUN = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_boot_0 = (boot_ok);\n wire guard_boot_1 = (!boot_ok);\n wire guard_ready_0 = (start);\n wire guard_ready_1 = (!start);\n wire guard_run_0 = (stop);\n wire guard_run_1 = (!stop);\n\n always @* begin\n next_state = state;\n case (state)\n F_BOOT: begin\n if (guard_boot_0)\n next_state = F_READY;\n else if (guard_boot_1)\n next_state = F_BOOT;\n end\n F_READY: begin\n if (guard_ready_0)\n next_state = F_RUN;\n else if (guard_ready_1)\n next_state = F_READY;\n end\n F_RUN: begin\n if (guard_run_0)\n next_state = F_READY;\n else if (guard_run_1)\n next_state = F_RUN;\n end\n default: next_state = F_BOOT;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_BOOT;\n else\n state <= next_state;\n end\n\n always @* begin\n booting = 1'b0;\n ready = 1'b0;\n running = 1'b0;\n case (state)\n F_BOOT: begin\n booting = 1'b1;\n ready = 1'b0;\n running = 1'b0;\n end\n F_READY: begin\n booting = 1'b0;\n ready = 1'b1;\n running = 1'b0;\n end\n F_RUN: begin\n booting = 1'b0;\n ready = 1'b0;\n running = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"mode_controller_0008\",\n \"category\": \"mode_controller\",\n \"template\": \"boot_ready_run\",\n \"description\": \"Mode controller implementing boot ready run behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"BOOT\"\n },\n \"inputs\": [\n \"boot_ok\",\n \"start\",\n \"stop\"\n ],\n \"outputs\": [\n \"booting\",\n \"ready\",\n \"running\"\n ],\n \"states\": [\n \"BOOT\",\n \"READY\",\n \"RUN\"\n ],\n \"state_outputs\": {\n \"BOOT\": {\n \"booting\": 1,\n \"ready\": 0,\n \"running\": 0\n },\n \"READY\": {\n \"booting\": 0,\n \"ready\": 1,\n \"running\": 0\n },\n \"RUN\": {\n \"booting\": 0,\n \"ready\": 0,\n \"running\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"BOOT\",\n \"when\": \"boot_ok\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"BOOT\",\n \"when\": \"!boot_ok\",\n \"to\": \"BOOT\"\n },\n {\n \"from\": \"READY\",\n \"when\": \"start\",\n \"to\": \"RUN\"\n },\n {\n \"from\": \"READY\",\n \"when\": \"!start\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"RUN\",\n \"when\": \"stop\",\n \"to\": \"READY\"\n },\n {\n \"from\": \"RUN\",\n \"when\": \"!stop\",\n \"to\": \"RUN\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({booting, ready, running})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to READY when boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (boot_ok)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to BOOT when !boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (!boot_ok)\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to RUN when start\",\n \"antecedent\": \"(!booting && ready && !running) && (start)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to READY when !start\",\n \"antecedent\": \"(!booting && ready && !running) && (!start)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to READY when stop\",\n \"antecedent\": \"(!booting && !ready && running) && (stop)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to RUN when !stop\",\n \"antecedent\": \"(!booting && !ready && running) && (!stop)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"BOOT\",\n \"old\": \"boot_ok\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"BOOT\",\n \"to\": \"READY\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"READY\",\n \"old\": \"start\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: mode_controller_0008\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({booting, ready, running}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (booting && !ready && !running));\n\n// P3_T1: BOOT transitions to READY when boot_ok.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((booting && !ready && !running) && (boot_ok)) |=> (!booting && ready && !running));\n\n// P4_T2: BOOT transitions to BOOT when !boot_ok.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((booting && !ready && !running) && (!boot_ok)) |=> (booting && !ready && !running));\n\n// P5_T3: READY transitions to RUN when start.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((!booting && ready && !running) && (start)) |=> (!booting && !ready && running));\n\n// P6_T4: READY transitions to READY when !start.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!booting && ready && !running) && (!start)) |=> (!booting && ready && !running));\n\n// P7_T5: RUN transitions to READY when stop.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!booting && !ready && running) && (stop)) |=> (!booting && ready && !running));\n\n// P8_T6: RUN transitions to RUN when !stop.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!booting && !ready && running) && (!stop)) |=> (!booting && !ready && running));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({booting, ready, running})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to READY when boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (boot_ok)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"BOOT transitions to BOOT when !boot_ok\",\n \"antecedent\": \"(booting && !ready && !running) && (!boot_ok)\",\n \"consequent\": \"booting && !ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to RUN when start\",\n \"antecedent\": \"(!booting && ready && !running) && (start)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"READY transitions to READY when !start\",\n \"antecedent\": \"(!booting && ready && !running) && (!start)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to READY when stop\",\n \"antecedent\": \"(!booting && !ready && running) && (stop)\",\n \"consequent\": \"!booting && ready && !running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"RUN transitions to RUN when !stop\",\n \"antecedent\": \"(!booting && !ready && running) && (!stop)\",\n \"consequent\": \"!booting && !ready && running\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module mode_controller_0008_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = (!boot_ok) ? BOOT : (BOOT);\\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module mode_controller_0008_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = (boot_ok) ? READY : ((!boot_ok) ? BOOT : (BOOT));\\n READY: next_state = (!start) ? READY : (READY);\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module mode_controller_0008_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire boot_ok,\\n input wire start,\\n input wire stop,\\n output reg booting,\\n output reg ready,\\n output reg running\\n);\\n localparam [1:0] BOOT = 2'd0;\\n localparam [1:0] READY = 2'd1;\\n localparam [1:0] RUN = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n BOOT: next_state = READY;\\n READY: next_state = (start) ? RUN : ((!start) ? READY : (READY));\\n RUN: next_state = (stop) ? READY : ((!stop) ? RUN : (RUN));\\n default: next_state = BOOT;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= BOOT;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b0;\\n case (state)\\n BOOT: begin\\n booting = 1'b1;\\n ready = 1'b0;\\n running = 1'b0;\\n end\\n READY: begin\\n booting = 1'b0;\\n ready = 1'b1;\\n running = 1'b0;\\n end\\n RUN: begin\\n booting = 1'b0;\\n ready = 1'b0;\\n running = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "protocol_controller_0008", "category": "protocol_controller", "description": "Session protocol opens, authenticates, transfers, closes, then signals completion.", "rtl_variant": "canonical_case.sv", "rtl": "module protocol_controller_0008_canonical_case (\n input wire clk,\n input wire rst,\n input wire open_ok,\n input wire auth_ok,\n input wire transfer_done,\n input wire close_ok,\n input wire abort,\n output reg opening,\n output reg authenticating,\n output reg transferring,\n output reg closing,\n output reg done,\n output reg failed\n);\n localparam [2:0] OPEN = 3'd0;\n localparam [2:0] AUTH = 3'd1;\n localparam [2:0] TRANSFER = 3'd2;\n localparam [2:0] CLOSE = 3'd3;\n localparam [2:0] DONE = 3'd4;\n localparam [2:0] FAILED = 3'd5;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\n DONE: next_state = OPEN;\n FAILED: next_state = OPEN;\n default: next_state = OPEN;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= OPEN;\n else\n state <= next_state;\n end\n\n always @* begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b0;\n case (state)\n OPEN: begin\n opening = 1'b1;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b0;\n end\n AUTH: begin\n opening = 1'b0;\n authenticating = 1'b1;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b0;\n end\n TRANSFER: begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b1;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b0;\n end\n CLOSE: begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b1;\n done = 1'b0;\n failed = 1'b0;\n end\n DONE: begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b1;\n failed = 1'b0;\n end\n FAILED: begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"protocol_controller_0008\",\n \"category\": \"protocol_controller\",\n \"template\": \"open_auth_transfer_close\",\n \"description\": \"Session protocol opens, authenticates, transfers, closes, then signals completion.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"OPEN\"\n },\n \"inputs\": [\n \"open_ok\",\n \"auth_ok\",\n \"transfer_done\",\n \"close_ok\",\n \"abort\"\n ],\n \"outputs\": [\n \"opening\",\n \"authenticating\",\n \"transferring\",\n \"closing\",\n \"done\",\n \"failed\"\n ],\n \"states\": [\n \"OPEN\",\n \"AUTH\",\n \"TRANSFER\",\n \"CLOSE\",\n \"DONE\",\n \"FAILED\"\n ],\n \"state_outputs\": {\n \"OPEN\": {\n \"opening\": 1,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"AUTH\": {\n \"opening\": 0,\n \"authenticating\": 1,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"TRANSFER\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 1,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"CLOSE\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 1,\n \"done\": 0,\n \"failed\": 0\n },\n \"DONE\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 1,\n \"failed\": 0\n },\n \"FAILED\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"OPEN\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"!abort && open_ok\",\n \"to\": \"AUTH\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"!abort && !open_ok\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"!abort && auth_ok\",\n \"to\": \"TRANSFER\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"!abort && !auth_ok\",\n \"to\": \"AUTH\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"!abort && transfer_done\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"!abort && !transfer_done\",\n \"to\": \"TRANSFER\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!abort && close_ok\",\n \"to\": \"DONE\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!abort && !close_ok\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"DONE\",\n \"when\": \"true\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"FAILED\",\n \"when\": \"true\",\n \"to\": \"OPEN\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"session phases are mutually exclusive\",\n \"expression\": \"$onehot({opening, authenticating, transferring, closing, done, failed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset begins in opening phase\",\n \"antecedent\": \"rst\",\n \"consequent\": \"opening\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_OPEN\",\n \"sva_name\": \"p_open\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful open advances to authentication\",\n \"antecedent\": \"opening && open_ok && !abort\",\n \"consequent\": \"authenticating\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_AUTH\",\n \"sva_name\": \"p_auth\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful authentication begins transfer\",\n \"antecedent\": \"authenticating && auth_ok && !abort\",\n \"consequent\": \"transferring\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_TRANSFER\",\n \"sva_name\": \"p_transfer\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"completed transfer enters closing\",\n \"antecedent\": \"transferring && transfer_done && !abort\",\n \"consequent\": \"closing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLOSE\",\n \"sva_name\": \"p_close\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful close completes the session\",\n \"antecedent\": \"closing && close_ok && !abort\",\n \"consequent\": \"done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_ABORT\",\n \"sva_name\": \"p_abort\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"abort from an active phase produces failure\",\n \"antecedent\": \"(opening || authenticating || transferring || closing) && abort\",\n \"consequent\": \"failed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_auth\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"AUTH\",\n \"old\": \"!abort && auth_ok\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_transfer_done\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"TRANSFER\",\n \"old\": \"!abort && transfer_done\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_close\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"CLOSE\",\n \"old\": \"!abort && close_ok\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: protocol_controller_0008\n\n// P1_ONEHOT: session phases are mutually exclusive.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({opening, authenticating, transferring, closing, done, failed}));\n\n// P2_RESET: reset begins in opening phase.\np_reset: assert property (@(posedge clk)\n (rst) |=> (opening));\n\n// P3_OPEN: successful open advances to authentication.\np_open: assert property (@(posedge clk) disable iff (rst)\n (opening && open_ok && !abort) |=> (authenticating));\n\n// P4_AUTH: successful authentication begins transfer.\np_auth: assert property (@(posedge clk) disable iff (rst)\n (authenticating && auth_ok && !abort) |=> (transferring));\n\n// P5_TRANSFER: completed transfer enters closing.\np_transfer: assert property (@(posedge clk) disable iff (rst)\n (transferring && transfer_done && !abort) |=> (closing));\n\n// P6_CLOSE: successful close completes the session.\np_close: assert property (@(posedge clk) disable iff (rst)\n (closing && close_ok && !abort) |=> (done));\n\n// P7_ABORT: abort from an active phase produces failure.\np_abort: assert property (@(posedge clk) disable iff (rst)\n ((opening || authenticating || transferring || closing) && abort) |=> (failed));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"session phases are mutually exclusive\",\n \"expression\": \"$onehot({opening, authenticating, transferring, closing, done, failed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset begins in opening phase\",\n \"antecedent\": \"rst\",\n \"consequent\": \"opening\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_OPEN\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful open advances to authentication\",\n \"antecedent\": \"opening && open_ok && !abort\",\n \"consequent\": \"authenticating\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_AUTH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful authentication begins transfer\",\n \"antecedent\": \"authenticating && auth_ok && !abort\",\n \"consequent\": \"transferring\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_TRANSFER\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"completed transfer enters closing\",\n \"antecedent\": \"transferring && transfer_done && !abort\",\n \"consequent\": \"closing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLOSE\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful close completes the session\",\n \"antecedent\": \"closing && close_ok && !abort\",\n \"consequent\": \"done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_ABORT\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"abort from an active phase produces failure\",\n \"antecedent\": \"(opening || authenticating || transferring || closing) && abort\",\n \"consequent\": \"failed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_auth.sv\": \"module protocol_controller_0008_mutant_ignore_auth (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && !auth_ok) ? AUTH : (AUTH));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_close.sv\": \"module protocol_controller_0008_mutant_ignore_close (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && !close_ok) ? CLOSE : (CLOSE));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_transfer_done.sv\": \"module protocol_controller_0008_mutant_ignore_transfer_done (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "protocol_controller_0008", "category": "protocol_controller", "description": "Session protocol opens, authenticates, transfers, closes, then signals completion.", "rtl_variant": "onehot_case.sv", "rtl": "module protocol_controller_0008_onehot_case (\n input wire clk,\n input wire rst,\n input wire open_ok,\n input wire auth_ok,\n input wire transfer_done,\n input wire close_ok,\n input wire abort,\n output reg opening,\n output reg authenticating,\n output reg transferring,\n output reg closing,\n output reg done,\n output reg failed\n);\n localparam [5:0] OPEN = 6'b000001;\n localparam [5:0] AUTH = 6'b000010;\n localparam [5:0] TRANSFER = 6'b000100;\n localparam [5:0] CLOSE = 6'b001000;\n localparam [5:0] DONE = 6'b010000;\n localparam [5:0] FAILED = 6'b100000;\n\n reg [5:0] state, next_state;\n\n always @* begin\n next_state = OPEN;\n case (state)\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\n DONE: next_state = OPEN;\n FAILED: next_state = OPEN;\n default: next_state = OPEN;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= OPEN;\n else\n state <= next_state;\n end\n\n always @* begin\n opening = (state == OPEN);\n authenticating = (state == AUTH);\n transferring = (state == TRANSFER);\n closing = (state == CLOSE);\n done = (state == DONE);\n failed = (state == FAILED);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"protocol_controller_0008\",\n \"category\": \"protocol_controller\",\n \"template\": \"open_auth_transfer_close\",\n \"description\": \"Session protocol opens, authenticates, transfers, closes, then signals completion.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"OPEN\"\n },\n \"inputs\": [\n \"open_ok\",\n \"auth_ok\",\n \"transfer_done\",\n \"close_ok\",\n \"abort\"\n ],\n \"outputs\": [\n \"opening\",\n \"authenticating\",\n \"transferring\",\n \"closing\",\n \"done\",\n \"failed\"\n ],\n \"states\": [\n \"OPEN\",\n \"AUTH\",\n \"TRANSFER\",\n \"CLOSE\",\n \"DONE\",\n \"FAILED\"\n ],\n \"state_outputs\": {\n \"OPEN\": {\n \"opening\": 1,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"AUTH\": {\n \"opening\": 0,\n \"authenticating\": 1,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"TRANSFER\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 1,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"CLOSE\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 1,\n \"done\": 0,\n \"failed\": 0\n },\n \"DONE\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 1,\n \"failed\": 0\n },\n \"FAILED\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"OPEN\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"!abort && open_ok\",\n \"to\": \"AUTH\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"!abort && !open_ok\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"!abort && auth_ok\",\n \"to\": \"TRANSFER\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"!abort && !auth_ok\",\n \"to\": \"AUTH\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"!abort && transfer_done\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"!abort && !transfer_done\",\n \"to\": \"TRANSFER\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!abort && close_ok\",\n \"to\": \"DONE\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!abort && !close_ok\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"DONE\",\n \"when\": \"true\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"FAILED\",\n \"when\": \"true\",\n \"to\": \"OPEN\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"session phases are mutually exclusive\",\n \"expression\": \"$onehot({opening, authenticating, transferring, closing, done, failed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset begins in opening phase\",\n \"antecedent\": \"rst\",\n \"consequent\": \"opening\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_OPEN\",\n \"sva_name\": \"p_open\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful open advances to authentication\",\n \"antecedent\": \"opening && open_ok && !abort\",\n \"consequent\": \"authenticating\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_AUTH\",\n \"sva_name\": \"p_auth\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful authentication begins transfer\",\n \"antecedent\": \"authenticating && auth_ok && !abort\",\n \"consequent\": \"transferring\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_TRANSFER\",\n \"sva_name\": \"p_transfer\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"completed transfer enters closing\",\n \"antecedent\": \"transferring && transfer_done && !abort\",\n \"consequent\": \"closing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLOSE\",\n \"sva_name\": \"p_close\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful close completes the session\",\n \"antecedent\": \"closing && close_ok && !abort\",\n \"consequent\": \"done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_ABORT\",\n \"sva_name\": \"p_abort\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"abort from an active phase produces failure\",\n \"antecedent\": \"(opening || authenticating || transferring || closing) && abort\",\n \"consequent\": \"failed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_auth\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"AUTH\",\n \"old\": \"!abort && auth_ok\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_transfer_done\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"TRANSFER\",\n \"old\": \"!abort && transfer_done\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_close\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"CLOSE\",\n \"old\": \"!abort && close_ok\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: protocol_controller_0008\n\n// P1_ONEHOT: session phases are mutually exclusive.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({opening, authenticating, transferring, closing, done, failed}));\n\n// P2_RESET: reset begins in opening phase.\np_reset: assert property (@(posedge clk)\n (rst) |=> (opening));\n\n// P3_OPEN: successful open advances to authentication.\np_open: assert property (@(posedge clk) disable iff (rst)\n (opening && open_ok && !abort) |=> (authenticating));\n\n// P4_AUTH: successful authentication begins transfer.\np_auth: assert property (@(posedge clk) disable iff (rst)\n (authenticating && auth_ok && !abort) |=> (transferring));\n\n// P5_TRANSFER: completed transfer enters closing.\np_transfer: assert property (@(posedge clk) disable iff (rst)\n (transferring && transfer_done && !abort) |=> (closing));\n\n// P6_CLOSE: successful close completes the session.\np_close: assert property (@(posedge clk) disable iff (rst)\n (closing && close_ok && !abort) |=> (done));\n\n// P7_ABORT: abort from an active phase produces failure.\np_abort: assert property (@(posedge clk) disable iff (rst)\n ((opening || authenticating || transferring || closing) && abort) |=> (failed));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"session phases are mutually exclusive\",\n \"expression\": \"$onehot({opening, authenticating, transferring, closing, done, failed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset begins in opening phase\",\n \"antecedent\": \"rst\",\n \"consequent\": \"opening\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_OPEN\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful open advances to authentication\",\n \"antecedent\": \"opening && open_ok && !abort\",\n \"consequent\": \"authenticating\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_AUTH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful authentication begins transfer\",\n \"antecedent\": \"authenticating && auth_ok && !abort\",\n \"consequent\": \"transferring\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_TRANSFER\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"completed transfer enters closing\",\n \"antecedent\": \"transferring && transfer_done && !abort\",\n \"consequent\": \"closing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLOSE\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful close completes the session\",\n \"antecedent\": \"closing && close_ok && !abort\",\n \"consequent\": \"done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_ABORT\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"abort from an active phase produces failure\",\n \"antecedent\": \"(opening || authenticating || transferring || closing) && abort\",\n \"consequent\": \"failed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_auth.sv\": \"module protocol_controller_0008_mutant_ignore_auth (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && !auth_ok) ? AUTH : (AUTH));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_close.sv\": \"module protocol_controller_0008_mutant_ignore_close (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && !close_ok) ? CLOSE : (CLOSE));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_transfer_done.sv\": \"module protocol_controller_0008_mutant_ignore_transfer_done (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "protocol_controller_0008", "category": "protocol_controller", "description": "Session protocol opens, authenticates, transfers, closes, then signals completion.", "rtl_variant": "nested_if.sv", "rtl": "module protocol_controller_0008_nested_if (\n input wire clk,\n input wire rst,\n input wire open_ok,\n input wire auth_ok,\n input wire transfer_done,\n input wire close_ok,\n input wire abort,\n output wire opening,\n output wire authenticating,\n output wire transferring,\n output wire closing,\n output wire done,\n output wire failed\n);\n localparam [2:0] S_OPEN = 3'd0;\n localparam [2:0] S_AUTH = 3'd1;\n localparam [2:0] S_TRANSFER = 3'd2;\n localparam [2:0] S_CLOSE = 3'd3;\n localparam [2:0] S_DONE = 3'd4;\n localparam [2:0] S_FAILED = 3'd5;\n\n reg [2:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_OPEN;\n end else begin\n if (state == S_OPEN) begin\n state <= (abort) ? S_FAILED : ((!abort && open_ok) ? S_AUTH : ((!abort && !open_ok) ? S_OPEN : (S_OPEN)));\n end\n else if (state == S_AUTH) begin\n state <= (abort) ? S_FAILED : ((!abort && auth_ok) ? S_TRANSFER : ((!abort && !auth_ok) ? S_AUTH : (S_AUTH)));\n end\n else if (state == S_TRANSFER) begin\n state <= (abort) ? S_FAILED : ((!abort && transfer_done) ? S_CLOSE : ((!abort && !transfer_done) ? S_TRANSFER : (S_TRANSFER)));\n end\n else if (state == S_CLOSE) begin\n state <= (abort) ? S_FAILED : ((!abort && close_ok) ? S_DONE : ((!abort && !close_ok) ? S_CLOSE : (S_CLOSE)));\n end\n else if (state == S_DONE) begin\n state <= S_OPEN;\n end\n else if (state == S_FAILED) begin\n state <= S_OPEN;\n end\n else begin\n state <= S_OPEN;\n end\n end\n end\n\n assign opening = (state == S_OPEN);\n assign authenticating = (state == S_AUTH);\n assign transferring = (state == S_TRANSFER);\n assign closing = (state == S_CLOSE);\n assign done = (state == S_DONE);\n assign failed = (state == S_FAILED);\nendmodule\n", "spec_json": "{\n \"design_id\": \"protocol_controller_0008\",\n \"category\": \"protocol_controller\",\n \"template\": \"open_auth_transfer_close\",\n \"description\": \"Session protocol opens, authenticates, transfers, closes, then signals completion.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"OPEN\"\n },\n \"inputs\": [\n \"open_ok\",\n \"auth_ok\",\n \"transfer_done\",\n \"close_ok\",\n \"abort\"\n ],\n \"outputs\": [\n \"opening\",\n \"authenticating\",\n \"transferring\",\n \"closing\",\n \"done\",\n \"failed\"\n ],\n \"states\": [\n \"OPEN\",\n \"AUTH\",\n \"TRANSFER\",\n \"CLOSE\",\n \"DONE\",\n \"FAILED\"\n ],\n \"state_outputs\": {\n \"OPEN\": {\n \"opening\": 1,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"AUTH\": {\n \"opening\": 0,\n \"authenticating\": 1,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"TRANSFER\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 1,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"CLOSE\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 1,\n \"done\": 0,\n \"failed\": 0\n },\n \"DONE\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 1,\n \"failed\": 0\n },\n \"FAILED\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"OPEN\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"!abort && open_ok\",\n \"to\": \"AUTH\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"!abort && !open_ok\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"!abort && auth_ok\",\n \"to\": \"TRANSFER\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"!abort && !auth_ok\",\n \"to\": \"AUTH\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"!abort && transfer_done\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"!abort && !transfer_done\",\n \"to\": \"TRANSFER\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!abort && close_ok\",\n \"to\": \"DONE\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!abort && !close_ok\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"DONE\",\n \"when\": \"true\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"FAILED\",\n \"when\": \"true\",\n \"to\": \"OPEN\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"session phases are mutually exclusive\",\n \"expression\": \"$onehot({opening, authenticating, transferring, closing, done, failed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset begins in opening phase\",\n \"antecedent\": \"rst\",\n \"consequent\": \"opening\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_OPEN\",\n \"sva_name\": \"p_open\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful open advances to authentication\",\n \"antecedent\": \"opening && open_ok && !abort\",\n \"consequent\": \"authenticating\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_AUTH\",\n \"sva_name\": \"p_auth\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful authentication begins transfer\",\n \"antecedent\": \"authenticating && auth_ok && !abort\",\n \"consequent\": \"transferring\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_TRANSFER\",\n \"sva_name\": \"p_transfer\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"completed transfer enters closing\",\n \"antecedent\": \"transferring && transfer_done && !abort\",\n \"consequent\": \"closing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLOSE\",\n \"sva_name\": \"p_close\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful close completes the session\",\n \"antecedent\": \"closing && close_ok && !abort\",\n \"consequent\": \"done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_ABORT\",\n \"sva_name\": \"p_abort\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"abort from an active phase produces failure\",\n \"antecedent\": \"(opening || authenticating || transferring || closing) && abort\",\n \"consequent\": \"failed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_auth\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"AUTH\",\n \"old\": \"!abort && auth_ok\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_transfer_done\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"TRANSFER\",\n \"old\": \"!abort && transfer_done\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_close\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"CLOSE\",\n \"old\": \"!abort && close_ok\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: protocol_controller_0008\n\n// P1_ONEHOT: session phases are mutually exclusive.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({opening, authenticating, transferring, closing, done, failed}));\n\n// P2_RESET: reset begins in opening phase.\np_reset: assert property (@(posedge clk)\n (rst) |=> (opening));\n\n// P3_OPEN: successful open advances to authentication.\np_open: assert property (@(posedge clk) disable iff (rst)\n (opening && open_ok && !abort) |=> (authenticating));\n\n// P4_AUTH: successful authentication begins transfer.\np_auth: assert property (@(posedge clk) disable iff (rst)\n (authenticating && auth_ok && !abort) |=> (transferring));\n\n// P5_TRANSFER: completed transfer enters closing.\np_transfer: assert property (@(posedge clk) disable iff (rst)\n (transferring && transfer_done && !abort) |=> (closing));\n\n// P6_CLOSE: successful close completes the session.\np_close: assert property (@(posedge clk) disable iff (rst)\n (closing && close_ok && !abort) |=> (done));\n\n// P7_ABORT: abort from an active phase produces failure.\np_abort: assert property (@(posedge clk) disable iff (rst)\n ((opening || authenticating || transferring || closing) && abort) |=> (failed));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"session phases are mutually exclusive\",\n \"expression\": \"$onehot({opening, authenticating, transferring, closing, done, failed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset begins in opening phase\",\n \"antecedent\": \"rst\",\n \"consequent\": \"opening\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_OPEN\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful open advances to authentication\",\n \"antecedent\": \"opening && open_ok && !abort\",\n \"consequent\": \"authenticating\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_AUTH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful authentication begins transfer\",\n \"antecedent\": \"authenticating && auth_ok && !abort\",\n \"consequent\": \"transferring\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_TRANSFER\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"completed transfer enters closing\",\n \"antecedent\": \"transferring && transfer_done && !abort\",\n \"consequent\": \"closing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLOSE\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful close completes the session\",\n \"antecedent\": \"closing && close_ok && !abort\",\n \"consequent\": \"done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_ABORT\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"abort from an active phase produces failure\",\n \"antecedent\": \"(opening || authenticating || transferring || closing) && abort\",\n \"consequent\": \"failed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_auth.sv\": \"module protocol_controller_0008_mutant_ignore_auth (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && !auth_ok) ? AUTH : (AUTH));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_close.sv\": \"module protocol_controller_0008_mutant_ignore_close (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && !close_ok) ? CLOSE : (CLOSE));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_transfer_done.sv\": \"module protocol_controller_0008_mutant_ignore_transfer_done (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "protocol_controller_0008", "category": "protocol_controller", "description": "Session protocol opens, authenticates, transfers, closes, then signals completion.", "rtl_variant": "factored_flags.sv", "rtl": "module protocol_controller_0008_factored_flags (\n input wire clk,\n input wire rst,\n input wire open_ok,\n input wire auth_ok,\n input wire transfer_done,\n input wire close_ok,\n input wire abort,\n output reg opening,\n output reg authenticating,\n output reg transferring,\n output reg closing,\n output reg done,\n output reg failed\n);\n localparam [2:0] F_OPEN = 3'd0;\n localparam [2:0] F_AUTH = 3'd1;\n localparam [2:0] F_TRANSFER = 3'd2;\n localparam [2:0] F_CLOSE = 3'd3;\n localparam [2:0] F_DONE = 3'd4;\n localparam [2:0] F_FAILED = 3'd5;\n\n reg [2:0] state, next_state;\n\n wire guard_open_0 = (abort);\n wire guard_open_1 = (!abort && open_ok);\n wire guard_open_2 = (!abort && !open_ok);\n wire guard_auth_0 = (abort);\n wire guard_auth_1 = (!abort && auth_ok);\n wire guard_auth_2 = (!abort && !auth_ok);\n wire guard_transfer_0 = (abort);\n wire guard_transfer_1 = (!abort && transfer_done);\n wire guard_transfer_2 = (!abort && !transfer_done);\n wire guard_close_0 = (abort);\n wire guard_close_1 = (!abort && close_ok);\n wire guard_close_2 = (!abort && !close_ok);\n\n always @* begin\n next_state = state;\n case (state)\n F_OPEN: begin\n if (guard_open_0)\n next_state = F_FAILED;\n else if (guard_open_1)\n next_state = F_AUTH;\n else if (guard_open_2)\n next_state = F_OPEN;\n end\n F_AUTH: begin\n if (guard_auth_0)\n next_state = F_FAILED;\n else if (guard_auth_1)\n next_state = F_TRANSFER;\n else if (guard_auth_2)\n next_state = F_AUTH;\n end\n F_TRANSFER: begin\n if (guard_transfer_0)\n next_state = F_FAILED;\n else if (guard_transfer_1)\n next_state = F_CLOSE;\n else if (guard_transfer_2)\n next_state = F_TRANSFER;\n end\n F_CLOSE: begin\n if (guard_close_0)\n next_state = F_FAILED;\n else if (guard_close_1)\n next_state = F_DONE;\n else if (guard_close_2)\n next_state = F_CLOSE;\n end\n F_DONE: begin\n next_state = F_OPEN;\n end\n F_FAILED: begin\n next_state = F_OPEN;\n end\n default: next_state = F_OPEN;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_OPEN;\n else\n state <= next_state;\n end\n\n always @* begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b0;\n case (state)\n F_OPEN: begin\n opening = 1'b1;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b0;\n end\n F_AUTH: begin\n opening = 1'b0;\n authenticating = 1'b1;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b0;\n end\n F_TRANSFER: begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b1;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b0;\n end\n F_CLOSE: begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b1;\n done = 1'b0;\n failed = 1'b0;\n end\n F_DONE: begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b1;\n failed = 1'b0;\n end\n F_FAILED: begin\n opening = 1'b0;\n authenticating = 1'b0;\n transferring = 1'b0;\n closing = 1'b0;\n done = 1'b0;\n failed = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"protocol_controller_0008\",\n \"category\": \"protocol_controller\",\n \"template\": \"open_auth_transfer_close\",\n \"description\": \"Session protocol opens, authenticates, transfers, closes, then signals completion.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"OPEN\"\n },\n \"inputs\": [\n \"open_ok\",\n \"auth_ok\",\n \"transfer_done\",\n \"close_ok\",\n \"abort\"\n ],\n \"outputs\": [\n \"opening\",\n \"authenticating\",\n \"transferring\",\n \"closing\",\n \"done\",\n \"failed\"\n ],\n \"states\": [\n \"OPEN\",\n \"AUTH\",\n \"TRANSFER\",\n \"CLOSE\",\n \"DONE\",\n \"FAILED\"\n ],\n \"state_outputs\": {\n \"OPEN\": {\n \"opening\": 1,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"AUTH\": {\n \"opening\": 0,\n \"authenticating\": 1,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"TRANSFER\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 1,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 0\n },\n \"CLOSE\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 1,\n \"done\": 0,\n \"failed\": 0\n },\n \"DONE\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 1,\n \"failed\": 0\n },\n \"FAILED\": {\n \"opening\": 0,\n \"authenticating\": 0,\n \"transferring\": 0,\n \"closing\": 0,\n \"done\": 0,\n \"failed\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"OPEN\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"!abort && open_ok\",\n \"to\": \"AUTH\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"!abort && !open_ok\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"!abort && auth_ok\",\n \"to\": \"TRANSFER\"\n },\n {\n \"from\": \"AUTH\",\n \"when\": \"!abort && !auth_ok\",\n \"to\": \"AUTH\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"!abort && transfer_done\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"TRANSFER\",\n \"when\": \"!abort && !transfer_done\",\n \"to\": \"TRANSFER\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"abort\",\n \"to\": \"FAILED\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!abort && close_ok\",\n \"to\": \"DONE\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!abort && !close_ok\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"DONE\",\n \"when\": \"true\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"FAILED\",\n \"when\": \"true\",\n \"to\": \"OPEN\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_ONEHOT\",\n \"sva_name\": \"p_onehot\",\n \"type\": \"invariant\",\n \"natural_language\": \"session phases are mutually exclusive\",\n \"expression\": \"$onehot({opening, authenticating, transferring, closing, done, failed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset begins in opening phase\",\n \"antecedent\": \"rst\",\n \"consequent\": \"opening\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_OPEN\",\n \"sva_name\": \"p_open\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful open advances to authentication\",\n \"antecedent\": \"opening && open_ok && !abort\",\n \"consequent\": \"authenticating\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_AUTH\",\n \"sva_name\": \"p_auth\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful authentication begins transfer\",\n \"antecedent\": \"authenticating && auth_ok && !abort\",\n \"consequent\": \"transferring\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_TRANSFER\",\n \"sva_name\": \"p_transfer\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"completed transfer enters closing\",\n \"antecedent\": \"transferring && transfer_done && !abort\",\n \"consequent\": \"closing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLOSE\",\n \"sva_name\": \"p_close\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful close completes the session\",\n \"antecedent\": \"closing && close_ok && !abort\",\n \"consequent\": \"done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_ABORT\",\n \"sva_name\": \"p_abort\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"abort from an active phase produces failure\",\n \"antecedent\": \"(opening || authenticating || transferring || closing) && abort\",\n \"consequent\": \"failed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_auth\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"AUTH\",\n \"old\": \"!abort && auth_ok\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_transfer_done\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"TRANSFER\",\n \"old\": \"!abort && transfer_done\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_close\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"CLOSE\",\n \"old\": \"!abort && close_ok\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: protocol_controller_0008\n\n// P1_ONEHOT: session phases are mutually exclusive.\np_onehot: assert property (@(posedge clk) disable iff (rst)\n $onehot({opening, authenticating, transferring, closing, done, failed}));\n\n// P2_RESET: reset begins in opening phase.\np_reset: assert property (@(posedge clk)\n (rst) |=> (opening));\n\n// P3_OPEN: successful open advances to authentication.\np_open: assert property (@(posedge clk) disable iff (rst)\n (opening && open_ok && !abort) |=> (authenticating));\n\n// P4_AUTH: successful authentication begins transfer.\np_auth: assert property (@(posedge clk) disable iff (rst)\n (authenticating && auth_ok && !abort) |=> (transferring));\n\n// P5_TRANSFER: completed transfer enters closing.\np_transfer: assert property (@(posedge clk) disable iff (rst)\n (transferring && transfer_done && !abort) |=> (closing));\n\n// P6_CLOSE: successful close completes the session.\np_close: assert property (@(posedge clk) disable iff (rst)\n (closing && close_ok && !abort) |=> (done));\n\n// P7_ABORT: abort from an active phase produces failure.\np_abort: assert property (@(posedge clk) disable iff (rst)\n ((opening || authenticating || transferring || closing) && abort) |=> (failed));\n", "properties_json": "[\n {\n \"id\": \"P1_ONEHOT\",\n \"type\": \"invariant\",\n \"natural_language\": \"session phases are mutually exclusive\",\n \"expression\": \"$onehot({opening, authenticating, transferring, closing, done, failed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset begins in opening phase\",\n \"antecedent\": \"rst\",\n \"consequent\": \"opening\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_OPEN\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful open advances to authentication\",\n \"antecedent\": \"opening && open_ok && !abort\",\n \"consequent\": \"authenticating\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_AUTH\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful authentication begins transfer\",\n \"antecedent\": \"authenticating && auth_ok && !abort\",\n \"consequent\": \"transferring\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_TRANSFER\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"completed transfer enters closing\",\n \"antecedent\": \"transferring && transfer_done && !abort\",\n \"consequent\": \"closing\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLOSE\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"successful close completes the session\",\n \"antecedent\": \"closing && close_ok && !abort\",\n \"consequent\": \"done\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_ABORT\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"abort from an active phase produces failure\",\n \"antecedent\": \"(opening || authenticating || transferring || closing) && abort\",\n \"consequent\": \"failed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_auth.sv\": \"module protocol_controller_0008_mutant_ignore_auth (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && !auth_ok) ? AUTH : (AUTH));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_close.sv\": \"module protocol_controller_0008_mutant_ignore_close (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && transfer_done) ? CLOSE : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER)));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && !close_ok) ? CLOSE : (CLOSE));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"ignore_transfer_done.sv\": \"module protocol_controller_0008_mutant_ignore_transfer_done (\\n input wire clk,\\n input wire rst,\\n input wire open_ok,\\n input wire auth_ok,\\n input wire transfer_done,\\n input wire close_ok,\\n input wire abort,\\n output reg opening,\\n output reg authenticating,\\n output reg transferring,\\n output reg closing,\\n output reg done,\\n output reg failed\\n);\\n localparam [2:0] OPEN = 3'd0;\\n localparam [2:0] AUTH = 3'd1;\\n localparam [2:0] TRANSFER = 3'd2;\\n localparam [2:0] CLOSE = 3'd3;\\n localparam [2:0] DONE = 3'd4;\\n localparam [2:0] FAILED = 3'd5;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n OPEN: next_state = (abort) ? FAILED : ((!abort && open_ok) ? AUTH : ((!abort && !open_ok) ? OPEN : (OPEN)));\\n AUTH: next_state = (abort) ? FAILED : ((!abort && auth_ok) ? TRANSFER : ((!abort && !auth_ok) ? AUTH : (AUTH)));\\n TRANSFER: next_state = (abort) ? FAILED : ((!abort && !transfer_done) ? TRANSFER : (TRANSFER));\\n CLOSE: next_state = (abort) ? FAILED : ((!abort && close_ok) ? DONE : ((!abort && !close_ok) ? CLOSE : (CLOSE)));\\n DONE: next_state = OPEN;\\n FAILED: next_state = OPEN;\\n default: next_state = OPEN;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= OPEN;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n case (state)\\n OPEN: begin\\n opening = 1'b1;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n AUTH: begin\\n opening = 1'b0;\\n authenticating = 1'b1;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n TRANSFER: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b1;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n CLOSE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b1;\\n done = 1'b0;\\n failed = 1'b0;\\n end\\n DONE: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b1;\\n failed = 1'b0;\\n end\\n FAILED: begin\\n opening = 1'b0;\\n authenticating = 1'b0;\\n transferring = 1'b0;\\n closing = 1'b0;\\n done = 1'b0;\\n failed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "protocol_controller_0009", "category": "protocol_controller", "description": "Protocol controller implementing open transfer close behavior.", "rtl_variant": "canonical_case.sv", "rtl": "module protocol_controller_0009_canonical_case (\n input wire clk,\n input wire rst,\n input wire open,\n input wire transfer_done,\n input wire close,\n output reg opened,\n output reg transferring,\n output reg closed\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] OPEN = 2'd1;\n localparam [1:0] XFER = 2'd2;\n localparam [1:0] CLOSE = 2'd3;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n IDLE: next_state = (open) ? OPEN : ((!open) ? IDLE : (IDLE));\n OPEN: next_state = XFER;\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n opened = 1'b0;\n transferring = 1'b0;\n closed = 1'b0;\n case (state)\n IDLE: begin\n opened = 1'b0;\n transferring = 1'b0;\n closed = 1'b0;\n end\n OPEN: begin\n opened = 1'b1;\n transferring = 1'b0;\n closed = 1'b0;\n end\n XFER: begin\n opened = 1'b0;\n transferring = 1'b1;\n closed = 1'b0;\n end\n CLOSE: begin\n opened = 1'b0;\n transferring = 1'b0;\n closed = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"protocol_controller_0009\",\n \"category\": \"protocol_controller\",\n \"template\": \"open_transfer_close\",\n \"description\": \"Protocol controller implementing open transfer close behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"open\",\n \"transfer_done\",\n \"close\"\n ],\n \"outputs\": [\n \"opened\",\n \"transferring\",\n \"closed\"\n ],\n \"states\": [\n \"IDLE\",\n \"OPEN\",\n \"XFER\",\n \"CLOSE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"opened\": 0,\n \"transferring\": 0,\n \"closed\": 0\n },\n \"OPEN\": {\n \"opened\": 1,\n \"transferring\": 0,\n \"closed\": 0\n },\n \"XFER\": {\n \"opened\": 0,\n \"transferring\": 1,\n \"closed\": 0\n },\n \"CLOSE\": {\n \"opened\": 0,\n \"transferring\": 0,\n \"closed\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"open\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!open\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"true\",\n \"to\": \"XFER\"\n },\n {\n \"from\": \"XFER\",\n \"when\": \"transfer_done\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"XFER\",\n \"when\": \"!transfer_done\",\n \"to\": \"XFER\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"close\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!close\",\n \"to\": \"CLOSE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({opened, transferring, closed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to OPEN when open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (open)\",\n \"consequent\": \"opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (!open)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OPEN transitions to XFER when true\",\n \"antecedent\": \"opened && !transferring && !closed\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to CLOSE when transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (transfer_done)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to XFER when !transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (!transfer_done)\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to IDLE when close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (close)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to CLOSE when !close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (!close)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"open\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"OPEN\"\n },\n {\n \"name\": \"drop_t4\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"XFER\",\n \"old\": \"transfer_done\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: protocol_controller_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({opened, transferring, closed}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!opened && !transferring && !closed));\n\n// P3_T1: IDLE transitions to OPEN when open.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && !closed) && (open)) |=> (opened && !transferring && !closed));\n\n// P4_T2: IDLE transitions to IDLE when !open.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && !closed) && (!open)) |=> (!opened && !transferring && !closed));\n\n// P5_T3: OPEN transitions to XFER when true.\np_t3: assert property (@(posedge clk) disable iff (rst)\n (opened && !transferring && !closed) |=> (!opened && transferring && !closed));\n\n// P6_T4: XFER transitions to CLOSE when transfer_done.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!opened && transferring && !closed) && (transfer_done)) |=> (!opened && !transferring && closed));\n\n// P7_T5: XFER transitions to XFER when !transfer_done.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!opened && transferring && !closed) && (!transfer_done)) |=> (!opened && transferring && !closed));\n\n// P8_T6: CLOSE transitions to IDLE when close.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && closed) && (close)) |=> (!opened && !transferring && !closed));\n\n// P9_T7: CLOSE transitions to CLOSE when !close.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && closed) && (!close)) |=> (!opened && !transferring && closed));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({opened, transferring, closed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to OPEN when open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (open)\",\n \"consequent\": \"opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (!open)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OPEN transitions to XFER when true\",\n \"antecedent\": \"opened && !transferring && !closed\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to CLOSE when transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (transfer_done)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to XFER when !transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (!transfer_done)\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to IDLE when close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (close)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to CLOSE when !close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (!close)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module protocol_controller_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!open) ? IDLE : (IDLE);\\n OPEN: next_state = XFER;\\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t4.sv\": \"module protocol_controller_0009_mutant_drop_t4 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (open) ? OPEN : ((!open) ? IDLE : (IDLE));\\n OPEN: next_state = XFER;\\n XFER: next_state = (!transfer_done) ? XFER : (XFER);\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module protocol_controller_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = OPEN;\\n OPEN: next_state = XFER;\\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "protocol_controller_0009", "category": "protocol_controller", "description": "Protocol controller implementing open transfer close behavior.", "rtl_variant": "onehot_case.sv", "rtl": "module protocol_controller_0009_onehot_case (\n input wire clk,\n input wire rst,\n input wire open,\n input wire transfer_done,\n input wire close,\n output reg opened,\n output reg transferring,\n output reg closed\n);\n localparam [3:0] IDLE = 4'b0001;\n localparam [3:0] OPEN = 4'b0010;\n localparam [3:0] XFER = 4'b0100;\n localparam [3:0] CLOSE = 4'b1000;\n\n reg [3:0] state, next_state;\n\n always @* begin\n next_state = IDLE;\n case (state)\n IDLE: next_state = (open) ? OPEN : ((!open) ? IDLE : (IDLE));\n OPEN: next_state = XFER;\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n opened = (state == OPEN);\n transferring = (state == XFER);\n closed = (state == CLOSE);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"protocol_controller_0009\",\n \"category\": \"protocol_controller\",\n \"template\": \"open_transfer_close\",\n \"description\": \"Protocol controller implementing open transfer close behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"open\",\n \"transfer_done\",\n \"close\"\n ],\n \"outputs\": [\n \"opened\",\n \"transferring\",\n \"closed\"\n ],\n \"states\": [\n \"IDLE\",\n \"OPEN\",\n \"XFER\",\n \"CLOSE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"opened\": 0,\n \"transferring\": 0,\n \"closed\": 0\n },\n \"OPEN\": {\n \"opened\": 1,\n \"transferring\": 0,\n \"closed\": 0\n },\n \"XFER\": {\n \"opened\": 0,\n \"transferring\": 1,\n \"closed\": 0\n },\n \"CLOSE\": {\n \"opened\": 0,\n \"transferring\": 0,\n \"closed\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"open\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!open\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"true\",\n \"to\": \"XFER\"\n },\n {\n \"from\": \"XFER\",\n \"when\": \"transfer_done\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"XFER\",\n \"when\": \"!transfer_done\",\n \"to\": \"XFER\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"close\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!close\",\n \"to\": \"CLOSE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({opened, transferring, closed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to OPEN when open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (open)\",\n \"consequent\": \"opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (!open)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OPEN transitions to XFER when true\",\n \"antecedent\": \"opened && !transferring && !closed\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to CLOSE when transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (transfer_done)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to XFER when !transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (!transfer_done)\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to IDLE when close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (close)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to CLOSE when !close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (!close)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"open\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"OPEN\"\n },\n {\n \"name\": \"drop_t4\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"XFER\",\n \"old\": \"transfer_done\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: protocol_controller_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({opened, transferring, closed}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!opened && !transferring && !closed));\n\n// P3_T1: IDLE transitions to OPEN when open.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && !closed) && (open)) |=> (opened && !transferring && !closed));\n\n// P4_T2: IDLE transitions to IDLE when !open.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && !closed) && (!open)) |=> (!opened && !transferring && !closed));\n\n// P5_T3: OPEN transitions to XFER when true.\np_t3: assert property (@(posedge clk) disable iff (rst)\n (opened && !transferring && !closed) |=> (!opened && transferring && !closed));\n\n// P6_T4: XFER transitions to CLOSE when transfer_done.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!opened && transferring && !closed) && (transfer_done)) |=> (!opened && !transferring && closed));\n\n// P7_T5: XFER transitions to XFER when !transfer_done.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!opened && transferring && !closed) && (!transfer_done)) |=> (!opened && transferring && !closed));\n\n// P8_T6: CLOSE transitions to IDLE when close.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && closed) && (close)) |=> (!opened && !transferring && !closed));\n\n// P9_T7: CLOSE transitions to CLOSE when !close.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && closed) && (!close)) |=> (!opened && !transferring && closed));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({opened, transferring, closed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to OPEN when open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (open)\",\n \"consequent\": \"opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (!open)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OPEN transitions to XFER when true\",\n \"antecedent\": \"opened && !transferring && !closed\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to CLOSE when transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (transfer_done)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to XFER when !transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (!transfer_done)\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to IDLE when close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (close)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to CLOSE when !close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (!close)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module protocol_controller_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!open) ? IDLE : (IDLE);\\n OPEN: next_state = XFER;\\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t4.sv\": \"module protocol_controller_0009_mutant_drop_t4 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (open) ? OPEN : ((!open) ? IDLE : (IDLE));\\n OPEN: next_state = XFER;\\n XFER: next_state = (!transfer_done) ? XFER : (XFER);\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module protocol_controller_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = OPEN;\\n OPEN: next_state = XFER;\\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "protocol_controller_0009", "category": "protocol_controller", "description": "Protocol controller implementing open transfer close behavior.", "rtl_variant": "nested_if.sv", "rtl": "module protocol_controller_0009_nested_if (\n input wire clk,\n input wire rst,\n input wire open,\n input wire transfer_done,\n input wire close,\n output wire opened,\n output wire transferring,\n output wire closed\n);\n localparam [1:0] S_IDLE = 2'd0;\n localparam [1:0] S_OPEN = 2'd1;\n localparam [1:0] S_XFER = 2'd2;\n localparam [1:0] S_CLOSE = 2'd3;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_IDLE;\n end else begin\n if (state == S_IDLE) begin\n state <= (open) ? S_OPEN : ((!open) ? S_IDLE : (S_IDLE));\n end\n else if (state == S_OPEN) begin\n state <= S_XFER;\n end\n else if (state == S_XFER) begin\n state <= (transfer_done) ? S_CLOSE : ((!transfer_done) ? S_XFER : (S_XFER));\n end\n else if (state == S_CLOSE) begin\n state <= (close) ? S_IDLE : ((!close) ? S_CLOSE : (S_CLOSE));\n end\n else begin\n state <= S_IDLE;\n end\n end\n end\n\n assign opened = (state == S_OPEN);\n assign transferring = (state == S_XFER);\n assign closed = (state == S_CLOSE);\nendmodule\n", "spec_json": "{\n \"design_id\": \"protocol_controller_0009\",\n \"category\": \"protocol_controller\",\n \"template\": \"open_transfer_close\",\n \"description\": \"Protocol controller implementing open transfer close behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"open\",\n \"transfer_done\",\n \"close\"\n ],\n \"outputs\": [\n \"opened\",\n \"transferring\",\n \"closed\"\n ],\n \"states\": [\n \"IDLE\",\n \"OPEN\",\n \"XFER\",\n \"CLOSE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"opened\": 0,\n \"transferring\": 0,\n \"closed\": 0\n },\n \"OPEN\": {\n \"opened\": 1,\n \"transferring\": 0,\n \"closed\": 0\n },\n \"XFER\": {\n \"opened\": 0,\n \"transferring\": 1,\n \"closed\": 0\n },\n \"CLOSE\": {\n \"opened\": 0,\n \"transferring\": 0,\n \"closed\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"open\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!open\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"true\",\n \"to\": \"XFER\"\n },\n {\n \"from\": \"XFER\",\n \"when\": \"transfer_done\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"XFER\",\n \"when\": \"!transfer_done\",\n \"to\": \"XFER\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"close\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!close\",\n \"to\": \"CLOSE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({opened, transferring, closed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to OPEN when open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (open)\",\n \"consequent\": \"opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (!open)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OPEN transitions to XFER when true\",\n \"antecedent\": \"opened && !transferring && !closed\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to CLOSE when transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (transfer_done)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to XFER when !transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (!transfer_done)\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to IDLE when close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (close)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to CLOSE when !close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (!close)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"open\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"OPEN\"\n },\n {\n \"name\": \"drop_t4\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"XFER\",\n \"old\": \"transfer_done\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: protocol_controller_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({opened, transferring, closed}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!opened && !transferring && !closed));\n\n// P3_T1: IDLE transitions to OPEN when open.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && !closed) && (open)) |=> (opened && !transferring && !closed));\n\n// P4_T2: IDLE transitions to IDLE when !open.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && !closed) && (!open)) |=> (!opened && !transferring && !closed));\n\n// P5_T3: OPEN transitions to XFER when true.\np_t3: assert property (@(posedge clk) disable iff (rst)\n (opened && !transferring && !closed) |=> (!opened && transferring && !closed));\n\n// P6_T4: XFER transitions to CLOSE when transfer_done.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!opened && transferring && !closed) && (transfer_done)) |=> (!opened && !transferring && closed));\n\n// P7_T5: XFER transitions to XFER when !transfer_done.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!opened && transferring && !closed) && (!transfer_done)) |=> (!opened && transferring && !closed));\n\n// P8_T6: CLOSE transitions to IDLE when close.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && closed) && (close)) |=> (!opened && !transferring && !closed));\n\n// P9_T7: CLOSE transitions to CLOSE when !close.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && closed) && (!close)) |=> (!opened && !transferring && closed));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({opened, transferring, closed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to OPEN when open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (open)\",\n \"consequent\": \"opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (!open)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OPEN transitions to XFER when true\",\n \"antecedent\": \"opened && !transferring && !closed\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to CLOSE when transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (transfer_done)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to XFER when !transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (!transfer_done)\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to IDLE when close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (close)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to CLOSE when !close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (!close)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module protocol_controller_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!open) ? IDLE : (IDLE);\\n OPEN: next_state = XFER;\\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t4.sv\": \"module protocol_controller_0009_mutant_drop_t4 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (open) ? OPEN : ((!open) ? IDLE : (IDLE));\\n OPEN: next_state = XFER;\\n XFER: next_state = (!transfer_done) ? XFER : (XFER);\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module protocol_controller_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = OPEN;\\n OPEN: next_state = XFER;\\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "protocol_controller_0009", "category": "protocol_controller", "description": "Protocol controller implementing open transfer close behavior.", "rtl_variant": "factored_flags.sv", "rtl": "module protocol_controller_0009_factored_flags (\n input wire clk,\n input wire rst,\n input wire open,\n input wire transfer_done,\n input wire close,\n output reg opened,\n output reg transferring,\n output reg closed\n);\n localparam [1:0] F_IDLE = 2'd0;\n localparam [1:0] F_OPEN = 2'd1;\n localparam [1:0] F_XFER = 2'd2;\n localparam [1:0] F_CLOSE = 2'd3;\n\n reg [1:0] state, next_state;\n\n wire guard_idle_0 = (open);\n wire guard_idle_1 = (!open);\n wire guard_xfer_0 = (transfer_done);\n wire guard_xfer_1 = (!transfer_done);\n wire guard_close_0 = (close);\n wire guard_close_1 = (!close);\n\n always @* begin\n next_state = state;\n case (state)\n F_IDLE: begin\n if (guard_idle_0)\n next_state = F_OPEN;\n else if (guard_idle_1)\n next_state = F_IDLE;\n end\n F_OPEN: begin\n next_state = F_XFER;\n end\n F_XFER: begin\n if (guard_xfer_0)\n next_state = F_CLOSE;\n else if (guard_xfer_1)\n next_state = F_XFER;\n end\n F_CLOSE: begin\n if (guard_close_0)\n next_state = F_IDLE;\n else if (guard_close_1)\n next_state = F_CLOSE;\n end\n default: next_state = F_IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n opened = 1'b0;\n transferring = 1'b0;\n closed = 1'b0;\n case (state)\n F_IDLE: begin\n opened = 1'b0;\n transferring = 1'b0;\n closed = 1'b0;\n end\n F_OPEN: begin\n opened = 1'b1;\n transferring = 1'b0;\n closed = 1'b0;\n end\n F_XFER: begin\n opened = 1'b0;\n transferring = 1'b1;\n closed = 1'b0;\n end\n F_CLOSE: begin\n opened = 1'b0;\n transferring = 1'b0;\n closed = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"protocol_controller_0009\",\n \"category\": \"protocol_controller\",\n \"template\": \"open_transfer_close\",\n \"description\": \"Protocol controller implementing open transfer close behavior.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"open\",\n \"transfer_done\",\n \"close\"\n ],\n \"outputs\": [\n \"opened\",\n \"transferring\",\n \"closed\"\n ],\n \"states\": [\n \"IDLE\",\n \"OPEN\",\n \"XFER\",\n \"CLOSE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"opened\": 0,\n \"transferring\": 0,\n \"closed\": 0\n },\n \"OPEN\": {\n \"opened\": 1,\n \"transferring\": 0,\n \"closed\": 0\n },\n \"XFER\": {\n \"opened\": 0,\n \"transferring\": 1,\n \"closed\": 0\n },\n \"CLOSE\": {\n \"opened\": 0,\n \"transferring\": 0,\n \"closed\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"open\",\n \"to\": \"OPEN\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!open\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"OPEN\",\n \"when\": \"true\",\n \"to\": \"XFER\"\n },\n {\n \"from\": \"XFER\",\n \"when\": \"transfer_done\",\n \"to\": \"CLOSE\"\n },\n {\n \"from\": \"XFER\",\n \"when\": \"!transfer_done\",\n \"to\": \"XFER\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"close\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"CLOSE\",\n \"when\": \"!close\",\n \"to\": \"CLOSE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({opened, transferring, closed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to OPEN when open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (open)\",\n \"consequent\": \"opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (!open)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OPEN transitions to XFER when true\",\n \"antecedent\": \"opened && !transferring && !closed\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to CLOSE when transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (transfer_done)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to XFER when !transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (!transfer_done)\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to IDLE when close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (close)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to CLOSE when !close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (!close)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"open\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"OPEN\"\n },\n {\n \"name\": \"drop_t4\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"XFER\",\n \"old\": \"transfer_done\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: protocol_controller_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({opened, transferring, closed}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!opened && !transferring && !closed));\n\n// P3_T1: IDLE transitions to OPEN when open.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && !closed) && (open)) |=> (opened && !transferring && !closed));\n\n// P4_T2: IDLE transitions to IDLE when !open.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && !closed) && (!open)) |=> (!opened && !transferring && !closed));\n\n// P5_T3: OPEN transitions to XFER when true.\np_t3: assert property (@(posedge clk) disable iff (rst)\n (opened && !transferring && !closed) |=> (!opened && transferring && !closed));\n\n// P6_T4: XFER transitions to CLOSE when transfer_done.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((!opened && transferring && !closed) && (transfer_done)) |=> (!opened && !transferring && closed));\n\n// P7_T5: XFER transitions to XFER when !transfer_done.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!opened && transferring && !closed) && (!transfer_done)) |=> (!opened && transferring && !closed));\n\n// P8_T6: CLOSE transitions to IDLE when close.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && closed) && (close)) |=> (!opened && !transferring && !closed));\n\n// P9_T7: CLOSE transitions to CLOSE when !close.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!opened && !transferring && closed) && (!close)) |=> (!opened && !transferring && closed));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({opened, transferring, closed})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to OPEN when open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (open)\",\n \"consequent\": \"opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !open\",\n \"antecedent\": \"(!opened && !transferring && !closed) && (!open)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"OPEN transitions to XFER when true\",\n \"antecedent\": \"opened && !transferring && !closed\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to CLOSE when transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (transfer_done)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"XFER transitions to XFER when !transfer_done\",\n \"antecedent\": \"(!opened && transferring && !closed) && (!transfer_done)\",\n \"consequent\": \"!opened && transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to IDLE when close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (close)\",\n \"consequent\": \"!opened && !transferring && !closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CLOSE transitions to CLOSE when !close\",\n \"antecedent\": \"(!opened && !transferring && closed) && (!close)\",\n \"consequent\": \"!opened && !transferring && closed\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module protocol_controller_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!open) ? IDLE : (IDLE);\\n OPEN: next_state = XFER;\\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t4.sv\": \"module protocol_controller_0009_mutant_drop_t4 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (open) ? OPEN : ((!open) ? IDLE : (IDLE));\\n OPEN: next_state = XFER;\\n XFER: next_state = (!transfer_done) ? XFER : (XFER);\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module protocol_controller_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire open,\\n input wire transfer_done,\\n input wire close,\\n output reg opened,\\n output reg transferring,\\n output reg closed\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] OPEN = 2'd1;\\n localparam [1:0] XFER = 2'd2;\\n localparam [1:0] CLOSE = 2'd3;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = OPEN;\\n OPEN: next_state = XFER;\\n XFER: next_state = (transfer_done) ? CLOSE : ((!transfer_done) ? XFER : (XFER));\\n CLOSE: next_state = (close) ? IDLE : ((!close) ? CLOSE : (CLOSE));\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n case (state)\\n IDLE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n OPEN: begin\\n opened = 1'b1;\\n transferring = 1'b0;\\n closed = 1'b0;\\n end\\n XFER: begin\\n opened = 1'b0;\\n transferring = 1'b1;\\n closed = 1'b0;\\n end\\n CLOSE: begin\\n opened = 1'b0;\\n transferring = 1'b0;\\n closed = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "pulse_event_0006", "category": "pulse_event", "description": "Pulse/event controller implementing cancelable pulse semantics.", "rtl_variant": "canonical_case.sv", "rtl": "module pulse_event_0006_canonical_case (\n input wire clk,\n input wire rst,\n input wire trigger,\n input wire cancel,\n output reg armed,\n output reg pulse,\n output reg cancelled\n);\n localparam [1:0] ARMED = 2'd0;\n localparam [1:0] PULSE = 2'd1;\n localparam [1:0] CANCEL = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n ARMED: next_state = (trigger && !cancel) ? PULSE : ((cancel) ? CANCEL : ((!trigger && !cancel) ? ARMED : (ARMED)));\n PULSE: next_state = ARMED;\n CANCEL: next_state = ARMED;\n default: next_state = ARMED;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= ARMED;\n else\n state <= next_state;\n end\n\n always @* begin\n armed = 1'b0;\n pulse = 1'b0;\n cancelled = 1'b0;\n case (state)\n ARMED: begin\n armed = 1'b1;\n pulse = 1'b0;\n cancelled = 1'b0;\n end\n PULSE: begin\n armed = 1'b0;\n pulse = 1'b1;\n cancelled = 1'b0;\n end\n CANCEL: begin\n armed = 1'b0;\n pulse = 1'b0;\n cancelled = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"pulse_event_0006\",\n \"category\": \"pulse_event\",\n \"template\": \"cancelable_pulse\",\n \"description\": \"Pulse/event controller implementing cancelable pulse semantics.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"ARMED\"\n },\n \"inputs\": [\n \"trigger\",\n \"cancel\"\n ],\n \"outputs\": [\n \"armed\",\n \"pulse\",\n \"cancelled\"\n ],\n \"states\": [\n \"ARMED\",\n \"PULSE\",\n \"CANCEL\"\n ],\n \"state_outputs\": {\n \"ARMED\": {\n \"armed\": 1,\n \"pulse\": 0,\n \"cancelled\": 0\n },\n \"PULSE\": {\n \"armed\": 0,\n \"pulse\": 1,\n \"cancelled\": 0\n },\n \"CANCEL\": {\n \"armed\": 0,\n \"pulse\": 0,\n \"cancelled\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"ARMED\",\n \"when\": \"trigger && !cancel\",\n \"to\": \"PULSE\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"cancel\",\n \"to\": \"CANCEL\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"!trigger && !cancel\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"PULSE\",\n \"when\": \"true\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"CANCEL\",\n \"when\": \"true\",\n \"to\": \"ARMED\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({armed, pulse, cancelled})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to PULSE when trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (trigger && !cancel)\",\n \"consequent\": \"!armed && pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to CANCEL when cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (cancel)\",\n \"consequent\": \"!armed && !pulse && cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to ARMED when !trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (!trigger && !cancel)\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to ARMED when true\",\n \"antecedent\": \"!armed && pulse && !cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CANCEL transitions to ARMED when true\",\n \"antecedent\": \"!armed && !pulse && cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"trigger && !cancel\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"cancel\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"ARMED\",\n \"to\": \"PULSE\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: pulse_event_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({armed, pulse, cancelled}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (armed && !pulse && !cancelled));\n\n// P3_T1: ARMED transitions to PULSE when trigger && !cancel.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (trigger && !cancel)) |=> (!armed && pulse && !cancelled));\n\n// P4_T2: ARMED transitions to CANCEL when cancel.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (cancel)) |=> (!armed && !pulse && cancelled));\n\n// P5_T3: ARMED transitions to ARMED when !trigger && !cancel.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (!trigger && !cancel)) |=> (armed && !pulse && !cancelled));\n\n// P6_T4: PULSE transitions to ARMED when true.\np_t4: assert property (@(posedge clk) disable iff (rst)\n (!armed && pulse && !cancelled) |=> (armed && !pulse && !cancelled));\n\n// P7_T5: CANCEL transitions to ARMED when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!armed && !pulse && cancelled) |=> (armed && !pulse && !cancelled));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({armed, pulse, cancelled})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to PULSE when trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (trigger && !cancel)\",\n \"consequent\": \"!armed && pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to CANCEL when cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (cancel)\",\n \"consequent\": \"!armed && !pulse && cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to ARMED when !trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (!trigger && !cancel)\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to ARMED when true\",\n \"antecedent\": \"!armed && pulse && !cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CANCEL transitions to ARMED when true\",\n \"antecedent\": \"!armed && !pulse && cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module pulse_event_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (cancel) ? CANCEL : ((!trigger && !cancel) ? ARMED : (ARMED));\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module pulse_event_0006_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (trigger && !cancel) ? PULSE : ((!trigger && !cancel) ? ARMED : (ARMED));\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module pulse_event_0006_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = PULSE;\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "pulse_event_0006", "category": "pulse_event", "description": "Pulse/event controller implementing cancelable pulse semantics.", "rtl_variant": "onehot_case.sv", "rtl": "module pulse_event_0006_onehot_case (\n input wire clk,\n input wire rst,\n input wire trigger,\n input wire cancel,\n output reg armed,\n output reg pulse,\n output reg cancelled\n);\n localparam [2:0] ARMED = 3'b001;\n localparam [2:0] PULSE = 3'b010;\n localparam [2:0] CANCEL = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = ARMED;\n case (state)\n ARMED: next_state = (trigger && !cancel) ? PULSE : ((cancel) ? CANCEL : ((!trigger && !cancel) ? ARMED : (ARMED)));\n PULSE: next_state = ARMED;\n CANCEL: next_state = ARMED;\n default: next_state = ARMED;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= ARMED;\n else\n state <= next_state;\n end\n\n always @* begin\n armed = (state == ARMED);\n pulse = (state == PULSE);\n cancelled = (state == CANCEL);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"pulse_event_0006\",\n \"category\": \"pulse_event\",\n \"template\": \"cancelable_pulse\",\n \"description\": \"Pulse/event controller implementing cancelable pulse semantics.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"ARMED\"\n },\n \"inputs\": [\n \"trigger\",\n \"cancel\"\n ],\n \"outputs\": [\n \"armed\",\n \"pulse\",\n \"cancelled\"\n ],\n \"states\": [\n \"ARMED\",\n \"PULSE\",\n \"CANCEL\"\n ],\n \"state_outputs\": {\n \"ARMED\": {\n \"armed\": 1,\n \"pulse\": 0,\n \"cancelled\": 0\n },\n \"PULSE\": {\n \"armed\": 0,\n \"pulse\": 1,\n \"cancelled\": 0\n },\n \"CANCEL\": {\n \"armed\": 0,\n \"pulse\": 0,\n \"cancelled\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"ARMED\",\n \"when\": \"trigger && !cancel\",\n \"to\": \"PULSE\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"cancel\",\n \"to\": \"CANCEL\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"!trigger && !cancel\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"PULSE\",\n \"when\": \"true\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"CANCEL\",\n \"when\": \"true\",\n \"to\": \"ARMED\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({armed, pulse, cancelled})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to PULSE when trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (trigger && !cancel)\",\n \"consequent\": \"!armed && pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to CANCEL when cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (cancel)\",\n \"consequent\": \"!armed && !pulse && cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to ARMED when !trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (!trigger && !cancel)\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to ARMED when true\",\n \"antecedent\": \"!armed && pulse && !cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CANCEL transitions to ARMED when true\",\n \"antecedent\": \"!armed && !pulse && cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"trigger && !cancel\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"cancel\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"ARMED\",\n \"to\": \"PULSE\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: pulse_event_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({armed, pulse, cancelled}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (armed && !pulse && !cancelled));\n\n// P3_T1: ARMED transitions to PULSE when trigger && !cancel.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (trigger && !cancel)) |=> (!armed && pulse && !cancelled));\n\n// P4_T2: ARMED transitions to CANCEL when cancel.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (cancel)) |=> (!armed && !pulse && cancelled));\n\n// P5_T3: ARMED transitions to ARMED when !trigger && !cancel.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (!trigger && !cancel)) |=> (armed && !pulse && !cancelled));\n\n// P6_T4: PULSE transitions to ARMED when true.\np_t4: assert property (@(posedge clk) disable iff (rst)\n (!armed && pulse && !cancelled) |=> (armed && !pulse && !cancelled));\n\n// P7_T5: CANCEL transitions to ARMED when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!armed && !pulse && cancelled) |=> (armed && !pulse && !cancelled));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({armed, pulse, cancelled})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to PULSE when trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (trigger && !cancel)\",\n \"consequent\": \"!armed && pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to CANCEL when cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (cancel)\",\n \"consequent\": \"!armed && !pulse && cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to ARMED when !trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (!trigger && !cancel)\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to ARMED when true\",\n \"antecedent\": \"!armed && pulse && !cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CANCEL transitions to ARMED when true\",\n \"antecedent\": \"!armed && !pulse && cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module pulse_event_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (cancel) ? CANCEL : ((!trigger && !cancel) ? ARMED : (ARMED));\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module pulse_event_0006_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (trigger && !cancel) ? PULSE : ((!trigger && !cancel) ? ARMED : (ARMED));\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module pulse_event_0006_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = PULSE;\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "pulse_event_0006", "category": "pulse_event", "description": "Pulse/event controller implementing cancelable pulse semantics.", "rtl_variant": "nested_if.sv", "rtl": "module pulse_event_0006_nested_if (\n input wire clk,\n input wire rst,\n input wire trigger,\n input wire cancel,\n output wire armed,\n output wire pulse,\n output wire cancelled\n);\n localparam [1:0] S_ARMED = 2'd0;\n localparam [1:0] S_PULSE = 2'd1;\n localparam [1:0] S_CANCEL = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_ARMED;\n end else begin\n if (state == S_ARMED) begin\n state <= (trigger && !cancel) ? S_PULSE : ((cancel) ? S_CANCEL : ((!trigger && !cancel) ? S_ARMED : (S_ARMED)));\n end\n else if (state == S_PULSE) begin\n state <= S_ARMED;\n end\n else if (state == S_CANCEL) begin\n state <= S_ARMED;\n end\n else begin\n state <= S_ARMED;\n end\n end\n end\n\n assign armed = (state == S_ARMED);\n assign pulse = (state == S_PULSE);\n assign cancelled = (state == S_CANCEL);\nendmodule\n", "spec_json": "{\n \"design_id\": \"pulse_event_0006\",\n \"category\": \"pulse_event\",\n \"template\": \"cancelable_pulse\",\n \"description\": \"Pulse/event controller implementing cancelable pulse semantics.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"ARMED\"\n },\n \"inputs\": [\n \"trigger\",\n \"cancel\"\n ],\n \"outputs\": [\n \"armed\",\n \"pulse\",\n \"cancelled\"\n ],\n \"states\": [\n \"ARMED\",\n \"PULSE\",\n \"CANCEL\"\n ],\n \"state_outputs\": {\n \"ARMED\": {\n \"armed\": 1,\n \"pulse\": 0,\n \"cancelled\": 0\n },\n \"PULSE\": {\n \"armed\": 0,\n \"pulse\": 1,\n \"cancelled\": 0\n },\n \"CANCEL\": {\n \"armed\": 0,\n \"pulse\": 0,\n \"cancelled\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"ARMED\",\n \"when\": \"trigger && !cancel\",\n \"to\": \"PULSE\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"cancel\",\n \"to\": \"CANCEL\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"!trigger && !cancel\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"PULSE\",\n \"when\": \"true\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"CANCEL\",\n \"when\": \"true\",\n \"to\": \"ARMED\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({armed, pulse, cancelled})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to PULSE when trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (trigger && !cancel)\",\n \"consequent\": \"!armed && pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to CANCEL when cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (cancel)\",\n \"consequent\": \"!armed && !pulse && cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to ARMED when !trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (!trigger && !cancel)\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to ARMED when true\",\n \"antecedent\": \"!armed && pulse && !cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CANCEL transitions to ARMED when true\",\n \"antecedent\": \"!armed && !pulse && cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"trigger && !cancel\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"cancel\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"ARMED\",\n \"to\": \"PULSE\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: pulse_event_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({armed, pulse, cancelled}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (armed && !pulse && !cancelled));\n\n// P3_T1: ARMED transitions to PULSE when trigger && !cancel.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (trigger && !cancel)) |=> (!armed && pulse && !cancelled));\n\n// P4_T2: ARMED transitions to CANCEL when cancel.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (cancel)) |=> (!armed && !pulse && cancelled));\n\n// P5_T3: ARMED transitions to ARMED when !trigger && !cancel.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (!trigger && !cancel)) |=> (armed && !pulse && !cancelled));\n\n// P6_T4: PULSE transitions to ARMED when true.\np_t4: assert property (@(posedge clk) disable iff (rst)\n (!armed && pulse && !cancelled) |=> (armed && !pulse && !cancelled));\n\n// P7_T5: CANCEL transitions to ARMED when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!armed && !pulse && cancelled) |=> (armed && !pulse && !cancelled));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({armed, pulse, cancelled})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to PULSE when trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (trigger && !cancel)\",\n \"consequent\": \"!armed && pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to CANCEL when cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (cancel)\",\n \"consequent\": \"!armed && !pulse && cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to ARMED when !trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (!trigger && !cancel)\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to ARMED when true\",\n \"antecedent\": \"!armed && pulse && !cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CANCEL transitions to ARMED when true\",\n \"antecedent\": \"!armed && !pulse && cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module pulse_event_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (cancel) ? CANCEL : ((!trigger && !cancel) ? ARMED : (ARMED));\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module pulse_event_0006_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (trigger && !cancel) ? PULSE : ((!trigger && !cancel) ? ARMED : (ARMED));\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module pulse_event_0006_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = PULSE;\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "pulse_event_0006", "category": "pulse_event", "description": "Pulse/event controller implementing cancelable pulse semantics.", "rtl_variant": "factored_flags.sv", "rtl": "module pulse_event_0006_factored_flags (\n input wire clk,\n input wire rst,\n input wire trigger,\n input wire cancel,\n output reg armed,\n output reg pulse,\n output reg cancelled\n);\n localparam [1:0] F_ARMED = 2'd0;\n localparam [1:0] F_PULSE = 2'd1;\n localparam [1:0] F_CANCEL = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_armed_0 = (trigger && !cancel);\n wire guard_armed_1 = (cancel);\n wire guard_armed_2 = (!trigger && !cancel);\n\n always @* begin\n next_state = state;\n case (state)\n F_ARMED: begin\n if (guard_armed_0)\n next_state = F_PULSE;\n else if (guard_armed_1)\n next_state = F_CANCEL;\n else if (guard_armed_2)\n next_state = F_ARMED;\n end\n F_PULSE: begin\n next_state = F_ARMED;\n end\n F_CANCEL: begin\n next_state = F_ARMED;\n end\n default: next_state = F_ARMED;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_ARMED;\n else\n state <= next_state;\n end\n\n always @* begin\n armed = 1'b0;\n pulse = 1'b0;\n cancelled = 1'b0;\n case (state)\n F_ARMED: begin\n armed = 1'b1;\n pulse = 1'b0;\n cancelled = 1'b0;\n end\n F_PULSE: begin\n armed = 1'b0;\n pulse = 1'b1;\n cancelled = 1'b0;\n end\n F_CANCEL: begin\n armed = 1'b0;\n pulse = 1'b0;\n cancelled = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"pulse_event_0006\",\n \"category\": \"pulse_event\",\n \"template\": \"cancelable_pulse\",\n \"description\": \"Pulse/event controller implementing cancelable pulse semantics.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"ARMED\"\n },\n \"inputs\": [\n \"trigger\",\n \"cancel\"\n ],\n \"outputs\": [\n \"armed\",\n \"pulse\",\n \"cancelled\"\n ],\n \"states\": [\n \"ARMED\",\n \"PULSE\",\n \"CANCEL\"\n ],\n \"state_outputs\": {\n \"ARMED\": {\n \"armed\": 1,\n \"pulse\": 0,\n \"cancelled\": 0\n },\n \"PULSE\": {\n \"armed\": 0,\n \"pulse\": 1,\n \"cancelled\": 0\n },\n \"CANCEL\": {\n \"armed\": 0,\n \"pulse\": 0,\n \"cancelled\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"ARMED\",\n \"when\": \"trigger && !cancel\",\n \"to\": \"PULSE\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"cancel\",\n \"to\": \"CANCEL\"\n },\n {\n \"from\": \"ARMED\",\n \"when\": \"!trigger && !cancel\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"PULSE\",\n \"when\": \"true\",\n \"to\": \"ARMED\"\n },\n {\n \"from\": \"CANCEL\",\n \"when\": \"true\",\n \"to\": \"ARMED\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({armed, pulse, cancelled})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to PULSE when trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (trigger && !cancel)\",\n \"consequent\": \"!armed && pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to CANCEL when cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (cancel)\",\n \"consequent\": \"!armed && !pulse && cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to ARMED when !trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (!trigger && !cancel)\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to ARMED when true\",\n \"antecedent\": \"!armed && pulse && !cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CANCEL transitions to ARMED when true\",\n \"antecedent\": \"!armed && !pulse && cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"trigger && !cancel\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"ARMED\",\n \"old\": \"cancel\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"ARMED\",\n \"to\": \"PULSE\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: pulse_event_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({armed, pulse, cancelled}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (armed && !pulse && !cancelled));\n\n// P3_T1: ARMED transitions to PULSE when trigger && !cancel.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (trigger && !cancel)) |=> (!armed && pulse && !cancelled));\n\n// P4_T2: ARMED transitions to CANCEL when cancel.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (cancel)) |=> (!armed && !pulse && cancelled));\n\n// P5_T3: ARMED transitions to ARMED when !trigger && !cancel.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((armed && !pulse && !cancelled) && (!trigger && !cancel)) |=> (armed && !pulse && !cancelled));\n\n// P6_T4: PULSE transitions to ARMED when true.\np_t4: assert property (@(posedge clk) disable iff (rst)\n (!armed && pulse && !cancelled) |=> (armed && !pulse && !cancelled));\n\n// P7_T5: CANCEL transitions to ARMED when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!armed && !pulse && cancelled) |=> (armed && !pulse && !cancelled));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({armed, pulse, cancelled})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to PULSE when trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (trigger && !cancel)\",\n \"consequent\": \"!armed && pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to CANCEL when cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (cancel)\",\n \"consequent\": \"!armed && !pulse && cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"ARMED transitions to ARMED when !trigger && !cancel\",\n \"antecedent\": \"(armed && !pulse && !cancelled) && (!trigger && !cancel)\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to ARMED when true\",\n \"antecedent\": \"!armed && pulse && !cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"CANCEL transitions to ARMED when true\",\n \"antecedent\": \"!armed && !pulse && cancelled\",\n \"consequent\": \"armed && !pulse && !cancelled\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module pulse_event_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (cancel) ? CANCEL : ((!trigger && !cancel) ? ARMED : (ARMED));\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t2.sv\": \"module pulse_event_0006_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = (trigger && !cancel) ? PULSE : ((!trigger && !cancel) ? ARMED : (ARMED));\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module pulse_event_0006_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire trigger,\\n input wire cancel,\\n output reg armed,\\n output reg pulse,\\n output reg cancelled\\n);\\n localparam [1:0] ARMED = 2'd0;\\n localparam [1:0] PULSE = 2'd1;\\n localparam [1:0] CANCEL = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n ARMED: next_state = PULSE;\\n PULSE: next_state = ARMED;\\n CANCEL: next_state = ARMED;\\n default: next_state = ARMED;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= ARMED;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n case (state)\\n ARMED: begin\\n armed = 1'b1;\\n pulse = 1'b0;\\n cancelled = 1'b0;\\n end\\n PULSE: begin\\n armed = 1'b0;\\n pulse = 1'b1;\\n cancelled = 1'b0;\\n end\\n CANCEL: begin\\n armed = 1'b0;\\n pulse = 1'b0;\\n cancelled = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "pulse_event_0009", "category": "pulse_event", "description": "Pulse/event controller implementing request complete pulse semantics.", "rtl_variant": "canonical_case.sv", "rtl": "module pulse_event_0009_canonical_case (\n input wire clk,\n input wire rst,\n input wire request,\n input wire complete,\n output reg waiting,\n output reg pulse,\n output reg idle\n);\n localparam [1:0] IDLE = 2'd0;\n localparam [1:0] WAIT = 2'd1;\n localparam [1:0] PULSE = 2'd2;\n\n reg [1:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n IDLE: next_state = (request) ? WAIT : ((!request) ? IDLE : (IDLE));\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\n PULSE: next_state = IDLE;\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n waiting = 1'b0;\n pulse = 1'b0;\n idle = 1'b0;\n case (state)\n IDLE: begin\n waiting = 1'b0;\n pulse = 1'b0;\n idle = 1'b1;\n end\n WAIT: begin\n waiting = 1'b1;\n pulse = 1'b0;\n idle = 1'b0;\n end\n PULSE: begin\n waiting = 1'b0;\n pulse = 1'b1;\n idle = 1'b0;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"pulse_event_0009\",\n \"category\": \"pulse_event\",\n \"template\": \"request_complete_pulse\",\n \"description\": \"Pulse/event controller implementing request complete pulse semantics.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"request\",\n \"complete\"\n ],\n \"outputs\": [\n \"waiting\",\n \"pulse\",\n \"idle\"\n ],\n \"states\": [\n \"IDLE\",\n \"WAIT\",\n \"PULSE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"waiting\": 0,\n \"pulse\": 0,\n \"idle\": 1\n },\n \"WAIT\": {\n \"waiting\": 1,\n \"pulse\": 0,\n \"idle\": 0\n },\n \"PULSE\": {\n \"waiting\": 0,\n \"pulse\": 1,\n \"idle\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"request\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!request\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"complete\",\n \"to\": \"PULSE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"!complete\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"PULSE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({waiting, pulse, idle})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (request)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (!request)\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to PULSE when complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (complete)\",\n \"consequent\": \"!waiting && pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (!complete)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to IDLE when true\",\n \"antecedent\": \"!waiting && pulse && !idle\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"request\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"WAIT\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"WAIT\",\n \"old\": \"complete\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: pulse_event_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({waiting, pulse, idle}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!waiting && !pulse && idle));\n\n// P3_T1: IDLE transitions to WAIT when request.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!waiting && !pulse && idle) && (request)) |=> (waiting && !pulse && !idle));\n\n// P4_T2: IDLE transitions to IDLE when !request.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!waiting && !pulse && idle) && (!request)) |=> (!waiting && !pulse && idle));\n\n// P5_T3: WAIT transitions to PULSE when complete.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((waiting && !pulse && !idle) && (complete)) |=> (!waiting && pulse && !idle));\n\n// P6_T4: WAIT transitions to WAIT when !complete.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((waiting && !pulse && !idle) && (!complete)) |=> (waiting && !pulse && !idle));\n\n// P7_T5: PULSE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!waiting && pulse && !idle) |=> (!waiting && !pulse && idle));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({waiting, pulse, idle})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (request)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (!request)\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to PULSE when complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (complete)\",\n \"consequent\": \"!waiting && pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (!complete)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to IDLE when true\",\n \"antecedent\": \"!waiting && pulse && !idle\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module pulse_event_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!request) ? IDLE : (IDLE);\\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module pulse_event_0009_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (request) ? WAIT : ((!request) ? IDLE : (IDLE));\\n WAIT: next_state = (!complete) ? WAIT : (WAIT);\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module pulse_event_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = WAIT;\\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "pulse_event_0009", "category": "pulse_event", "description": "Pulse/event controller implementing request complete pulse semantics.", "rtl_variant": "onehot_case.sv", "rtl": "module pulse_event_0009_onehot_case (\n input wire clk,\n input wire rst,\n input wire request,\n input wire complete,\n output reg waiting,\n output reg pulse,\n output reg idle\n);\n localparam [2:0] IDLE = 3'b001;\n localparam [2:0] WAIT = 3'b010;\n localparam [2:0] PULSE = 3'b100;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = IDLE;\n case (state)\n IDLE: next_state = (request) ? WAIT : ((!request) ? IDLE : (IDLE));\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\n PULSE: next_state = IDLE;\n default: next_state = IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n waiting = (state == WAIT);\n pulse = (state == PULSE);\n idle = (state == IDLE);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"pulse_event_0009\",\n \"category\": \"pulse_event\",\n \"template\": \"request_complete_pulse\",\n \"description\": \"Pulse/event controller implementing request complete pulse semantics.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"request\",\n \"complete\"\n ],\n \"outputs\": [\n \"waiting\",\n \"pulse\",\n \"idle\"\n ],\n \"states\": [\n \"IDLE\",\n \"WAIT\",\n \"PULSE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"waiting\": 0,\n \"pulse\": 0,\n \"idle\": 1\n },\n \"WAIT\": {\n \"waiting\": 1,\n \"pulse\": 0,\n \"idle\": 0\n },\n \"PULSE\": {\n \"waiting\": 0,\n \"pulse\": 1,\n \"idle\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"request\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!request\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"complete\",\n \"to\": \"PULSE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"!complete\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"PULSE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({waiting, pulse, idle})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (request)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (!request)\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to PULSE when complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (complete)\",\n \"consequent\": \"!waiting && pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (!complete)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to IDLE when true\",\n \"antecedent\": \"!waiting && pulse && !idle\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"request\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"WAIT\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"WAIT\",\n \"old\": \"complete\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: pulse_event_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({waiting, pulse, idle}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!waiting && !pulse && idle));\n\n// P3_T1: IDLE transitions to WAIT when request.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!waiting && !pulse && idle) && (request)) |=> (waiting && !pulse && !idle));\n\n// P4_T2: IDLE transitions to IDLE when !request.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!waiting && !pulse && idle) && (!request)) |=> (!waiting && !pulse && idle));\n\n// P5_T3: WAIT transitions to PULSE when complete.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((waiting && !pulse && !idle) && (complete)) |=> (!waiting && pulse && !idle));\n\n// P6_T4: WAIT transitions to WAIT when !complete.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((waiting && !pulse && !idle) && (!complete)) |=> (waiting && !pulse && !idle));\n\n// P7_T5: PULSE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!waiting && pulse && !idle) |=> (!waiting && !pulse && idle));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({waiting, pulse, idle})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (request)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (!request)\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to PULSE when complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (complete)\",\n \"consequent\": \"!waiting && pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (!complete)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to IDLE when true\",\n \"antecedent\": \"!waiting && pulse && !idle\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module pulse_event_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!request) ? IDLE : (IDLE);\\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module pulse_event_0009_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (request) ? WAIT : ((!request) ? IDLE : (IDLE));\\n WAIT: next_state = (!complete) ? WAIT : (WAIT);\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module pulse_event_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = WAIT;\\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "pulse_event_0009", "category": "pulse_event", "description": "Pulse/event controller implementing request complete pulse semantics.", "rtl_variant": "nested_if.sv", "rtl": "module pulse_event_0009_nested_if (\n input wire clk,\n input wire rst,\n input wire request,\n input wire complete,\n output wire waiting,\n output wire pulse,\n output wire idle\n);\n localparam [1:0] S_IDLE = 2'd0;\n localparam [1:0] S_WAIT = 2'd1;\n localparam [1:0] S_PULSE = 2'd2;\n\n reg [1:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_IDLE;\n end else begin\n if (state == S_IDLE) begin\n state <= (request) ? S_WAIT : ((!request) ? S_IDLE : (S_IDLE));\n end\n else if (state == S_WAIT) begin\n state <= (complete) ? S_PULSE : ((!complete) ? S_WAIT : (S_WAIT));\n end\n else if (state == S_PULSE) begin\n state <= S_IDLE;\n end\n else begin\n state <= S_IDLE;\n end\n end\n end\n\n assign waiting = (state == S_WAIT);\n assign pulse = (state == S_PULSE);\n assign idle = (state == S_IDLE);\nendmodule\n", "spec_json": "{\n \"design_id\": \"pulse_event_0009\",\n \"category\": \"pulse_event\",\n \"template\": \"request_complete_pulse\",\n \"description\": \"Pulse/event controller implementing request complete pulse semantics.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"request\",\n \"complete\"\n ],\n \"outputs\": [\n \"waiting\",\n \"pulse\",\n \"idle\"\n ],\n \"states\": [\n \"IDLE\",\n \"WAIT\",\n \"PULSE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"waiting\": 0,\n \"pulse\": 0,\n \"idle\": 1\n },\n \"WAIT\": {\n \"waiting\": 1,\n \"pulse\": 0,\n \"idle\": 0\n },\n \"PULSE\": {\n \"waiting\": 0,\n \"pulse\": 1,\n \"idle\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"request\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!request\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"complete\",\n \"to\": \"PULSE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"!complete\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"PULSE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({waiting, pulse, idle})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (request)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (!request)\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to PULSE when complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (complete)\",\n \"consequent\": \"!waiting && pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (!complete)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to IDLE when true\",\n \"antecedent\": \"!waiting && pulse && !idle\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"request\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"WAIT\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"WAIT\",\n \"old\": \"complete\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: pulse_event_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({waiting, pulse, idle}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!waiting && !pulse && idle));\n\n// P3_T1: IDLE transitions to WAIT when request.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!waiting && !pulse && idle) && (request)) |=> (waiting && !pulse && !idle));\n\n// P4_T2: IDLE transitions to IDLE when !request.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!waiting && !pulse && idle) && (!request)) |=> (!waiting && !pulse && idle));\n\n// P5_T3: WAIT transitions to PULSE when complete.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((waiting && !pulse && !idle) && (complete)) |=> (!waiting && pulse && !idle));\n\n// P6_T4: WAIT transitions to WAIT when !complete.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((waiting && !pulse && !idle) && (!complete)) |=> (waiting && !pulse && !idle));\n\n// P7_T5: PULSE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!waiting && pulse && !idle) |=> (!waiting && !pulse && idle));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({waiting, pulse, idle})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (request)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (!request)\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to PULSE when complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (complete)\",\n \"consequent\": \"!waiting && pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (!complete)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to IDLE when true\",\n \"antecedent\": \"!waiting && pulse && !idle\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module pulse_event_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!request) ? IDLE : (IDLE);\\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module pulse_event_0009_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (request) ? WAIT : ((!request) ? IDLE : (IDLE));\\n WAIT: next_state = (!complete) ? WAIT : (WAIT);\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module pulse_event_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = WAIT;\\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "pulse_event_0009", "category": "pulse_event", "description": "Pulse/event controller implementing request complete pulse semantics.", "rtl_variant": "factored_flags.sv", "rtl": "module pulse_event_0009_factored_flags (\n input wire clk,\n input wire rst,\n input wire request,\n input wire complete,\n output reg waiting,\n output reg pulse,\n output reg idle\n);\n localparam [1:0] F_IDLE = 2'd0;\n localparam [1:0] F_WAIT = 2'd1;\n localparam [1:0] F_PULSE = 2'd2;\n\n reg [1:0] state, next_state;\n\n wire guard_idle_0 = (request);\n wire guard_idle_1 = (!request);\n wire guard_wait_0 = (complete);\n wire guard_wait_1 = (!complete);\n\n always @* begin\n next_state = state;\n case (state)\n F_IDLE: begin\n if (guard_idle_0)\n next_state = F_WAIT;\n else if (guard_idle_1)\n next_state = F_IDLE;\n end\n F_WAIT: begin\n if (guard_wait_0)\n next_state = F_PULSE;\n else if (guard_wait_1)\n next_state = F_WAIT;\n end\n F_PULSE: begin\n next_state = F_IDLE;\n end\n default: next_state = F_IDLE;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_IDLE;\n else\n state <= next_state;\n end\n\n always @* begin\n waiting = 1'b0;\n pulse = 1'b0;\n idle = 1'b0;\n case (state)\n F_IDLE: begin\n waiting = 1'b0;\n pulse = 1'b0;\n idle = 1'b1;\n end\n F_WAIT: begin\n waiting = 1'b1;\n pulse = 1'b0;\n idle = 1'b0;\n end\n F_PULSE: begin\n waiting = 1'b0;\n pulse = 1'b1;\n idle = 1'b0;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"pulse_event_0009\",\n \"category\": \"pulse_event\",\n \"template\": \"request_complete_pulse\",\n \"description\": \"Pulse/event controller implementing request complete pulse semantics.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"IDLE\"\n },\n \"inputs\": [\n \"request\",\n \"complete\"\n ],\n \"outputs\": [\n \"waiting\",\n \"pulse\",\n \"idle\"\n ],\n \"states\": [\n \"IDLE\",\n \"WAIT\",\n \"PULSE\"\n ],\n \"state_outputs\": {\n \"IDLE\": {\n \"waiting\": 0,\n \"pulse\": 0,\n \"idle\": 1\n },\n \"WAIT\": {\n \"waiting\": 1,\n \"pulse\": 0,\n \"idle\": 0\n },\n \"PULSE\": {\n \"waiting\": 0,\n \"pulse\": 1,\n \"idle\": 0\n }\n },\n \"transitions\": [\n {\n \"from\": \"IDLE\",\n \"when\": \"request\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"IDLE\",\n \"when\": \"!request\",\n \"to\": \"IDLE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"complete\",\n \"to\": \"PULSE\"\n },\n {\n \"from\": \"WAIT\",\n \"when\": \"!complete\",\n \"to\": \"WAIT\"\n },\n {\n \"from\": \"PULSE\",\n \"when\": \"true\",\n \"to\": \"IDLE\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({waiting, pulse, idle})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (request)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (!request)\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to PULSE when complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (complete)\",\n \"consequent\": \"!waiting && pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (!complete)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to IDLE when true\",\n \"antecedent\": \"!waiting && pulse && !idle\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"IDLE\",\n \"old\": \"request\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"IDLE\",\n \"to\": \"WAIT\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"WAIT\",\n \"old\": \"complete\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: pulse_event_0009\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({waiting, pulse, idle}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!waiting && !pulse && idle));\n\n// P3_T1: IDLE transitions to WAIT when request.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!waiting && !pulse && idle) && (request)) |=> (waiting && !pulse && !idle));\n\n// P4_T2: IDLE transitions to IDLE when !request.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!waiting && !pulse && idle) && (!request)) |=> (!waiting && !pulse && idle));\n\n// P5_T3: WAIT transitions to PULSE when complete.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((waiting && !pulse && !idle) && (complete)) |=> (!waiting && pulse && !idle));\n\n// P6_T4: WAIT transitions to WAIT when !complete.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((waiting && !pulse && !idle) && (!complete)) |=> (waiting && !pulse && !idle));\n\n// P7_T5: PULSE transitions to IDLE when true.\np_t5: assert property (@(posedge clk) disable iff (rst)\n (!waiting && pulse && !idle) |=> (!waiting && !pulse && idle));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({waiting, pulse, idle})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to WAIT when request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (request)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"IDLE transitions to IDLE when !request\",\n \"antecedent\": \"(!waiting && !pulse && idle) && (!request)\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to PULSE when complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (complete)\",\n \"consequent\": \"!waiting && pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"WAIT transitions to WAIT when !complete\",\n \"antecedent\": \"(waiting && !pulse && !idle) && (!complete)\",\n \"consequent\": \"waiting && !pulse && !idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"PULSE transitions to IDLE when true\",\n \"antecedent\": \"!waiting && pulse && !idle\",\n \"consequent\": \"!waiting && !pulse && idle\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module pulse_event_0009_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (!request) ? IDLE : (IDLE);\\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module pulse_event_0009_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = (request) ? WAIT : ((!request) ? IDLE : (IDLE));\\n WAIT: next_state = (!complete) ? WAIT : (WAIT);\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module pulse_event_0009_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire complete,\\n output reg waiting,\\n output reg pulse,\\n output reg idle\\n);\\n localparam [1:0] IDLE = 2'd0;\\n localparam [1:0] WAIT = 2'd1;\\n localparam [1:0] PULSE = 2'd2;\\n\\n reg [1:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n IDLE: next_state = WAIT;\\n WAIT: next_state = (complete) ? PULSE : ((!complete) ? WAIT : (WAIT));\\n PULSE: next_state = IDLE;\\n default: next_state = IDLE;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= IDLE;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b0;\\n case (state)\\n IDLE: begin\\n waiting = 1'b0;\\n pulse = 1'b0;\\n idle = 1'b1;\\n end\\n WAIT: begin\\n waiting = 1'b1;\\n pulse = 1'b0;\\n idle = 1'b0;\\n end\\n PULSE: begin\\n waiting = 1'b0;\\n pulse = 1'b1;\\n idle = 1'b0;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "rate_limiter_0007", "category": "rate_limiter", "description": "Windowed quota tracks both requests used and the current phase before quota reset.", "rtl_variant": "canonical_next.sv", "rtl": "module rate_limiter_0007_canonical_next (\n input wire clk,\n input wire rst,\n input wire request,\n input wire advance_window,\n output wire [1:0] used,\n output wire [1:0] phase,\n output wire allow,\n output wire exhausted\n);\n\n reg [1:0] used_reg;\n reg [1:0] phase_reg;\n\n reg [1:0] next_used_reg;\n reg [1:0] next_phase_reg;\n\n always @* begin\n if (advance_window) next_used_reg = 2'd0;\n else if (!advance_window && request && (used_reg < 2'd3)) next_used_reg = used_reg + 2'd1;\n else next_used_reg = used_reg;\n if (advance_window && (phase_reg < 2'd3)) next_phase_reg = phase_reg + 2'd1;\n else if (advance_window && (phase_reg == 2'd3)) next_phase_reg = 2'd0;\n else next_phase_reg = phase_reg;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n used_reg <= 2'd0;\n phase_reg <= 2'd0;\n end\n else begin\n used_reg <= next_used_reg;\n phase_reg <= next_phase_reg;\n end\n end\n\n assign used = used_reg;\n assign phase = phase_reg;\n assign allow = used_reg < 2'd3;\n assign exhausted = used_reg == 2'd3;\nendmodule\n", "spec_json": "{\n \"design_id\": \"rate_limiter_0007\",\n \"category\": \"rate_limiter\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"windowed_quota\",\n \"description\": \"Windowed quota tracks both requests used and the current phase before quota reset.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"request\",\n \"advance_window\"\n ],\n \"outputs\": [\n \"used\",\n \"phase\",\n \"allow\",\n \"exhausted\"\n ],\n \"signal_widths\": {\n \"used\": 2,\n \"phase\": 2\n },\n \"registers\": [\n {\n \"name\": \"used_reg\",\n \"width\": 2,\n \"reset_value\": \"2'd0\"\n },\n {\n \"name\": \"phase_reg\",\n \"width\": 2,\n \"reset_value\": \"2'd0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All RTL variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"used\": \"used_reg\",\n \"phase\": \"phase_reg\",\n \"allow\": \"used_reg < 2'd3\",\n \"exhausted\": \"used_reg == 2'd3\"\n },\n \"update_rules\": {\n \"used_reg\": [\n {\n \"when\": \"advance_window\",\n \"value\": \"2'd0\"\n },\n {\n \"when\": \"!advance_window && request && (used_reg < 2'd3)\",\n \"value\": \"used_reg + 2'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"used_reg\"\n }\n ],\n \"phase_reg\": [\n {\n \"when\": \"advance_window && (phase_reg < 2'd3)\",\n \"value\": \"phase_reg + 2'd1\"\n },\n {\n \"when\": \"advance_window && (phase_reg == 2'd3)\",\n \"value\": \"2'd0\"\n },\n {\n \"when\": \"true\",\n \"value\": \"phase_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is true until three requests are used\",\n \"expression\": \"allow == (used < 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_EXHAUSTED\",\n \"sva_name\": \"p_exhausted\",\n \"type\": \"invariant\",\n \"natural_language\": \"exhausted is true at quota three\",\n \"expression\": \"exhausted == (used == 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at phase zero with unused quota\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(used == 2'd0) && (phase == 2'd0)\",\n \"delay\": 1\n },\n {\n \"id\": \"P4_USE\",\n \"sva_name\": \"p_use\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"an allowed request consumes one unit\",\n \"antecedent\": \"!advance_window && request && (used < 2'd3)\",\n \"consequent\": \"used == ($past(used) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_NEW_WINDOW\",\n \"sva_name\": \"p_new_window\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the window resets quota usage\",\n \"antecedent\": \"advance_window\",\n \"consequent\": \"used == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_PHASE_ADV\",\n \"sva_name\": \"p_phase_adv\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advance_window increments phase before wrap\",\n \"antecedent\": \"advance_window && (phase < 2'd3)\",\n \"consequent\": \"phase == ($past(phase) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_EXHAUST_HOLD\",\n \"sva_name\": \"p_exhaust_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"requests cannot exceed the exhausted quota\",\n \"antecedent\": \"!advance_window && request && exhausted\",\n \"consequent\": \"used == 2'd3\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_PHASE_WRAP\",\n \"sva_name\": \"p_phase_wrap\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the final phase wraps the window phase to zero\",\n \"antecedent\": \"advance_window && (phase == 2'd3)\",\n \"consequent\": \"phase == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"never_reset_quota\",\n \"register\": \"used_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"advance_window\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_request\",\n \"register\": \"used_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!advance_window && request && (used_reg < 2'd3)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"never_wrap_phase\",\n \"register\": \"phase_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"advance_window && (phase_reg == 2'd3)\",\n \"new\": \"false\"\n }\n ]\n}\n", "properties_sva": "// P1_ALLOW: allow is true until three requests are used\nproperty p_allow;\n @(posedge clk) disable iff (rst) (allow == (used < 2'd3));\nendproperty\nassert property (p_allow);\n\n// P2_EXHAUSTED: exhausted is true at quota three\nproperty p_exhausted;\n @(posedge clk) disable iff (rst) (exhausted == (used == 2'd3));\nendproperty\nassert property (p_exhausted);\n\n// P3_RESET: reset starts at phase zero with unused quota\nproperty p_reset;\n @(posedge clk) (rst) |=> ((used == 2'd0) && (phase == 2'd0));\nendproperty\nassert property (p_reset);\n\n// P4_USE: an allowed request consumes one unit\nproperty p_use;\n @(posedge clk) disable iff (rst) (!advance_window && request && (used < 2'd3)) |=> (used == ($past(used) + 2'd1));\nendproperty\nassert property (p_use);\n\n// P5_NEW_WINDOW: advancing the window resets quota usage\nproperty p_new_window;\n @(posedge clk) disable iff (rst) (advance_window) |=> (used == 2'd0);\nendproperty\nassert property (p_new_window);\n\n// P6_PHASE_ADV: advance_window increments phase before wrap\nproperty p_phase_adv;\n @(posedge clk) disable iff (rst) (advance_window && (phase < 2'd3)) |=> (phase == ($past(phase) + 2'd1));\nendproperty\nassert property (p_phase_adv);\n\n// P7_EXHAUST_HOLD: requests cannot exceed the exhausted quota\nproperty p_exhaust_hold;\n @(posedge clk) disable iff (rst) (!advance_window && request && exhausted) |=> (used == 2'd3);\nendproperty\nassert property (p_exhaust_hold);\n\n// P8_PHASE_WRAP: advancing the final phase wraps the window phase to zero\nproperty p_phase_wrap;\n @(posedge clk) disable iff (rst) (advance_window && (phase == 2'd3)) |=> (phase == 2'd0);\nendproperty\nassert property (p_phase_wrap);\n", "properties_json": "[\n {\n \"id\": \"P1_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is true until three requests are used\",\n \"expression\": \"allow == (used < 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_EXHAUSTED\",\n \"sva_name\": \"p_exhausted\",\n \"type\": \"invariant\",\n \"natural_language\": \"exhausted is true at quota three\",\n \"expression\": \"exhausted == (used == 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at phase zero with unused quota\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(used == 2'd0) && (phase == 2'd0)\",\n \"delay\": 1\n },\n {\n \"id\": \"P4_USE\",\n \"sva_name\": \"p_use\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"an allowed request consumes one unit\",\n \"antecedent\": \"!advance_window && request && (used < 2'd3)\",\n \"consequent\": \"used == ($past(used) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_NEW_WINDOW\",\n \"sva_name\": \"p_new_window\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the window resets quota usage\",\n \"antecedent\": \"advance_window\",\n \"consequent\": \"used == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_PHASE_ADV\",\n \"sva_name\": \"p_phase_adv\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advance_window increments phase before wrap\",\n \"antecedent\": \"advance_window && (phase < 2'd3)\",\n \"consequent\": \"phase == ($past(phase) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_EXHAUST_HOLD\",\n \"sva_name\": \"p_exhaust_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"requests cannot exceed the exhausted quota\",\n \"antecedent\": \"!advance_window && request && exhausted\",\n \"consequent\": \"used == 2'd3\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_PHASE_WRAP\",\n \"sva_name\": \"p_phase_wrap\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the final phase wraps the window phase to zero\",\n \"antecedent\": \"advance_window && (phase == 2'd3)\",\n \"consequent\": \"phase == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_request.sv\": \"module rate_limiter_0007_mutant_ignore_request (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (advance_window) used_reg <= 2'd0;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\", \"never_reset_quota.sv\": \"module rate_limiter_0007_mutant_never_reset_quota (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\", \"never_wrap_phase.sv\": \"module rate_limiter_0007_mutant_never_wrap_phase (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (advance_window) used_reg <= 2'd0;\\n else if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\"}"} {"family_id": "rate_limiter_0007", "category": "rate_limiter", "description": "Windowed quota tracks both requests used and the current phase before quota reset.", "rtl_variant": "sequential_priority.sv", "rtl": "module rate_limiter_0007_sequential_priority (\n input wire clk,\n input wire rst,\n input wire request,\n input wire advance_window,\n output wire [1:0] used,\n output wire [1:0] phase,\n output wire allow,\n output wire exhausted\n);\n\n reg [1:0] used_reg;\n reg [1:0] phase_reg;\n\n always @(posedge clk) begin\n if (rst) begin\n used_reg <= 2'd0;\n phase_reg <= 2'd0;\n end\n else begin\n if (advance_window) used_reg <= 2'd0;\n else if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\n else used_reg <= used_reg;\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\n else phase_reg <= phase_reg;\n end\n end\n\n assign used = used_reg;\n assign phase = phase_reg;\n assign allow = used_reg < 2'd3;\n assign exhausted = used_reg == 2'd3;\nendmodule\n", "spec_json": "{\n \"design_id\": \"rate_limiter_0007\",\n \"category\": \"rate_limiter\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"windowed_quota\",\n \"description\": \"Windowed quota tracks both requests used and the current phase before quota reset.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"request\",\n \"advance_window\"\n ],\n \"outputs\": [\n \"used\",\n \"phase\",\n \"allow\",\n \"exhausted\"\n ],\n \"signal_widths\": {\n \"used\": 2,\n \"phase\": 2\n },\n \"registers\": [\n {\n \"name\": \"used_reg\",\n \"width\": 2,\n \"reset_value\": \"2'd0\"\n },\n {\n \"name\": \"phase_reg\",\n \"width\": 2,\n \"reset_value\": \"2'd0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All RTL variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"used\": \"used_reg\",\n \"phase\": \"phase_reg\",\n \"allow\": \"used_reg < 2'd3\",\n \"exhausted\": \"used_reg == 2'd3\"\n },\n \"update_rules\": {\n \"used_reg\": [\n {\n \"when\": \"advance_window\",\n \"value\": \"2'd0\"\n },\n {\n \"when\": \"!advance_window && request && (used_reg < 2'd3)\",\n \"value\": \"used_reg + 2'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"used_reg\"\n }\n ],\n \"phase_reg\": [\n {\n \"when\": \"advance_window && (phase_reg < 2'd3)\",\n \"value\": \"phase_reg + 2'd1\"\n },\n {\n \"when\": \"advance_window && (phase_reg == 2'd3)\",\n \"value\": \"2'd0\"\n },\n {\n \"when\": \"true\",\n \"value\": \"phase_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is true until three requests are used\",\n \"expression\": \"allow == (used < 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_EXHAUSTED\",\n \"sva_name\": \"p_exhausted\",\n \"type\": \"invariant\",\n \"natural_language\": \"exhausted is true at quota three\",\n \"expression\": \"exhausted == (used == 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at phase zero with unused quota\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(used == 2'd0) && (phase == 2'd0)\",\n \"delay\": 1\n },\n {\n \"id\": \"P4_USE\",\n \"sva_name\": \"p_use\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"an allowed request consumes one unit\",\n \"antecedent\": \"!advance_window && request && (used < 2'd3)\",\n \"consequent\": \"used == ($past(used) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_NEW_WINDOW\",\n \"sva_name\": \"p_new_window\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the window resets quota usage\",\n \"antecedent\": \"advance_window\",\n \"consequent\": \"used == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_PHASE_ADV\",\n \"sva_name\": \"p_phase_adv\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advance_window increments phase before wrap\",\n \"antecedent\": \"advance_window && (phase < 2'd3)\",\n \"consequent\": \"phase == ($past(phase) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_EXHAUST_HOLD\",\n \"sva_name\": \"p_exhaust_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"requests cannot exceed the exhausted quota\",\n \"antecedent\": \"!advance_window && request && exhausted\",\n \"consequent\": \"used == 2'd3\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_PHASE_WRAP\",\n \"sva_name\": \"p_phase_wrap\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the final phase wraps the window phase to zero\",\n \"antecedent\": \"advance_window && (phase == 2'd3)\",\n \"consequent\": \"phase == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"never_reset_quota\",\n \"register\": \"used_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"advance_window\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_request\",\n \"register\": \"used_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!advance_window && request && (used_reg < 2'd3)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"never_wrap_phase\",\n \"register\": \"phase_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"advance_window && (phase_reg == 2'd3)\",\n \"new\": \"false\"\n }\n ]\n}\n", "properties_sva": "// P1_ALLOW: allow is true until three requests are used\nproperty p_allow;\n @(posedge clk) disable iff (rst) (allow == (used < 2'd3));\nendproperty\nassert property (p_allow);\n\n// P2_EXHAUSTED: exhausted is true at quota three\nproperty p_exhausted;\n @(posedge clk) disable iff (rst) (exhausted == (used == 2'd3));\nendproperty\nassert property (p_exhausted);\n\n// P3_RESET: reset starts at phase zero with unused quota\nproperty p_reset;\n @(posedge clk) (rst) |=> ((used == 2'd0) && (phase == 2'd0));\nendproperty\nassert property (p_reset);\n\n// P4_USE: an allowed request consumes one unit\nproperty p_use;\n @(posedge clk) disable iff (rst) (!advance_window && request && (used < 2'd3)) |=> (used == ($past(used) + 2'd1));\nendproperty\nassert property (p_use);\n\n// P5_NEW_WINDOW: advancing the window resets quota usage\nproperty p_new_window;\n @(posedge clk) disable iff (rst) (advance_window) |=> (used == 2'd0);\nendproperty\nassert property (p_new_window);\n\n// P6_PHASE_ADV: advance_window increments phase before wrap\nproperty p_phase_adv;\n @(posedge clk) disable iff (rst) (advance_window && (phase < 2'd3)) |=> (phase == ($past(phase) + 2'd1));\nendproperty\nassert property (p_phase_adv);\n\n// P7_EXHAUST_HOLD: requests cannot exceed the exhausted quota\nproperty p_exhaust_hold;\n @(posedge clk) disable iff (rst) (!advance_window && request && exhausted) |=> (used == 2'd3);\nendproperty\nassert property (p_exhaust_hold);\n\n// P8_PHASE_WRAP: advancing the final phase wraps the window phase to zero\nproperty p_phase_wrap;\n @(posedge clk) disable iff (rst) (advance_window && (phase == 2'd3)) |=> (phase == 2'd0);\nendproperty\nassert property (p_phase_wrap);\n", "properties_json": "[\n {\n \"id\": \"P1_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is true until three requests are used\",\n \"expression\": \"allow == (used < 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_EXHAUSTED\",\n \"sva_name\": \"p_exhausted\",\n \"type\": \"invariant\",\n \"natural_language\": \"exhausted is true at quota three\",\n \"expression\": \"exhausted == (used == 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at phase zero with unused quota\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(used == 2'd0) && (phase == 2'd0)\",\n \"delay\": 1\n },\n {\n \"id\": \"P4_USE\",\n \"sva_name\": \"p_use\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"an allowed request consumes one unit\",\n \"antecedent\": \"!advance_window && request && (used < 2'd3)\",\n \"consequent\": \"used == ($past(used) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_NEW_WINDOW\",\n \"sva_name\": \"p_new_window\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the window resets quota usage\",\n \"antecedent\": \"advance_window\",\n \"consequent\": \"used == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_PHASE_ADV\",\n \"sva_name\": \"p_phase_adv\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advance_window increments phase before wrap\",\n \"antecedent\": \"advance_window && (phase < 2'd3)\",\n \"consequent\": \"phase == ($past(phase) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_EXHAUST_HOLD\",\n \"sva_name\": \"p_exhaust_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"requests cannot exceed the exhausted quota\",\n \"antecedent\": \"!advance_window && request && exhausted\",\n \"consequent\": \"used == 2'd3\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_PHASE_WRAP\",\n \"sva_name\": \"p_phase_wrap\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the final phase wraps the window phase to zero\",\n \"antecedent\": \"advance_window && (phase == 2'd3)\",\n \"consequent\": \"phase == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_request.sv\": \"module rate_limiter_0007_mutant_ignore_request (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (advance_window) used_reg <= 2'd0;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\", \"never_reset_quota.sv\": \"module rate_limiter_0007_mutant_never_reset_quota (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\", \"never_wrap_phase.sv\": \"module rate_limiter_0007_mutant_never_wrap_phase (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (advance_window) used_reg <= 2'd0;\\n else if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\"}"} {"family_id": "rate_limiter_0007", "category": "rate_limiter", "description": "Windowed quota tracks both requests used and the current phase before quota reset.", "rtl_variant": "ternary_next.sv", "rtl": "module rate_limiter_0007_ternary_next (\n input wire clk,\n input wire rst,\n input wire request,\n input wire advance_window,\n output wire [1:0] used,\n output wire [1:0] phase,\n output wire allow,\n output wire exhausted\n);\n\n reg [1:0] used_reg;\n reg [1:0] phase_reg;\n\n wire [1:0] next_used_reg;\n wire [1:0] next_phase_reg;\n\n assign next_used_reg = (advance_window) ? (2'd0) : ((!advance_window && request && (used_reg < 2'd3)) ? (used_reg + 2'd1) : (used_reg));\n assign next_phase_reg = (advance_window && (phase_reg < 2'd3)) ? (phase_reg + 2'd1) : ((advance_window && (phase_reg == 2'd3)) ? (2'd0) : (phase_reg));\n\n always @(posedge clk) begin\n if (rst) begin\n used_reg <= 2'd0;\n phase_reg <= 2'd0;\n end\n else begin\n used_reg <= next_used_reg;\n phase_reg <= next_phase_reg;\n end\n end\n\n assign used = used_reg;\n assign phase = phase_reg;\n assign allow = used_reg < 2'd3;\n assign exhausted = used_reg == 2'd3;\nendmodule\n", "spec_json": "{\n \"design_id\": \"rate_limiter_0007\",\n \"category\": \"rate_limiter\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"windowed_quota\",\n \"description\": \"Windowed quota tracks both requests used and the current phase before quota reset.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"request\",\n \"advance_window\"\n ],\n \"outputs\": [\n \"used\",\n \"phase\",\n \"allow\",\n \"exhausted\"\n ],\n \"signal_widths\": {\n \"used\": 2,\n \"phase\": 2\n },\n \"registers\": [\n {\n \"name\": \"used_reg\",\n \"width\": 2,\n \"reset_value\": \"2'd0\"\n },\n {\n \"name\": \"phase_reg\",\n \"width\": 2,\n \"reset_value\": \"2'd0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All RTL variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"used\": \"used_reg\",\n \"phase\": \"phase_reg\",\n \"allow\": \"used_reg < 2'd3\",\n \"exhausted\": \"used_reg == 2'd3\"\n },\n \"update_rules\": {\n \"used_reg\": [\n {\n \"when\": \"advance_window\",\n \"value\": \"2'd0\"\n },\n {\n \"when\": \"!advance_window && request && (used_reg < 2'd3)\",\n \"value\": \"used_reg + 2'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"used_reg\"\n }\n ],\n \"phase_reg\": [\n {\n \"when\": \"advance_window && (phase_reg < 2'd3)\",\n \"value\": \"phase_reg + 2'd1\"\n },\n {\n \"when\": \"advance_window && (phase_reg == 2'd3)\",\n \"value\": \"2'd0\"\n },\n {\n \"when\": \"true\",\n \"value\": \"phase_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is true until three requests are used\",\n \"expression\": \"allow == (used < 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_EXHAUSTED\",\n \"sva_name\": \"p_exhausted\",\n \"type\": \"invariant\",\n \"natural_language\": \"exhausted is true at quota three\",\n \"expression\": \"exhausted == (used == 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at phase zero with unused quota\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(used == 2'd0) && (phase == 2'd0)\",\n \"delay\": 1\n },\n {\n \"id\": \"P4_USE\",\n \"sva_name\": \"p_use\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"an allowed request consumes one unit\",\n \"antecedent\": \"!advance_window && request && (used < 2'd3)\",\n \"consequent\": \"used == ($past(used) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_NEW_WINDOW\",\n \"sva_name\": \"p_new_window\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the window resets quota usage\",\n \"antecedent\": \"advance_window\",\n \"consequent\": \"used == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_PHASE_ADV\",\n \"sva_name\": \"p_phase_adv\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advance_window increments phase before wrap\",\n \"antecedent\": \"advance_window && (phase < 2'd3)\",\n \"consequent\": \"phase == ($past(phase) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_EXHAUST_HOLD\",\n \"sva_name\": \"p_exhaust_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"requests cannot exceed the exhausted quota\",\n \"antecedent\": \"!advance_window && request && exhausted\",\n \"consequent\": \"used == 2'd3\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_PHASE_WRAP\",\n \"sva_name\": \"p_phase_wrap\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the final phase wraps the window phase to zero\",\n \"antecedent\": \"advance_window && (phase == 2'd3)\",\n \"consequent\": \"phase == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"never_reset_quota\",\n \"register\": \"used_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"advance_window\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_request\",\n \"register\": \"used_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!advance_window && request && (used_reg < 2'd3)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"never_wrap_phase\",\n \"register\": \"phase_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"advance_window && (phase_reg == 2'd3)\",\n \"new\": \"false\"\n }\n ]\n}\n", "properties_sva": "// P1_ALLOW: allow is true until three requests are used\nproperty p_allow;\n @(posedge clk) disable iff (rst) (allow == (used < 2'd3));\nendproperty\nassert property (p_allow);\n\n// P2_EXHAUSTED: exhausted is true at quota three\nproperty p_exhausted;\n @(posedge clk) disable iff (rst) (exhausted == (used == 2'd3));\nendproperty\nassert property (p_exhausted);\n\n// P3_RESET: reset starts at phase zero with unused quota\nproperty p_reset;\n @(posedge clk) (rst) |=> ((used == 2'd0) && (phase == 2'd0));\nendproperty\nassert property (p_reset);\n\n// P4_USE: an allowed request consumes one unit\nproperty p_use;\n @(posedge clk) disable iff (rst) (!advance_window && request && (used < 2'd3)) |=> (used == ($past(used) + 2'd1));\nendproperty\nassert property (p_use);\n\n// P5_NEW_WINDOW: advancing the window resets quota usage\nproperty p_new_window;\n @(posedge clk) disable iff (rst) (advance_window) |=> (used == 2'd0);\nendproperty\nassert property (p_new_window);\n\n// P6_PHASE_ADV: advance_window increments phase before wrap\nproperty p_phase_adv;\n @(posedge clk) disable iff (rst) (advance_window && (phase < 2'd3)) |=> (phase == ($past(phase) + 2'd1));\nendproperty\nassert property (p_phase_adv);\n\n// P7_EXHAUST_HOLD: requests cannot exceed the exhausted quota\nproperty p_exhaust_hold;\n @(posedge clk) disable iff (rst) (!advance_window && request && exhausted) |=> (used == 2'd3);\nendproperty\nassert property (p_exhaust_hold);\n\n// P8_PHASE_WRAP: advancing the final phase wraps the window phase to zero\nproperty p_phase_wrap;\n @(posedge clk) disable iff (rst) (advance_window && (phase == 2'd3)) |=> (phase == 2'd0);\nendproperty\nassert property (p_phase_wrap);\n", "properties_json": "[\n {\n \"id\": \"P1_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is true until three requests are used\",\n \"expression\": \"allow == (used < 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_EXHAUSTED\",\n \"sva_name\": \"p_exhausted\",\n \"type\": \"invariant\",\n \"natural_language\": \"exhausted is true at quota three\",\n \"expression\": \"exhausted == (used == 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at phase zero with unused quota\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(used == 2'd0) && (phase == 2'd0)\",\n \"delay\": 1\n },\n {\n \"id\": \"P4_USE\",\n \"sva_name\": \"p_use\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"an allowed request consumes one unit\",\n \"antecedent\": \"!advance_window && request && (used < 2'd3)\",\n \"consequent\": \"used == ($past(used) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_NEW_WINDOW\",\n \"sva_name\": \"p_new_window\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the window resets quota usage\",\n \"antecedent\": \"advance_window\",\n \"consequent\": \"used == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_PHASE_ADV\",\n \"sva_name\": \"p_phase_adv\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advance_window increments phase before wrap\",\n \"antecedent\": \"advance_window && (phase < 2'd3)\",\n \"consequent\": \"phase == ($past(phase) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_EXHAUST_HOLD\",\n \"sva_name\": \"p_exhaust_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"requests cannot exceed the exhausted quota\",\n \"antecedent\": \"!advance_window && request && exhausted\",\n \"consequent\": \"used == 2'd3\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_PHASE_WRAP\",\n \"sva_name\": \"p_phase_wrap\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the final phase wraps the window phase to zero\",\n \"antecedent\": \"advance_window && (phase == 2'd3)\",\n \"consequent\": \"phase == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_request.sv\": \"module rate_limiter_0007_mutant_ignore_request (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (advance_window) used_reg <= 2'd0;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\", \"never_reset_quota.sv\": \"module rate_limiter_0007_mutant_never_reset_quota (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\", \"never_wrap_phase.sv\": \"module rate_limiter_0007_mutant_never_wrap_phase (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (advance_window) used_reg <= 2'd0;\\n else if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\"}"} {"family_id": "rate_limiter_0007", "category": "rate_limiter", "description": "Windowed quota tracks both requests used and the current phase before quota reset.", "rtl_variant": "function_update.sv", "rtl": "module rate_limiter_0007_function_update (\n input wire clk,\n input wire rst,\n input wire request,\n input wire advance_window,\n output wire [1:0] used,\n output wire [1:0] phase,\n output wire allow,\n output wire exhausted\n);\n\n reg [1:0] used_reg;\n reg [1:0] phase_reg;\n\n function automatic [1:0] compute_next_used_reg;\n input [1:0] current_used_reg;\n input [1:0] current_phase_reg;\n input request;\n input advance_window;\n begin\n if (advance_window) compute_next_used_reg = 2'd0;\n else if (!advance_window && request && (current_used_reg < 2'd3)) compute_next_used_reg = current_used_reg + 2'd1;\n else compute_next_used_reg = current_used_reg;\n end\n endfunction\n\n function automatic [1:0] compute_next_phase_reg;\n input [1:0] current_used_reg;\n input [1:0] current_phase_reg;\n input request;\n input advance_window;\n begin\n if (advance_window && (current_phase_reg < 2'd3)) compute_next_phase_reg = current_phase_reg + 2'd1;\n else if (advance_window && (current_phase_reg == 2'd3)) compute_next_phase_reg = 2'd0;\n else compute_next_phase_reg = current_phase_reg;\n end\n endfunction\n\n wire [1:0] next_used_reg;\n wire [1:0] next_phase_reg;\n\n assign next_used_reg = compute_next_used_reg(used_reg, phase_reg, request, advance_window);\n assign next_phase_reg = compute_next_phase_reg(used_reg, phase_reg, request, advance_window);\n\n always @(posedge clk) begin\n if (rst) begin\n used_reg <= 2'd0;\n phase_reg <= 2'd0;\n end\n else begin\n used_reg <= next_used_reg;\n phase_reg <= next_phase_reg;\n end\n end\n\n assign used = used_reg;\n assign phase = phase_reg;\n assign allow = used_reg < 2'd3;\n assign exhausted = used_reg == 2'd3;\nendmodule\n", "spec_json": "{\n \"design_id\": \"rate_limiter_0007\",\n \"category\": \"rate_limiter\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"windowed_quota\",\n \"description\": \"Windowed quota tracks both requests used and the current phase before quota reset.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"request\",\n \"advance_window\"\n ],\n \"outputs\": [\n \"used\",\n \"phase\",\n \"allow\",\n \"exhausted\"\n ],\n \"signal_widths\": {\n \"used\": 2,\n \"phase\": 2\n },\n \"registers\": [\n {\n \"name\": \"used_reg\",\n \"width\": 2,\n \"reset_value\": \"2'd0\"\n },\n {\n \"name\": \"phase_reg\",\n \"width\": 2,\n \"reset_value\": \"2'd0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All RTL variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"used\": \"used_reg\",\n \"phase\": \"phase_reg\",\n \"allow\": \"used_reg < 2'd3\",\n \"exhausted\": \"used_reg == 2'd3\"\n },\n \"update_rules\": {\n \"used_reg\": [\n {\n \"when\": \"advance_window\",\n \"value\": \"2'd0\"\n },\n {\n \"when\": \"!advance_window && request && (used_reg < 2'd3)\",\n \"value\": \"used_reg + 2'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"used_reg\"\n }\n ],\n \"phase_reg\": [\n {\n \"when\": \"advance_window && (phase_reg < 2'd3)\",\n \"value\": \"phase_reg + 2'd1\"\n },\n {\n \"when\": \"advance_window && (phase_reg == 2'd3)\",\n \"value\": \"2'd0\"\n },\n {\n \"when\": \"true\",\n \"value\": \"phase_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is true until three requests are used\",\n \"expression\": \"allow == (used < 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_EXHAUSTED\",\n \"sva_name\": \"p_exhausted\",\n \"type\": \"invariant\",\n \"natural_language\": \"exhausted is true at quota three\",\n \"expression\": \"exhausted == (used == 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at phase zero with unused quota\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(used == 2'd0) && (phase == 2'd0)\",\n \"delay\": 1\n },\n {\n \"id\": \"P4_USE\",\n \"sva_name\": \"p_use\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"an allowed request consumes one unit\",\n \"antecedent\": \"!advance_window && request && (used < 2'd3)\",\n \"consequent\": \"used == ($past(used) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_NEW_WINDOW\",\n \"sva_name\": \"p_new_window\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the window resets quota usage\",\n \"antecedent\": \"advance_window\",\n \"consequent\": \"used == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_PHASE_ADV\",\n \"sva_name\": \"p_phase_adv\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advance_window increments phase before wrap\",\n \"antecedent\": \"advance_window && (phase < 2'd3)\",\n \"consequent\": \"phase == ($past(phase) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_EXHAUST_HOLD\",\n \"sva_name\": \"p_exhaust_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"requests cannot exceed the exhausted quota\",\n \"antecedent\": \"!advance_window && request && exhausted\",\n \"consequent\": \"used == 2'd3\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_PHASE_WRAP\",\n \"sva_name\": \"p_phase_wrap\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the final phase wraps the window phase to zero\",\n \"antecedent\": \"advance_window && (phase == 2'd3)\",\n \"consequent\": \"phase == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"never_reset_quota\",\n \"register\": \"used_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"advance_window\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_request\",\n \"register\": \"used_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!advance_window && request && (used_reg < 2'd3)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"never_wrap_phase\",\n \"register\": \"phase_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"advance_window && (phase_reg == 2'd3)\",\n \"new\": \"false\"\n }\n ]\n}\n", "properties_sva": "// P1_ALLOW: allow is true until three requests are used\nproperty p_allow;\n @(posedge clk) disable iff (rst) (allow == (used < 2'd3));\nendproperty\nassert property (p_allow);\n\n// P2_EXHAUSTED: exhausted is true at quota three\nproperty p_exhausted;\n @(posedge clk) disable iff (rst) (exhausted == (used == 2'd3));\nendproperty\nassert property (p_exhausted);\n\n// P3_RESET: reset starts at phase zero with unused quota\nproperty p_reset;\n @(posedge clk) (rst) |=> ((used == 2'd0) && (phase == 2'd0));\nendproperty\nassert property (p_reset);\n\n// P4_USE: an allowed request consumes one unit\nproperty p_use;\n @(posedge clk) disable iff (rst) (!advance_window && request && (used < 2'd3)) |=> (used == ($past(used) + 2'd1));\nendproperty\nassert property (p_use);\n\n// P5_NEW_WINDOW: advancing the window resets quota usage\nproperty p_new_window;\n @(posedge clk) disable iff (rst) (advance_window) |=> (used == 2'd0);\nendproperty\nassert property (p_new_window);\n\n// P6_PHASE_ADV: advance_window increments phase before wrap\nproperty p_phase_adv;\n @(posedge clk) disable iff (rst) (advance_window && (phase < 2'd3)) |=> (phase == ($past(phase) + 2'd1));\nendproperty\nassert property (p_phase_adv);\n\n// P7_EXHAUST_HOLD: requests cannot exceed the exhausted quota\nproperty p_exhaust_hold;\n @(posedge clk) disable iff (rst) (!advance_window && request && exhausted) |=> (used == 2'd3);\nendproperty\nassert property (p_exhaust_hold);\n\n// P8_PHASE_WRAP: advancing the final phase wraps the window phase to zero\nproperty p_phase_wrap;\n @(posedge clk) disable iff (rst) (advance_window && (phase == 2'd3)) |=> (phase == 2'd0);\nendproperty\nassert property (p_phase_wrap);\n", "properties_json": "[\n {\n \"id\": \"P1_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is true until three requests are used\",\n \"expression\": \"allow == (used < 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_EXHAUSTED\",\n \"sva_name\": \"p_exhausted\",\n \"type\": \"invariant\",\n \"natural_language\": \"exhausted is true at quota three\",\n \"expression\": \"exhausted == (used == 2'd3)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at phase zero with unused quota\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(used == 2'd0) && (phase == 2'd0)\",\n \"delay\": 1\n },\n {\n \"id\": \"P4_USE\",\n \"sva_name\": \"p_use\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"an allowed request consumes one unit\",\n \"antecedent\": \"!advance_window && request && (used < 2'd3)\",\n \"consequent\": \"used == ($past(used) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_NEW_WINDOW\",\n \"sva_name\": \"p_new_window\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the window resets quota usage\",\n \"antecedent\": \"advance_window\",\n \"consequent\": \"used == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_PHASE_ADV\",\n \"sva_name\": \"p_phase_adv\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advance_window increments phase before wrap\",\n \"antecedent\": \"advance_window && (phase < 2'd3)\",\n \"consequent\": \"phase == ($past(phase) + 2'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_EXHAUST_HOLD\",\n \"sva_name\": \"p_exhaust_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"requests cannot exceed the exhausted quota\",\n \"antecedent\": \"!advance_window && request && exhausted\",\n \"consequent\": \"used == 2'd3\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_PHASE_WRAP\",\n \"sva_name\": \"p_phase_wrap\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"advancing the final phase wraps the window phase to zero\",\n \"antecedent\": \"advance_window && (phase == 2'd3)\",\n \"consequent\": \"phase == 2'd0\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_request.sv\": \"module rate_limiter_0007_mutant_ignore_request (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (advance_window) used_reg <= 2'd0;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\", \"never_reset_quota.sv\": \"module rate_limiter_0007_mutant_never_reset_quota (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else if (advance_window && (phase_reg == 2'd3)) phase_reg <= 2'd0;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\", \"never_wrap_phase.sv\": \"module rate_limiter_0007_mutant_never_wrap_phase (\\n input wire clk,\\n input wire rst,\\n input wire request,\\n input wire advance_window,\\n output wire [1:0] used,\\n output wire [1:0] phase,\\n output wire allow,\\n output wire exhausted\\n);\\n\\n reg [1:0] used_reg;\\n reg [1:0] phase_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n used_reg <= 2'd0;\\n phase_reg <= 2'd0;\\n end\\n else begin\\n if (advance_window) used_reg <= 2'd0;\\n else if (!advance_window && request && (used_reg < 2'd3)) used_reg <= used_reg + 2'd1;\\n else used_reg <= used_reg;\\n if (advance_window && (phase_reg < 2'd3)) phase_reg <= phase_reg + 2'd1;\\n else phase_reg <= phase_reg;\\n end\\n end\\n\\n assign used = used_reg;\\n assign phase = phase_reg;\\n assign allow = used_reg < 2'd3;\\n assign exhausted = used_reg == 2'd3;\\nendmodule\\n\"}"} {"family_id": "rate_limiter_0009", "category": "rate_limiter", "description": "Rate-control state implementing admission tokens.", "rtl_variant": "canonical_next.sv", "rtl": "module rate_limiter_0009_canonical_next (\n input wire clk,\n input wire rst,\n input wire admit,\n input wire return_token,\n output reg [2:0] tokens,\n output wire allow\n);\n\n reg [2:0] next_tokens;\n\n always @* begin\n if (return_token && (tokens < 3'd7)) next_tokens = tokens + 3'd1;\n else if (!return_token && admit && (tokens > 3'd0)) next_tokens = tokens - 3'd1;\n else next_tokens = tokens;\n end\n\n always @(posedge clk) begin\n if (rst)\n tokens <= 3'd3;\n else\n tokens <= next_tokens;\n end\n\n assign allow = tokens != 3'd0;\nendmodule\n", "spec_json": "{\n \"design_id\": \"rate_limiter_0009\",\n \"category\": \"rate_limiter\",\n \"model_type\": \"register_rules\",\n \"template\": \"admission_tokens\",\n \"description\": \"Rate-control state implementing admission tokens.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"admit\",\n \"return_token\"\n ],\n \"outputs\": [\n \"tokens\",\n \"allow\"\n ],\n \"signal_widths\": {\n \"tokens\": 3\n },\n \"registers\": [\n {\n \"name\": \"tokens\",\n \"width\": 3,\n \"reset_value\": \"3'd3\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"allow\": \"tokens != 3'd0\"\n },\n \"update_rules\": [\n {\n \"when\": \"return_token && (tokens < 3'd7)\",\n \"value\": \"tokens + 3'd1\"\n },\n {\n \"when\": \"!return_token && admit && (tokens > 3'd0)\",\n \"value\": \"tokens - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"tokens\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"tokens == 3'd3\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is consistent with the observable register value\",\n \"expression\": \"allow == (tokens != 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule return_token && (tokens < 3'd7) produces the specified next value\",\n \"antecedent\": \"return_token && (tokens < 3'd7)\",\n \"consequent\": \"tokens == ($past(tokens) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\",\n \"antecedent\": \"!return_token && admit && (tokens > 3'd0)\",\n \"consequent\": \"tokens == ($past(tokens) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))\",\n \"consequent\": \"tokens == $past(tokens)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_first_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"return_token && (tokens < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_second_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!return_token && admit && (tokens > 3'd0)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"broaden_second_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!return_token && admit && (tokens > 3'd0)\",\n \"new\": \"true\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for rate_limiter_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (tokens == 3'd3);\nendproperty\nassert property (p_reset_value);\n\n// P2_ALLOW: allow is consistent with the observable register value\nproperty p_allow;\n @(posedge clk) disable iff (rst) (allow == (tokens != 3'd0));\nendproperty\nassert property (p_allow);\n\n// P3_RULE: update rule return_token && (tokens < 3'd7) produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (return_token && (tokens < 3'd7)) |=> (tokens == ($past(tokens) + 3'd1));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!return_token && admit && (tokens > 3'd0)) |=> (tokens == ($past(tokens) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))) |=> (tokens == $past(tokens));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"tokens == 3'd3\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is consistent with the observable register value\",\n \"expression\": \"allow == (tokens != 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule return_token && (tokens < 3'd7) produces the specified next value\",\n \"antecedent\": \"return_token && (tokens < 3'd7)\",\n \"consequent\": \"tokens == ($past(tokens) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\",\n \"antecedent\": \"!return_token && admit && (tokens > 3'd0)\",\n \"consequent\": \"tokens == ($past(tokens) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))\",\n \"consequent\": \"tokens == $past(tokens)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"broaden_second_rule.sv\": \"module rate_limiter_0009_mutant_broaden_second_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\\n else tokens <= tokens - 3'd1;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\", \"drop_first_rule.sv\": \"module rate_limiter_0009_mutant_drop_first_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (!return_token && admit && (tokens > 3'd0)) tokens <= tokens - 3'd1;\\n else tokens <= tokens;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\", \"drop_second_rule.sv\": \"module rate_limiter_0009_mutant_drop_second_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\\n else tokens <= tokens;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\"}"} {"family_id": "rate_limiter_0009", "category": "rate_limiter", "description": "Rate-control state implementing admission tokens.", "rtl_variant": "sequential_priority.sv", "rtl": "module rate_limiter_0009_sequential_priority (\n input wire clk,\n input wire rst,\n input wire admit,\n input wire return_token,\n output reg [2:0] tokens,\n output wire allow\n);\n\n always @(posedge clk) begin\n if (rst) begin\n tokens <= 3'd3;\n end\n else begin\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\n else if (!return_token && admit && (tokens > 3'd0)) tokens <= tokens - 3'd1;\n else tokens <= tokens;\n end\n end\n\n assign allow = tokens != 3'd0;\nendmodule\n", "spec_json": "{\n \"design_id\": \"rate_limiter_0009\",\n \"category\": \"rate_limiter\",\n \"model_type\": \"register_rules\",\n \"template\": \"admission_tokens\",\n \"description\": \"Rate-control state implementing admission tokens.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"admit\",\n \"return_token\"\n ],\n \"outputs\": [\n \"tokens\",\n \"allow\"\n ],\n \"signal_widths\": {\n \"tokens\": 3\n },\n \"registers\": [\n {\n \"name\": \"tokens\",\n \"width\": 3,\n \"reset_value\": \"3'd3\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"allow\": \"tokens != 3'd0\"\n },\n \"update_rules\": [\n {\n \"when\": \"return_token && (tokens < 3'd7)\",\n \"value\": \"tokens + 3'd1\"\n },\n {\n \"when\": \"!return_token && admit && (tokens > 3'd0)\",\n \"value\": \"tokens - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"tokens\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"tokens == 3'd3\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is consistent with the observable register value\",\n \"expression\": \"allow == (tokens != 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule return_token && (tokens < 3'd7) produces the specified next value\",\n \"antecedent\": \"return_token && (tokens < 3'd7)\",\n \"consequent\": \"tokens == ($past(tokens) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\",\n \"antecedent\": \"!return_token && admit && (tokens > 3'd0)\",\n \"consequent\": \"tokens == ($past(tokens) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))\",\n \"consequent\": \"tokens == $past(tokens)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_first_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"return_token && (tokens < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_second_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!return_token && admit && (tokens > 3'd0)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"broaden_second_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!return_token && admit && (tokens > 3'd0)\",\n \"new\": \"true\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for rate_limiter_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (tokens == 3'd3);\nendproperty\nassert property (p_reset_value);\n\n// P2_ALLOW: allow is consistent with the observable register value\nproperty p_allow;\n @(posedge clk) disable iff (rst) (allow == (tokens != 3'd0));\nendproperty\nassert property (p_allow);\n\n// P3_RULE: update rule return_token && (tokens < 3'd7) produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (return_token && (tokens < 3'd7)) |=> (tokens == ($past(tokens) + 3'd1));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!return_token && admit && (tokens > 3'd0)) |=> (tokens == ($past(tokens) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))) |=> (tokens == $past(tokens));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"tokens == 3'd3\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is consistent with the observable register value\",\n \"expression\": \"allow == (tokens != 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule return_token && (tokens < 3'd7) produces the specified next value\",\n \"antecedent\": \"return_token && (tokens < 3'd7)\",\n \"consequent\": \"tokens == ($past(tokens) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\",\n \"antecedent\": \"!return_token && admit && (tokens > 3'd0)\",\n \"consequent\": \"tokens == ($past(tokens) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))\",\n \"consequent\": \"tokens == $past(tokens)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"broaden_second_rule.sv\": \"module rate_limiter_0009_mutant_broaden_second_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\\n else tokens <= tokens - 3'd1;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\", \"drop_first_rule.sv\": \"module rate_limiter_0009_mutant_drop_first_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (!return_token && admit && (tokens > 3'd0)) tokens <= tokens - 3'd1;\\n else tokens <= tokens;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\", \"drop_second_rule.sv\": \"module rate_limiter_0009_mutant_drop_second_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\\n else tokens <= tokens;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\"}"} {"family_id": "rate_limiter_0009", "category": "rate_limiter", "description": "Rate-control state implementing admission tokens.", "rtl_variant": "ternary_next.sv", "rtl": "module rate_limiter_0009_ternary_next (\n input wire clk,\n input wire rst,\n input wire admit,\n input wire return_token,\n output reg [2:0] tokens,\n output wire allow\n);\n\n wire [2:0] next_tokens;\n\n assign next_tokens = (return_token && (tokens < 3'd7)) ? (tokens + 3'd1) : ((!return_token && admit && (tokens > 3'd0)) ? (tokens - 3'd1) : (tokens));\n\n always @(posedge clk) begin\n if (rst)\n tokens <= 3'd3;\n else\n tokens <= next_tokens;\n end\n\n assign allow = tokens != 3'd0;\nendmodule\n", "spec_json": "{\n \"design_id\": \"rate_limiter_0009\",\n \"category\": \"rate_limiter\",\n \"model_type\": \"register_rules\",\n \"template\": \"admission_tokens\",\n \"description\": \"Rate-control state implementing admission tokens.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"admit\",\n \"return_token\"\n ],\n \"outputs\": [\n \"tokens\",\n \"allow\"\n ],\n \"signal_widths\": {\n \"tokens\": 3\n },\n \"registers\": [\n {\n \"name\": \"tokens\",\n \"width\": 3,\n \"reset_value\": \"3'd3\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"allow\": \"tokens != 3'd0\"\n },\n \"update_rules\": [\n {\n \"when\": \"return_token && (tokens < 3'd7)\",\n \"value\": \"tokens + 3'd1\"\n },\n {\n \"when\": \"!return_token && admit && (tokens > 3'd0)\",\n \"value\": \"tokens - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"tokens\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"tokens == 3'd3\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is consistent with the observable register value\",\n \"expression\": \"allow == (tokens != 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule return_token && (tokens < 3'd7) produces the specified next value\",\n \"antecedent\": \"return_token && (tokens < 3'd7)\",\n \"consequent\": \"tokens == ($past(tokens) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\",\n \"antecedent\": \"!return_token && admit && (tokens > 3'd0)\",\n \"consequent\": \"tokens == ($past(tokens) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))\",\n \"consequent\": \"tokens == $past(tokens)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_first_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"return_token && (tokens < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_second_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!return_token && admit && (tokens > 3'd0)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"broaden_second_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!return_token && admit && (tokens > 3'd0)\",\n \"new\": \"true\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for rate_limiter_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (tokens == 3'd3);\nendproperty\nassert property (p_reset_value);\n\n// P2_ALLOW: allow is consistent with the observable register value\nproperty p_allow;\n @(posedge clk) disable iff (rst) (allow == (tokens != 3'd0));\nendproperty\nassert property (p_allow);\n\n// P3_RULE: update rule return_token && (tokens < 3'd7) produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (return_token && (tokens < 3'd7)) |=> (tokens == ($past(tokens) + 3'd1));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!return_token && admit && (tokens > 3'd0)) |=> (tokens == ($past(tokens) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))) |=> (tokens == $past(tokens));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"tokens == 3'd3\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is consistent with the observable register value\",\n \"expression\": \"allow == (tokens != 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule return_token && (tokens < 3'd7) produces the specified next value\",\n \"antecedent\": \"return_token && (tokens < 3'd7)\",\n \"consequent\": \"tokens == ($past(tokens) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\",\n \"antecedent\": \"!return_token && admit && (tokens > 3'd0)\",\n \"consequent\": \"tokens == ($past(tokens) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))\",\n \"consequent\": \"tokens == $past(tokens)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"broaden_second_rule.sv\": \"module rate_limiter_0009_mutant_broaden_second_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\\n else tokens <= tokens - 3'd1;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\", \"drop_first_rule.sv\": \"module rate_limiter_0009_mutant_drop_first_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (!return_token && admit && (tokens > 3'd0)) tokens <= tokens - 3'd1;\\n else tokens <= tokens;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\", \"drop_second_rule.sv\": \"module rate_limiter_0009_mutant_drop_second_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\\n else tokens <= tokens;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\"}"} {"family_id": "rate_limiter_0009", "category": "rate_limiter", "description": "Rate-control state implementing admission tokens.", "rtl_variant": "function_update.sv", "rtl": "module rate_limiter_0009_function_update (\n input wire clk,\n input wire rst,\n input wire admit,\n input wire return_token,\n output reg [2:0] tokens,\n output wire allow\n);\n\n function automatic [2:0] compute_next_tokens;\n input [2:0] current;\n input admit;\n input return_token;\n begin\n if (return_token && (current < 3'd7)) compute_next_tokens = current + 3'd1;\n else if (!return_token && admit && (current > 3'd0)) compute_next_tokens = current - 3'd1;\n else compute_next_tokens = current;\n end\n endfunction\n\n wire [2:0] next_tokens;\n\n assign next_tokens = compute_next_tokens(tokens, admit, return_token);\n\n always @(posedge clk) begin\n if (rst)\n tokens <= 3'd3;\n else\n tokens <= next_tokens;\n end\n\n assign allow = tokens != 3'd0;\nendmodule\n", "spec_json": "{\n \"design_id\": \"rate_limiter_0009\",\n \"category\": \"rate_limiter\",\n \"model_type\": \"register_rules\",\n \"template\": \"admission_tokens\",\n \"description\": \"Rate-control state implementing admission tokens.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"admit\",\n \"return_token\"\n ],\n \"outputs\": [\n \"tokens\",\n \"allow\"\n ],\n \"signal_widths\": {\n \"tokens\": 3\n },\n \"registers\": [\n {\n \"name\": \"tokens\",\n \"width\": 3,\n \"reset_value\": \"3'd3\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"allow\": \"tokens != 3'd0\"\n },\n \"update_rules\": [\n {\n \"when\": \"return_token && (tokens < 3'd7)\",\n \"value\": \"tokens + 3'd1\"\n },\n {\n \"when\": \"!return_token && admit && (tokens > 3'd0)\",\n \"value\": \"tokens - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"tokens\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"tokens == 3'd3\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is consistent with the observable register value\",\n \"expression\": \"allow == (tokens != 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule return_token && (tokens < 3'd7) produces the specified next value\",\n \"antecedent\": \"return_token && (tokens < 3'd7)\",\n \"consequent\": \"tokens == ($past(tokens) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\",\n \"antecedent\": \"!return_token && admit && (tokens > 3'd0)\",\n \"consequent\": \"tokens == ($past(tokens) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))\",\n \"consequent\": \"tokens == $past(tokens)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_first_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"return_token && (tokens < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_second_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!return_token && admit && (tokens > 3'd0)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"broaden_second_rule\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!return_token && admit && (tokens > 3'd0)\",\n \"new\": \"true\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for rate_limiter_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (tokens == 3'd3);\nendproperty\nassert property (p_reset_value);\n\n// P2_ALLOW: allow is consistent with the observable register value\nproperty p_allow;\n @(posedge clk) disable iff (rst) (allow == (tokens != 3'd0));\nendproperty\nassert property (p_allow);\n\n// P3_RULE: update rule return_token && (tokens < 3'd7) produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (return_token && (tokens < 3'd7)) |=> (tokens == ($past(tokens) + 3'd1));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!return_token && admit && (tokens > 3'd0)) |=> (tokens == ($past(tokens) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))) |=> (tokens == $past(tokens));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"tokens == 3'd3\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_ALLOW\",\n \"sva_name\": \"p_allow\",\n \"type\": \"invariant\",\n \"natural_language\": \"allow is consistent with the observable register value\",\n \"expression\": \"allow == (tokens != 3'd0)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule return_token && (tokens < 3'd7) produces the specified next value\",\n \"antecedent\": \"return_token && (tokens < 3'd7)\",\n \"consequent\": \"tokens == ($past(tokens) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !return_token && admit && (tokens > 3'd0) produces the specified next value\",\n \"antecedent\": \"!return_token && admit && (tokens > 3'd0)\",\n \"consequent\": \"tokens == ($past(tokens) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(return_token && (tokens < 3'd7)) && !(!return_token && admit && (tokens > 3'd0))\",\n \"consequent\": \"tokens == $past(tokens)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"broaden_second_rule.sv\": \"module rate_limiter_0009_mutant_broaden_second_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\\n else tokens <= tokens - 3'd1;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\", \"drop_first_rule.sv\": \"module rate_limiter_0009_mutant_drop_first_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (!return_token && admit && (tokens > 3'd0)) tokens <= tokens - 3'd1;\\n else tokens <= tokens;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\", \"drop_second_rule.sv\": \"module rate_limiter_0009_mutant_drop_second_rule (\\n input wire clk,\\n input wire rst,\\n input wire admit,\\n input wire return_token,\\n output reg [2:0] tokens,\\n output wire allow\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n tokens <= 3'd3;\\n end\\n else begin\\n if (return_token && (tokens < 3'd7)) tokens <= tokens + 3'd1;\\n else tokens <= tokens;\\n end\\n end\\n\\n assign allow = tokens != 3'd0;\\nendmodule\\n\"}"} {"family_id": "saturating_arithmetic_0009", "category": "saturating_arithmetic", "description": "Accumulator records whether either saturation boundary has ever been reached.", "rtl_variant": "canonical_next.sv", "rtl": "module saturating_arithmetic_0009_canonical_next (\n input wire clk,\n input wire rst,\n input wire clear_history,\n input wire inc,\n input wire dec,\n output wire [2:0] value,\n output wire hit_low,\n output wire hit_high\n);\n\n reg [2:0] value_reg;\n reg low_reg;\n reg high_reg;\n\n reg [2:0] next_value_reg;\n reg next_low_reg;\n reg next_high_reg;\n\n always @* begin\n if (inc && !dec && (value_reg < 3'd6)) next_value_reg = value_reg + 3'd1;\n else if (dec && !inc && (value_reg > 3'd1)) next_value_reg = value_reg - 3'd1;\n else next_value_reg = value_reg;\n if (clear_history) next_low_reg = 1'b0;\n else if (dec && !inc && (value_reg == 3'd2)) next_low_reg = 1'b1;\n else next_low_reg = low_reg;\n if (clear_history) next_high_reg = 1'b0;\n else if (inc && !dec && (value_reg == 3'd5)) next_high_reg = 1'b1;\n else next_high_reg = high_reg;\n end\n\n always @(posedge clk) begin\n if (rst) begin\n value_reg <= 3'd3;\n low_reg <= 1'b0;\n high_reg <= 1'b0;\n end\n else begin\n value_reg <= next_value_reg;\n low_reg <= next_low_reg;\n high_reg <= next_high_reg;\n end\n end\n\n assign value = value_reg;\n assign hit_low = low_reg;\n assign hit_high = high_reg;\nendmodule\n", "spec_json": "{\n \"design_id\": \"saturating_arithmetic_0009\",\n \"category\": \"saturating_arithmetic\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"saturation_history_accumulator\",\n \"description\": \"Accumulator records whether either saturation boundary has ever been reached.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"clear_history\",\n \"inc\",\n \"dec\"\n ],\n \"outputs\": [\n \"value\",\n \"hit_low\",\n \"hit_high\"\n ],\n \"signal_widths\": {\n \"value\": 3\n },\n \"registers\": [\n {\n \"name\": \"value_reg\",\n \"width\": 3,\n \"reset_value\": \"3'd3\"\n },\n {\n \"name\": \"low_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n },\n {\n \"name\": \"high_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All RTL variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"value\": \"value_reg\",\n \"hit_low\": \"low_reg\",\n \"hit_high\": \"high_reg\"\n },\n \"update_rules\": {\n \"value_reg\": [\n {\n \"when\": \"inc && !dec && (value_reg < 3'd6)\",\n \"value\": \"value_reg + 3'd1\"\n },\n {\n \"when\": \"dec && !inc && (value_reg > 3'd1)\",\n \"value\": \"value_reg - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"value_reg\"\n }\n ],\n \"low_reg\": [\n {\n \"when\": \"clear_history\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"dec && !inc && (value_reg == 3'd2)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"low_reg\"\n }\n ],\n \"high_reg\": [\n {\n \"when\": \"clear_history\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"inc && !dec && (value_reg == 3'd5)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"high_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at the midpoint with clear history\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(value == 3'd3) && !hit_low && !hit_high\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_INC\",\n \"sva_name\": \"p_inc\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive increment advances below the high bound\",\n \"antecedent\": \"inc && !dec && (value < 3'd6)\",\n \"consequent\": \"value == ($past(value) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_DEC\",\n \"sva_name\": \"p_dec\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive decrement advances above the low bound\",\n \"antecedent\": \"dec && !inc && (value > 3'd1)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HIGH_HISTORY\",\n \"sva_name\": \"p_high_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the high boundary records high history\",\n \"antecedent\": \"!clear_history && inc && !dec && (value == 3'd5)\",\n \"consequent\": \"hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_LOW_HISTORY\",\n \"sva_name\": \"p_low_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the low boundary records low history\",\n \"antecedent\": \"!clear_history && dec && !inc && (value == 3'd2)\",\n \"consequent\": \"hit_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLEAR_HISTORY\",\n \"sva_name\": \"p_clear_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"clear_history clears both sticky history bits\",\n \"antecedent\": \"clear_history\",\n \"consequent\": \"!hit_low && !hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"never_record_low\",\n \"register\": \"low_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"dec && !inc && (value_reg == 3'd2)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"never_record_high\",\n \"register\": \"high_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"inc && !dec && (value_reg == 3'd5)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_clear_high\",\n \"register\": \"high_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"clear_history\",\n \"new\": \"false\"\n }\n ]\n}\n", "properties_sva": "// P1_RESET: reset starts at the midpoint with clear history\nproperty p_reset;\n @(posedge clk) (rst) |=> ((value == 3'd3) && !hit_low && !hit_high);\nendproperty\nassert property (p_reset);\n\n// P2_INC: exclusive increment advances below the high bound\nproperty p_inc;\n @(posedge clk) disable iff (rst) (inc && !dec && (value < 3'd6)) |=> (value == ($past(value) + 3'd1));\nendproperty\nassert property (p_inc);\n\n// P3_DEC: exclusive decrement advances above the low bound\nproperty p_dec;\n @(posedge clk) disable iff (rst) (dec && !inc && (value > 3'd1)) |=> (value == ($past(value) - 3'd1));\nendproperty\nassert property (p_dec);\n\n// P4_HIGH_HISTORY: reaching the high boundary records high history\nproperty p_high_history;\n @(posedge clk) disable iff (rst) (!clear_history && inc && !dec && (value == 3'd5)) |=> (hit_high);\nendproperty\nassert property (p_high_history);\n\n// P5_LOW_HISTORY: reaching the low boundary records low history\nproperty p_low_history;\n @(posedge clk) disable iff (rst) (!clear_history && dec && !inc && (value == 3'd2)) |=> (hit_low);\nendproperty\nassert property (p_low_history);\n\n// P6_CLEAR_HISTORY: clear_history clears both sticky history bits\nproperty p_clear_history;\n @(posedge clk) disable iff (rst) (clear_history) |=> (!hit_low && !hit_high);\nendproperty\nassert property (p_clear_history);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at the midpoint with clear history\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(value == 3'd3) && !hit_low && !hit_high\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_INC\",\n \"sva_name\": \"p_inc\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive increment advances below the high bound\",\n \"antecedent\": \"inc && !dec && (value < 3'd6)\",\n \"consequent\": \"value == ($past(value) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_DEC\",\n \"sva_name\": \"p_dec\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive decrement advances above the low bound\",\n \"antecedent\": \"dec && !inc && (value > 3'd1)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HIGH_HISTORY\",\n \"sva_name\": \"p_high_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the high boundary records high history\",\n \"antecedent\": \"!clear_history && inc && !dec && (value == 3'd5)\",\n \"consequent\": \"hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_LOW_HISTORY\",\n \"sva_name\": \"p_low_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the low boundary records low history\",\n \"antecedent\": \"!clear_history && dec && !inc && (value == 3'd2)\",\n \"consequent\": \"hit_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLEAR_HISTORY\",\n \"sva_name\": \"p_clear_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"clear_history clears both sticky history bits\",\n \"antecedent\": \"clear_history\",\n \"consequent\": \"!hit_low && !hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_clear_high.sv\": \"module saturating_arithmetic_0009_mutant_ignore_clear_high (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\\n else low_reg <= low_reg;\\n if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\", \"never_record_high.sv\": \"module saturating_arithmetic_0009_mutant_never_record_high (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\\n else low_reg <= low_reg;\\n if (clear_history) high_reg <= 1'b0;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\", \"never_record_low.sv\": \"module saturating_arithmetic_0009_mutant_never_record_low (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else low_reg <= low_reg;\\n if (clear_history) high_reg <= 1'b0;\\n else if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\"}"} {"family_id": "saturating_arithmetic_0009", "category": "saturating_arithmetic", "description": "Accumulator records whether either saturation boundary has ever been reached.", "rtl_variant": "sequential_priority.sv", "rtl": "module saturating_arithmetic_0009_sequential_priority (\n input wire clk,\n input wire rst,\n input wire clear_history,\n input wire inc,\n input wire dec,\n output wire [2:0] value,\n output wire hit_low,\n output wire hit_high\n);\n\n reg [2:0] value_reg;\n reg low_reg;\n reg high_reg;\n\n always @(posedge clk) begin\n if (rst) begin\n value_reg <= 3'd3;\n low_reg <= 1'b0;\n high_reg <= 1'b0;\n end\n else begin\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\n else value_reg <= value_reg;\n if (clear_history) low_reg <= 1'b0;\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\n else low_reg <= low_reg;\n if (clear_history) high_reg <= 1'b0;\n else if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\n else high_reg <= high_reg;\n end\n end\n\n assign value = value_reg;\n assign hit_low = low_reg;\n assign hit_high = high_reg;\nendmodule\n", "spec_json": "{\n \"design_id\": \"saturating_arithmetic_0009\",\n \"category\": \"saturating_arithmetic\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"saturation_history_accumulator\",\n \"description\": \"Accumulator records whether either saturation boundary has ever been reached.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"clear_history\",\n \"inc\",\n \"dec\"\n ],\n \"outputs\": [\n \"value\",\n \"hit_low\",\n \"hit_high\"\n ],\n \"signal_widths\": {\n \"value\": 3\n },\n \"registers\": [\n {\n \"name\": \"value_reg\",\n \"width\": 3,\n \"reset_value\": \"3'd3\"\n },\n {\n \"name\": \"low_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n },\n {\n \"name\": \"high_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All RTL variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"value\": \"value_reg\",\n \"hit_low\": \"low_reg\",\n \"hit_high\": \"high_reg\"\n },\n \"update_rules\": {\n \"value_reg\": [\n {\n \"when\": \"inc && !dec && (value_reg < 3'd6)\",\n \"value\": \"value_reg + 3'd1\"\n },\n {\n \"when\": \"dec && !inc && (value_reg > 3'd1)\",\n \"value\": \"value_reg - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"value_reg\"\n }\n ],\n \"low_reg\": [\n {\n \"when\": \"clear_history\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"dec && !inc && (value_reg == 3'd2)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"low_reg\"\n }\n ],\n \"high_reg\": [\n {\n \"when\": \"clear_history\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"inc && !dec && (value_reg == 3'd5)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"high_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at the midpoint with clear history\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(value == 3'd3) && !hit_low && !hit_high\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_INC\",\n \"sva_name\": \"p_inc\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive increment advances below the high bound\",\n \"antecedent\": \"inc && !dec && (value < 3'd6)\",\n \"consequent\": \"value == ($past(value) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_DEC\",\n \"sva_name\": \"p_dec\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive decrement advances above the low bound\",\n \"antecedent\": \"dec && !inc && (value > 3'd1)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HIGH_HISTORY\",\n \"sva_name\": \"p_high_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the high boundary records high history\",\n \"antecedent\": \"!clear_history && inc && !dec && (value == 3'd5)\",\n \"consequent\": \"hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_LOW_HISTORY\",\n \"sva_name\": \"p_low_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the low boundary records low history\",\n \"antecedent\": \"!clear_history && dec && !inc && (value == 3'd2)\",\n \"consequent\": \"hit_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLEAR_HISTORY\",\n \"sva_name\": \"p_clear_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"clear_history clears both sticky history bits\",\n \"antecedent\": \"clear_history\",\n \"consequent\": \"!hit_low && !hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"never_record_low\",\n \"register\": \"low_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"dec && !inc && (value_reg == 3'd2)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"never_record_high\",\n \"register\": \"high_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"inc && !dec && (value_reg == 3'd5)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_clear_high\",\n \"register\": \"high_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"clear_history\",\n \"new\": \"false\"\n }\n ]\n}\n", "properties_sva": "// P1_RESET: reset starts at the midpoint with clear history\nproperty p_reset;\n @(posedge clk) (rst) |=> ((value == 3'd3) && !hit_low && !hit_high);\nendproperty\nassert property (p_reset);\n\n// P2_INC: exclusive increment advances below the high bound\nproperty p_inc;\n @(posedge clk) disable iff (rst) (inc && !dec && (value < 3'd6)) |=> (value == ($past(value) + 3'd1));\nendproperty\nassert property (p_inc);\n\n// P3_DEC: exclusive decrement advances above the low bound\nproperty p_dec;\n @(posedge clk) disable iff (rst) (dec && !inc && (value > 3'd1)) |=> (value == ($past(value) - 3'd1));\nendproperty\nassert property (p_dec);\n\n// P4_HIGH_HISTORY: reaching the high boundary records high history\nproperty p_high_history;\n @(posedge clk) disable iff (rst) (!clear_history && inc && !dec && (value == 3'd5)) |=> (hit_high);\nendproperty\nassert property (p_high_history);\n\n// P5_LOW_HISTORY: reaching the low boundary records low history\nproperty p_low_history;\n @(posedge clk) disable iff (rst) (!clear_history && dec && !inc && (value == 3'd2)) |=> (hit_low);\nendproperty\nassert property (p_low_history);\n\n// P6_CLEAR_HISTORY: clear_history clears both sticky history bits\nproperty p_clear_history;\n @(posedge clk) disable iff (rst) (clear_history) |=> (!hit_low && !hit_high);\nendproperty\nassert property (p_clear_history);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at the midpoint with clear history\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(value == 3'd3) && !hit_low && !hit_high\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_INC\",\n \"sva_name\": \"p_inc\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive increment advances below the high bound\",\n \"antecedent\": \"inc && !dec && (value < 3'd6)\",\n \"consequent\": \"value == ($past(value) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_DEC\",\n \"sva_name\": \"p_dec\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive decrement advances above the low bound\",\n \"antecedent\": \"dec && !inc && (value > 3'd1)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HIGH_HISTORY\",\n \"sva_name\": \"p_high_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the high boundary records high history\",\n \"antecedent\": \"!clear_history && inc && !dec && (value == 3'd5)\",\n \"consequent\": \"hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_LOW_HISTORY\",\n \"sva_name\": \"p_low_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the low boundary records low history\",\n \"antecedent\": \"!clear_history && dec && !inc && (value == 3'd2)\",\n \"consequent\": \"hit_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLEAR_HISTORY\",\n \"sva_name\": \"p_clear_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"clear_history clears both sticky history bits\",\n \"antecedent\": \"clear_history\",\n \"consequent\": \"!hit_low && !hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_clear_high.sv\": \"module saturating_arithmetic_0009_mutant_ignore_clear_high (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\\n else low_reg <= low_reg;\\n if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\", \"never_record_high.sv\": \"module saturating_arithmetic_0009_mutant_never_record_high (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\\n else low_reg <= low_reg;\\n if (clear_history) high_reg <= 1'b0;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\", \"never_record_low.sv\": \"module saturating_arithmetic_0009_mutant_never_record_low (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else low_reg <= low_reg;\\n if (clear_history) high_reg <= 1'b0;\\n else if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\"}"} {"family_id": "saturating_arithmetic_0009", "category": "saturating_arithmetic", "description": "Accumulator records whether either saturation boundary has ever been reached.", "rtl_variant": "ternary_next.sv", "rtl": "module saturating_arithmetic_0009_ternary_next (\n input wire clk,\n input wire rst,\n input wire clear_history,\n input wire inc,\n input wire dec,\n output wire [2:0] value,\n output wire hit_low,\n output wire hit_high\n);\n\n reg [2:0] value_reg;\n reg low_reg;\n reg high_reg;\n\n wire [2:0] next_value_reg;\n wire next_low_reg;\n wire next_high_reg;\n\n assign next_value_reg = (inc && !dec && (value_reg < 3'd6)) ? (value_reg + 3'd1) : ((dec && !inc && (value_reg > 3'd1)) ? (value_reg - 3'd1) : (value_reg));\n assign next_low_reg = (clear_history) ? (1'b0) : ((dec && !inc && (value_reg == 3'd2)) ? (1'b1) : (low_reg));\n assign next_high_reg = (clear_history) ? (1'b0) : ((inc && !dec && (value_reg == 3'd5)) ? (1'b1) : (high_reg));\n\n always @(posedge clk) begin\n if (rst) begin\n value_reg <= 3'd3;\n low_reg <= 1'b0;\n high_reg <= 1'b0;\n end\n else begin\n value_reg <= next_value_reg;\n low_reg <= next_low_reg;\n high_reg <= next_high_reg;\n end\n end\n\n assign value = value_reg;\n assign hit_low = low_reg;\n assign hit_high = high_reg;\nendmodule\n", "spec_json": "{\n \"design_id\": \"saturating_arithmetic_0009\",\n \"category\": \"saturating_arithmetic\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"saturation_history_accumulator\",\n \"description\": \"Accumulator records whether either saturation boundary has ever been reached.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"clear_history\",\n \"inc\",\n \"dec\"\n ],\n \"outputs\": [\n \"value\",\n \"hit_low\",\n \"hit_high\"\n ],\n \"signal_widths\": {\n \"value\": 3\n },\n \"registers\": [\n {\n \"name\": \"value_reg\",\n \"width\": 3,\n \"reset_value\": \"3'd3\"\n },\n {\n \"name\": \"low_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n },\n {\n \"name\": \"high_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All RTL variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"value\": \"value_reg\",\n \"hit_low\": \"low_reg\",\n \"hit_high\": \"high_reg\"\n },\n \"update_rules\": {\n \"value_reg\": [\n {\n \"when\": \"inc && !dec && (value_reg < 3'd6)\",\n \"value\": \"value_reg + 3'd1\"\n },\n {\n \"when\": \"dec && !inc && (value_reg > 3'd1)\",\n \"value\": \"value_reg - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"value_reg\"\n }\n ],\n \"low_reg\": [\n {\n \"when\": \"clear_history\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"dec && !inc && (value_reg == 3'd2)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"low_reg\"\n }\n ],\n \"high_reg\": [\n {\n \"when\": \"clear_history\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"inc && !dec && (value_reg == 3'd5)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"high_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at the midpoint with clear history\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(value == 3'd3) && !hit_low && !hit_high\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_INC\",\n \"sva_name\": \"p_inc\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive increment advances below the high bound\",\n \"antecedent\": \"inc && !dec && (value < 3'd6)\",\n \"consequent\": \"value == ($past(value) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_DEC\",\n \"sva_name\": \"p_dec\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive decrement advances above the low bound\",\n \"antecedent\": \"dec && !inc && (value > 3'd1)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HIGH_HISTORY\",\n \"sva_name\": \"p_high_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the high boundary records high history\",\n \"antecedent\": \"!clear_history && inc && !dec && (value == 3'd5)\",\n \"consequent\": \"hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_LOW_HISTORY\",\n \"sva_name\": \"p_low_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the low boundary records low history\",\n \"antecedent\": \"!clear_history && dec && !inc && (value == 3'd2)\",\n \"consequent\": \"hit_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLEAR_HISTORY\",\n \"sva_name\": \"p_clear_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"clear_history clears both sticky history bits\",\n \"antecedent\": \"clear_history\",\n \"consequent\": \"!hit_low && !hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"never_record_low\",\n \"register\": \"low_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"dec && !inc && (value_reg == 3'd2)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"never_record_high\",\n \"register\": \"high_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"inc && !dec && (value_reg == 3'd5)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_clear_high\",\n \"register\": \"high_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"clear_history\",\n \"new\": \"false\"\n }\n ]\n}\n", "properties_sva": "// P1_RESET: reset starts at the midpoint with clear history\nproperty p_reset;\n @(posedge clk) (rst) |=> ((value == 3'd3) && !hit_low && !hit_high);\nendproperty\nassert property (p_reset);\n\n// P2_INC: exclusive increment advances below the high bound\nproperty p_inc;\n @(posedge clk) disable iff (rst) (inc && !dec && (value < 3'd6)) |=> (value == ($past(value) + 3'd1));\nendproperty\nassert property (p_inc);\n\n// P3_DEC: exclusive decrement advances above the low bound\nproperty p_dec;\n @(posedge clk) disable iff (rst) (dec && !inc && (value > 3'd1)) |=> (value == ($past(value) - 3'd1));\nendproperty\nassert property (p_dec);\n\n// P4_HIGH_HISTORY: reaching the high boundary records high history\nproperty p_high_history;\n @(posedge clk) disable iff (rst) (!clear_history && inc && !dec && (value == 3'd5)) |=> (hit_high);\nendproperty\nassert property (p_high_history);\n\n// P5_LOW_HISTORY: reaching the low boundary records low history\nproperty p_low_history;\n @(posedge clk) disable iff (rst) (!clear_history && dec && !inc && (value == 3'd2)) |=> (hit_low);\nendproperty\nassert property (p_low_history);\n\n// P6_CLEAR_HISTORY: clear_history clears both sticky history bits\nproperty p_clear_history;\n @(posedge clk) disable iff (rst) (clear_history) |=> (!hit_low && !hit_high);\nendproperty\nassert property (p_clear_history);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at the midpoint with clear history\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(value == 3'd3) && !hit_low && !hit_high\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_INC\",\n \"sva_name\": \"p_inc\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive increment advances below the high bound\",\n \"antecedent\": \"inc && !dec && (value < 3'd6)\",\n \"consequent\": \"value == ($past(value) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_DEC\",\n \"sva_name\": \"p_dec\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive decrement advances above the low bound\",\n \"antecedent\": \"dec && !inc && (value > 3'd1)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HIGH_HISTORY\",\n \"sva_name\": \"p_high_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the high boundary records high history\",\n \"antecedent\": \"!clear_history && inc && !dec && (value == 3'd5)\",\n \"consequent\": \"hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_LOW_HISTORY\",\n \"sva_name\": \"p_low_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the low boundary records low history\",\n \"antecedent\": \"!clear_history && dec && !inc && (value == 3'd2)\",\n \"consequent\": \"hit_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLEAR_HISTORY\",\n \"sva_name\": \"p_clear_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"clear_history clears both sticky history bits\",\n \"antecedent\": \"clear_history\",\n \"consequent\": \"!hit_low && !hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_clear_high.sv\": \"module saturating_arithmetic_0009_mutant_ignore_clear_high (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\\n else low_reg <= low_reg;\\n if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\", \"never_record_high.sv\": \"module saturating_arithmetic_0009_mutant_never_record_high (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\\n else low_reg <= low_reg;\\n if (clear_history) high_reg <= 1'b0;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\", \"never_record_low.sv\": \"module saturating_arithmetic_0009_mutant_never_record_low (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else low_reg <= low_reg;\\n if (clear_history) high_reg <= 1'b0;\\n else if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\"}"} {"family_id": "saturating_arithmetic_0009", "category": "saturating_arithmetic", "description": "Accumulator records whether either saturation boundary has ever been reached.", "rtl_variant": "function_update.sv", "rtl": "module saturating_arithmetic_0009_function_update (\n input wire clk,\n input wire rst,\n input wire clear_history,\n input wire inc,\n input wire dec,\n output wire [2:0] value,\n output wire hit_low,\n output wire hit_high\n);\n\n reg [2:0] value_reg;\n reg low_reg;\n reg high_reg;\n\n function automatic [2:0] compute_next_value_reg;\n input [2:0] current_value_reg;\n input current_low_reg;\n input current_high_reg;\n input clear_history;\n input inc;\n input dec;\n begin\n if (inc && !dec && (current_value_reg < 3'd6)) compute_next_value_reg = current_value_reg + 3'd1;\n else if (dec && !inc && (current_value_reg > 3'd1)) compute_next_value_reg = current_value_reg - 3'd1;\n else compute_next_value_reg = current_value_reg;\n end\n endfunction\n\n function automatic compute_next_low_reg;\n input [2:0] current_value_reg;\n input current_low_reg;\n input current_high_reg;\n input clear_history;\n input inc;\n input dec;\n begin\n if (clear_history) compute_next_low_reg = 1'b0;\n else if (dec && !inc && (current_value_reg == 3'd2)) compute_next_low_reg = 1'b1;\n else compute_next_low_reg = current_low_reg;\n end\n endfunction\n\n function automatic compute_next_high_reg;\n input [2:0] current_value_reg;\n input current_low_reg;\n input current_high_reg;\n input clear_history;\n input inc;\n input dec;\n begin\n if (clear_history) compute_next_high_reg = 1'b0;\n else if (inc && !dec && (current_value_reg == 3'd5)) compute_next_high_reg = 1'b1;\n else compute_next_high_reg = current_high_reg;\n end\n endfunction\n\n wire [2:0] next_value_reg;\n wire next_low_reg;\n wire next_high_reg;\n\n assign next_value_reg = compute_next_value_reg(value_reg, low_reg, high_reg, clear_history, inc, dec);\n assign next_low_reg = compute_next_low_reg(value_reg, low_reg, high_reg, clear_history, inc, dec);\n assign next_high_reg = compute_next_high_reg(value_reg, low_reg, high_reg, clear_history, inc, dec);\n\n always @(posedge clk) begin\n if (rst) begin\n value_reg <= 3'd3;\n low_reg <= 1'b0;\n high_reg <= 1'b0;\n end\n else begin\n value_reg <= next_value_reg;\n low_reg <= next_low_reg;\n high_reg <= next_high_reg;\n end\n end\n\n assign value = value_reg;\n assign hit_low = low_reg;\n assign hit_high = high_reg;\nendmodule\n", "spec_json": "{\n \"design_id\": \"saturating_arithmetic_0009\",\n \"category\": \"saturating_arithmetic\",\n \"model_type\": \"multi_register_rules\",\n \"template\": \"saturation_history_accumulator\",\n \"description\": \"Accumulator records whether either saturation boundary has ever been reached.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"clear_history\",\n \"inc\",\n \"dec\"\n ],\n \"outputs\": [\n \"value\",\n \"hit_low\",\n \"hit_high\"\n ],\n \"signal_widths\": {\n \"value\": 3\n },\n \"registers\": [\n {\n \"name\": \"value_reg\",\n \"width\": 3,\n \"reset_value\": \"3'd3\"\n },\n {\n \"name\": \"low_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n },\n {\n \"name\": \"high_reg\",\n \"width\": 1,\n \"reset_value\": \"1'b0\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"Properties use interface-visible behavior only.\",\n \"All RTL variants must be observationally equivalent.\"\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"manually_authored\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n },\n \"derived_outputs\": {\n \"value\": \"value_reg\",\n \"hit_low\": \"low_reg\",\n \"hit_high\": \"high_reg\"\n },\n \"update_rules\": {\n \"value_reg\": [\n {\n \"when\": \"inc && !dec && (value_reg < 3'd6)\",\n \"value\": \"value_reg + 3'd1\"\n },\n {\n \"when\": \"dec && !inc && (value_reg > 3'd1)\",\n \"value\": \"value_reg - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"value_reg\"\n }\n ],\n \"low_reg\": [\n {\n \"when\": \"clear_history\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"dec && !inc && (value_reg == 3'd2)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"low_reg\"\n }\n ],\n \"high_reg\": [\n {\n \"when\": \"clear_history\",\n \"value\": \"1'b0\"\n },\n {\n \"when\": \"inc && !dec && (value_reg == 3'd5)\",\n \"value\": \"1'b1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"high_reg\"\n }\n ]\n },\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at the midpoint with clear history\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(value == 3'd3) && !hit_low && !hit_high\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_INC\",\n \"sva_name\": \"p_inc\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive increment advances below the high bound\",\n \"antecedent\": \"inc && !dec && (value < 3'd6)\",\n \"consequent\": \"value == ($past(value) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_DEC\",\n \"sva_name\": \"p_dec\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive decrement advances above the low bound\",\n \"antecedent\": \"dec && !inc && (value > 3'd1)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HIGH_HISTORY\",\n \"sva_name\": \"p_high_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the high boundary records high history\",\n \"antecedent\": \"!clear_history && inc && !dec && (value == 3'd5)\",\n \"consequent\": \"hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_LOW_HISTORY\",\n \"sva_name\": \"p_low_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the low boundary records low history\",\n \"antecedent\": \"!clear_history && dec && !inc && (value == 3'd2)\",\n \"consequent\": \"hit_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLEAR_HISTORY\",\n \"sva_name\": \"p_clear_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"clear_history clears both sticky history bits\",\n \"antecedent\": \"clear_history\",\n \"consequent\": \"!hit_low && !hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"never_record_low\",\n \"register\": \"low_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"dec && !inc && (value_reg == 3'd2)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"never_record_high\",\n \"register\": \"high_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"inc && !dec && (value_reg == 3'd5)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_clear_high\",\n \"register\": \"high_reg\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"clear_history\",\n \"new\": \"false\"\n }\n ]\n}\n", "properties_sva": "// P1_RESET: reset starts at the midpoint with clear history\nproperty p_reset;\n @(posedge clk) (rst) |=> ((value == 3'd3) && !hit_low && !hit_high);\nendproperty\nassert property (p_reset);\n\n// P2_INC: exclusive increment advances below the high bound\nproperty p_inc;\n @(posedge clk) disable iff (rst) (inc && !dec && (value < 3'd6)) |=> (value == ($past(value) + 3'd1));\nendproperty\nassert property (p_inc);\n\n// P3_DEC: exclusive decrement advances above the low bound\nproperty p_dec;\n @(posedge clk) disable iff (rst) (dec && !inc && (value > 3'd1)) |=> (value == ($past(value) - 3'd1));\nendproperty\nassert property (p_dec);\n\n// P4_HIGH_HISTORY: reaching the high boundary records high history\nproperty p_high_history;\n @(posedge clk) disable iff (rst) (!clear_history && inc && !dec && (value == 3'd5)) |=> (hit_high);\nendproperty\nassert property (p_high_history);\n\n// P5_LOW_HISTORY: reaching the low boundary records low history\nproperty p_low_history;\n @(posedge clk) disable iff (rst) (!clear_history && dec && !inc && (value == 3'd2)) |=> (hit_low);\nendproperty\nassert property (p_low_history);\n\n// P6_CLEAR_HISTORY: clear_history clears both sticky history bits\nproperty p_clear_history;\n @(posedge clk) disable iff (rst) (clear_history) |=> (!hit_low && !hit_high);\nendproperty\nassert property (p_clear_history);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset starts at the midpoint with clear history\",\n \"antecedent\": \"rst\",\n \"consequent\": \"(value == 3'd3) && !hit_low && !hit_high\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_INC\",\n \"sva_name\": \"p_inc\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive increment advances below the high bound\",\n \"antecedent\": \"inc && !dec && (value < 3'd6)\",\n \"consequent\": \"value == ($past(value) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_DEC\",\n \"sva_name\": \"p_dec\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"exclusive decrement advances above the low bound\",\n \"antecedent\": \"dec && !inc && (value > 3'd1)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_HIGH_HISTORY\",\n \"sva_name\": \"p_high_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the high boundary records high history\",\n \"antecedent\": \"!clear_history && inc && !dec && (value == 3'd5)\",\n \"consequent\": \"hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_LOW_HISTORY\",\n \"sva_name\": \"p_low_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reaching the low boundary records low history\",\n \"antecedent\": \"!clear_history && dec && !inc && (value == 3'd2)\",\n \"consequent\": \"hit_low\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_CLEAR_HISTORY\",\n \"sva_name\": \"p_clear_history\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"clear_history clears both sticky history bits\",\n \"antecedent\": \"clear_history\",\n \"consequent\": \"!hit_low && !hit_high\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_clear_high.sv\": \"module saturating_arithmetic_0009_mutant_ignore_clear_high (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\\n else low_reg <= low_reg;\\n if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\", \"never_record_high.sv\": \"module saturating_arithmetic_0009_mutant_never_record_high (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else if (dec && !inc && (value_reg == 3'd2)) low_reg <= 1'b1;\\n else low_reg <= low_reg;\\n if (clear_history) high_reg <= 1'b0;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\", \"never_record_low.sv\": \"module saturating_arithmetic_0009_mutant_never_record_low (\\n input wire clk,\\n input wire rst,\\n input wire clear_history,\\n input wire inc,\\n input wire dec,\\n output wire [2:0] value,\\n output wire hit_low,\\n output wire hit_high\\n);\\n\\n reg [2:0] value_reg;\\n reg low_reg;\\n reg high_reg;\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value_reg <= 3'd3;\\n low_reg <= 1'b0;\\n high_reg <= 1'b0;\\n end\\n else begin\\n if (inc && !dec && (value_reg < 3'd6)) value_reg <= value_reg + 3'd1;\\n else if (dec && !inc && (value_reg > 3'd1)) value_reg <= value_reg - 3'd1;\\n else value_reg <= value_reg;\\n if (clear_history) low_reg <= 1'b0;\\n else low_reg <= low_reg;\\n if (clear_history) high_reg <= 1'b0;\\n else if (inc && !dec && (value_reg == 3'd5)) high_reg <= 1'b1;\\n else high_reg <= high_reg;\\n end\\n end\\n\\n assign value = value_reg;\\n assign hit_low = low_reg;\\n assign hit_high = high_reg;\\nendmodule\\n\"}"} {"family_id": "saturating_arithmetic_0007", "category": "saturating_arithmetic", "description": "Saturating arithmetic unit implementing sat floor two.", "rtl_variant": "canonical_next.sv", "rtl": "module saturating_arithmetic_0007_canonical_next (\n input wire clk,\n input wire rst,\n input wire dec,\n input wire restore,\n output reg [2:0] value,\n output wire at_floor\n);\n\n reg [2:0] next_value;\n\n always @* begin\n if (restore) next_value = 3'd7;\n else if (!restore && dec && (value > 3'd2)) next_value = value - 3'd1;\n else next_value = value;\n end\n\n always @(posedge clk) begin\n if (rst)\n value <= 3'd7;\n else\n value <= next_value;\n end\n\n assign at_floor = value == 3'd2;\nendmodule\n", "spec_json": "{\n \"design_id\": \"saturating_arithmetic_0007\",\n \"category\": \"saturating_arithmetic\",\n \"model_type\": \"register_rules\",\n \"template\": \"sat_floor_two\",\n \"description\": \"Saturating arithmetic unit implementing sat floor two.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"dec\",\n \"restore\"\n ],\n \"outputs\": [\n \"value\",\n \"at_floor\"\n ],\n \"signal_widths\": {\n \"value\": 3\n },\n \"registers\": [\n {\n \"name\": \"value\",\n \"width\": 3,\n \"reset_value\": \"3'd7\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_floor\": \"value == 3'd2\"\n },\n \"update_rules\": [\n {\n \"when\": \"restore\",\n \"value\": \"3'd7\"\n },\n {\n \"when\": \"!restore && dec && (value > 3'd2)\",\n \"value\": \"value - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"value\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"value == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_FLOOR\",\n \"sva_name\": \"p_at_floor\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_floor is consistent with the observable register value\",\n \"expression\": \"at_floor == (value == 3'd2)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule restore produces the specified next value\",\n \"antecedent\": \"restore\",\n \"consequent\": \"value == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !restore && dec && (value > 3'd2) produces the specified next value\",\n \"antecedent\": \"!restore && dec && (value > 3'd2)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(restore) && !(!restore && dec && (value > 3'd2))\",\n \"consequent\": \"value == $past(value)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_rule_1\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"restore\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_rule_2\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!restore && dec && (value > 3'd2)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"broaden_rule_3\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!restore && dec && (value > 3'd2)\",\n \"new\": \"true\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for saturating_arithmetic_0007\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (value == 3'd7);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_FLOOR: at_floor is consistent with the observable register value\nproperty p_at_floor;\n @(posedge clk) disable iff (rst) (at_floor == (value == 3'd2));\nendproperty\nassert property (p_at_floor);\n\n// P3_RULE: update rule restore produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (restore) |=> (value == (3'd7));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !restore && dec && (value > 3'd2) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!restore && dec && (value > 3'd2)) |=> (value == ($past(value) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(restore) && !(!restore && dec && (value > 3'd2))) |=> (value == $past(value));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"value == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_FLOOR\",\n \"sva_name\": \"p_at_floor\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_floor is consistent with the observable register value\",\n \"expression\": \"at_floor == (value == 3'd2)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule restore produces the specified next value\",\n \"antecedent\": \"restore\",\n \"consequent\": \"value == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !restore && dec && (value > 3'd2) produces the specified next value\",\n \"antecedent\": \"!restore && dec && (value > 3'd2)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(restore) && !(!restore && dec && (value > 3'd2))\",\n \"consequent\": \"value == $past(value)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"broaden_rule_3.sv\": \"module saturating_arithmetic_0007_mutant_broaden_rule_3 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (restore) value <= 3'd7;\\n else value <= value - 3'd1;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\", \"drop_rule_1.sv\": \"module saturating_arithmetic_0007_mutant_drop_rule_1 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (!restore && dec && (value > 3'd2)) value <= value - 3'd1;\\n else value <= value;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\", \"drop_rule_2.sv\": \"module saturating_arithmetic_0007_mutant_drop_rule_2 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (restore) value <= 3'd7;\\n else value <= value;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\"}"} {"family_id": "saturating_arithmetic_0007", "category": "saturating_arithmetic", "description": "Saturating arithmetic unit implementing sat floor two.", "rtl_variant": "sequential_priority.sv", "rtl": "module saturating_arithmetic_0007_sequential_priority (\n input wire clk,\n input wire rst,\n input wire dec,\n input wire restore,\n output reg [2:0] value,\n output wire at_floor\n);\n\n always @(posedge clk) begin\n if (rst) begin\n value <= 3'd7;\n end\n else begin\n if (restore) value <= 3'd7;\n else if (!restore && dec && (value > 3'd2)) value <= value - 3'd1;\n else value <= value;\n end\n end\n\n assign at_floor = value == 3'd2;\nendmodule\n", "spec_json": "{\n \"design_id\": \"saturating_arithmetic_0007\",\n \"category\": \"saturating_arithmetic\",\n \"model_type\": \"register_rules\",\n \"template\": \"sat_floor_two\",\n \"description\": \"Saturating arithmetic unit implementing sat floor two.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"dec\",\n \"restore\"\n ],\n \"outputs\": [\n \"value\",\n \"at_floor\"\n ],\n \"signal_widths\": {\n \"value\": 3\n },\n \"registers\": [\n {\n \"name\": \"value\",\n \"width\": 3,\n \"reset_value\": \"3'd7\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_floor\": \"value == 3'd2\"\n },\n \"update_rules\": [\n {\n \"when\": \"restore\",\n \"value\": \"3'd7\"\n },\n {\n \"when\": \"!restore && dec && (value > 3'd2)\",\n \"value\": \"value - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"value\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"value == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_FLOOR\",\n \"sva_name\": \"p_at_floor\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_floor is consistent with the observable register value\",\n \"expression\": \"at_floor == (value == 3'd2)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule restore produces the specified next value\",\n \"antecedent\": \"restore\",\n \"consequent\": \"value == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !restore && dec && (value > 3'd2) produces the specified next value\",\n \"antecedent\": \"!restore && dec && (value > 3'd2)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(restore) && !(!restore && dec && (value > 3'd2))\",\n \"consequent\": \"value == $past(value)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_rule_1\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"restore\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_rule_2\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!restore && dec && (value > 3'd2)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"broaden_rule_3\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!restore && dec && (value > 3'd2)\",\n \"new\": \"true\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for saturating_arithmetic_0007\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (value == 3'd7);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_FLOOR: at_floor is consistent with the observable register value\nproperty p_at_floor;\n @(posedge clk) disable iff (rst) (at_floor == (value == 3'd2));\nendproperty\nassert property (p_at_floor);\n\n// P3_RULE: update rule restore produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (restore) |=> (value == (3'd7));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !restore && dec && (value > 3'd2) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!restore && dec && (value > 3'd2)) |=> (value == ($past(value) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(restore) && !(!restore && dec && (value > 3'd2))) |=> (value == $past(value));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"value == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_FLOOR\",\n \"sva_name\": \"p_at_floor\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_floor is consistent with the observable register value\",\n \"expression\": \"at_floor == (value == 3'd2)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule restore produces the specified next value\",\n \"antecedent\": \"restore\",\n \"consequent\": \"value == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !restore && dec && (value > 3'd2) produces the specified next value\",\n \"antecedent\": \"!restore && dec && (value > 3'd2)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(restore) && !(!restore && dec && (value > 3'd2))\",\n \"consequent\": \"value == $past(value)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"broaden_rule_3.sv\": \"module saturating_arithmetic_0007_mutant_broaden_rule_3 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (restore) value <= 3'd7;\\n else value <= value - 3'd1;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\", \"drop_rule_1.sv\": \"module saturating_arithmetic_0007_mutant_drop_rule_1 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (!restore && dec && (value > 3'd2)) value <= value - 3'd1;\\n else value <= value;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\", \"drop_rule_2.sv\": \"module saturating_arithmetic_0007_mutant_drop_rule_2 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (restore) value <= 3'd7;\\n else value <= value;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\"}"} {"family_id": "saturating_arithmetic_0007", "category": "saturating_arithmetic", "description": "Saturating arithmetic unit implementing sat floor two.", "rtl_variant": "ternary_next.sv", "rtl": "module saturating_arithmetic_0007_ternary_next (\n input wire clk,\n input wire rst,\n input wire dec,\n input wire restore,\n output reg [2:0] value,\n output wire at_floor\n);\n\n wire [2:0] next_value;\n\n assign next_value = (restore) ? (3'd7) : ((!restore && dec && (value > 3'd2)) ? (value - 3'd1) : (value));\n\n always @(posedge clk) begin\n if (rst)\n value <= 3'd7;\n else\n value <= next_value;\n end\n\n assign at_floor = value == 3'd2;\nendmodule\n", "spec_json": "{\n \"design_id\": \"saturating_arithmetic_0007\",\n \"category\": \"saturating_arithmetic\",\n \"model_type\": \"register_rules\",\n \"template\": \"sat_floor_two\",\n \"description\": \"Saturating arithmetic unit implementing sat floor two.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"dec\",\n \"restore\"\n ],\n \"outputs\": [\n \"value\",\n \"at_floor\"\n ],\n \"signal_widths\": {\n \"value\": 3\n },\n \"registers\": [\n {\n \"name\": \"value\",\n \"width\": 3,\n \"reset_value\": \"3'd7\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_floor\": \"value == 3'd2\"\n },\n \"update_rules\": [\n {\n \"when\": \"restore\",\n \"value\": \"3'd7\"\n },\n {\n \"when\": \"!restore && dec && (value > 3'd2)\",\n \"value\": \"value - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"value\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"value == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_FLOOR\",\n \"sva_name\": \"p_at_floor\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_floor is consistent with the observable register value\",\n \"expression\": \"at_floor == (value == 3'd2)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule restore produces the specified next value\",\n \"antecedent\": \"restore\",\n \"consequent\": \"value == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !restore && dec && (value > 3'd2) produces the specified next value\",\n \"antecedent\": \"!restore && dec && (value > 3'd2)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(restore) && !(!restore && dec && (value > 3'd2))\",\n \"consequent\": \"value == $past(value)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_rule_1\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"restore\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_rule_2\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!restore && dec && (value > 3'd2)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"broaden_rule_3\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!restore && dec && (value > 3'd2)\",\n \"new\": \"true\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for saturating_arithmetic_0007\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (value == 3'd7);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_FLOOR: at_floor is consistent with the observable register value\nproperty p_at_floor;\n @(posedge clk) disable iff (rst) (at_floor == (value == 3'd2));\nendproperty\nassert property (p_at_floor);\n\n// P3_RULE: update rule restore produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (restore) |=> (value == (3'd7));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !restore && dec && (value > 3'd2) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!restore && dec && (value > 3'd2)) |=> (value == ($past(value) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(restore) && !(!restore && dec && (value > 3'd2))) |=> (value == $past(value));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"value == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_FLOOR\",\n \"sva_name\": \"p_at_floor\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_floor is consistent with the observable register value\",\n \"expression\": \"at_floor == (value == 3'd2)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule restore produces the specified next value\",\n \"antecedent\": \"restore\",\n \"consequent\": \"value == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !restore && dec && (value > 3'd2) produces the specified next value\",\n \"antecedent\": \"!restore && dec && (value > 3'd2)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(restore) && !(!restore && dec && (value > 3'd2))\",\n \"consequent\": \"value == $past(value)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"broaden_rule_3.sv\": \"module saturating_arithmetic_0007_mutant_broaden_rule_3 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (restore) value <= 3'd7;\\n else value <= value - 3'd1;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\", \"drop_rule_1.sv\": \"module saturating_arithmetic_0007_mutant_drop_rule_1 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (!restore && dec && (value > 3'd2)) value <= value - 3'd1;\\n else value <= value;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\", \"drop_rule_2.sv\": \"module saturating_arithmetic_0007_mutant_drop_rule_2 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (restore) value <= 3'd7;\\n else value <= value;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\"}"} {"family_id": "saturating_arithmetic_0007", "category": "saturating_arithmetic", "description": "Saturating arithmetic unit implementing sat floor two.", "rtl_variant": "function_update.sv", "rtl": "module saturating_arithmetic_0007_function_update (\n input wire clk,\n input wire rst,\n input wire dec,\n input wire restore,\n output reg [2:0] value,\n output wire at_floor\n);\n\n function automatic [2:0] compute_next_value;\n input [2:0] current;\n input dec;\n input restore;\n begin\n if (restore) compute_next_value = 3'd7;\n else if (!restore && dec && (current > 3'd2)) compute_next_value = current - 3'd1;\n else compute_next_value = current;\n end\n endfunction\n\n wire [2:0] next_value;\n\n assign next_value = compute_next_value(value, dec, restore);\n\n always @(posedge clk) begin\n if (rst)\n value <= 3'd7;\n else\n value <= next_value;\n end\n\n assign at_floor = value == 3'd2;\nendmodule\n", "spec_json": "{\n \"design_id\": \"saturating_arithmetic_0007\",\n \"category\": \"saturating_arithmetic\",\n \"model_type\": \"register_rules\",\n \"template\": \"sat_floor_two\",\n \"description\": \"Saturating arithmetic unit implementing sat floor two.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"dec\",\n \"restore\"\n ],\n \"outputs\": [\n \"value\",\n \"at_floor\"\n ],\n \"signal_widths\": {\n \"value\": 3\n },\n \"registers\": [\n {\n \"name\": \"value\",\n \"width\": 3,\n \"reset_value\": \"3'd7\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"at_floor\": \"value == 3'd2\"\n },\n \"update_rules\": [\n {\n \"when\": \"restore\",\n \"value\": \"3'd7\"\n },\n {\n \"when\": \"!restore && dec && (value > 3'd2)\",\n \"value\": \"value - 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"value\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"value == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_FLOOR\",\n \"sva_name\": \"p_at_floor\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_floor is consistent with the observable register value\",\n \"expression\": \"at_floor == (value == 3'd2)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule restore produces the specified next value\",\n \"antecedent\": \"restore\",\n \"consequent\": \"value == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !restore && dec && (value > 3'd2) produces the specified next value\",\n \"antecedent\": \"!restore && dec && (value > 3'd2)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(restore) && !(!restore && dec && (value > 3'd2))\",\n \"consequent\": \"value == $past(value)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_rule_1\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"restore\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_rule_2\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!restore && dec && (value > 3'd2)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"broaden_rule_3\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!restore && dec && (value > 3'd2)\",\n \"new\": \"true\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for saturating_arithmetic_0007\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (value == 3'd7);\nendproperty\nassert property (p_reset_value);\n\n// P2_AT_FLOOR: at_floor is consistent with the observable register value\nproperty p_at_floor;\n @(posedge clk) disable iff (rst) (at_floor == (value == 3'd2));\nendproperty\nassert property (p_at_floor);\n\n// P3_RULE: update rule restore produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (restore) |=> (value == (3'd7));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !restore && dec && (value > 3'd2) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!restore && dec && (value > 3'd2)) |=> (value == ($past(value) - 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(restore) && !(!restore && dec && (value > 3'd2))) |=> (value == $past(value));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"value == 3'd7\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_AT_FLOOR\",\n \"sva_name\": \"p_at_floor\",\n \"type\": \"invariant\",\n \"natural_language\": \"at_floor is consistent with the observable register value\",\n \"expression\": \"at_floor == (value == 3'd2)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule restore produces the specified next value\",\n \"antecedent\": \"restore\",\n \"consequent\": \"value == (3'd7)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !restore && dec && (value > 3'd2) produces the specified next value\",\n \"antecedent\": \"!restore && dec && (value > 3'd2)\",\n \"consequent\": \"value == ($past(value) - 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(restore) && !(!restore && dec && (value > 3'd2))\",\n \"consequent\": \"value == $past(value)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"broaden_rule_3.sv\": \"module saturating_arithmetic_0007_mutant_broaden_rule_3 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (restore) value <= 3'd7;\\n else value <= value - 3'd1;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\", \"drop_rule_1.sv\": \"module saturating_arithmetic_0007_mutant_drop_rule_1 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (!restore && dec && (value > 3'd2)) value <= value - 3'd1;\\n else value <= value;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\", \"drop_rule_2.sv\": \"module saturating_arithmetic_0007_mutant_drop_rule_2 (\\n input wire clk,\\n input wire rst,\\n input wire dec,\\n input wire restore,\\n output reg [2:0] value,\\n output wire at_floor\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n value <= 3'd7;\\n end\\n else begin\\n if (restore) value <= 3'd7;\\n else value <= value;\\n end\\n end\\n\\n assign at_floor = value == 3'd2;\\nendmodule\\n\"}"} {"family_id": "sequence_detector_0007", "category": "sequence_detector", "description": "Overlapping serial sequence detector for pattern 1001.", "rtl_variant": "canonical_case.sv", "rtl": "module sequence_detector_0007_canonical_case (\n input wire clk,\n input wire rst,\n input wire bit_in,\n output reg progress1,\n output reg progress2,\n output reg progress3,\n output reg match\n);\n localparam [2:0] S0 = 3'd0;\n localparam [2:0] S1 = 3'd1;\n localparam [2:0] S2 = 3'd2;\n localparam [2:0] S3 = 3'd3;\n localparam [2:0] MATCH = 3'd4;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n S0: next_state = (!bit_in) ? S0 : ((bit_in) ? S1 : (S0));\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\n default: next_state = S0;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= S0;\n else\n state <= next_state;\n end\n\n always @* begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n case (state)\n S0: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n end\n S1: begin\n progress1 = 1'b1;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n end\n S2: begin\n progress1 = 1'b0;\n progress2 = 1'b1;\n progress3 = 1'b0;\n match = 1'b0;\n end\n S3: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b1;\n match = 1'b0;\n end\n MATCH: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"sequence_detector_0007\",\n \"category\": \"sequence_detector\",\n \"template\": \"pattern_1001\",\n \"description\": \"Overlapping serial sequence detector for pattern 1001.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"S0\"\n },\n \"inputs\": [\n \"bit_in\"\n ],\n \"outputs\": [\n \"progress1\",\n \"progress2\",\n \"progress3\",\n \"match\"\n ],\n \"states\": [\n \"S0\",\n \"S1\",\n \"S2\",\n \"S3\",\n \"MATCH\"\n ],\n \"state_outputs\": {\n \"S0\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S1\": {\n \"progress1\": 1,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S2\": {\n \"progress1\": 0,\n \"progress2\": 1,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S3\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 1,\n \"match\": 0\n },\n \"MATCH\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"S0\",\n \"when\": \"!bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S0\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"!bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"!bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"bit_in\",\n \"to\": \"MATCH\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"!bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S2 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"sva_name\": \"p_t10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"force_exit_t1\",\n \"kind\": \"force_transition\",\n \"from\": \"S0\",\n \"to\": \"S1\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S0\",\n \"old\": \"bit_in\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S1\",\n \"old\": \"!bit_in\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: sequence_detector_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({progress1, progress2, progress3, match}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P3_T1: S0 transitions to S0 when !bit_in.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P4_T2: S0 transitions to S1 when bit_in.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P5_T3: S1 transitions to S2 when !bit_in.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P6_T4: S1 transitions to S1 when bit_in.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P7_T5: S2 transitions to S3 when !bit_in.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P8_T6: S2 transitions to S1 when bit_in.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P9_T7: S3 transitions to S0 when !bit_in.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P10_T8: S3 transitions to MATCH when bit_in.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && match));\n\n// P11_T9: MATCH transitions to S2 when !bit_in.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (!bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P12_T10: MATCH transitions to S1 when bit_in.\np_t10: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S2 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t2.sv\": \"module sequence_detector_0007_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S0 : (S0);\\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module sequence_detector_0007_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S0 : ((bit_in) ? S1 : (S0));\\n S1: next_state = (bit_in) ? S1 : (S1);\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t1.sv\": \"module sequence_detector_0007_mutant_force_exit_t1 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = S1;\\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "sequence_detector_0007", "category": "sequence_detector", "description": "Overlapping serial sequence detector for pattern 1001.", "rtl_variant": "onehot_case.sv", "rtl": "module sequence_detector_0007_onehot_case (\n input wire clk,\n input wire rst,\n input wire bit_in,\n output reg progress1,\n output reg progress2,\n output reg progress3,\n output reg match\n);\n localparam [4:0] S0 = 5'b00001;\n localparam [4:0] S1 = 5'b00010;\n localparam [4:0] S2 = 5'b00100;\n localparam [4:0] S3 = 5'b01000;\n localparam [4:0] MATCH = 5'b10000;\n\n reg [4:0] state, next_state;\n\n always @* begin\n next_state = S0;\n case (state)\n S0: next_state = (!bit_in) ? S0 : ((bit_in) ? S1 : (S0));\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\n default: next_state = S0;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= S0;\n else\n state <= next_state;\n end\n\n always @* begin\n progress1 = (state == S1);\n progress2 = (state == S2);\n progress3 = (state == S3);\n match = (state == MATCH);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"sequence_detector_0007\",\n \"category\": \"sequence_detector\",\n \"template\": \"pattern_1001\",\n \"description\": \"Overlapping serial sequence detector for pattern 1001.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"S0\"\n },\n \"inputs\": [\n \"bit_in\"\n ],\n \"outputs\": [\n \"progress1\",\n \"progress2\",\n \"progress3\",\n \"match\"\n ],\n \"states\": [\n \"S0\",\n \"S1\",\n \"S2\",\n \"S3\",\n \"MATCH\"\n ],\n \"state_outputs\": {\n \"S0\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S1\": {\n \"progress1\": 1,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S2\": {\n \"progress1\": 0,\n \"progress2\": 1,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S3\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 1,\n \"match\": 0\n },\n \"MATCH\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"S0\",\n \"when\": \"!bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S0\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"!bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"!bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"bit_in\",\n \"to\": \"MATCH\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"!bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S2 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"sva_name\": \"p_t10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"force_exit_t1\",\n \"kind\": \"force_transition\",\n \"from\": \"S0\",\n \"to\": \"S1\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S0\",\n \"old\": \"bit_in\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S1\",\n \"old\": \"!bit_in\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: sequence_detector_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({progress1, progress2, progress3, match}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P3_T1: S0 transitions to S0 when !bit_in.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P4_T2: S0 transitions to S1 when bit_in.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P5_T3: S1 transitions to S2 when !bit_in.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P6_T4: S1 transitions to S1 when bit_in.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P7_T5: S2 transitions to S3 when !bit_in.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P8_T6: S2 transitions to S1 when bit_in.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P9_T7: S3 transitions to S0 when !bit_in.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P10_T8: S3 transitions to MATCH when bit_in.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && match));\n\n// P11_T9: MATCH transitions to S2 when !bit_in.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (!bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P12_T10: MATCH transitions to S1 when bit_in.\np_t10: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S2 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t2.sv\": \"module sequence_detector_0007_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S0 : (S0);\\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module sequence_detector_0007_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S0 : ((bit_in) ? S1 : (S0));\\n S1: next_state = (bit_in) ? S1 : (S1);\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t1.sv\": \"module sequence_detector_0007_mutant_force_exit_t1 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = S1;\\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "sequence_detector_0007", "category": "sequence_detector", "description": "Overlapping serial sequence detector for pattern 1001.", "rtl_variant": "nested_if.sv", "rtl": "module sequence_detector_0007_nested_if (\n input wire clk,\n input wire rst,\n input wire bit_in,\n output wire progress1,\n output wire progress2,\n output wire progress3,\n output wire match\n);\n localparam [2:0] S_S0 = 3'd0;\n localparam [2:0] S_S1 = 3'd1;\n localparam [2:0] S_S2 = 3'd2;\n localparam [2:0] S_S3 = 3'd3;\n localparam [2:0] S_MATCH = 3'd4;\n\n reg [2:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_S0;\n end else begin\n if (state == S_S0) begin\n state <= (!bit_in) ? S_S0 : ((bit_in) ? S_S1 : (S_S0));\n end\n else if (state == S_S1) begin\n state <= (!bit_in) ? S_S2 : ((bit_in) ? S_S1 : (S_S1));\n end\n else if (state == S_S2) begin\n state <= (!bit_in) ? S_S3 : ((bit_in) ? S_S1 : (S_S2));\n end\n else if (state == S_S3) begin\n state <= (!bit_in) ? S_S0 : ((bit_in) ? S_MATCH : (S_S3));\n end\n else if (state == S_MATCH) begin\n state <= (!bit_in) ? S_S2 : ((bit_in) ? S_S1 : (S_MATCH));\n end\n else begin\n state <= S_S0;\n end\n end\n end\n\n assign progress1 = (state == S_S1);\n assign progress2 = (state == S_S2);\n assign progress3 = (state == S_S3);\n assign match = (state == S_MATCH);\nendmodule\n", "spec_json": "{\n \"design_id\": \"sequence_detector_0007\",\n \"category\": \"sequence_detector\",\n \"template\": \"pattern_1001\",\n \"description\": \"Overlapping serial sequence detector for pattern 1001.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"S0\"\n },\n \"inputs\": [\n \"bit_in\"\n ],\n \"outputs\": [\n \"progress1\",\n \"progress2\",\n \"progress3\",\n \"match\"\n ],\n \"states\": [\n \"S0\",\n \"S1\",\n \"S2\",\n \"S3\",\n \"MATCH\"\n ],\n \"state_outputs\": {\n \"S0\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S1\": {\n \"progress1\": 1,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S2\": {\n \"progress1\": 0,\n \"progress2\": 1,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S3\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 1,\n \"match\": 0\n },\n \"MATCH\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"S0\",\n \"when\": \"!bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S0\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"!bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"!bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"bit_in\",\n \"to\": \"MATCH\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"!bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S2 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"sva_name\": \"p_t10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"force_exit_t1\",\n \"kind\": \"force_transition\",\n \"from\": \"S0\",\n \"to\": \"S1\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S0\",\n \"old\": \"bit_in\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S1\",\n \"old\": \"!bit_in\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: sequence_detector_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({progress1, progress2, progress3, match}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P3_T1: S0 transitions to S0 when !bit_in.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P4_T2: S0 transitions to S1 when bit_in.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P5_T3: S1 transitions to S2 when !bit_in.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P6_T4: S1 transitions to S1 when bit_in.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P7_T5: S2 transitions to S3 when !bit_in.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P8_T6: S2 transitions to S1 when bit_in.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P9_T7: S3 transitions to S0 when !bit_in.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P10_T8: S3 transitions to MATCH when bit_in.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && match));\n\n// P11_T9: MATCH transitions to S2 when !bit_in.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (!bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P12_T10: MATCH transitions to S1 when bit_in.\np_t10: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S2 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t2.sv\": \"module sequence_detector_0007_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S0 : (S0);\\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module sequence_detector_0007_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S0 : ((bit_in) ? S1 : (S0));\\n S1: next_state = (bit_in) ? S1 : (S1);\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t1.sv\": \"module sequence_detector_0007_mutant_force_exit_t1 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = S1;\\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "sequence_detector_0007", "category": "sequence_detector", "description": "Overlapping serial sequence detector for pattern 1001.", "rtl_variant": "factored_flags.sv", "rtl": "module sequence_detector_0007_factored_flags (\n input wire clk,\n input wire rst,\n input wire bit_in,\n output reg progress1,\n output reg progress2,\n output reg progress3,\n output reg match\n);\n localparam [2:0] F_S0 = 3'd0;\n localparam [2:0] F_S1 = 3'd1;\n localparam [2:0] F_S2 = 3'd2;\n localparam [2:0] F_S3 = 3'd3;\n localparam [2:0] F_MATCH = 3'd4;\n\n reg [2:0] state, next_state;\n\n wire guard_s0_0 = (!bit_in);\n wire guard_s0_1 = (bit_in);\n wire guard_s1_0 = (!bit_in);\n wire guard_s1_1 = (bit_in);\n wire guard_s2_0 = (!bit_in);\n wire guard_s2_1 = (bit_in);\n wire guard_s3_0 = (!bit_in);\n wire guard_s3_1 = (bit_in);\n wire guard_match_0 = (!bit_in);\n wire guard_match_1 = (bit_in);\n\n always @* begin\n next_state = state;\n case (state)\n F_S0: begin\n if (guard_s0_0)\n next_state = F_S0;\n else if (guard_s0_1)\n next_state = F_S1;\n end\n F_S1: begin\n if (guard_s1_0)\n next_state = F_S2;\n else if (guard_s1_1)\n next_state = F_S1;\n end\n F_S2: begin\n if (guard_s2_0)\n next_state = F_S3;\n else if (guard_s2_1)\n next_state = F_S1;\n end\n F_S3: begin\n if (guard_s3_0)\n next_state = F_S0;\n else if (guard_s3_1)\n next_state = F_MATCH;\n end\n F_MATCH: begin\n if (guard_match_0)\n next_state = F_S2;\n else if (guard_match_1)\n next_state = F_S1;\n end\n default: next_state = F_S0;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_S0;\n else\n state <= next_state;\n end\n\n always @* begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n case (state)\n F_S0: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n end\n F_S1: begin\n progress1 = 1'b1;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n end\n F_S2: begin\n progress1 = 1'b0;\n progress2 = 1'b1;\n progress3 = 1'b0;\n match = 1'b0;\n end\n F_S3: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b1;\n match = 1'b0;\n end\n F_MATCH: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"sequence_detector_0007\",\n \"category\": \"sequence_detector\",\n \"template\": \"pattern_1001\",\n \"description\": \"Overlapping serial sequence detector for pattern 1001.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"S0\"\n },\n \"inputs\": [\n \"bit_in\"\n ],\n \"outputs\": [\n \"progress1\",\n \"progress2\",\n \"progress3\",\n \"match\"\n ],\n \"states\": [\n \"S0\",\n \"S1\",\n \"S2\",\n \"S3\",\n \"MATCH\"\n ],\n \"state_outputs\": {\n \"S0\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S1\": {\n \"progress1\": 1,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S2\": {\n \"progress1\": 0,\n \"progress2\": 1,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S3\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 1,\n \"match\": 0\n },\n \"MATCH\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"S0\",\n \"when\": \"!bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S0\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"!bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"!bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"bit_in\",\n \"to\": \"MATCH\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"!bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"bit_in\",\n \"to\": \"S1\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S2 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"sva_name\": \"p_t10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"force_exit_t1\",\n \"kind\": \"force_transition\",\n \"from\": \"S0\",\n \"to\": \"S1\"\n },\n {\n \"name\": \"drop_t2\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S0\",\n \"old\": \"bit_in\",\n \"new\": \"false\"\n },\n {\n \"name\": \"drop_t3\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S1\",\n \"old\": \"!bit_in\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: sequence_detector_0007\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({progress1, progress2, progress3, match}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P3_T1: S0 transitions to S0 when !bit_in.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P4_T2: S0 transitions to S1 when bit_in.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P5_T3: S1 transitions to S2 when !bit_in.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P6_T4: S1 transitions to S1 when bit_in.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P7_T5: S2 transitions to S3 when !bit_in.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P8_T6: S2 transitions to S1 when bit_in.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P9_T7: S3 transitions to S0 when !bit_in.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P10_T8: S3 transitions to MATCH when bit_in.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && match));\n\n// P11_T9: MATCH transitions to S2 when !bit_in.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (!bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P12_T10: MATCH transitions to S1 when bit_in.\np_t10: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S0 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S2 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S1 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t2.sv\": \"module sequence_detector_0007_mutant_drop_t2 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S0 : (S0);\\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"drop_t3.sv\": \"module sequence_detector_0007_mutant_drop_t3 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S0 : ((bit_in) ? S1 : (S0));\\n S1: next_state = (bit_in) ? S1 : (S1);\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t1.sv\": \"module sequence_detector_0007_mutant_force_exit_t1 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = S1;\\n S1: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S1 : (S2));\\n S3: next_state = (!bit_in) ? S0 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S2 : ((bit_in) ? S1 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "sequence_detector_0006", "category": "sequence_detector", "description": "Overlapping serial sequence detector for pattern 0101.", "rtl_variant": "canonical_case.sv", "rtl": "module sequence_detector_0006_canonical_case (\n input wire clk,\n input wire rst,\n input wire bit_in,\n output reg progress1,\n output reg progress2,\n output reg progress3,\n output reg match\n);\n localparam [2:0] S0 = 3'd0;\n localparam [2:0] S1 = 3'd1;\n localparam [2:0] S2 = 3'd2;\n localparam [2:0] S3 = 3'd3;\n localparam [2:0] MATCH = 3'd4;\n\n reg [2:0] state, next_state;\n\n always @* begin\n next_state = state;\n case (state)\n S0: next_state = (!bit_in) ? S1 : ((bit_in) ? S0 : (S0));\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\n default: next_state = S0;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= S0;\n else\n state <= next_state;\n end\n\n always @* begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n case (state)\n S0: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n end\n S1: begin\n progress1 = 1'b1;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n end\n S2: begin\n progress1 = 1'b0;\n progress2 = 1'b1;\n progress3 = 1'b0;\n match = 1'b0;\n end\n S3: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b1;\n match = 1'b0;\n end\n MATCH: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"sequence_detector_0006\",\n \"category\": \"sequence_detector\",\n \"template\": \"pattern_0101\",\n \"description\": \"Overlapping serial sequence detector for pattern 0101.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"S0\"\n },\n \"inputs\": [\n \"bit_in\"\n ],\n \"outputs\": [\n \"progress1\",\n \"progress2\",\n \"progress3\",\n \"match\"\n ],\n \"states\": [\n \"S0\",\n \"S1\",\n \"S2\",\n \"S3\",\n \"MATCH\"\n ],\n \"state_outputs\": {\n \"S0\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S1\": {\n \"progress1\": 1,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S2\": {\n \"progress1\": 0,\n \"progress2\": 1,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S3\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 1,\n \"match\": 0\n },\n \"MATCH\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"S0\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S0\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"bit_in\",\n \"to\": \"MATCH\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"sva_name\": \"p_t10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S0\",\n \"old\": \"!bit_in\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"S0\",\n \"to\": \"S1\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"S1\",\n \"to\": \"S2\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: sequence_detector_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({progress1, progress2, progress3, match}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P3_T1: S0 transitions to S1 when !bit_in.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P4_T2: S0 transitions to S0 when bit_in.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P5_T3: S1 transitions to S1 when !bit_in.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P6_T4: S1 transitions to S2 when bit_in.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P7_T5: S2 transitions to S3 when !bit_in.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P8_T6: S2 transitions to S0 when bit_in.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P9_T7: S3 transitions to S1 when !bit_in.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P10_T8: S3 transitions to MATCH when bit_in.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && match));\n\n// P11_T9: MATCH transitions to S3 when !bit_in.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P12_T10: MATCH transitions to S0 when bit_in.\np_t10: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module sequence_detector_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (bit_in) ? S0 : (S0);\\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module sequence_detector_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = S1;\\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module sequence_detector_0006_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S1 : ((bit_in) ? S0 : (S0));\\n S1: next_state = S2;\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "sequence_detector_0006", "category": "sequence_detector", "description": "Overlapping serial sequence detector for pattern 0101.", "rtl_variant": "onehot_case.sv", "rtl": "module sequence_detector_0006_onehot_case (\n input wire clk,\n input wire rst,\n input wire bit_in,\n output reg progress1,\n output reg progress2,\n output reg progress3,\n output reg match\n);\n localparam [4:0] S0 = 5'b00001;\n localparam [4:0] S1 = 5'b00010;\n localparam [4:0] S2 = 5'b00100;\n localparam [4:0] S3 = 5'b01000;\n localparam [4:0] MATCH = 5'b10000;\n\n reg [4:0] state, next_state;\n\n always @* begin\n next_state = S0;\n case (state)\n S0: next_state = (!bit_in) ? S1 : ((bit_in) ? S0 : (S0));\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\n default: next_state = S0;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= S0;\n else\n state <= next_state;\n end\n\n always @* begin\n progress1 = (state == S1);\n progress2 = (state == S2);\n progress3 = (state == S3);\n match = (state == MATCH);\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"sequence_detector_0006\",\n \"category\": \"sequence_detector\",\n \"template\": \"pattern_0101\",\n \"description\": \"Overlapping serial sequence detector for pattern 0101.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"S0\"\n },\n \"inputs\": [\n \"bit_in\"\n ],\n \"outputs\": [\n \"progress1\",\n \"progress2\",\n \"progress3\",\n \"match\"\n ],\n \"states\": [\n \"S0\",\n \"S1\",\n \"S2\",\n \"S3\",\n \"MATCH\"\n ],\n \"state_outputs\": {\n \"S0\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S1\": {\n \"progress1\": 1,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S2\": {\n \"progress1\": 0,\n \"progress2\": 1,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S3\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 1,\n \"match\": 0\n },\n \"MATCH\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"S0\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S0\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"bit_in\",\n \"to\": \"MATCH\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"sva_name\": \"p_t10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S0\",\n \"old\": \"!bit_in\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"S0\",\n \"to\": \"S1\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"S1\",\n \"to\": \"S2\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: sequence_detector_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({progress1, progress2, progress3, match}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P3_T1: S0 transitions to S1 when !bit_in.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P4_T2: S0 transitions to S0 when bit_in.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P5_T3: S1 transitions to S1 when !bit_in.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P6_T4: S1 transitions to S2 when bit_in.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P7_T5: S2 transitions to S3 when !bit_in.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P8_T6: S2 transitions to S0 when bit_in.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P9_T7: S3 transitions to S1 when !bit_in.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P10_T8: S3 transitions to MATCH when bit_in.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && match));\n\n// P11_T9: MATCH transitions to S3 when !bit_in.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P12_T10: MATCH transitions to S0 when bit_in.\np_t10: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module sequence_detector_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (bit_in) ? S0 : (S0);\\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module sequence_detector_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = S1;\\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module sequence_detector_0006_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S1 : ((bit_in) ? S0 : (S0));\\n S1: next_state = S2;\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "sequence_detector_0006", "category": "sequence_detector", "description": "Overlapping serial sequence detector for pattern 0101.", "rtl_variant": "nested_if.sv", "rtl": "module sequence_detector_0006_nested_if (\n input wire clk,\n input wire rst,\n input wire bit_in,\n output wire progress1,\n output wire progress2,\n output wire progress3,\n output wire match\n);\n localparam [2:0] S_S0 = 3'd0;\n localparam [2:0] S_S1 = 3'd1;\n localparam [2:0] S_S2 = 3'd2;\n localparam [2:0] S_S3 = 3'd3;\n localparam [2:0] S_MATCH = 3'd4;\n\n reg [2:0] state;\n\n always @(posedge clk) begin\n if (rst) begin\n state <= S_S0;\n end else begin\n if (state == S_S0) begin\n state <= (!bit_in) ? S_S1 : ((bit_in) ? S_S0 : (S_S0));\n end\n else if (state == S_S1) begin\n state <= (!bit_in) ? S_S1 : ((bit_in) ? S_S2 : (S_S1));\n end\n else if (state == S_S2) begin\n state <= (!bit_in) ? S_S3 : ((bit_in) ? S_S0 : (S_S2));\n end\n else if (state == S_S3) begin\n state <= (!bit_in) ? S_S1 : ((bit_in) ? S_MATCH : (S_S3));\n end\n else if (state == S_MATCH) begin\n state <= (!bit_in) ? S_S3 : ((bit_in) ? S_S0 : (S_MATCH));\n end\n else begin\n state <= S_S0;\n end\n end\n end\n\n assign progress1 = (state == S_S1);\n assign progress2 = (state == S_S2);\n assign progress3 = (state == S_S3);\n assign match = (state == S_MATCH);\nendmodule\n", "spec_json": "{\n \"design_id\": \"sequence_detector_0006\",\n \"category\": \"sequence_detector\",\n \"template\": \"pattern_0101\",\n \"description\": \"Overlapping serial sequence detector for pattern 0101.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"S0\"\n },\n \"inputs\": [\n \"bit_in\"\n ],\n \"outputs\": [\n \"progress1\",\n \"progress2\",\n \"progress3\",\n \"match\"\n ],\n \"states\": [\n \"S0\",\n \"S1\",\n \"S2\",\n \"S3\",\n \"MATCH\"\n ],\n \"state_outputs\": {\n \"S0\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S1\": {\n \"progress1\": 1,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S2\": {\n \"progress1\": 0,\n \"progress2\": 1,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S3\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 1,\n \"match\": 0\n },\n \"MATCH\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"S0\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S0\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"bit_in\",\n \"to\": \"MATCH\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"sva_name\": \"p_t10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S0\",\n \"old\": \"!bit_in\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"S0\",\n \"to\": \"S1\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"S1\",\n \"to\": \"S2\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: sequence_detector_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({progress1, progress2, progress3, match}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P3_T1: S0 transitions to S1 when !bit_in.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P4_T2: S0 transitions to S0 when bit_in.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P5_T3: S1 transitions to S1 when !bit_in.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P6_T4: S1 transitions to S2 when bit_in.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P7_T5: S2 transitions to S3 when !bit_in.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P8_T6: S2 transitions to S0 when bit_in.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P9_T7: S3 transitions to S1 when !bit_in.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P10_T8: S3 transitions to MATCH when bit_in.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && match));\n\n// P11_T9: MATCH transitions to S3 when !bit_in.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P12_T10: MATCH transitions to S0 when bit_in.\np_t10: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module sequence_detector_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (bit_in) ? S0 : (S0);\\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module sequence_detector_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = S1;\\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module sequence_detector_0006_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S1 : ((bit_in) ? S0 : (S0));\\n S1: next_state = S2;\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "sequence_detector_0006", "category": "sequence_detector", "description": "Overlapping serial sequence detector for pattern 0101.", "rtl_variant": "factored_flags.sv", "rtl": "module sequence_detector_0006_factored_flags (\n input wire clk,\n input wire rst,\n input wire bit_in,\n output reg progress1,\n output reg progress2,\n output reg progress3,\n output reg match\n);\n localparam [2:0] F_S0 = 3'd0;\n localparam [2:0] F_S1 = 3'd1;\n localparam [2:0] F_S2 = 3'd2;\n localparam [2:0] F_S3 = 3'd3;\n localparam [2:0] F_MATCH = 3'd4;\n\n reg [2:0] state, next_state;\n\n wire guard_s0_0 = (!bit_in);\n wire guard_s0_1 = (bit_in);\n wire guard_s1_0 = (!bit_in);\n wire guard_s1_1 = (bit_in);\n wire guard_s2_0 = (!bit_in);\n wire guard_s2_1 = (bit_in);\n wire guard_s3_0 = (!bit_in);\n wire guard_s3_1 = (bit_in);\n wire guard_match_0 = (!bit_in);\n wire guard_match_1 = (bit_in);\n\n always @* begin\n next_state = state;\n case (state)\n F_S0: begin\n if (guard_s0_0)\n next_state = F_S1;\n else if (guard_s0_1)\n next_state = F_S0;\n end\n F_S1: begin\n if (guard_s1_0)\n next_state = F_S1;\n else if (guard_s1_1)\n next_state = F_S2;\n end\n F_S2: begin\n if (guard_s2_0)\n next_state = F_S3;\n else if (guard_s2_1)\n next_state = F_S0;\n end\n F_S3: begin\n if (guard_s3_0)\n next_state = F_S1;\n else if (guard_s3_1)\n next_state = F_MATCH;\n end\n F_MATCH: begin\n if (guard_match_0)\n next_state = F_S3;\n else if (guard_match_1)\n next_state = F_S0;\n end\n default: next_state = F_S0;\n endcase\n end\n\n always @(posedge clk) begin\n if (rst)\n state <= F_S0;\n else\n state <= next_state;\n end\n\n always @* begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n case (state)\n F_S0: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n end\n F_S1: begin\n progress1 = 1'b1;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b0;\n end\n F_S2: begin\n progress1 = 1'b0;\n progress2 = 1'b1;\n progress3 = 1'b0;\n match = 1'b0;\n end\n F_S3: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b1;\n match = 1'b0;\n end\n F_MATCH: begin\n progress1 = 1'b0;\n progress2 = 1'b0;\n progress3 = 1'b0;\n match = 1'b1;\n end\n default: begin end\n endcase\n end\nendmodule\n", "spec_json": "{\n \"design_id\": \"sequence_detector_0006\",\n \"category\": \"sequence_detector\",\n \"template\": \"pattern_0101\",\n \"description\": \"Overlapping serial sequence detector for pattern 0101.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true,\n \"state\": \"S0\"\n },\n \"inputs\": [\n \"bit_in\"\n ],\n \"outputs\": [\n \"progress1\",\n \"progress2\",\n \"progress3\",\n \"match\"\n ],\n \"states\": [\n \"S0\",\n \"S1\",\n \"S2\",\n \"S3\",\n \"MATCH\"\n ],\n \"state_outputs\": {\n \"S0\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S1\": {\n \"progress1\": 1,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S2\": {\n \"progress1\": 0,\n \"progress2\": 1,\n \"progress3\": 0,\n \"match\": 0\n },\n \"S3\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 1,\n \"match\": 0\n },\n \"MATCH\": {\n \"progress1\": 0,\n \"progress2\": 0,\n \"progress3\": 0,\n \"match\": 1\n }\n },\n \"transitions\": [\n {\n \"from\": \"S0\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S0\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S1\",\n \"when\": \"bit_in\",\n \"to\": \"S2\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"S2\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"!bit_in\",\n \"to\": \"S1\"\n },\n {\n \"from\": \"S3\",\n \"when\": \"bit_in\",\n \"to\": \"MATCH\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"!bit_in\",\n \"to\": \"S3\"\n },\n {\n \"from\": \"MATCH\",\n \"when\": \"bit_in\",\n \"to\": \"S0\"\n }\n ],\n \"rtl_variants\": [\n \"canonical_case\",\n \"onehot_case\",\n \"nested_if\",\n \"factored_flags\"\n ],\n \"notes\": [\n \"All benchmark properties use interface-visible signals only.\",\n \"All RTL variants must be observationally equivalent after reset.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"sva_name\": \"p_state_encoding\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"sva_name\": \"p_reset_state\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"sva_name\": \"p_t1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"sva_name\": \"p_t2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"sva_name\": \"p_t3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"sva_name\": \"p_t4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"sva_name\": \"p_t5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"sva_name\": \"p_t6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"sva_name\": \"p_t7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"sva_name\": \"p_t8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"sva_name\": \"p_t9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"sva_name\": \"p_t10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"drop_t1\",\n \"kind\": \"replace_transition_guard\",\n \"from\": \"S0\",\n \"old\": \"!bit_in\",\n \"new\": \"false\"\n },\n {\n \"name\": \"force_exit_t2\",\n \"kind\": \"force_transition\",\n \"from\": \"S0\",\n \"to\": \"S1\"\n },\n {\n \"name\": \"force_exit_t3\",\n \"kind\": \"force_transition\",\n \"from\": \"S1\",\n \"to\": \"S2\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Generated from spec.json.\n// Design: sequence_detector_0006\n\n// P1_STATE_ENCODING: observable state outputs always encode at most one active mode.\np_state_encoding: assert property (@(posedge clk) disable iff (rst)\n $onehot0({progress1, progress2, progress3, match}));\n\n// P2_RESET: reset returns the controller to its reset behavior.\np_reset_state: assert property (@(posedge clk)\n (rst) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P3_T1: S0 transitions to S1 when !bit_in.\np_t1: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P4_T2: S0 transitions to S0 when bit_in.\np_t2: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P5_T3: S1 transitions to S1 when !bit_in.\np_t3: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P6_T4: S1 transitions to S2 when bit_in.\np_t4: assert property (@(posedge clk) disable iff (rst)\n ((progress1 && !progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && progress2 && !progress3 && !match));\n\n// P7_T5: S2 transitions to S3 when !bit_in.\np_t5: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P8_T6: S2 transitions to S0 when bit_in.\np_t6: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && progress2 && !progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n\n// P9_T7: S3 transitions to S1 when !bit_in.\np_t7: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (!bit_in)) |=> (progress1 && !progress2 && !progress3 && !match));\n\n// P10_T8: S3 transitions to MATCH when bit_in.\np_t8: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && progress3 && !match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && match));\n\n// P11_T9: MATCH transitions to S3 when !bit_in.\np_t9: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (!bit_in)) |=> (!progress1 && !progress2 && progress3 && !match));\n\n// P12_T10: MATCH transitions to S0 when bit_in.\np_t10: assert property (@(posedge clk) disable iff (rst)\n ((!progress1 && !progress2 && !progress3 && match) && (bit_in)) |=> (!progress1 && !progress2 && !progress3 && !match));\n", "properties_json": "[\n {\n \"id\": \"P1_STATE_ENCODING\",\n \"type\": \"invariant\",\n \"natural_language\": \"observable state outputs always encode at most one active mode\",\n \"expression\": \"$onehot0({progress1, progress2, progress3, match})\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P2_RESET\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset returns the controller to its reset behavior\",\n \"antecedent\": \"rst\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1\n },\n {\n \"id\": \"P3_T1\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_T2\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S0 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_T3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S1 when !bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P6_T4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S1 transitions to S2 when bit_in\",\n \"antecedent\": \"(progress1 && !progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P7_T5\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P8_T6\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S2 transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && progress2 && !progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P9_T7\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to S1 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (!bit_in)\",\n \"consequent\": \"progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P10_T8\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"S3 transitions to MATCH when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && progress3 && !match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P11_T9\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S3 when !bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (!bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P12_T10\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"MATCH transitions to S0 when bit_in\",\n \"antecedent\": \"(!progress1 && !progress2 && !progress3 && match) && (bit_in)\",\n \"consequent\": \"!progress1 && !progress2 && !progress3 && !match\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"drop_t1.sv\": \"module sequence_detector_0006_mutant_drop_t1 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (bit_in) ? S0 : (S0);\\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t2.sv\": \"module sequence_detector_0006_mutant_force_exit_t2 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = S1;\\n S1: next_state = (!bit_in) ? S1 : ((bit_in) ? S2 : (S1));\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\", \"force_exit_t3.sv\": \"module sequence_detector_0006_mutant_force_exit_t3 (\\n input wire clk,\\n input wire rst,\\n input wire bit_in,\\n output reg progress1,\\n output reg progress2,\\n output reg progress3,\\n output reg match\\n);\\n localparam [2:0] S0 = 3'd0;\\n localparam [2:0] S1 = 3'd1;\\n localparam [2:0] S2 = 3'd2;\\n localparam [2:0] S3 = 3'd3;\\n localparam [2:0] MATCH = 3'd4;\\n\\n reg [2:0] state, next_state;\\n\\n always @* begin\\n next_state = state;\\n case (state)\\n S0: next_state = (!bit_in) ? S1 : ((bit_in) ? S0 : (S0));\\n S1: next_state = S2;\\n S2: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (S2));\\n S3: next_state = (!bit_in) ? S1 : ((bit_in) ? MATCH : (S3));\\n MATCH: next_state = (!bit_in) ? S3 : ((bit_in) ? S0 : (MATCH));\\n default: next_state = S0;\\n endcase\\n end\\n\\n always @(posedge clk) begin\\n if (rst)\\n state <= S0;\\n else\\n state <= next_state;\\n end\\n\\n always @* begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n case (state)\\n S0: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S1: begin\\n progress1 = 1'b1;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S2: begin\\n progress1 = 1'b0;\\n progress2 = 1'b1;\\n progress3 = 1'b0;\\n match = 1'b0;\\n end\\n S3: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b1;\\n match = 1'b0;\\n end\\n MATCH: begin\\n progress1 = 1'b0;\\n progress2 = 1'b0;\\n progress3 = 1'b0;\\n match = 1'b1;\\n end\\n default: begin end\\n endcase\\n end\\nendmodule\\n\"}"} {"family_id": "timer_0009", "category": "timer_watchdog", "description": "Pausable elapsed timer with clear and enable.", "rtl_variant": "canonical_next.sv", "rtl": "module timer_0009_canonical_next (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [2:0] count,\n output wire done\n);\n\n reg [2:0] next_count;\n\n always @* begin\n if (clear) next_count = 3'd0;\n else if (!clear && enable && (count < 3'd5)) next_count = count + 3'd1;\n else next_count = count;\n end\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd0;\n else\n count <= next_count;\n end\n\n assign done = count == 3'd5;\nendmodule\n", "spec_json": "{\n \"design_id\": \"timer_0009\",\n \"category\": \"timer_watchdog\",\n \"model_type\": \"register_rules\",\n \"template\": \"pausable_timer\",\n \"description\": \"Pausable elapsed timer with clear and enable.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"clear\",\n \"enable\"\n ],\n \"outputs\": [\n \"count\",\n \"done\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"done\": \"count == 3'd5\"\n },\n \"update_rules\": [\n {\n \"when\": \"clear\",\n \"value\": \"3'd0\"\n },\n {\n \"when\": \"!clear && enable && (count < 3'd5)\",\n \"value\": \"count + 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_DONE\",\n \"sva_name\": \"p_done\",\n \"type\": \"invariant\",\n \"natural_language\": \"done is consistent with the observable register value\",\n \"expression\": \"done == (count == 3'd5)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule clear produces the specified next value\",\n \"antecedent\": \"clear\",\n \"consequent\": \"count == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !clear && enable && (count < 3'd5) produces the specified next value\",\n \"antecedent\": \"!clear && enable && (count < 3'd5)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(clear) && !(!clear && enable && (count < 3'd5))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_clear\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"clear\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_enable\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!clear && enable && (count < 3'd5)\",\n \"new\": \"!clear && (count < 3'd5)\"\n },\n {\n \"name\": \"never_advance\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!clear && enable && (count < 3'd5)\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for timer_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_DONE: done is consistent with the observable register value\nproperty p_done;\n @(posedge clk) disable iff (rst) (done == (count == 3'd5));\nendproperty\nassert property (p_done);\n\n// P3_RULE: update rule clear produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (clear) |=> (count == (3'd0));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !clear && enable && (count < 3'd5) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!clear && enable && (count < 3'd5)) |=> (count == ($past(count) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(clear) && !(!clear && enable && (count < 3'd5))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_DONE\",\n \"sva_name\": \"p_done\",\n \"type\": \"invariant\",\n \"natural_language\": \"done is consistent with the observable register value\",\n \"expression\": \"done == (count == 3'd5)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule clear produces the specified next value\",\n \"antecedent\": \"clear\",\n \"consequent\": \"count == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !clear && enable && (count < 3'd5) produces the specified next value\",\n \"antecedent\": \"!clear && enable && (count < 3'd5)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(clear) && !(!clear && enable && (count < 3'd5))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_clear.sv\": \"module timer_0009_mutant_ignore_clear (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (!clear && enable && (count < 3'd5)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\", \"ignore_enable.sv\": \"module timer_0009_mutant_ignore_enable (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (clear) count <= 3'd0;\\n else if (!clear && (count < 3'd5)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\", \"never_advance.sv\": \"module timer_0009_mutant_never_advance (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (clear) count <= 3'd0;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\"}"} {"family_id": "timer_0009", "category": "timer_watchdog", "description": "Pausable elapsed timer with clear and enable.", "rtl_variant": "sequential_priority.sv", "rtl": "module timer_0009_sequential_priority (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [2:0] count,\n output wire done\n);\n\n always @(posedge clk) begin\n if (rst) begin\n count <= 3'd0;\n end\n else begin\n if (clear) count <= 3'd0;\n else if (!clear && enable && (count < 3'd5)) count <= count + 3'd1;\n else count <= count;\n end\n end\n\n assign done = count == 3'd5;\nendmodule\n", "spec_json": "{\n \"design_id\": \"timer_0009\",\n \"category\": \"timer_watchdog\",\n \"model_type\": \"register_rules\",\n \"template\": \"pausable_timer\",\n \"description\": \"Pausable elapsed timer with clear and enable.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"clear\",\n \"enable\"\n ],\n \"outputs\": [\n \"count\",\n \"done\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"done\": \"count == 3'd5\"\n },\n \"update_rules\": [\n {\n \"when\": \"clear\",\n \"value\": \"3'd0\"\n },\n {\n \"when\": \"!clear && enable && (count < 3'd5)\",\n \"value\": \"count + 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_DONE\",\n \"sva_name\": \"p_done\",\n \"type\": \"invariant\",\n \"natural_language\": \"done is consistent with the observable register value\",\n \"expression\": \"done == (count == 3'd5)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule clear produces the specified next value\",\n \"antecedent\": \"clear\",\n \"consequent\": \"count == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !clear && enable && (count < 3'd5) produces the specified next value\",\n \"antecedent\": \"!clear && enable && (count < 3'd5)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(clear) && !(!clear && enable && (count < 3'd5))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_clear\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"clear\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_enable\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!clear && enable && (count < 3'd5)\",\n \"new\": \"!clear && (count < 3'd5)\"\n },\n {\n \"name\": \"never_advance\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!clear && enable && (count < 3'd5)\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for timer_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_DONE: done is consistent with the observable register value\nproperty p_done;\n @(posedge clk) disable iff (rst) (done == (count == 3'd5));\nendproperty\nassert property (p_done);\n\n// P3_RULE: update rule clear produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (clear) |=> (count == (3'd0));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !clear && enable && (count < 3'd5) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!clear && enable && (count < 3'd5)) |=> (count == ($past(count) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(clear) && !(!clear && enable && (count < 3'd5))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_DONE\",\n \"sva_name\": \"p_done\",\n \"type\": \"invariant\",\n \"natural_language\": \"done is consistent with the observable register value\",\n \"expression\": \"done == (count == 3'd5)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule clear produces the specified next value\",\n \"antecedent\": \"clear\",\n \"consequent\": \"count == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !clear && enable && (count < 3'd5) produces the specified next value\",\n \"antecedent\": \"!clear && enable && (count < 3'd5)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(clear) && !(!clear && enable && (count < 3'd5))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_clear.sv\": \"module timer_0009_mutant_ignore_clear (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (!clear && enable && (count < 3'd5)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\", \"ignore_enable.sv\": \"module timer_0009_mutant_ignore_enable (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (clear) count <= 3'd0;\\n else if (!clear && (count < 3'd5)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\", \"never_advance.sv\": \"module timer_0009_mutant_never_advance (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (clear) count <= 3'd0;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\"}"} {"family_id": "timer_0009", "category": "timer_watchdog", "description": "Pausable elapsed timer with clear and enable.", "rtl_variant": "ternary_next.sv", "rtl": "module timer_0009_ternary_next (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [2:0] count,\n output wire done\n);\n\n wire [2:0] next_count;\n\n assign next_count = (clear) ? (3'd0) : ((!clear && enable && (count < 3'd5)) ? (count + 3'd1) : (count));\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd0;\n else\n count <= next_count;\n end\n\n assign done = count == 3'd5;\nendmodule\n", "spec_json": "{\n \"design_id\": \"timer_0009\",\n \"category\": \"timer_watchdog\",\n \"model_type\": \"register_rules\",\n \"template\": \"pausable_timer\",\n \"description\": \"Pausable elapsed timer with clear and enable.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"clear\",\n \"enable\"\n ],\n \"outputs\": [\n \"count\",\n \"done\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"done\": \"count == 3'd5\"\n },\n \"update_rules\": [\n {\n \"when\": \"clear\",\n \"value\": \"3'd0\"\n },\n {\n \"when\": \"!clear && enable && (count < 3'd5)\",\n \"value\": \"count + 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_DONE\",\n \"sva_name\": \"p_done\",\n \"type\": \"invariant\",\n \"natural_language\": \"done is consistent with the observable register value\",\n \"expression\": \"done == (count == 3'd5)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule clear produces the specified next value\",\n \"antecedent\": \"clear\",\n \"consequent\": \"count == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !clear && enable && (count < 3'd5) produces the specified next value\",\n \"antecedent\": \"!clear && enable && (count < 3'd5)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(clear) && !(!clear && enable && (count < 3'd5))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_clear\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"clear\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_enable\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!clear && enable && (count < 3'd5)\",\n \"new\": \"!clear && (count < 3'd5)\"\n },\n {\n \"name\": \"never_advance\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!clear && enable && (count < 3'd5)\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for timer_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_DONE: done is consistent with the observable register value\nproperty p_done;\n @(posedge clk) disable iff (rst) (done == (count == 3'd5));\nendproperty\nassert property (p_done);\n\n// P3_RULE: update rule clear produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (clear) |=> (count == (3'd0));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !clear && enable && (count < 3'd5) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!clear && enable && (count < 3'd5)) |=> (count == ($past(count) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(clear) && !(!clear && enable && (count < 3'd5))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_DONE\",\n \"sva_name\": \"p_done\",\n \"type\": \"invariant\",\n \"natural_language\": \"done is consistent with the observable register value\",\n \"expression\": \"done == (count == 3'd5)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule clear produces the specified next value\",\n \"antecedent\": \"clear\",\n \"consequent\": \"count == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !clear && enable && (count < 3'd5) produces the specified next value\",\n \"antecedent\": \"!clear && enable && (count < 3'd5)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(clear) && !(!clear && enable && (count < 3'd5))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_clear.sv\": \"module timer_0009_mutant_ignore_clear (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (!clear && enable && (count < 3'd5)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\", \"ignore_enable.sv\": \"module timer_0009_mutant_ignore_enable (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (clear) count <= 3'd0;\\n else if (!clear && (count < 3'd5)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\", \"never_advance.sv\": \"module timer_0009_mutant_never_advance (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (clear) count <= 3'd0;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\"}"} {"family_id": "timer_0009", "category": "timer_watchdog", "description": "Pausable elapsed timer with clear and enable.", "rtl_variant": "function_update.sv", "rtl": "module timer_0009_function_update (\n input wire clk,\n input wire rst,\n input wire clear,\n input wire enable,\n output reg [2:0] count,\n output wire done\n);\n\n function automatic [2:0] compute_next_count;\n input [2:0] current;\n input clear;\n input enable;\n begin\n if (clear) compute_next_count = 3'd0;\n else if (!clear && enable && (current < 3'd5)) compute_next_count = current + 3'd1;\n else compute_next_count = current;\n end\n endfunction\n\n wire [2:0] next_count;\n\n assign next_count = compute_next_count(count, clear, enable);\n\n always @(posedge clk) begin\n if (rst)\n count <= 3'd0;\n else\n count <= next_count;\n end\n\n assign done = count == 3'd5;\nendmodule\n", "spec_json": "{\n \"design_id\": \"timer_0009\",\n \"category\": \"timer_watchdog\",\n \"model_type\": \"register_rules\",\n \"template\": \"pausable_timer\",\n \"description\": \"Pausable elapsed timer with clear and enable.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"clear\",\n \"enable\"\n ],\n \"outputs\": [\n \"count\",\n \"done\"\n ],\n \"signal_widths\": {\n \"count\": 3\n },\n \"registers\": [\n {\n \"name\": \"count\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"done\": \"count == 3'd5\"\n },\n \"update_rules\": [\n {\n \"when\": \"clear\",\n \"value\": \"3'd0\"\n },\n {\n \"when\": \"!clear && enable && (count < 3'd5)\",\n \"value\": \"count + 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"count\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_DONE\",\n \"sva_name\": \"p_done\",\n \"type\": \"invariant\",\n \"natural_language\": \"done is consistent with the observable register value\",\n \"expression\": \"done == (count == 3'd5)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule clear produces the specified next value\",\n \"antecedent\": \"clear\",\n \"consequent\": \"count == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !clear && enable && (count < 3'd5) produces the specified next value\",\n \"antecedent\": \"!clear && enable && (count < 3'd5)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(clear) && !(!clear && enable && (count < 3'd5))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_clear\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"clear\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_enable\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!clear && enable && (count < 3'd5)\",\n \"new\": \"!clear && (count < 3'd5)\"\n },\n {\n \"name\": \"never_advance\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!clear && enable && (count < 3'd5)\",\n \"new\": \"false\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for timer_0009\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (count == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_DONE: done is consistent with the observable register value\nproperty p_done;\n @(posedge clk) disable iff (rst) (done == (count == 3'd5));\nendproperty\nassert property (p_done);\n\n// P3_RULE: update rule clear produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (clear) |=> (count == (3'd0));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !clear && enable && (count < 3'd5) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!clear && enable && (count < 3'd5)) |=> (count == ($past(count) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(clear) && !(!clear && enable && (count < 3'd5))) |=> (count == $past(count));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"count == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_DONE\",\n \"sva_name\": \"p_done\",\n \"type\": \"invariant\",\n \"natural_language\": \"done is consistent with the observable register value\",\n \"expression\": \"done == (count == 3'd5)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule clear produces the specified next value\",\n \"antecedent\": \"clear\",\n \"consequent\": \"count == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !clear && enable && (count < 3'd5) produces the specified next value\",\n \"antecedent\": \"!clear && enable && (count < 3'd5)\",\n \"consequent\": \"count == ($past(count) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(clear) && !(!clear && enable && (count < 3'd5))\",\n \"consequent\": \"count == $past(count)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"ignore_clear.sv\": \"module timer_0009_mutant_ignore_clear (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (!clear && enable && (count < 3'd5)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\", \"ignore_enable.sv\": \"module timer_0009_mutant_ignore_enable (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (clear) count <= 3'd0;\\n else if (!clear && (count < 3'd5)) count <= count + 3'd1;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\", \"never_advance.sv\": \"module timer_0009_mutant_never_advance (\\n input wire clk,\\n input wire rst,\\n input wire clear,\\n input wire enable,\\n output reg [2:0] count,\\n output wire done\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n count <= 3'd0;\\n end\\n else begin\\n if (clear) count <= 3'd0;\\n else count <= count;\\n end\\n end\\n\\n assign done = count == 3'd5;\\nendmodule\\n\"}"} {"family_id": "timer_0008", "category": "timer_watchdog", "description": "Watchdog increments until kick resets it and saturates at timeout.", "rtl_variant": "canonical_next.sv", "rtl": "module timer_0008_canonical_next (\n input wire clk,\n input wire rst,\n input wire kick,\n input wire tick,\n output reg [2:0] age,\n output wire timeout\n);\n\n reg [2:0] next_age;\n\n always @* begin\n if (kick) next_age = 3'd0;\n else if (!kick && tick && (age < 3'd7)) next_age = age + 3'd1;\n else next_age = age;\n end\n\n always @(posedge clk) begin\n if (rst)\n age <= 3'd0;\n else\n age <= next_age;\n end\n\n assign timeout = age == 3'd7;\nendmodule\n", "spec_json": "{\n \"design_id\": \"timer_0008\",\n \"category\": \"timer_watchdog\",\n \"model_type\": \"register_rules\",\n \"template\": \"reloadable_watchdog\",\n \"description\": \"Watchdog increments until kick resets it and saturates at timeout.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"kick\",\n \"tick\"\n ],\n \"outputs\": [\n \"age\",\n \"timeout\"\n ],\n \"signal_widths\": {\n \"age\": 3\n },\n \"registers\": [\n {\n \"name\": \"age\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"timeout\": \"age == 3'd7\"\n },\n \"update_rules\": [\n {\n \"when\": \"kick\",\n \"value\": \"3'd0\"\n },\n {\n \"when\": \"!kick && tick && (age < 3'd7)\",\n \"value\": \"age + 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"age\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"age == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_TIMEOUT\",\n \"sva_name\": \"p_timeout\",\n \"type\": \"invariant\",\n \"natural_language\": \"timeout is consistent with the observable register value\",\n \"expression\": \"timeout == (age == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule kick produces the specified next value\",\n \"antecedent\": \"kick\",\n \"consequent\": \"age == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !kick && tick && (age < 3'd7) produces the specified next value\",\n \"antecedent\": \"!kick && tick && (age < 3'd7)\",\n \"consequent\": \"age == ($past(age) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(kick) && !(!kick && tick && (age < 3'd7))\",\n \"consequent\": \"age == $past(age)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_kick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"kick\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_tick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!kick && tick && (age < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"age_without_tick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!kick && tick && (age < 3'd7)\",\n \"new\": \"!kick && (age < 3'd7)\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for timer_0008\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (age == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_TIMEOUT: timeout is consistent with the observable register value\nproperty p_timeout;\n @(posedge clk) disable iff (rst) (timeout == (age == 3'd7));\nendproperty\nassert property (p_timeout);\n\n// P3_RULE: update rule kick produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (kick) |=> (age == (3'd0));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !kick && tick && (age < 3'd7) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!kick && tick && (age < 3'd7)) |=> (age == ($past(age) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(kick) && !(!kick && tick && (age < 3'd7))) |=> (age == $past(age));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"age == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_TIMEOUT\",\n \"sva_name\": \"p_timeout\",\n \"type\": \"invariant\",\n \"natural_language\": \"timeout is consistent with the observable register value\",\n \"expression\": \"timeout == (age == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule kick produces the specified next value\",\n \"antecedent\": \"kick\",\n \"consequent\": \"age == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !kick && tick && (age < 3'd7) produces the specified next value\",\n \"antecedent\": \"!kick && tick && (age < 3'd7)\",\n \"consequent\": \"age == ($past(age) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(kick) && !(!kick && tick && (age < 3'd7))\",\n \"consequent\": \"age == $past(age)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"age_without_tick.sv\": \"module timer_0008_mutant_age_without_tick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (kick) age <= 3'd0;\\n else if (!kick && (age < 3'd7)) age <= age + 3'd1;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\", \"ignore_kick.sv\": \"module timer_0008_mutant_ignore_kick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (!kick && tick && (age < 3'd7)) age <= age + 3'd1;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\", \"ignore_tick.sv\": \"module timer_0008_mutant_ignore_tick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (kick) age <= 3'd0;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\"}"} {"family_id": "timer_0008", "category": "timer_watchdog", "description": "Watchdog increments until kick resets it and saturates at timeout.", "rtl_variant": "sequential_priority.sv", "rtl": "module timer_0008_sequential_priority (\n input wire clk,\n input wire rst,\n input wire kick,\n input wire tick,\n output reg [2:0] age,\n output wire timeout\n);\n\n always @(posedge clk) begin\n if (rst) begin\n age <= 3'd0;\n end\n else begin\n if (kick) age <= 3'd0;\n else if (!kick && tick && (age < 3'd7)) age <= age + 3'd1;\n else age <= age;\n end\n end\n\n assign timeout = age == 3'd7;\nendmodule\n", "spec_json": "{\n \"design_id\": \"timer_0008\",\n \"category\": \"timer_watchdog\",\n \"model_type\": \"register_rules\",\n \"template\": \"reloadable_watchdog\",\n \"description\": \"Watchdog increments until kick resets it and saturates at timeout.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"kick\",\n \"tick\"\n ],\n \"outputs\": [\n \"age\",\n \"timeout\"\n ],\n \"signal_widths\": {\n \"age\": 3\n },\n \"registers\": [\n {\n \"name\": \"age\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"timeout\": \"age == 3'd7\"\n },\n \"update_rules\": [\n {\n \"when\": \"kick\",\n \"value\": \"3'd0\"\n },\n {\n \"when\": \"!kick && tick && (age < 3'd7)\",\n \"value\": \"age + 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"age\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"age == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_TIMEOUT\",\n \"sva_name\": \"p_timeout\",\n \"type\": \"invariant\",\n \"natural_language\": \"timeout is consistent with the observable register value\",\n \"expression\": \"timeout == (age == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule kick produces the specified next value\",\n \"antecedent\": \"kick\",\n \"consequent\": \"age == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !kick && tick && (age < 3'd7) produces the specified next value\",\n \"antecedent\": \"!kick && tick && (age < 3'd7)\",\n \"consequent\": \"age == ($past(age) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(kick) && !(!kick && tick && (age < 3'd7))\",\n \"consequent\": \"age == $past(age)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_kick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"kick\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_tick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!kick && tick && (age < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"age_without_tick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!kick && tick && (age < 3'd7)\",\n \"new\": \"!kick && (age < 3'd7)\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for timer_0008\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (age == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_TIMEOUT: timeout is consistent with the observable register value\nproperty p_timeout;\n @(posedge clk) disable iff (rst) (timeout == (age == 3'd7));\nendproperty\nassert property (p_timeout);\n\n// P3_RULE: update rule kick produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (kick) |=> (age == (3'd0));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !kick && tick && (age < 3'd7) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!kick && tick && (age < 3'd7)) |=> (age == ($past(age) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(kick) && !(!kick && tick && (age < 3'd7))) |=> (age == $past(age));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"age == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_TIMEOUT\",\n \"sva_name\": \"p_timeout\",\n \"type\": \"invariant\",\n \"natural_language\": \"timeout is consistent with the observable register value\",\n \"expression\": \"timeout == (age == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule kick produces the specified next value\",\n \"antecedent\": \"kick\",\n \"consequent\": \"age == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !kick && tick && (age < 3'd7) produces the specified next value\",\n \"antecedent\": \"!kick && tick && (age < 3'd7)\",\n \"consequent\": \"age == ($past(age) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(kick) && !(!kick && tick && (age < 3'd7))\",\n \"consequent\": \"age == $past(age)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"age_without_tick.sv\": \"module timer_0008_mutant_age_without_tick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (kick) age <= 3'd0;\\n else if (!kick && (age < 3'd7)) age <= age + 3'd1;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\", \"ignore_kick.sv\": \"module timer_0008_mutant_ignore_kick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (!kick && tick && (age < 3'd7)) age <= age + 3'd1;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\", \"ignore_tick.sv\": \"module timer_0008_mutant_ignore_tick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (kick) age <= 3'd0;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\"}"} {"family_id": "timer_0008", "category": "timer_watchdog", "description": "Watchdog increments until kick resets it and saturates at timeout.", "rtl_variant": "ternary_next.sv", "rtl": "module timer_0008_ternary_next (\n input wire clk,\n input wire rst,\n input wire kick,\n input wire tick,\n output reg [2:0] age,\n output wire timeout\n);\n\n wire [2:0] next_age;\n\n assign next_age = (kick) ? (3'd0) : ((!kick && tick && (age < 3'd7)) ? (age + 3'd1) : (age));\n\n always @(posedge clk) begin\n if (rst)\n age <= 3'd0;\n else\n age <= next_age;\n end\n\n assign timeout = age == 3'd7;\nendmodule\n", "spec_json": "{\n \"design_id\": \"timer_0008\",\n \"category\": \"timer_watchdog\",\n \"model_type\": \"register_rules\",\n \"template\": \"reloadable_watchdog\",\n \"description\": \"Watchdog increments until kick resets it and saturates at timeout.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"kick\",\n \"tick\"\n ],\n \"outputs\": [\n \"age\",\n \"timeout\"\n ],\n \"signal_widths\": {\n \"age\": 3\n },\n \"registers\": [\n {\n \"name\": \"age\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"timeout\": \"age == 3'd7\"\n },\n \"update_rules\": [\n {\n \"when\": \"kick\",\n \"value\": \"3'd0\"\n },\n {\n \"when\": \"!kick && tick && (age < 3'd7)\",\n \"value\": \"age + 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"age\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"age == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_TIMEOUT\",\n \"sva_name\": \"p_timeout\",\n \"type\": \"invariant\",\n \"natural_language\": \"timeout is consistent with the observable register value\",\n \"expression\": \"timeout == (age == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule kick produces the specified next value\",\n \"antecedent\": \"kick\",\n \"consequent\": \"age == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !kick && tick && (age < 3'd7) produces the specified next value\",\n \"antecedent\": \"!kick && tick && (age < 3'd7)\",\n \"consequent\": \"age == ($past(age) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(kick) && !(!kick && tick && (age < 3'd7))\",\n \"consequent\": \"age == $past(age)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_kick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"kick\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_tick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!kick && tick && (age < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"age_without_tick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!kick && tick && (age < 3'd7)\",\n \"new\": \"!kick && (age < 3'd7)\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for timer_0008\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (age == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_TIMEOUT: timeout is consistent with the observable register value\nproperty p_timeout;\n @(posedge clk) disable iff (rst) (timeout == (age == 3'd7));\nendproperty\nassert property (p_timeout);\n\n// P3_RULE: update rule kick produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (kick) |=> (age == (3'd0));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !kick && tick && (age < 3'd7) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!kick && tick && (age < 3'd7)) |=> (age == ($past(age) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(kick) && !(!kick && tick && (age < 3'd7))) |=> (age == $past(age));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"age == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_TIMEOUT\",\n \"sva_name\": \"p_timeout\",\n \"type\": \"invariant\",\n \"natural_language\": \"timeout is consistent with the observable register value\",\n \"expression\": \"timeout == (age == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule kick produces the specified next value\",\n \"antecedent\": \"kick\",\n \"consequent\": \"age == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !kick && tick && (age < 3'd7) produces the specified next value\",\n \"antecedent\": \"!kick && tick && (age < 3'd7)\",\n \"consequent\": \"age == ($past(age) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(kick) && !(!kick && tick && (age < 3'd7))\",\n \"consequent\": \"age == $past(age)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"age_without_tick.sv\": \"module timer_0008_mutant_age_without_tick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (kick) age <= 3'd0;\\n else if (!kick && (age < 3'd7)) age <= age + 3'd1;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\", \"ignore_kick.sv\": \"module timer_0008_mutant_ignore_kick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (!kick && tick && (age < 3'd7)) age <= age + 3'd1;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\", \"ignore_tick.sv\": \"module timer_0008_mutant_ignore_tick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (kick) age <= 3'd0;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\"}"} {"family_id": "timer_0008", "category": "timer_watchdog", "description": "Watchdog increments until kick resets it and saturates at timeout.", "rtl_variant": "function_update.sv", "rtl": "module timer_0008_function_update (\n input wire clk,\n input wire rst,\n input wire kick,\n input wire tick,\n output reg [2:0] age,\n output wire timeout\n);\n\n function automatic [2:0] compute_next_age;\n input [2:0] current;\n input kick;\n input tick;\n begin\n if (kick) compute_next_age = 3'd0;\n else if (!kick && tick && (current < 3'd7)) compute_next_age = current + 3'd1;\n else compute_next_age = current;\n end\n endfunction\n\n wire [2:0] next_age;\n\n assign next_age = compute_next_age(age, kick, tick);\n\n always @(posedge clk) begin\n if (rst)\n age <= 3'd0;\n else\n age <= next_age;\n end\n\n assign timeout = age == 3'd7;\nendmodule\n", "spec_json": "{\n \"design_id\": \"timer_0008\",\n \"category\": \"timer_watchdog\",\n \"model_type\": \"register_rules\",\n \"template\": \"reloadable_watchdog\",\n \"description\": \"Watchdog increments until kick resets it and saturates at timeout.\",\n \"clock\": {\n \"name\": \"clk\",\n \"edge\": \"posedge\"\n },\n \"reset\": {\n \"name\": \"rst\",\n \"active\": \"high\",\n \"synchronous\": true\n },\n \"inputs\": [\n \"kick\",\n \"tick\"\n ],\n \"outputs\": [\n \"age\",\n \"timeout\"\n ],\n \"signal_widths\": {\n \"age\": 3\n },\n \"registers\": [\n {\n \"name\": \"age\",\n \"width\": 3,\n \"reset_value\": \"3'd0\",\n \"observable\": true\n }\n ],\n \"derived_outputs\": {\n \"timeout\": \"age == 3'd7\"\n },\n \"update_rules\": [\n {\n \"when\": \"kick\",\n \"value\": \"3'd0\"\n },\n {\n \"when\": \"!kick && tick && (age < 3'd7)\",\n \"value\": \"age + 3'd1\"\n },\n {\n \"when\": \"true\",\n \"value\": \"age\"\n }\n ],\n \"rtl_variants\": [\n {\n \"name\": \"canonical\",\n \"module_suffix\": \"canonical_next\",\n \"file\": \"canonical_next.sv\"\n },\n {\n \"name\": \"sequential\",\n \"module_suffix\": \"sequential_priority\",\n \"file\": \"sequential_priority.sv\"\n },\n {\n \"name\": \"ternary\",\n \"module_suffix\": \"ternary_next\",\n \"file\": \"ternary_next.sv\"\n },\n {\n \"name\": \"function\",\n \"module_suffix\": \"function_update\",\n \"file\": \"function_update.sv\"\n }\n ],\n \"notes\": [\n \"The state register is interface-visible and part of observable equivalence.\",\n \"All benchmark properties use interface-visible signals only.\"\n ],\n \"properties\": [\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"age == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_TIMEOUT\",\n \"sva_name\": \"p_timeout\",\n \"type\": \"invariant\",\n \"natural_language\": \"timeout is consistent with the observable register value\",\n \"expression\": \"timeout == (age == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule kick produces the specified next value\",\n \"antecedent\": \"kick\",\n \"consequent\": \"age == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !kick && tick && (age < 3'd7) produces the specified next value\",\n \"antecedent\": \"!kick && tick && (age < 3'd7)\",\n \"consequent\": \"age == ($past(age) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(kick) && !(!kick && tick && (age < 3'd7))\",\n \"consequent\": \"age == $past(age)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n ],\n \"mutants\": [\n {\n \"name\": \"ignore_kick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"kick\",\n \"new\": \"false\"\n },\n {\n \"name\": \"ignore_tick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!kick && tick && (age < 3'd7)\",\n \"new\": \"false\"\n },\n {\n \"name\": \"age_without_tick\",\n \"kind\": \"replace_update_guard\",\n \"old\": \"!kick && tick && (age < 3'd7)\",\n \"new\": \"!kick && (age < 3'd7)\"\n }\n ],\n \"provenance\": {\n \"source_type\": \"original_synthetic\",\n \"source\": \"EquivSVA\",\n \"behavior_spec_creation\": \"programmatic_template_instantiation\",\n \"rtl_generation\": \"programmatic_from_behavior_spec\",\n \"derived_from_external_benchmark\": false\n }\n}\n", "properties_sva": "// Gold interface properties for timer_0008\n\n// P1_RESET: reset restores the register to its reset value\nproperty p_reset_value;\n @(posedge clk) (rst) |=> (age == 3'd0);\nendproperty\nassert property (p_reset_value);\n\n// P2_TIMEOUT: timeout is consistent with the observable register value\nproperty p_timeout;\n @(posedge clk) disable iff (rst) (timeout == (age == 3'd7));\nendproperty\nassert property (p_timeout);\n\n// P3_RULE: update rule kick produces the specified next value\nproperty p_rule_3;\n @(posedge clk) disable iff (rst) (kick) |=> (age == (3'd0));\nendproperty\nassert property (p_rule_3);\n\n// P4_RULE: update rule !kick && tick && (age < 3'd7) produces the specified next value\nproperty p_rule_4;\n @(posedge clk) disable iff (rst) (!kick && tick && (age < 3'd7)) |=> (age == ($past(age) + 3'd1));\nendproperty\nassert property (p_rule_4);\n\n// P5_HOLD: when no update rule fires the register holds its value\nproperty p_hold;\n @(posedge clk) disable iff (rst) (!(kick) && !(!kick && tick && (age < 3'd7))) |=> (age == $past(age));\nendproperty\nassert property (p_hold);\n", "properties_json": "[\n {\n \"id\": \"P1_RESET\",\n \"sva_name\": \"p_reset_value\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"reset restores the register to its reset value\",\n \"antecedent\": \"rst\",\n \"consequent\": \"age == 3'd0\",\n \"delay\": 1\n },\n {\n \"id\": \"P2_TIMEOUT\",\n \"sva_name\": \"p_timeout\",\n \"type\": \"invariant\",\n \"natural_language\": \"timeout is consistent with the observable register value\",\n \"expression\": \"timeout == (age == 3'd7)\",\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P3_RULE\",\n \"sva_name\": \"p_rule_3\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule kick produces the specified next value\",\n \"antecedent\": \"kick\",\n \"consequent\": \"age == (3'd0)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P4_RULE\",\n \"sva_name\": \"p_rule_4\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"update rule !kick && tick && (age < 3'd7) produces the specified next value\",\n \"antecedent\": \"!kick && tick && (age < 3'd7)\",\n \"consequent\": \"age == ($past(age) + 3'd1)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n },\n {\n \"id\": \"P5_HOLD\",\n \"sva_name\": \"p_hold\",\n \"type\": \"next_cycle_implication\",\n \"natural_language\": \"when no update rule fires the register holds its value\",\n \"antecedent\": \"!(kick) && !(!kick && tick && (age < 3'd7))\",\n \"consequent\": \"age == $past(age)\",\n \"delay\": 1,\n \"disable\": \"rst\"\n }\n]\n", "mutants_json": "{\"age_without_tick.sv\": \"module timer_0008_mutant_age_without_tick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (kick) age <= 3'd0;\\n else if (!kick && (age < 3'd7)) age <= age + 3'd1;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\", \"ignore_kick.sv\": \"module timer_0008_mutant_ignore_kick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (!kick && tick && (age < 3'd7)) age <= age + 3'd1;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\", \"ignore_tick.sv\": \"module timer_0008_mutant_ignore_tick (\\n input wire clk,\\n input wire rst,\\n input wire kick,\\n input wire tick,\\n output reg [2:0] age,\\n output wire timeout\\n);\\n\\n always @(posedge clk) begin\\n if (rst) begin\\n age <= 3'd0;\\n end\\n else begin\\n if (kick) age <= 3'd0;\\n else age <= age;\\n end\\n end\\n\\n assign timeout = age == 3'd7;\\nendmodule\\n\"}"}