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rtl-augmented-v3

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rtl-augmented-v3 / qossayrida_PipelineProcessorDesign /sim_script_map.json

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	{
	"PipelineProcessor/PipelineProcessor/src/alu/ALU.v": "ALU_TB_sim.sh",
	"PipelineProcessor/PipelineProcessor/src/instruction_memory/InstructionMemory.v": "InstructionMemory_TB_sim.sh",
	"PipelineProcessor/PipelineProcessor/src/utilities/Extender.v": "Extender_TB_sim.sh",
	"PipelineProcessor/PipelineProcessor/src/utilities/Compare.v": "Compare_TB_sim.sh",
	"PipelineProcessor/PipelineProcessor/src/stages/EXEStage.v": "EXEStage_TB_sim.sh",
	"PipelineProcessor/PipelineProcessor/src/stages/IFStage.v": "IFStage_TB_sim.sh"
	}