diff --git a/qossayrida_PipelineProcessorDesign/candidates/ALU__ALU/golden_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/ALU__ALU/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..97d07f99fdc833b66e418d2471a2bc26dfff0db9 Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/ALU__ALU/golden_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/ALU__ALU/sim.sh b/qossayrida_PipelineProcessorDesign/candidates/ALU__ALU/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..91e5b2504a41a35a7fec73effd9d7d23c39a8794 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/ALU__ALU/sim.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +set -euo pipefail +if ! command -v python &>/dev/null; then + _TMPBIN=$(mktemp -d) + ln -s "$(command -v python3)" "$_TMPBIN/python" + export PATH="$_TMPBIN:$PATH" + trap 'rm -rf "$_TMPBIN"' EXIT +fi +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -s ALU_TB -o /tmp/sim_ALU_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/alu/ALU.v" +vvp /tmp/sim_ALU_TB -fst diff --git a/qossayrida_PipelineProcessorDesign/candidates/Compare__Compare/golden_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/Compare__Compare/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..8c2654cbcb3bf1dd6e5c61c82ea385140e4a0d43 Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/Compare__Compare/golden_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/Compare__Compare/sim.sh b/qossayrida_PipelineProcessorDesign/candidates/Compare__Compare/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..1e1d9643c19ac471ea7ff2d96881a26eac9a1f02 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/Compare__Compare/sim.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +set -euo pipefail +if ! command -v python &>/dev/null; then + _TMPBIN=$(mktemp -d) + ln -s "$(command -v python3)" "$_TMPBIN/python" + export PATH="$_TMPBIN:$PATH" + trap 'rm -rf "$_TMPBIN"' EXIT +fi +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -s Compare_TB -o /tmp/sim_Compare_TB "$SRCDIR/PipelineProcessor/src/utilities/Compare.v" +vvp /tmp/sim_Compare_TB -fst diff --git a/qossayrida_PipelineProcessorDesign/candidates/EXEStage__EXEStage/golden_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/EXEStage__EXEStage/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..9ec912a2ff9718d46ed4f26a471e29826f15a8f1 Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/EXEStage__EXEStage/golden_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/EXEStage__EXEStage/sim.sh b/qossayrida_PipelineProcessorDesign/candidates/EXEStage__EXEStage/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..9d1659526c350d3bf336b6068af6e18dea919163 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/EXEStage__EXEStage/sim.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +set -euo pipefail +if ! command -v python &>/dev/null; then + _TMPBIN=$(mktemp -d) + ln -s "$(command -v python3)" "$_TMPBIN/python" + export PATH="$_TMPBIN:$PATH" + trap 'rm -rf "$_TMPBIN"' EXIT +fi +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -s EXEStage_TB -o /tmp/sim_EXEStage_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/alu/ALU.v" "$SRCDIR/PipelineProcessor/src/stages/EXEStage.v" +vvp /tmp/sim_EXEStage_TB -fst diff --git a/qossayrida_PipelineProcessorDesign/candidates/Extender__Extender/golden_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/Extender__Extender/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..1efd62de93d0d86d703e0601dfe70398ca96993a Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/Extender__Extender/golden_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/Extender__Extender/sim.sh b/qossayrida_PipelineProcessorDesign/candidates/Extender__Extender/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..d9bfe9e4eb7c5bce2a2f5a3757e0b20a01a4f79d --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/Extender__Extender/sim.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +set -euo pipefail +if ! command -v python &>/dev/null; then + _TMPBIN=$(mktemp -d) + ln -s "$(command -v python3)" "$_TMPBIN/python" + export PATH="$_TMPBIN:$PATH" + trap 'rm -rf "$_TMPBIN"' EXIT +fi +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -s Extender_TB -o /tmp/sim_Extender_TB "$SRCDIR/PipelineProcessor/src/utilities/Extender.v" +vvp /tmp/sim_Extender_TB -fst diff --git a/qossayrida_PipelineProcessorDesign/candidates/IFStage__IFStage/golden_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/IFStage__IFStage/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..bd05a98290ad1bf66618669fe8f12fdb10861ebf Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/IFStage__IFStage/golden_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/IFStage__IFStage/sim.sh b/qossayrida_PipelineProcessorDesign/candidates/IFStage__IFStage/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..44b03a94dc78d13d44d9e2f176d5a9e3f527d9eb --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/IFStage__IFStage/sim.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +set -euo pipefail +if ! command -v python &>/dev/null; then + _TMPBIN=$(mktemp -d) + ln -s "$(command -v python3)" "$_TMPBIN/python" + export PATH="$_TMPBIN:$PATH" + trap 'rm -rf "$_TMPBIN"' EXIT +fi +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -s IFStage_TB -o /tmp/sim_IFStage_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/instruction_memory/InstructionMemory.v" "$SRCDIR/PipelineProcessor/src/utilities/mux.v" "$SRCDIR/PipelineProcessor/src/stages/IFStage.v" +vvp /tmp/sim_IFStage_TB -fst diff --git a/qossayrida_PipelineProcessorDesign/candidates/IFStage__mux/golden_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/IFStage__mux/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..bd05a98290ad1bf66618669fe8f12fdb10861ebf Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/IFStage__mux/golden_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/IFStage__mux/sim.sh b/qossayrida_PipelineProcessorDesign/candidates/IFStage__mux/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..44b03a94dc78d13d44d9e2f176d5a9e3f527d9eb --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/IFStage__mux/sim.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +set -euo pipefail +if ! command -v python &>/dev/null; then + _TMPBIN=$(mktemp -d) + ln -s "$(command -v python3)" "$_TMPBIN/python" + export PATH="$_TMPBIN:$PATH" + trap 'rm -rf "$_TMPBIN"' EXIT +fi +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -s IFStage_TB -o /tmp/sim_IFStage_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/instruction_memory/InstructionMemory.v" "$SRCDIR/PipelineProcessor/src/utilities/mux.v" "$SRCDIR/PipelineProcessor/src/stages/IFStage.v" +vvp /tmp/sim_IFStage_TB -fst diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/buggy_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..e6f033f68714d2c6a727f888f981b046e9b05938 Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/buggy_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/diff.patch b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..179e5799b23235b6f9d77f5f511eef9518bf9d33 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/diff.patch @@ -0,0 +1,11 @@ +--- a/PipelineProcessor/src/instruction_memory/InstructionMemory.v ++++ b/PipelineProcessor/src/instruction_memory/InstructionMemory.v +@@ -11,7 +11,7 @@ + always @(posedge clk) begin + + if (!stall) +- instruction <= {instructionMemory[address + 1], instructionMemory[address]}; ++ instruction <= {instructionMemory[address], instructionMemory[address + 1]}; + + end + diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/metadata.json b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..25ed367e73893087dc990aee7bf934993049c5af --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "concat_swap", + "task_type": "behavioral_bug", + "files_modified": [ + "PipelineProcessor/src/instruction_memory/InstructionMemory.v" + ], + "bug_description": "Reordered concatenation {instructionMemory[address + 1], instructionMemory[address]} to {instructionMemory[address], instructionMemory[address + 1]} \u2014 swaps the high and low bytes of the fetched instruction, causing the instruction word to be byte-swapped", + "signals_affected": [ + "instruction" + ], + "simulation_status": "sim_ok", + "problem_statement": "Instruction fetch produces incorrect byte ordering beginning at t=5ns. When the instruction pointer accesses memory, the instruction signal outputs 0x0052 (0000000101010010), but the byte arrangement does not conform to the defined memory layout. The high and low bytes appear to be reversed relative to the memory addresses being accessed, resulting in corrupted opcodes being presented to the decode stage. This discrepancy is consistent across all instruction fetches, suggesting a systematic error in how instruction bytes are assembled from memory.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/sim_log.txt b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..edebbb03125259cc4389935e90859233987bb9e5 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/concat_swap/sim_log.txt @@ -0,0 +1,18 @@ +FST info: dumpfile wave_InstructionMemory.fst opened for output. +At time 0, Address = 0000, Instruction = xxxx +At time 5, Address = 0000, Instruction = 0152 +At time 20, Address = 0002, Instruction = 0152 +At time 25, Address = 0002, Instruction = 0354 +At time 30, Address = 0004, Instruction = 0354 +At time 35, Address = 0004, Instruction = 5016 +At time 40, Address = 0006, Instruction = 5016 +At time 45, Address = 0006, Instruction = 0576 +At time 50, Address = 0008, Instruction = 0576 +At time 55, Address = 0008, Instruction = xxxx +At time 60, Address = 000a, Instruction = xxxx +At time 70, Address = 000c, Instruction = xxxx +At time 80, Address = 000e, Instruction = xxxx +At time 90, Address = 0010, Instruction = xxxx +At time 100, Address = 0012, Instruction = xxxx +At time 110, Address = 0014, Instruction = xxxx +/tmp/sim4_simsh_mf_7s8z9/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v:131: $finish called at 130 (1s) diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/buggy_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..01cd0ca77818d491bb2f8eb2a673b20c65544803 Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/buggy_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/diff.patch b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..155c92a122afaf88fe2cdab735b094bb858042c7 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/diff.patch @@ -0,0 +1,12 @@ +--- a/PipelineProcessor/src/instruction_memory/InstructionMemory.v ++++ b/PipelineProcessor/src/instruction_memory/InstructionMemory.v +@@ -10,8 +10,7 @@ + + always @(posedge clk) begin + +- if (!stall) +- instruction <= {instructionMemory[address + 1], instructionMemory[address]}; ++ instruction <= {instructionMemory[address + 1], instructionMemory[address]}; + + end + diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/metadata.json b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..1996a0ccd7ee9fe15bbaf0c75fef71ad9ddc202f --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "PipelineProcessor/src/instruction_memory/InstructionMemory.v" + ], + "bug_description": "Removed '!stall' enable condition from sequential block \u2014 instruction output now updates every clock edge regardless of the stall signal", + "signals_affected": [ + "instruction" + ], + "simulation_status": "sim_ok", + "problem_statement": "When the stall signal is asserted, the instruction register should hold its current value across clock edges. However, the waveform shows that the instruction signal continues to update on every clock cycle, ignoring the stall condition. At t=5, the instruction signal updates to 0101001000000001 while stall is active, when it should have remained unchanged. This indicates the instruction output is not properly responding to stall assertions, causing the pipeline to advance instructions even during stall periods and breaking pipeline flow control.", + "diff_summary": "5 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/sim_log.txt b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..ca51206d92f47538bcd8d4a8d399fa886d788201 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/missing_enable/sim_log.txt @@ -0,0 +1,18 @@ +FST info: dumpfile wave_InstructionMemory.fst opened for output. +At time 0, Address = 0000, Instruction = xxxx +At time 5, Address = 0000, Instruction = 5201 +At time 20, Address = 0002, Instruction = 5201 +At time 25, Address = 0002, Instruction = 5403 +At time 30, Address = 0004, Instruction = 5403 +At time 35, Address = 0004, Instruction = 1650 +At time 40, Address = 0006, Instruction = 1650 +At time 45, Address = 0006, Instruction = 7605 +At time 50, Address = 0008, Instruction = 7605 +At time 55, Address = 0008, Instruction = xxxx +At time 60, Address = 000a, Instruction = xxxx +At time 70, Address = 000c, Instruction = xxxx +At time 80, Address = 000e, Instruction = xxxx +At time 90, Address = 0010, Instruction = xxxx +At time 100, Address = 0012, Instruction = xxxx +At time 110, Address = 0014, Instruction = xxxx +/tmp/sim4_simsh_hb2xb6lt/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v:130: $finish called at 130 (1s) diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/buggy_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..47f118f4b31f7c87fb9891e83fbcac6123ba7ad1 Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/buggy_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/diff.patch b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..a7cf52070fe3d6c55249f27507447cbccfa8a200 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/diff.patch @@ -0,0 +1,11 @@ +--- a/PipelineProcessor/src/instruction_memory/InstructionMemory.v ++++ b/PipelineProcessor/src/instruction_memory/InstructionMemory.v +@@ -87,7 +87,7 @@ + .kill(kill), + .stall(stall), + .address(address), +- .instruction(instruction) ++ .instruction() + ); + + // Clock generation diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/metadata.json b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..70ea8312d52138ecf0b08b665640b0442dd76a5f --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "unconnected_port", + "task_type": "behavioral_bug", + "files_modified": [ + "PipelineProcessor/src/instruction_memory/InstructionMemory.v" + ], + "bug_description": "Disconnected 'instruction' output port of InstructionMemory instantiation in testbench \u2014 'instruction' wire in InstructionMemory_TB is now floating", + "signals_affected": [ + "instruction" + ], + "simulation_status": "sim_ok", + "problem_statement": "During testbench execution, the `instruction` output signal from InstructionMemory fails to update with valid instruction values. At t=5, when the module is expected to present the first instruction fetch result, `instruction` is observed at 0101001000000001 and does not transition to subsequent instruction values as memory addresses change. The signal appears to be stuck at this initial value or not properly propagating from the memory output, suggesting a potential issue with the output data path or signal connectivity in the instantiation. This prevents proper verification of the instruction fetch functionality and downstream pipeline stages that depend on receiving correct instruction encodings.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/sim_log.txt b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..4c52c6e5861d222ba3d0757ab59db66d8fa9fda5 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/unconnected_port/sim_log.txt @@ -0,0 +1,13 @@ +FST info: dumpfile wave_InstructionMemory.fst opened for output. +At time 0, Address = 0000, Instruction = zzzz +At time 20, Address = 0002, Instruction = zzzz +At time 30, Address = 0004, Instruction = zzzz +At time 40, Address = 0006, Instruction = zzzz +At time 50, Address = 0008, Instruction = zzzz +At time 60, Address = 000a, Instruction = zzzz +At time 70, Address = 000c, Instruction = zzzz +At time 80, Address = 000e, Instruction = zzzz +At time 90, Address = 0010, Instruction = zzzz +At time 100, Address = 0012, Instruction = zzzz +At time 110, Address = 0014, Instruction = zzzz +/tmp/sim4_simsh_o7_64cgo/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v:131: $finish called at 130 (1s) diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/buggy_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..bcc7a7fd278a740466916b5e294bf641d6e1b76e Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/diff.patch b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..60ee668776bfcee80175fbc62e03a2bef4c33510 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/PipelineProcessor/src/instruction_memory/InstructionMemory.v ++++ b/PipelineProcessor/src/instruction_memory/InstructionMemory.v +@@ -5,7 +5,7 @@ + ); + + +- reg [7:0] instructionMemory [0:255]; // the size will be 2 ^ 16 ++ reg [5:0] instructionMemory [0:255]; // the size will be 2 ^ 16 + + + always @(posedge clk) begin diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/metadata.json b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..988a27c74e039a67eafb2cbedec2f5fc93af932f --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "wrong_bitwidth", + "task_type": "behavioral_bug", + "files_modified": [ + "PipelineProcessor/src/instruction_memory/InstructionMemory.v" + ], + "bug_description": "Truncated 'instructionMemory' register array from 8 bits to 6 bits, causing upper 2 bits of each stored byte to be lost, resulting in corrupted instructions being fetched", + "signals_affected": [ + "instructionMemory" + ], + "simulation_status": "sim_ok", + "problem_statement": "Instructions fetched from instructionMemory are being corrupted during storage or retrieval. At t=5ns, the instruction signal shows 0x0201, but based on the instruction encoding for this operation, the upper bits [7:6] should be set, not zeroed. This pattern is consistent across multiple test cycles\u2014any instruction with high-valued bytes written to instructionMemory comes back with those upper bits lost, causing invalid or unexpected opcodes to be executed. The 8-bit values being stored should be fully preserved, but it appears only 6 bits are being retained. Need to verify that instructionMemory is sized correctly to hold complete instruction bytes without truncation.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/golden_waveform.fst b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..bd05a98290ad1bf66618669fe8f12fdb10861ebf Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/golden_waveform.fst differ diff --git a/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/sim.sh b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..a7813d0df31d89d8add73050c76032b8f84b5990 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/candidates/InstructionMemory__InstructionMemory/sim.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +set -euo pipefail +if ! command -v python &>/dev/null; then + _TMPBIN=$(mktemp -d) + ln -s "$(command -v python3)" "$_TMPBIN/python" + export PATH="$_TMPBIN:$PATH" + trap 'rm -rf "$_TMPBIN"' EXIT +fi +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -s InstructionMemory_TB -o /tmp/sim_InstructionMemory_TB "$SRCDIR/PipelineProcessor/src/integration/parameter.v" "$SRCDIR/PipelineProcessor/src/instruction_memory/InstructionMemory.v" +vvp /tmp/sim_InstructionMemory_TB -fst diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/Edfmap.ini b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/Edfmap.ini new file mode 100644 index 0000000000000000000000000000000000000000..4df4f13783804977cf77146b39d5f37c2ba0e827 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/Edfmap.ini @@ -0,0 +1,1380 @@ + +[$GENERAL$] +INIT=Z +prefix=EDF_ +user_names=no +edif2sdf_mapfile= +logfile=efd2vhd.log + +[$EXPORT$] +FMAP=NO +HMAP=NO + +[$properties$] +AMULTSEL= +CYMODE= +INIT= +FD INIT=integer +FDC INIT=integer +FDCE INIT=integer +FDCE_1 INIT=integer +FDCP INIT=integer +FDCPE INIT=integer +FDCPE_1 INIT=integer +FDCP_1 INIT=integer +FDC_1 INIT=integer +FDD INIT=integer +FDDC INIT=integer +FDDCE INIT=integer +FDDCP INIT=integer +FDDCPE INIT=integer +FDDP INIT=integer +FDDPE INIT=integer +FDDRCPE INIT=integer +FDDRRSE INIT=integer +FDE INIT=integer +FDE_1 INIT=integer +FDP INIT=integer +FDPE INIT=integer +FDPE_1 INIT=integer +FDP_1 INIT=integer +FDR INIT=integer +FDRE INIT=integer +FDRE_1 INIT=integer +FDRS INIT=integer +FDRSE INIT=integer +FDRSE_1 INIT=integer +FDRS_1 INIT=integer +FDR_1 INIT=integer +FDS INIT=integer +FDSE INIT=integer +FDSE_1 INIT=integer +FDS_1 INIT=integer +FD_1 INIT=integer +FJKC INIT=integer +FJKCE INIT=integer +FJKP INIT=integer +FJKPE INIT=integer +FJKRSE INIT=integer +FJKSRE INIT=integer +FTC INIT=integer +FTCE INIT=integer +FTCLE INIT=integer +FTCLEX INIT=integer +FTP INIT=integer +FTPE INIT=integer +FTPLE INIT=integer +FTRSE INIT=integer +FTRSLE INIT=integer +FTSRE INIT=integer +FTSRLE INIT=integer +FTCP INIT=integer +GTPA1_DUAL RXPRBSERR_LOOPBACK_0=integer +GTPA1_DUAL RXPRBSERR_LOOPBACK_1=integer +GTXE1 RXPRBSERR_LOOPBACK=integer +IDDR INIT_Q1=integer +IDDR INIT_Q2=integer +IDDR2 INIT_Q0=integer +IDDR2 INIT_Q1=integer +IDDR_2CLK INIT_Q1=integer +IDDR_2CLK INIT_Q2=integer +IFD INIT=integer +IFD_1 INIT=integer +IFDI INIT=integer +IFDI_1 INIT=integer +IFDX INIT=integer +IFDX_1 INIT=integer +IFDXI INIT=integer +IFDXI_1 INIT=integer +ILD INIT=integer +ILD_1 INIT=integer +ILDI INIT=integer +ILDI_1 INIT=integer +ILDX INIT=integer +ILDX_1 INIT=integer +ILDXI INIT=integer +ILDXI_1 INIT=integer +ISERDES INIT_Q1=integer +ISERDES INIT_Q2=integer +ISERDES INIT_Q3=integer +ISERDES INIT_Q4=integer +ISERDES SRVAL_Q1=integer +ISERDES SRVAL_Q2=integer +ISERDES SRVAL_Q3=integer +ISERDES SRVAL_Q4=integer +ISERDES_NODELAY INIT_Q1=integer +ISERDES_NODELAY INIT_Q2=integer +ISERDES_NODELAY INIT_Q3=integer +ISERDES_NODELAY INIT_Q4=integer +ISERDES_NODELAY SRVAL_Q1=integer +ISERDES_NODELAY SRVAL_Q2=integer +ISERDES_NODELAY SRVAL_Q3=integer +ISERDES_NODELAY SRVAL_Q4=integer +LD INIT=integer +LDC INIT=integer +LDCE INIT=integer +LDCE_1 INIT=integer +LDCP INIT=integer +LDCPE INIT=integer +LDCPE_1 INIT=integer +LDCP_1 INIT=integer +LDC_1 INIT=integer +LDE INIT=integer +LDE_1 INIT=integer +LDG INIT=integer +LDP INIT=integer +LDPE INIT=integer +LDPE_1 INIT=integer +LDP_1 INIT=integer +LD_1 INIT=integer +ODDR INIT=integer +ODDR2 INIT=integer +OFD INIT=integer +OFD_1 INIT=integer +OFDE INIT=integer +OFDE_1 INIT=integer +OFDI INIT=integer +OFDI_1 INIT=integer +OFDT INIT=integer +OFDT_1 INIT=integer +OFDX INIT=integer +OFDX_1 INIT=integer +OFDXI INIT=integer +OFDXI_1 INIT=integer +OSERDES INIT_OQ=integer +OSERDES SRVAL_OQ=integer +OSERDES INIT_TQ=integer +OSERDES SRVAL_TQ=integer +OSERDES INIT_OQ=integer +OSERDES INIT_TQ=integer +OSERDES SRVAL_OQ=integer +OSERDES SRVAL_TQ=integer +lut_function= +eqn= +INIT_00= +INIT_01= +INIT_02= +INIT_03= +INIT_04= +INIT_05= +INIT_06= +INIT_07= +INIT_08= +INIT_09= +INIT_0A= +INIT_0B= +INIT_0C= +INIT_0D= +INIT_0E= +INIT_0F= + +INIT_10= +INIT_11= +INIT_12= +INIT_13= +INIT_14= +INIT_15= +INIT_16= +INIT_17= +INIT_18= +INIT_19= +INIT_1A= +INIT_1B= +INIT_1C= +INIT_1D= +INIT_1E= +INIT_1F= + +INIT_20= +INIT_21= +INIT_22= +INIT_23= +INIT_24= +INIT_25= +INIT_26= +INIT_27= +INIT_28= +INIT_29= +INIT_2A= +INIT_2B= +INIT_2C= +INIT_2D= +INIT_2E= +INIT_2F= + +INIT_30= +INIT_31= +INIT_32= +INIT_33= +INIT_34= +INIT_35= +INIT_36= +INIT_37= +INIT_38= +INIT_39= +INIT_3A= +INIT_3B= +INIT_3C= +INIT_3D= +INIT_3E= +INIT_3F= + +INIT_40= +INIT_41= +INIT_42= +INIT_43= +INIT_44= +INIT_45= +INIT_46= +INIT_47= +INIT_48= +INIT_49= +INIT_4A= +INIT_4B= +INIT_4C= +INIT_4D= +INIT_4E= +INIT_4F= + +INIT_50= +INIT_51= +INIT_52= +INIT_53= +INIT_54= +INIT_55= +INIT_56= +INIT_57= +INIT_58= +INIT_59= +INIT_5A= +INIT_5B= +INIT_5C= +INIT_5D= +INIT_5E= +INIT_5F= + +INIT_60= +INIT_61= +INIT_62= +INIT_63= +INIT_64= +INIT_65= +INIT_66= +INIT_67= +INIT_68= +INIT_69= +INIT_6A= +INIT_6B= +INIT_6C= +INIT_6D= +INIT_6E= +INIT_6F= + +INITP_00= +INITP_01= +INITP_02= +INITP_03= +INITP_04= +INITP_05= +INITP_06= +INITP_07= + +LPM_TYPE= +LPM_WIDTH=integer +LPM_DIRECTION= +P_WIDTH= +P_OFFSET= +CLKDV_DIVIDE=real +DUTY_CYCLE_CORRECTION=bool +WIDTH=integer +DIVIDE1_BY=integer +DIVIDE2_BY=integer +TimingChecksOn=bool +Xon=bool +MsgOn=bool +SEL_F500K=bool +SEL_F16K=bool +SEL_F490=bool +SEL_F15=bool + +;added for virtex4 library +CLKFX_DIVIDE=integer +CLKFX_MULTIPLY=integer +CLKIN_DIVIDE_BY_2=bool +CLKIN_PERIOD=real +CLKOUT_PHASE_SHIFT= +CLK_FEEDBACK= +DCM_PERFORMANCE_MODE= +DESKEW_ADJUST= +DFS_FREQUENCY_MODE= +DLL_FREQUENCY_MODE= +FACTORY_JF= +STARTUP_WAIT=bool +PHASE_SHIFT=integer +MONITOR_MODE= +SIM_MONITOR_FILE= +JTAG_CHAIN=integer +INIT_OUT=integer +PRESELECT_I0=bool +PRESELECT_I1=bool +BUFR_DIVIDE= +DSS_MODE= +AREG=integer +B_INPUT= +BREG=integer +CARRYINREG=integer +CARRYINSELREG=integer +CREG=integer +LEGACY_MODE= +MREG=integer +OPMODEREG=integer +PREG=integer +SUBTRACTREG=integer +ALMOST_FULL_OFFSET= +ALMOST_EMPTY_OFFSET= +DATA_WIDTH=integer +FIRST_WORD_FALL_THROUGH=bool +REFCLKSEL= +SYNCLK1OUTEN= +SYNCLK2OUTEN= +CAPACITANCE= +IOSTANDARD= +DIFF_TERM=bool +ICAP_WIDTH= +DDR_CLK_EDGE= +INIT_Q1= +INIT_Q2= +INIT_Q3= +INIT_Q4= +SRTYPE= +IOBDELAY= +IOBDELAY_TYPE= +IOBDELAY_VALUE=integer +DRIVE=integer +SLEW= +INIT_BITSLIPCNT= +;INIT_CE= ;2 elems bit_vector +;INIT_RANK1_PARTIAL= ;5 elems bit_vector +;INIT_RANK2= ;6 elems bit_vector +;INIT_RANK3= ;6 elems bit_vector +BITSLIP_ENABLE=bool +DATA_RATE= +INTERFACE_TYPE= +NUM_CE=integer +SERDES_MODE= +SRVAL_Q1= +SRVAL_Q2= +SRVAL_Q3= +SRVAL_Q4= +INIT_LOADCNT= +SERDES_MODE= +DATA_RATE_OQ= +INIT_OQ= +;INIT_ORANK1= ;6 elems bit_vector +INIT_ORANK2_PARTIAL= +DATA_RATE_TQ= +TRISTATE_WIDTH=integer +INIT_TQ= +INIT_TRANK1= +SRVAL_OQ= +SRVAL_TQ= +EN_REL=bool +RST_DEASSERT_CLK= +DOA_REG=integer +DOB_REG=integer +INIT_A= +INIT_B= +INVERT_CLK_DOA_REG=bool +INVERT_CLK_DOB_REG=bool +RAM_EXTENSION_A= +RAM_EXTENSION_B= +READ_WIDTH_A=integer +READ_WIDTH_B=integer +SIM_COLLISION_CHECK= +SRVAL_A= +SRVAL_B= +WRITE_MODE_A= +WRITE_MODE_B= +WRITE_WIDTH_A=integer +WRITE_WIDTH_B=integer +SRVAL= +WRITE_MODE= +DISABLE_COLLISION_CHECK=bool +ALIGN_COMMA_WORD=integer +BANDGAPSEL=bool +CCCB_ARBITRATOR_DISABLE=bool +CHAN_BOND_LIMIT=integer +CHAN_BOND_MODE= +CHAN_BOND_ONE_SHOT=bool +;CHAN_BOND_SEQ_1_1= ;11 elems bit_vector +;CHAN_BOND_SEQ_1_2= ;11 elems bit_vector +;CHAN_BOND_SEQ_1_3= ;11 elems bit_vector +;CHAN_BOND_SEQ_1_4= ;11 elems bit_vector +CHAN_BOND_SEQ_1_MASK= +;CHAN_BOND_SEQ_2_1= ;11 elems bit_vector +;CHAN_BOND_SEQ_2_2= ;11 elems bit_vector +;CHAN_BOND_SEQ_2_3= ;11 elems bit_vector +;CHAN_BOND_SEQ_2_4= ;11 elems bit_vector +CHAN_BOND_SEQ_2_MASK= +CHAN_BOND_SEQ_2_USE=bool +CHAN_BOND_SEQ_LEN=integer +CLK_CORRECT_USE=bool +CLK_COR_8B10B_DE=bool +CLK_COR_MAX_LAT=integer +CLK_COR_MIN_LAT=integer +;CLK_COR_SEQ_1_2= ;11 elems bit_vector +;CLK_COR_SEQ_1_3= ;11 elems bit_vector +;CLK_COR_SEQ_1_4= ;11 elems bit_vector +CLK_COR_SEQ_1_MASK= +;CLK_COR_SEQ_2_1= ;11 elems bit_vector +;CLK_COR_SEQ_2_2= ;11 elems bit_vector +;CLK_COR_SEQ_2_3= ;11 elems bit_vector +;CLK_COR_SEQ_2_4= ;11 elems bit_vector +CLK_COR_SEQ_2_MASK= +CLK_COR_SEQ_2_USE=bool +CLK_COR_SEQ_DROP=bool +CLK_COR_SEQ_LEN=integer +COMMA32=bool +;COMMA_10B_MASK= ;10 elems bit_vector +;CYCLE_LIMIT_SEL= ;2 elems bit_vector +;DCDR_FILTER= ;3 elems bit_vector +DEC_MCOMMA_DETECT=bool +DEC_PCOMMA_DETECT=bool +DEC_VALID_COMMA_ONLY=bool +;DIGRX_FWDCLK= ;2 elems bit_vector +DIGRX_SYNC_MODE=bool +ENABLE_DCDR=bool +;FDET_HYS_CAL= ;3 elems bit_vector +;FDET_HYS_SEL= ;3 elems bit_vector +;FDET_LCK_CAL= ;3 elems bit_vector +;FDET_LCK_SEL= ;3 elems bit_vector +;LOOPCAL_WAIT= ;2 elems bit_vector +MCOMMA_32B_VALUE= +MCOMMA_DETECT=bool +OPPOSITE_SELECT=bool +PCOMMA_32B_VALUE= +PCOMMA_DETECT=bool +PCS_BIT_SLIP=bool +PMACLKENABLE=bool +PMACOREPWRENABLE=bool +PMA_BIT_SLIP=bool +POWER_ENABLE=bool +REPEATER=bool +;RXAFEEQ= ;9 elems bit_vector +;RXASYNCDIVIDE= ;2 elems bit_vector +RXBY_32=bool +;RXCDRLOS= ;6 elems bit_vector +RXCLK0_FORCE_PMACLK=bool +;RXCLKMODE= ;6 elems bit_vector +RXCPSEL=bool +RXCRCCLOCKDOUBLE=bool +RXCRCENABLE=bool +RXCRCINITVAL= +RXCRCINVERTGEN=bool +RXCRCSAMECLOCK=bool +;RXCYCLE_LIMIT_SEL= ;2 elems bit_vector +;RXDATA_SEL= ;2 elems bit_vector +RXDCCOUPLE=bool +RXDIGRESET=bool +RXDIGRX=bool +RXENABLE=bool +RXEQ= +RXFDCAL_CLOCK_DIVIDE= +;RXFDET_HYS_CAL= ;3 elems bit_vector +;RXFDET_HYS_SEL= ;3 elems bit_vector +;RXFDET_LCK_CAL= ;3 elems bit_vector +;RXFDET_LCK_SEL= ;3 elems bit_vector +RXLB=bool +;RXLKADJ= ;5 elems bit_vector +;RXLOOPCAL_WAIT= ;2 elems bit_vector +RXLOOPFILT= +RXOUTDIV2SEL_A= +RXOUTDIV2SEL_B= +RXPD=bool +RXPLLNDIVSEL= +RXPMACLKSEL= +;RXRCPADJ= ;3 elems bit_vector +RXRECCLK1_USE_SYNC=bool +;RXSLOWDOWN_CAL= ;2 elems bit_vector +RXTADJ=bool +RXUSRDIVISOR=integer +;RXVCODAC_INIT= ;10 elems bit_vector +RXVCO_CTRL_ENABLE=bool +RX_BUFFER_USE=bool +;RX_CLOCK_DIVIDER= ;2 elems bit_vector +RX_LOS_INVALID_INCR=integer +RX_LOS_THRESHOLD=integer +SAMPLE_8X=bool +SH_CNT_MAX=integer +SH_INVALID_CNT_MAX=integer +;SLOWDOWN_CAL= ;2 elems bit_vector +TXABPMACLKSEL= +;TXASYNCDIVIDE= ;2 elems bit_vector +TXCLK0_FORCE_PMACLK=bool +TXCLKMODE= +TXCPSEL=bool +TXCRCCLOCKDOUBLE=bool +TXCRCENABLE=bool +TXCRCINITVAL= +TXCRCINVERTGEN=bool +TXCRCSAMECLOCK=bool +;TXDATA_SEL= ;2 elems bit_vector +;TXDAT_PRDRV_DAC= ;3 elems bit_vector +;TXDAT_TAP_DAC= ;5 elems bit_vector +TXENABLE=bool +TXFDCAL_CLOCK_DIVIDE= +TXHIGHSIGNALEN=bool +TXLOOPFILT= +TXOUTCLK1_USE_SYNC=bool +TXOUTDIV2SEL= +TXPD=bool +TXPHASESEL=bool +TXPLLNDIVSEL= +;TXPOST_PRDRV_DAC= ;3 elems bit_vector +;TXPOST_TAP_DAC= ;5 elems bit_vector +TXPOST_TAP_PD=bool +;TXPRE_PRDRV_DAC= ;3 elems bit_vector +;TXPRE_TAP_DAC= ;5 elems bit_vector +TXPRE_TAP_PD=bool +TXSLEWRATE=bool +TXTERMTRIM= +TX_BUFFER_USE=bool +;TX_CLOCK_DIVIDER= ;2 elems bit_vector +;VCODAC_INIT= ;10 elems bit_vector +VCO_CTRL_ENABLE=bool + + +;added for virtex5 library +A_INPUT= +ACASCREG=integer +ALUMODEREG=integer +AUTORESET_PATTERN_DETEC=bool +AUTORESET_PATTERN_DETECT_OPTINV= +BANDWIDTH= +BCASCREG=integer +CLKFBOUT_MULT=integer +CLKFBOUT_PHASE=real +CLKIN1_PERIOD=real +CLKIN2_PERIOD=real +CLKOUT0_DIVIDE=integer +CLKOUT0_DUTY_CYCLE=real +CLKOUT0_PHASE=real +CLKOUT1_DIVIDE=integer +CLKOUT1_DUTY_CYCLE=real +CLKOUT1_PHASE=real +CLKOUT2_DIVIDE=integer +CLKOUT2_DUTY_CYCLE=real +CLKOUT2_PHASE=real +CLKOUT3_DIVIDE=integer +CLKOUT3_DUTY_CYCLE=real +CLKOUT3_PHASE=real +CLKOUT4_DIVIDE=integer +CLKOUT4_DUTY_CYCLE=real +CLKOUT4_PHASE=real +CLKOUT5_DIVIDE=integer +CLKOUT5_DUTY_CYCLE=real +CLKOUT5_PHASE=real +COMPENSATION= +CRC_INIT= +DELAY_SRC= +DIVCLK_DIVIDE=integer +DO_REG=integer +EN_ECC_READ=bool +EN_ECC_SCRUB=bool +EN_ECC_WRITE=bool +EN_SYN=bool +IDELAY_TYPE= +IDELAY_VALUE=integer +INIT_70= +INIT_71= +INIT_72= +INIT_73= +INIT_74= +INIT_75= +INIT_76= +INIT_77= +INIT_78= +INIT_79= +INIT_7A= +INIT_7B= +INIT_7C= +INIT_7D= +INIT_7E= +INIT_7F= +INIT_C= +INIT_D= +INITP_08= +INITP_09= +INITP_0A= +INITP_0B= +INITP_0C= +INITP_0D= +INITP_0E= +INITP_0F= +MASK= +MULTCARRYINREG=integer +ODELAY_VALUE=integer +PATTERN= +PLL_PMCD_MODE=bool +POLYNOMIAL= +REF_JITTER=real +RESET_ON_LOSS_OF_LOCK=bool +SEL_MASK= +SEL_PATTERN= +SEL_ROUNDING_MASK= +USE_MULT= +USE_PATTERN_DETECT= +USE_SIMD= +;end of virtex5 + +;added for virtex5 (ise9.1i sp2) +CLKFBOUT_DESKEW_ADJUST= +CLKOUT0_DESKEW_ADJUST= +CLKOUT1_DESKEW_ADJUST= +CLKOUT2_DESKEW_ADJUST= +CLKOUT3_DESKEW_ADJUST= +CLKOUT4_DESKEW_ADJUST= +CLKOUT5_DESKEW_ADJUST= +;end of virtex5 (ise9.1i sp2) + +;added for virtex5 (ise9.2i sp1) +PCS_COM_CFG= +SIGNAL_PATTERN= +INIT_FILE= +;end of virtex5 (ise9.2i sp1) + +;added for virtex5 (ise 10.1i) +SIM_MODE= +;end + +;added for spartan6, virtex6 (ise 11.2) +A0REG=integer +A1REG=integer +AC_CAP_DIS_0=bool +AC_CAP_DIS_1=bool +ADREG=integer +AUTORESET_PATDET= +B0REG=integer +B1REG=integer +BUFFER_TYPE= +BYPASS_GCLK_FF=bool +CARRYINSEL= +CARRYOUTREG=integer +CHAN_BOND_2_MAX_SKEW_0=integer +CINVCTRL_SEL=bool +CLK_SEL_TYPE= +CLKCM_CFG=bool +CLKFBOUT_MULT_F=real +CLKFXDV_DIVIDE=integer +CLKFX_MD_MAX=real +CLKFBOUT_USE_FINE_PS=bool +CLKOUT0_DIVIDE_F=real +CLKOUT0_USE_FINE_PS=bool +CLKOUT1_USE_FINE_PS=bool +CLKOUT2_USE_FINE_PS=bool +CLKOUT3_USE_FINE_PS=bool +CLKOUT4_CASCADE=bool +CLKOUT4_USE_FINE_PS=bool +CLKOUT5_USE_FINE_PS=bool +CLKOUT6_DIVIDE=integer +CLKOUT6_DUTY_CYCLE=real +CLKOUT6_PHASE=real +CLKOUT6_USE_FINE_PS=bool +CLKRCV_TRST=bool +CLOCK_HOLD=bool +COUNTER_WRAPAROUND= +DATA_RATE_OT= +DDR3_DATA=integer +DISABLE_JTAG=bool +DIVIDE_BYPASS=bool +DIVIDE=integer +DFS_BANDWIDTH= +DQSMASK_ENABLE=bool +DYN_CLK_INV_EN=bool +DYN_CLKDIV_INV_EN=bool +EN_RSTRAM_A=bool +EN_RSTRAM_B=bool +FARSRC= +HIGH_PERFORMANCE_MODE=bool +I_INVERT=bool +IBUF_DELAY_VALUE= +IBUF_LOW_PWR=bool +IDELAY2_VALUE=integer +IDELAY_MODE= +IFD_DELAY_VALUE= +ISERDESE1 INIT_Q1=integer +ISERDESE1 INIT_Q2=integer +ISERDESE1 INIT_Q3=integer +ISERDESE1 INIT_Q4=integer +OSERDESE1 INIT_OQ=integer +OSERDESE1 INIT_TQ=integer +INMODEREG=integer +InstancePath= +ODELAY_TYPE= +OFB_USED=bool +ONESHOT=bool +OUTPUT_MODE= +PROG_MD_BANDWIDTH= +PROG_USR=bool +RAM_MODE= +REF_JITTER1=real +REF_JITTER2=real +REFCLK_FREQUENCY=real +;REFCLKOUT_DLY= ;10 elems bit_vector +RST_PRIORITY_A= +RST_PRIORITY_B= +RSTREG_PRIORITY_A= +RSTREG_PRIORITY_B= +RSTTYPE= +SETUP_ALL= +SIM_DEVICE= +SIM_EFUSE_VALUE= +SIM_TAPDELAY_VALUE=integer +SPREAD_SPECTRUM= +ISERDESE1 SRVAL_Q1=integer +ISERDESE1 SRVAL_Q2=integer +ISERDESE1 SRVAL_Q3=integer +ISERDESE1 SRVAL_Q4=integer +OSERDESE1 SRVAL_OQ=integer +OSERDESE1 SRVAL_TQ=integer +TRAIN_PATTERN=integer +USE_DOUBLER=bool +USE_DPORT=bool +;end of spartan6, virtex6 (ise 11.2) + +; added for virtex6 (ise 11.3) +TX_PMADATA_OPT=integer +ENABLE_SYNC=bool +;end of virtex6 (ise 11.3) + + +; added for virtex7 (ise 13.3) +IBUFDS_DIFF_OUT_IBUFDISABLE DIFF_TERM= +IBUFDS_DIFF_OUT_INTERMDISABLE DIFF_TERM= +IBUFDS_IBUFDISABLE DIFF_TERM= +IBUFDS_INTERMDISABLE DIFF_TERM= +IOBUFDS_DCIEN DIFF_TERM= +IOBUFDS_DIFF_OUT_DCIEN DIFF_TERM= +IOBUFDS_INTERMDISABLE DIFF_TERM= +DQS_BIAS_MODE= +IBUF_IBUFDISABLE IBUF_LOW_PWR= +IBUF_INTERMDISABLE IBUF_LOW_PWR= +IBUFDS_DIFF_OUT_IBUFDISABLE IBUF_LOW_PWR= +IBUFDS_DIFF_OUT_INTERMDISABLE IBUF_LOW_PWR= +IBUFDS_IBUFDISABLE IBUF_LOW_PWR= +IBUFDS_INTERMDISABLE IBUF_LOW_PWR= +IOBUF_DCIEN IBUF_LOW_PWR= +IOBUF_INTERMDISABLE IBUF_LOW_PWR= +IOBUFDS_DCIEN IBUF_LOW_PWR= +IOBUFDS_DIFF_OUT_DCIEN IBUF_LOW_PWR= +IOBUFDS_INTERMDISABLE IBUF_LOW_PWR= +MEMREFCLK_PERIOD=real +PHASEREFCLK_PERIOD=real +SEL_CLK_OFFSET=integer +USE_IBUFDISABLE= +;end of virtex7 (ise 13.3) + +; added for virtex7 (ise 13.4) +;CLKSWING_CFG= ;2 elems bit_vector +SS_EN= +SS_MODE= +SS_MOD_PERIOD=integer +;end of virtex7 (ISE 13.4) + +IS_C_INVERTED=integer +IS_CLR_INVERTED=integer +IS_D_INVERTED=integer + +[$LIBMAP$] +work=. +xilinx=xabelsim +xilinxun= +simprims=simprim +DESIGNS= + +;FPGA Express +VIRTEXE=VIRTEX +COOLRUNNER=XC9500 +COOLRUNNER2=COOLRUNNERII +SPARTAN2E=SPARTAN2E +SPARTAN3=SPARTAN3 +SPARTAN3A=SPARTAN3A +SPARTAN3E=SPARTAN3E +SPARTANXL=SPARTANX +XC3000A=XC3000 +XC3000L=XC3000 +XC3100A=XC3000 +XC3100L=XC3000 +XC4000EX=XC4000X +XC4000L=XC4000E +XC4000XL=XC4000X +XC4000XLA=XC4000X +XC4000XV=XC4000X +XC9500XL=XC9500 +XC9500XV=XC9500 + +;Synplify +COOLRUNNERII=COOLRUNNERII +Unilib=unisim +XC4000=unisim +XC5000=unisim + +;Exemplar +xcv=unisim +xcv2=unisim +xcv2p=unisim +xcve=unisim +xi3=unisim +xi31=unisim +xi31a=unisim +xi3a=unisim +xi3l=unisim +xi3t=unisim +xi4=unisim +xi4a=unisim +xi4e=unisim +xi4et=unisim +xi4ex=unisim +xi4h=unisim +xi4l=unisim +xi4t=unisim +xi4xl=unisim +xi4xla=unisim +xi4xv=unisim +xi5=unisim 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-0,0 +1,76 @@ +[Project] +Current Flow=Generic +VCS=0 +version=4 +Current Config=compile +[Configurations] +compile=PipelineProcessor +[Library] +PipelineProcessor=.\PipelineProcessor\PipelineProcessor.lib +[$LibMap$] +PipelineProcessor=. +Active_lib= +[Settings] +FLOW_TYPE=HDL +LANGUAGE=VERILOG +REFRESH_FLOW=1 +FLOWTOOLS=NONE +FAMILY= +[Files] +alu/ALU.v=-1 +data_memory/DataMemory.v=-1 +instruction_memory/InstructionMemory.v=-1 +register_file/RegisterFile.v=-1 +control_unit/ControlUnit.v=-1 +integration/parameter.v=-1 +integration/ClockGenerator.v=-1 +integration/PipelineProcessor.v=-1 +stages/IFStage.v=-1 +stages/MEMStage.v=-1 +stages/EXEStage.v=-1 +stages/IDStage.v=-1 +register/MEM_2_WB.v=-1 +register/EXE_2_MEM.v=-1 +register/ID_2_EXE.v=-1 +register/IF_2_ID.v=-1 +utilities/mux.v=-1 +utilities/Extender.v=-1 +utilities/Compare.v=-1 +stages/MEMStage.v=-1 +stages/MEMStage.v=-1 +[Files.Data] +.\src\alu\ALU.v=Verilog Source Code +.\src\data_memory\DataMemory.v=Verilog Source Code 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file mode 100644 index 0000000000000000000000000000000000000000..e32edca0ef0269f78ca6301c82df5d11a0a6725b Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/PipelineProcessor/slp/slp_catalog.info differ diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/bde.set b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/bde.set new file mode 100644 index 0000000000000000000000000000000000000000..12751b2ffbe4ef49945eeab701c78bb49a5045d2 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/bde.set @@ -0,0 +1,73 @@ +########## +BUS DEFAULT TYPE +STD_LOGIC_VECTOR +########## +CHECK DIAGRAM +YES +########## +GND DEFAULT TYPE +STD_LOGIC +########## +GND DEFAULT VALUE +'0' +########## +HANGING WIRE DEFAULT TYPE +STD_LOGIC +########## +HANGING WIRE DEFAULT VALUE +'Z' +########## +LIBRARIES +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_signed.all; +use IEEE.std_logic_unsigned.all; +########## +VCC DEFAULT TYPE +STD_LOGIC +########## +VCC DEFAULT VALUE +'1' +########## +VERILOG DANGLING DEFAULT VALUE +1'bZ +########## +VERILOG DESIGN UNIT HEADER +`timescale 1ps / 1ps +########## +VERILOG GND DEFAULT VALUE +1'b0 +########## +VERILOG VCC DEFAULT VALUE +1'b1 +########## +WIRE DEFAULT TYPE +STD_LOGIC +########## +VERILOG VCC DEFAULT TYPE +supply1 +########## +VERILOG GND DEFAULT TYPE +supply0 +########## +USE GLOBAL DEFAULTS +1 +########## +INCREMENT NETS +0 +########## +INCREMENT NET FACTOR +1 +########## +INCREMENT NET START +0 +########## +INCLUDE ACTIVE LIBRARY CLAUSE +0 +########## +PAGE_DEFAULT_HEIGHT +1700 +########## +PAGE_DEFAULT_WIDTH +2200 \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compilation.order b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compilation.order new file mode 100644 index 0000000000000000000000000000000000000000..bb6dc98b0b3eb402bcbd43ed0c802075fc00754c --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compilation.order @@ -0,0 +1,19 @@ +.\src\alu\ALU.v +.\src\data_memory\DataMemory.v +.\src\instruction_memory\InstructionMemory.v +.\src\register_file\RegisterFile.v +.\src\control_unit\ControlUnit.v +.\src\integration\parameter.v +.\src\integration\ClockGenerator.v +.\src\integration\PipelineProcessor.v +.\src\stages\IFStage.v +.\src\stages\MEMStage.v +.\src\stages\EXEStage.v +.\src\stages\IDStage.v +.\src\register\MEM_2_WB.v +.\src\register\EXE_2_MEM.v +.\src\register\ID_2_EXE.v +.\src\register\IF_2_ID.v +.\src\utilities\mux.v +.\src\utilities\Extender.v +.\src\utilities\Compare.v diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile.cfg b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile.cfg new file mode 100644 index 0000000000000000000000000000000000000000..7efd62be7f121b58cebc041ff94683522d761cc8 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile.cfg @@ -0,0 +1,110 @@ +[View] +Entity=PipelineProcessor +Architecture= +TopLevelType=3 +[file:.\src\PipelineProcessor.v] +Enabled=1 +[file:.\src\integration\PipelineProcessor.v] +Enabled=1 +[file:.\src\ClockGenerator.v] +Enabled=1 +[file:.\src\integration\ClockGenerator.v] +Enabled=1 +[file:.\src\parameter.v] +Enabled=1 +[file:.\src\integration\parameter.v] +Enabled=1 +[file:.\src\DataMemory.v] +Enabled=1 +[file:.\src\data_memory\DataMemory.v] +Enabled=1 +[file:.\src\InstructionMemory.v] +Enabled=1 +[file:.\src\instruction_memory\InstructionMemory.v] +Enabled=1 +[file:.\src\RegisterFile.v] +Enabled=1 +[file:.\src\register_file\RegisterFile.v] +Enabled=1 +[file:.\src\ControlUnit.v] +Enabled=1 +[file:.\src\control_unit\ControlUnit.v] +Enabled=1 +[file:.\src\ALU.v] +Enabled=1 +[file:.\src\alu\ALU.v] +Enabled=1 +[file:.\src\DataMemoryTestbench.v] +Enabled=1 +[file:.\src\data_memory\DataMemoryTestbench.v] +Enabled=1 +[file:.\src\IFStage.v] +Enabled=1 +[file:.\src\stages\IFStage.v] +Enabled=1 +[file:.\src\mux.v] +Enabled=1 +[file:.\src\PC.v] +Enabled=1 +[file:.\src\DCStage.v] +Enabled=1 +[file:.\src\Compare.v] +Enabled=1 +[file:.\src\utilities\Compare.v] +Enabled=1 +[file:.\src\stages\IDStage.v] +Enabled=1 +[file:.\src\Extender.v] +Enabled=1 +[file:.\src\utilities\Extender.v] +Enabled=1 +[file:.\src\utilities\PC.v] +Enabled=1 +[file:.\src\EXEStage.v] +Enabled=1 +[file:.\src\stages\EXEStage.v] +Enabled=1 +[file:.\src\MEMStage.v] +Enabled=1 +[file:.\src\stages\MEMStage.v] +Enabled=1 +[file:.\src\WBStage.v] +Enabled=1 +[file:.\src\stages\WBStage.v] +Enabled=1 +[file:.\src\IF_2_ID.v] +Enabled=1 +[file:.\src\register\IF_2_ID.v] +Enabled=1 +[file:.\src\ID_2_EXE.v] +Enabled=1 +[file:.\src\register\ID_2_EXE.v] +Enabled=1 +[file:.\src\EXE_2_MEM.v] +Enabled=1 +[file:.\src\register\EXE_2_MEM.v] +Enabled=1 +[file:.\src\MEM_2_WB.v] +Enabled=1 +[file:.\src\register\MEM_2_WB.v] +Enabled=1 +[file:.\src\utilities\mux.v] +Enabled=1 +[file:.\src\integration\stages\MEMStage.v] +Enabled=1 +[file:.\src\integration\stages\EXEStage.v] +Enabled=1 +[file:.\src\integration\stages\IDStage.v] +Enabled=1 +[file:.\src\integration\stages\IFStage.v] +Enabled=1 +[file:.\src\utilities\stages\MEMStage.v] +Enabled=1 +[file:.\src\utilities\stages\EXEStage.v] +Enabled=1 +[file:.\src\utilities\stages\IDStage.v] +Enabled=1 +[file:.\src\utilities\stages\IFStage.v] +Enabled=1 +[file:.\src\IF_Stage\IFStage.v] +Enabled=1 diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/PipelineProcessor.erf b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/PipelineProcessor.erf new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/sources.sth b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/sources.sth new file mode 100644 index 0000000000000000000000000000000000000000..46e6d26d2e17e37160cf4beb4371fdcbce01c7d5 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/sources.sth @@ -0,0 +1,20 @@ +[Files List] +C:/Aldec/Active-HDL-Student-Edition/vlib/std/src/standard.vhd=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/mux.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/data_memory/DataMemory.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/alu/ALU.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/Compare.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register_file/RegisterFile.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/Extender.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/instruction_memory/InstructionMemory.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/MEM_2_WB.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/MEMStage.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/EXE_2_MEM.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/EXEStage.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/ID_2_EXE.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/IDStage.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/IF_2_ID.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/IFStage.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/control_unit/ControlUnit.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/integration/ClockGenerator.v=S +C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/integration/PipelineProcessor.v=S diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/vcp_cmd.log b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/vcp_cmd.log new file mode 100644 index 0000000000000000000000000000000000000000..8304ed2d27471277b87740531b964d795c110e45 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/vcp_cmd.log @@ -0,0 +1 @@ + -a -ls -r -mg mega_win64 8 mega.elb mega.dbg mega.itf mega.cli mega.rep mega.ext mega.tms -fl "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/library.cfg" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/projlib.cfg" -w PipelineProcessor -b PipelineProcessor -o "../compile" -u "C:/Aldec/Active-HDL-Student-Edition/bin/systf.dll" -g "5" -O2 -p "C:\Users\user\Documents\Verilog\PipelineProcessorDesign\PipelineProcessor\PipelineProcessor" -tmp "C:\Users\user\AppData\Local\Temp\10944_526926468" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/alu/ALU.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/data_memory/DataMemory.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/instruction_memory/InstructionMemory.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register_file/RegisterFile.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/control_unit/ControlUnit.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/integration/parameter.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/integration/ClockGenerator.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/integration/PipelineProcessor.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/IFStage.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/MEMStage.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/EXEStage.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/IDStage.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/MEM_2_WB.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/EXE_2_MEM.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/ID_2_EXE.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/IF_2_ID.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/mux.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/Extender.v" "C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/Compare.v" -sve -sv2k17 \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/vlog.cmd b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/vlog.cmd new file mode 100644 index 0000000000000000000000000000000000000000..954429b10497ff30164b91b997d434f34a931cfc --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/compile/vlog.cmd @@ -0,0 +1 @@ +-o C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/compile -lc C:/Users/user/Documents/Verilog/PipelineProcessorDesign/library.cfg -fl C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/projlib.cfg -pli "C:/Aldec/Active-HDL-Student-Edition/bin/systf.dll" -O2 -sve -msg 5 -sv2k17 -work PipelineProcessor C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/alu/ALU.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/data_memory/DataMemory.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/instruction_memory/InstructionMemory.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register_file/RegisterFile.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/control_unit/ControlUnit.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/integration/parameter.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/integration/ClockGenerator.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/integration/PipelineProcessor.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/IFStage.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/MEMStage.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/EXEStage.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/stages/IDStage.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/MEM_2_WB.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/EXE_2_MEM.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/ID_2_EXE.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/register/IF_2_ID.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/mux.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/Extender.v C:/Users/user/Documents/Verilog/PipelineProcessorDesign/PipelineProcessor/src/utilities/Compare.v \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/log/console.log b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/log/console.log new file mode 100644 index 0000000000000000000000000000000000000000..37e9459fabd1bc92c68432d030b7c27e3a9eb3f0 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/log/console.log @@ -0,0 +1,33 @@ +# ELBREAD: Elaboration process. +# ELBREAD: Elaboration time 0.0 [s]. +alog -O2 -sve -msg 5 -sv2k17 -work PipelineProcessor $dsn/src/alu/ALU.v $dsn/src/data_memory/DataMemory.v $dsn/src/instruction_memory/InstructionMemory.v $dsn/src/register_file/RegisterFile.v $dsn/src/control_unit/ControlUnit.v $dsn/src/integration/parameter.v $dsn/src/integration/ClockGenerator.v $dsn/src/integration/PipelineProcessor.v $dsn/src/stages/IFStage.v $dsn/src/stages/MEMStage.v $dsn/src/stages/EXEStage.v $dsn/src/stages/IDStage.v $dsn/src/register/MEM_2_WB.v $dsn/src/register/EXE_2_MEM.v $dsn/src/register/ID_2_EXE.v $dsn/src/register/IF_2_ID.v $dsn/src/utilities/mux.v $dsn/src/utilities/Extender.v $dsn/src/utilities/Compare.v +# Info: VCP2876 register_file/RegisterFile.v : (25, 17): Implicit net declaration, symbol R7 has not been declared in module RegisterFile. +# Error: VCP2000 control_unit/ControlUnit.v : (13, 22): Syntax error. Unexpected token: ,. +# Error: VCP2020 control_unit/ControlUnit.v : (71, 16): begin...end pair(s) mismatch detected. 2 tokens are missing. +# Error: VCP2020 control_unit/ControlUnit.v : (71, 16): module/macromodule...endmodule pair(s) mismatch detected. 1 tokens are missing. +# Error: VCP2000 control_unit/ControlUnit.v : (71, 16): Syntax error. Unexpected token: endcase[_ENDCASE]. +# Compile failure 4 Errors 0 Warnings Analysis time: 0[s]. +alog -O2 -sve -msg 5 -sv2k17 -work PipelineProcessor $dsn/src/alu/ALU.v $dsn/src/data_memory/DataMemory.v $dsn/src/instruction_memory/InstructionMemory.v $dsn/src/register_file/RegisterFile.v $dsn/src/control_unit/ControlUnit.v $dsn/src/integration/parameter.v $dsn/src/integration/ClockGenerator.v $dsn/src/integration/PipelineProcessor.v $dsn/src/stages/IFStage.v $dsn/src/stages/MEMStage.v $dsn/src/stages/EXEStage.v $dsn/src/stages/IDStage.v $dsn/src/register/MEM_2_WB.v $dsn/src/register/EXE_2_MEM.v $dsn/src/register/ID_2_EXE.v $dsn/src/register/IF_2_ID.v $dsn/src/utilities/mux.v $dsn/src/utilities/Extender.v $dsn/src/utilities/Compare.v +# Info: VCP2876 register_file/RegisterFile.v : (25, 17): Implicit net declaration, symbol R7 has not been declared in module RegisterFile. +# Error: VCP2000 control_unit/ControlUnit.v : (13, 22): Syntax error. Unexpected token: ,. +# Error: VCP2020 control_unit/ControlUnit.v : (71, 16): begin...end pair(s) mismatch detected. 2 tokens are missing. +# Error: VCP2020 control_unit/ControlUnit.v : (71, 16): module/macromodule...endmodule pair(s) mismatch detected. 1 tokens are missing. +# Error: VCP2000 control_unit/ControlUnit.v : (71, 16): Syntax error. Unexpected token: endcase[_ENDCASE]. +# Compile failure 4 Errors 0 Warnings Analysis time: 0[s]. +alog -O2 -sve -msg 5 -sv2k17 -work PipelineProcessor $dsn/src/alu/ALU.v $dsn/src/data_memory/DataMemory.v $dsn/src/instruction_memory/InstructionMemory.v $dsn/src/register_file/RegisterFile.v $dsn/src/control_unit/ControlUnit.v $dsn/src/integration/parameter.v $dsn/src/integration/ClockGenerator.v $dsn/src/integration/PipelineProcessor.v $dsn/src/stages/IFStage.v $dsn/src/stages/MEMStage.v $dsn/src/stages/EXEStage.v $dsn/src/stages/IDStage.v $dsn/src/register/MEM_2_WB.v $dsn/src/register/EXE_2_MEM.v $dsn/src/register/ID_2_EXE.v $dsn/src/register/IF_2_ID.v $dsn/src/utilities/mux.v $dsn/src/utilities/Extender.v $dsn/src/utilities/Compare.v +# Info: VCP2876 register_file/RegisterFile.v : (25, 17): Implicit net declaration, symbol R7 has not been declared in module RegisterFile. +# Error: VCP2000 control_unit/ControlUnit.v : (13, 22): Syntax error. Unexpected token: ,. +# Error: VCP2020 control_unit/ControlUnit.v : (71, 16): begin...end pair(s) mismatch detected. 2 tokens are missing. +# Error: VCP2020 control_unit/ControlUnit.v : (71, 16): module/macromodule...endmodule pair(s) mismatch detected. 1 tokens are missing. +# Error: VCP2000 control_unit/ControlUnit.v : (71, 16): Syntax error. Unexpected token: endcase[_ENDCASE]. +# Compile failure 4 Errors 0 Warnings Analysis time: 0[s]. +alog -O2 -sve -msg 5 -sv2k17 -work PipelineProcessor $dsn/src/alu/ALU.v $dsn/src/data_memory/DataMemory.v $dsn/src/instruction_memory/InstructionMemory.v $dsn/src/register_file/RegisterFile.v $dsn/src/control_unit/ControlUnit.v $dsn/src/integration/parameter.v $dsn/src/integration/ClockGenerator.v $dsn/src/integration/PipelineProcessor.v $dsn/src/stages/IFStage.v $dsn/src/stages/MEMStage.v $dsn/src/stages/EXEStage.v $dsn/src/stages/IDStage.v $dsn/src/register/MEM_2_WB.v $dsn/src/register/EXE_2_MEM.v $dsn/src/register/ID_2_EXE.v $dsn/src/register/IF_2_ID.v $dsn/src/utilities/mux.v $dsn/src/utilities/Extender.v $dsn/src/utilities/Compare.v +# Info: VCP2876 register_file/RegisterFile.v : (25, 17): Implicit net declaration, symbol R7 has not been declared in module RegisterFile. +# Unit top modules: ALU_TB DataMemory_TB InstructionMemory_TB RegisterFile_TB PipelineProcessor IFStage_TB MEMStage_TB EXEStage_TB IDStage_TB Extender_TB Compare_TB. +# Compile success 0 Errors 0 Warnings Analysis time: 0[s]. +# done +alog -O2 -sve -msg 5 -sv2k17 -work PipelineProcessor $dsn/src/alu/ALU.v $dsn/src/data_memory/DataMemory.v $dsn/src/instruction_memory/InstructionMemory.v $dsn/src/register_file/RegisterFile.v $dsn/src/control_unit/ControlUnit.v $dsn/src/integration/parameter.v $dsn/src/integration/ClockGenerator.v $dsn/src/integration/PipelineProcessor.v $dsn/src/stages/IFStage.v $dsn/src/stages/MEMStage.v $dsn/src/stages/EXEStage.v $dsn/src/stages/IDStage.v $dsn/src/register/MEM_2_WB.v $dsn/src/register/EXE_2_MEM.v $dsn/src/register/ID_2_EXE.v $dsn/src/register/IF_2_ID.v $dsn/src/utilities/mux.v $dsn/src/utilities/Extender.v $dsn/src/utilities/Compare.v +# Info: VCP2876 register_file/RegisterFile.v : (25, 17): Implicit net declaration, symbol R7 has not been declared in module RegisterFile. +# Unit top modules: ALU_TB DataMemory_TB InstructionMemory_TB RegisterFile_TB PipelineProcessor IFStage_TB MEMStage_TB EXEStage_TB IDStage_TB Extender_TB Compare_TB. +# Compile success 0 Errors 0 Warnings Analysis time: 0[s]. +# done diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/pipelineprocessor.wsp b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/pipelineprocessor.wsp new file mode 100644 index 0000000000000000000000000000000000000000..dbaadfe2787bad7116e24862cbca8a69a6fd1101 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/pipelineprocessor.wsp @@ -0,0 +1,507 @@ +[CACHESIMPLE|Aldec.SymbolsCommands.7] +Built-in symbols=0 +PipelineProcessor=0 +[COMPILESTATUS|.\src\PipelineProcessor.v] +FileTimeLow=2049199500 +FileTimeHigh=31108195 +Status=Modified +[CACHEDOC|Aldec.Hde.HdePlugIn.7|.\PipelineProcessor\src\PipelineProcessor.v|] +CurrentLine=0 +CurrentColumn=12 +Bookmarks=-1 +BookmarksLength=3 +ZoomFactor=0 +Frame=0 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index 0000000000000000000000000000000000000000..a673421a46e9d4e11c58c40bb1b998b7ff42f0ee --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/alu/ALU.v @@ -0,0 +1,68 @@ +module ALU( + input wire signed [15:0] A, B, + input wire [1:0] ALUop, + output reg signed [15:0] Output +); + + + always @(*) begin + case (ALUop) + ALU_OP_AND: Output <= A & B; + ALU_OP_ADD: Output <= A + B; + ALU_OP_SUB: Output <= A - B; + default: Output <= 16'b0; + endcase + end + + +endmodule + + +module ALU_TB; + + reg signed [15:0] A, B; // Declare testbench registers as signed + wire signed [15:0] Output; // Declare output wire as signed + reg [1:0] ALUop; + + // Instantiate the ALU + ALU alu(A, B, ALUop , Output); + + initial begin + // Unsigned test cases + #0 + A <= 16'd3; + B <= 16'd2; + ALUop <= ALU_OP_AND; + #10; + + A <= 16'd30; + B <= 16'd20; + ALUop <= ALU_OP_SUB; + #10; + + A <= 16'd30; + B <= 16'd30; + ALUop <= ALU_OP_ADD; + #10; + + // Signed test cases + A <= 16'sd15; + B <= -16'sd10; + ALUop <= ALU_OP_ADD; + #10; + + A <= -16'sd20; + B <= 16'sd25; + ALUop <= ALU_OP_SUB; + #10; + + A <= -16'sd10; + B <= -16'sd5; + ALUop <= ALU_OP_AND; + #10; + + $finish; + end + +endmodule + diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/control_unit/ControlUnit.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/control_unit/ControlUnit.v new file mode 100644 index 0000000000000000000000000000000000000000..93cd2ab853ba511fd2f6e2c746c3eb056e3bfe99 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/control_unit/ControlUnit.v @@ -0,0 +1,164 @@ +module MainAluControl ( + input [3:0] opCode, + input [2:0] Rd, + input mode,stall, + output reg [16:0] signlas +); + +// SRC1{2} SRC2 RegDst ExtOp ExtPlace AluSRC ALUOP{2} DataInSrc MemRd MemWr NumOfByte{2} WBdata{2} RegWr + +always @ (opCode,mode) begin + + if (stall == 0) begin + case (opCode) + AND: signlas <= {2'b00 , 1'b1 , 1'b0 , 1'bx , 1'bx , 1'b0 , 2'b00 , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'b01 , 1'b1}; + ADD: signlas <= {2'b00 , 1'b1 , 1'b0 , 1'bx , 1'bx , 1'b0 , 2'b01 , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'b01 , 1'b1}; + SUB: signlas <= {2'b00 , 1'b1 , 1'b0 , 1'bx , 1'bx , 1'b0 , 2'b10 , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'b01 , 1'b1}; + ADDI: signlas <= {2'b00 , 1'b0 , 1'b0 , 1'b1 , 1'b0 , 1'b1 , 2'b01 , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'b01 , 1'b1}; + ANDI: signlas <= {2'b00 , 1'b0 , 1'b0 , 1'b1 , 1'b0 , 1'b1 , 2'b00 , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'b01 , 1'b1}; + LW: signlas <= {2'b00 , 1'bx , 1'b0 , 1'b1 , 1'b0 , 1'b1 , 2'b01 , 1'bx , 1'b1 , 1'b0 , 2'b00 , 2'b10 , 1'b1}; + SW: signlas <= {2'b00 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'b1 , 2'b01 , 1'b1 , 1'b0 , 1'b1 , 2'b10 , 2'bxx , 1'b0}; + LoadByte: + begin + if (!mode) begin + signlas <= {2'b00 , 1'bx , 1'b0 , 1'b1 , 1'b0 , 1'b1 , 2'b01 , 1'bx , 1'b1 , 1'b0 , 2'b01 , 2'b10 , 1'b1}; + end else begin + signlas <= {2'b00 , 1'bx , 1'b0 , 1'b1 , 1'b0 , 1'b1 , 2'b01 , 1'bx , 1'b1 , 1'b0 , 2'b10 , 2'b10 , 1'b1}; + end + end + + BranchGreater: + begin + if (!mode) begin + signlas <= {2'b00 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + end else begin + signlas <= {2'b01 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + end + end + + BranchLess: + begin + if (!mode) begin + signlas <= {2'b00 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + end else begin + signlas <= {2'b01 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + end + end + + BranchEqual: + begin + if (!mode) begin + signlas <= {2'b00 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + end else begin + signlas <= {2'b01 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + end + end + + BranchNotEqual: + begin + if (!mode) begin + signlas <= {2'b00 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + end else begin + signlas <= {2'b01 , 1'b0 , 1'bx , 1'b1 , 1'b0 , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + end + end + + JMP: signlas <= {2'bxx , 1'bx , 1'bx , 1'bx , 1'bx , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + CALL: signlas <= {2'bxx , 1'bx , 1'b1 , 1'bx , 1'bx , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'b00 , 1'b1}; + RET: signlas <= {2'b10 , 1'bx , 1'bx , 1'bx , 1'bx , 1'bx , 2'bxx , 1'bx , 1'b0 , 1'b0 , 2'bxx , 2'bxx , 1'b0}; + SV: signlas <= {2'b01 , 1'b0 , 1'bx , 1'b0 , 1'b1 , 1'b0 , 2'b01 , 1'b0 , 1'b0 , 1'b1 , 2'bxx , 2'bxx , 1'b0}; + + endcase + + end + + else begin + signlas <= 16'b0; + end + + end + + initial begin + $monitor("%0t ==> opcode=%d , Rd=%d , signlas[0]=%b",$time,opCode,Rd,signlas[0] ) ; + end +endmodule + + + + + + +module PcControl ( + input [3:0] opCode, + input stall, + input GT,LT,EQ, + output reg [1:0] PcSrc, + output reg kill +); + + initial begin + PcSrc=0; + kill=0; + end + + always @ (*) begin + if ((opCode==BranchGreater && GT) || (opCode==BranchLess && LT) || (opCode==BranchEqual && EQ) || (opCode==BranchNotEqual && !EQ)) begin + PcSrc=2; + kill=1; + end else if (opCode == JMP || opCode == CALL) begin + PcSrc=1; + kill=1; + end else if (opCode == RET) begin + PcSrc=3; + kill=1; + end else begin + PcSrc=0; + kill=0; + end + end + + +endmodule + + +module HazardDetect ( + input [3:0] opCode, + input [2:0] RS1,RS2,Rd2,Rd3,Rd4, + input EX_RegWr, MEM_RegWr ,WB_RegWr,EX_MemRd, + output reg stall, + output reg [1:0] ForwardA,ForwardB +); + + initial begin + stall=0; + end + + always @(*) begin + // ForwardA logic + if ((RS1 != 0) && (RS1 == Rd2) && EX_RegWr) + ForwardA = 1; + else if ((RS1 != 0) && (RS1 == Rd3) && MEM_RegWr) + ForwardA = 2; + else if ((RS1 != 0) && (RS1 == Rd4) && WB_RegWr) + ForwardA = 3; + else + ForwardA = 0; + + // ForwardB logic + if ((RS2 != 0) && (RS2 == Rd2) && EX_RegWr) + ForwardB = 1; + else if ((RS2 != 0) && (RS2 == Rd3) && MEM_RegWr) + ForwardB = 2; + else if ((RS2 != 0) && (RS2 == Rd4) && WB_RegWr) + ForwardB = 3; + else + ForwardB = 0; + + // Stall logic + if (EX_MemRd && ((ForwardA == 1) || (ForwardB == 1))) + stall = 1; + else + stall = 0; + end + +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/data_memory/DataMemory.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/data_memory/DataMemory.v new file mode 100644 index 0000000000000000000000000000000000000000..19dd082bf7bf7f8ea952a5bf3d21e01965ec7ed5 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/data_memory/DataMemory.v @@ -0,0 +1,144 @@ +module DataMemory ( + input wire clk, + input wire wrEnable, + input wire rdEnable, + input wire [1:0]numberOfByte, + input wire [15:0] address, + input wire [15:0] in, + output reg [15:0] out, +); + + reg [7:0] memory [0:255]; // the size will be 2 ^ 16 + + initial begin + memory[0] = 8'd0; + memory[1] = 8'd1; + memory[2] = 8'd2; + memory[3] = 8'd3; + memory[4] = 8'd3; + end + + always @(posedge clk) begin + #1 + if (wrEnable) begin + + memory[address] = in[7:0]; + + // Writing 16-bit data to two consecutive memory locations + if (numberOfByte == 2'b10) + memory[address + 1] = in[15:8]; + + end + end + + + always @(posedge clk) begin + #1 + if (rdEnable) + if (numberOfByte == 2'b00) begin + // Reading 16-bit data from two consecutive memory locations + out = {memory[address + 1], memory[address]}; + end else if (numberOfByte == 2'b01) begin + // Reading 8-bit data from one memory location with MSB = 00000000 + out = {8'b00000000, memory[address]}; + end else if (numberOfByte == 2'b10) begin + // Sign extend memory[address] and store to out + out = {{8{memory[address][7]}}, memory[address]}; + end + + end + + initial begin + $monitor("%0t ==> memory[0]=%b , memory[1]=%b , memory[2]=%b , memory[3]=%b , memory[4]=%b",$time,memory[0],memory[1],memory[2],memory[3],memory[4]); + $monitor("%0t ==> memory[5]=%b , memory[6]=%b , memory[7]=%b , memory[8]=%b , memory[9]=%b",$time,memory[5],memory[6],memory[7],memory[8],memory[9]); + end +endmodule + + +module DataMemory_TB; + // Inputs + reg clk; + reg wrEnable; + reg rdEnable; + reg [1:0] numberOfByte; + reg [15:0] address; + reg [15:0] in; + + // Outputs + wire [15:0] out; + + // Instantiate the DataMemory module + DataMemory uut ( + .clk(clk), + .wrEnable(wrEnable), + .rdEnable(rdEnable), + .numberOfByte(numberOfByte), + .address(address), + .in(in), + .out(out) + ); + + // Clock generation + initial begin + clk = 0; + forever #5 clk = ~clk; // Clock period is 10 units + end + + // Test sequence + initial begin + // Initialize inputs + wrEnable = 0; + rdEnable = 0; + numberOfByte = 2'b00; + address = 16'd0; + in = 16'd0; + + // Wait for the initial memory content to be displayed + #10; + + // Test writing 8-bit data + wrEnable = 1; + address = 16'd1; + in = 16'h0045; // Write 0x45 to memory[1] + numberOfByte = 2'b00; + #10; + + // Test writing 16-bit data + address = 16'd2; + in = 16'h1294; // Write 0x34 to memory[2] and 0x12 to memory[3] + numberOfByte = 2'b10; + #10; + + // Disable write enable + wrEnable = 0; + + // Test reading 16-bit data + rdEnable = 1; + address = 16'd2; + numberOfByte = 2'b00; // Read 16-bit data from memory[2] and memory[3] + #10; + + // Test reading 8-bit data with zero extension + address = 16'd2; + numberOfByte = 2'b01; // Read 8-bit data from memory[1] with zero extension + #10; + + // Test reading 8-bit data with sign extension + address = 16'd2; + numberOfByte = 2'b10; // Read 8-bit data from memory[4] with sign extension + #10; + + // Disable read enable + rdEnable = 0; + + // Finish the simulation + #10; + $finish; + end + + // Monitor output and memory content + initial begin + $monitor("Time: %0t | address = %h | in = %h | out = %h | wrEnable = %b | rdEnable = %b | numberOfByte = %b", + $time, address, in, out, wrEnable, rdEnable, numberOfByte); + end +endmodule diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v new file mode 100644 index 0000000000000000000000000000000000000000..60c600270963e5bad2a102ce2c13ad105a948c0f --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/instruction_memory/InstructionMemory.v @@ -0,0 +1,136 @@ +module InstructionMemory( + input wire clk,kill,stall, + input wire [15:0] address, + output reg [0:15] instruction +); + + + reg [7:0] instructionMemory [0:255]; // the size will be 2 ^ 16 + + + always @(posedge clk) begin + + if (!stall) + instruction <= {instructionMemory[address + 1], instructionMemory[address]}; + + end + + initial begin + + // ****************************************************************************** + // ****************************************************************************** + // Courtesy of Dr. Aziz + // We change the format for I-type instruction as follows + // + // [15-12] Opcode , [11-9] Rd , [8-6] Rs1 , [5] M , [4-0] Imm + // ****************************************************************************** + // ****************************************************************************** + + {instructionMemory[1],instructionMemory[0]} = {LW, R1, R0, 1'b0, 5'b00001}; // Load memory[1:2] into R1 + {instructionMemory[3],instructionMemory[2]} = {LW, R2, R0, 1'b0, 5'b00011}; // Load memory[3:4] into R2 + {instructionMemory[5],instructionMemory[4]} = {ADD, R3, R1, R2, 3'b000}; // R3 = R1 + R2 + {instructionMemory[7],instructionMemory[6]} = {SW, R3, R0, 1'b0, 5'b00101}; // Store R3 in memory[5:6] + +// {instructionMemory[1],instructionMemory[0]} = {AND, R4, R6, R7, 3'b000}; +// {instructionMemory[3],instructionMemory[2]} = {ADD, R6, R4, R2, 3'b000}; +// {instructionMemory[5],instructionMemory[4]} = {SUB, R5, R3, R5, 3'b000}; +// {instructionMemory[7],instructionMemory[6]} = {SV , R1, 1'b0 , 8'hFF}; +// {instructionMemory[9],instructionMemory[8]} = {LW , R7, R0 ,1'b0, 5'h01}; +// {instructionMemory[11],instructionMemory[10]} = {CALL , 12'h010}; +// {instructionMemory[13],instructionMemory[12]} = {LW , R3, R0 ,1'b0, 5'b00001}; +// {instructionMemory[15],instructionMemory[14]} = {LW , R4, R1 ,1'b0, 5'b00000}; +// {instructionMemory[17],instructionMemory[16]} = {SW , R4, R2 ,1'b0, 5'b00000}; +// {instructionMemory[19],instructionMemory[18]} = {ADD, R4, R6, R7, 3'b000}; +// {instructionMemory[21],instructionMemory[20]} = {RET , 12'h000}; + + +// Program 2 +// {instructionMemory[1],instructionMemory[0]} = {AND, R4, R6, R7, 3'b000}; +// {instructionMemory[3],instructionMemory[2]} = {JMP, 12'h00A}; +// {instructionMemory[5],instructionMemory[4]} = {SUB, R5, R3, R5, 3'b000}; +// {instructionMemory[7],instructionMemory[6]} = {SV , R1, 1'b0 , 8'hFF}; +// {instructionMemory[9],instructionMemory[8]} = {LBu , R3, R0 ,1'b0, 5'h01}; +// {instructionMemory[11],instructionMemory[10]} = {LBs , R3, R1 ,1'b1, 5'h00}; +// {instructionMemory[13],instructionMemory[12]} = {ADD , R3, R3,R2 ,3'b000}; + + +// Program 3 +// {instructionMemory[1],instructionMemory[0]} = {AND, R4, R6, R7, 3'b000}; +// {instructionMemory[3],instructionMemory[2]} = {JMP, 12'h00A}; +// {instructionMemory[5],instructionMemory[4]} = {SUB, R5, R3, R5, 3'b000}; +// {instructionMemory[7],instructionMemory[6]} = {SV , R1, 1'b0 , 8'hFF}; +// {instructionMemory[9],instructionMemory[8]} = {LBu , R3, R0 ,1'b0, 5'h01}; +// {instructionMemory[11],instructionMemory[10]} = {AND, R4, R6, R7, 3'b000}; +// {instructionMemory[13],instructionMemory[12]} = {BEQ , R4, R4 ,1'b0,5'h03}; +// {instructionMemory[15],instructionMemory[14]} = {AND, R4, R6, R7, 3'b000}; +// {instructionMemory[17],instructionMemory[16]} = {ADD , R3, R3,R2 ,3'b000}; + + end + +endmodule + + +module InstructionMemory_TB; + + // Inputs + reg clk; + reg kill; + reg stall; + reg [15:0] address; + + // Outputs + wire [15:0] instruction; + + // Instantiate the Unit Under Test (UUT) + InstructionMemory uut ( + .clk(clk), + .kill(kill), + .stall(stall), + .address(address), + .instruction(instruction) + ); + + // Clock generation + initial begin + clk = 0; + forever #5 clk = ~clk; // 10 ns period + end + + initial begin + // Initialize Inputs + kill = 0; + stall = 0; + address = 0; + + // Wait for global reset to finish + #10; + + // Test sequence + address = 16'h0000; #10; // Expecting first instruction + address = 16'h0002; #10; // Expecting second instruction + address = 16'h0004; #10; // Expecting third instruction + address = 16'h0006; #10; // Expecting fourth instruction + address = 16'h0008; #10; // Expecting fifth instruction + address = 16'h000A; #10; // Expecting sixth instruction + address = 16'h000C; #10; // Expecting seventh instruction + address = 16'h000E; #10; // Expecting eighth instruction + address = 16'h0010; #10; // Expecting ninth instruction + address = 16'h0012; #10; // Expecting tenth instruction + + // Test stall signal + stall = 1; + address = 16'h0014; #10; // No change in instruction + stall = 0; #10; // Fetch new instruction + + // End of simulation + $finish; + end + + // Display instruction output for debugging + initial begin + $monitor("At time %t, Address = %h, Instruction = %h", $time, address, instruction); + end + +endmodule + + diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/ClockGenerator.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/ClockGenerator.v new file mode 100644 index 0000000000000000000000000000000000000000..90e6fba4108b5dae0dc42b9c56e409ed28b39146 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/ClockGenerator.v @@ -0,0 +1,15 @@ +module ClockGenerator (output reg clk); + + +initial begin + clk=LOW; + $display("(%0t) ==> The clk was initialize", $time); +end + + +always #5 begin + clk=~clk; +end + + +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/PipelineProcessor.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/PipelineProcessor.v new file mode 100644 index 0000000000000000000000000000000000000000..d98b67b29880ded4a56a346ae49f280d691e45ee --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/PipelineProcessor.v @@ -0,0 +1,239 @@ +module PipelineProcessor (); + + initial begin + #190 $finish; + end + + + + //****************************************************** + // clock + //****************************************************** + + wire clk; + + ClockGenerator clock( + .clk(clk) + ); + + //****************************************************** + // registers + //****************************************************** + + wire [15:0] inst_IF, inst_ID; + wire [15:0] PC_IF, PC_ID, PC_EXE,PC_MEM; + + + wire [15:0] valueA_ID, valueA_EXE; + wire [15:0] valueB_ID, valueB_EXE,valueB_MEM; + wire [15:0] immediate_ID , immediate_EXE,immediate_MEM; + wire [2:0] Rd_ID,Rd_EXE,Rd_MEM,Rd_WB; + + wire [2:0] Ra_ID,Rb_ID; + + wire [15:0] AluResult_EXE,AluResult_MEM; + + + wire [15:0] DataWB_MEM,DataWB_WB; + + wire stall, GT, LT, EQ, kill; + wire [1:0] PcSrc,ForwardA, ForwardB; + + + wire [16:0] signals; + wire [10:0] EXE_signals; + wire [7:0] MEM_signals; + wire WB_signals; + + + wire [15:0] I_TypeImmediate, J_TypeImmediate, ReturnAddress; + + + + + + + + //****************************************************** + // Control unit + //****************************************************** + + // Control Unit + MainAluControl main_alu_control ( + .opCode(inst_ID[15:12]), + .Rd(inst_ID[11:9]), + .mode(inst_ID[5]), + .stall(stall), + .signlas(signals) + ); + + // PC Control + PcControl pc_control ( + .opCode(inst_ID[15:12]), + .stall(stall), + .GT(GT), + .LT(LT), + .EQ(EQ), + .PcSrc(PcSrc), + .kill(kill) + ); + + // Hazard Detection + HazardDetect hazard_detect ( + .opCode(inst_ID[15:12]), + .RS1(Ra_ID), + .RS2(Rb_ID), + .Rd2(Rd_EXE), + .Rd3(Rd_MEM), + .Rd4(Rd_WB), + .EX_RegWr(EXE_signals[0]), + .MEM_RegWr(MEM_signals[0]), + .WB_RegWr(WB_signals), + .EX_MemRd(EXE_signals[6]), + .stall(stall), + .ForwardA(ForwardA), + .ForwardB(ForwardB) + ); + + + //****************************************************** + // Pipeline IF stages + //****************************************************** + + + // IF Stage + IFStage if_stage ( + .clk(clk), + .stall(stall), + .kill(kill), + .PCsrc(PcSrc), + .I_TypeImmediate(I_TypeImmediate), + .J_TypeImmediate(J_TypeImmediate), + .ReturnAddress(ReturnAddress), + .NPC(PC_IF), + .inst_IF(inst_IF) + ); + + IF2ID IF2ID_registers ( + .clk(clk), + .stall(stall), + .PCIN(PC_IF), + .instructionIN(inst_IF), + + //output + .PC(PC_ID), + .instruction(inst_ID) + ); + + + + //****************************************************** + // Pipeline ID stages + //****************************************************** + + + IDStage id_stage ( + .clk(clk), + .ForwardA(ForwardA), + .ForwardB(ForwardB), + .WB_signals(WB_signals), + .signals(signals[16:11]), // Passing relevant bits of signals + .inst_ID(inst_ID), + .PC_ID(PC_ID), + .AluResult_EXE(AluResult_EXE), + .DataWB_MEM(DataWB_MEM), + .DataWB_WB(DataWB_WB), + .DestinationRegister(Rd_WB), + .I_TypeImmediate(I_TypeImmediate), + .J_TypeImmediate(J_TypeImmediate), + .ReturnAddress(ReturnAddress), + .immediate_ID(immediate_ID), + .valueA_ID(valueA_ID), + .valueB_ID(valueB_ID), + .Rd_ID(Rd_ID), + .Ra_ID(Ra_ID), + .Rb_ID(Rb_ID), + .gt(GT), + .lt(LT), + .eq(EQ) + ); + + ID2EXE ID2EXE_registers ( + .clk(clk), + .stall(stall), + .valueAIN(valueA_ID) , + .valueBIN(valueB_ID), + .immIN(immediate_ID), + .PCIN(PC_ID), + .RdIN(Rd_ID), + .EXE_signals_IN(signals[10:0]), + + // output + .valueA(valueA_EXE), + .valueB(valueB_EXE), + .imm(immediate_EXE), + .PC(PC_EXE), + .Rd(Rd_EXE), + .EXE_signals(EXE_signals) + ); + + //****************************************************** + // Pipeline EXE stages + //****************************************************** + + EXEStage exe_stage ( + .clk(clk), + .immediate_EXE(immediate_EXE), + .valueA_EXE(valueA_EXE), + .valueB_EXE(valueB_EXE), + .signals(EXE_signals[10:8]), + .AluResult_EXE(AluResult_EXE) + ); + + EXE2MEM EXE2MEM_registers ( + .clk(clk), + .valueFromALU_IN(AluResult_EXE), + .valueFromReg_IN(valueB_EXE), + .immIN(immediate_EXE), + .PCIN(PC_EXE), + .RdIN(Rd_EXE), + .MEM_signals_IN(EXE_signals[7:0]), + + // output + .valueFromALU(AluResult_MEM), + .valueFromReg(valueB_MEM), + .imm(immediate_MEM), + .PC(PC_MEM), + .Rd(Rd_MEM), + .MEM_signals(MEM_signals) + ); + + + + //****************************************************** + // Pipeline MEM stages + //****************************************************** + + + MEMStage mem_stage ( + .clk(clk), + .AluResult_MEM(AluResult_MEM), + .immediate_MEM(immediate_MEM), + .valueB_MEM(valueB_MEM), + .PC_MEM(PC_MEM), + .signals(MEM_signals[7:1]), + .DataWB_MEM(DataWB_MEM) + ); + + MEM2WB MEM2WB_registers( + .clk(clk), + .DataWB_IN(DataWB_MEM), + .Rd_IN(Rd_MEM), + .WB_signal_IN(MEM_signals[0]), + .DataWB(DataWB_WB), + .Rd(Rd_WB), + .WB_signal(WB_signals) + ); + + +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/parameter.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/parameter.v new file mode 100644 index 0000000000000000000000000000000000000000..e475aed69ad54c9d9309ab802fc7c2432b38577b --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/integration/parameter.v @@ -0,0 +1,48 @@ +parameter + + LOW = 0, + HIGH = 1, + + OP_CODE_LENGTH=3'd4, + AND = 4'b0000, // AND operation + ADD = 4'b0001, // ADD operation + SUB = 4'b0010, // SUB operation + ADDI = 4'b0011, // ADD Immediate + ANDI = 4'b0100, // AND Immediate + LW = 4'b0101, // Load Word + LoadByte = 4'b0110, + LBu = 4'b0110, // Load Byte unsigned + LBs = 4'b0110, // Load Byte signed + + SW = 4'b0111, // Store Word + BranchGreater = 4'b1000, // Branch if Greater + BGT = 4'b1000, // Branch if Greater Than + BGTZ = 4'b1000, // Branch if Greater Than Zero + BranchLess = 4'b1001, + BLT = 4'b1001, // Branch if Less Than + BLTZ = 4'b1001, // Branch if Less Than Zero + BranchEqual = 4'b1010, + BEQ = 4'b1010, // Branch if Equal + BEQZ = 4'b1010, // Branch if Equal to Zero + BranchNotEqual = 4'b1011, + BNE = 4'b1011, // Branch if Not Equal + BNEZ = 4'b1011, // Branch if Not Equal to Zero + + JMP = 4'b1100, // Jump + CALL = 4'b1101, // Call subroutine + RET = 4'b1110, // Return from subroutine + SV = 4'b1111, // Store value + + R0 = 3'd0, // zero register + R1 = 3'd1, // general purpose register + R2 = 3'd2, // general purpose register + R3 = 3'd3, // general purpose register + R4 = 3'd4, // general purpose register + R5 = 3'd5, // general purpose register + R6 = 3'd6, // general purpose register + R7 = 3'd7, // general purpose register + + ALU_OP_CODE_LENGTH=3'd2, + ALU_OP_AND = 2'b00, + ALU_OP_ADD = 2'b01, + ALU_OP_SUB = 2'b10; \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/EXE_2_MEM.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/EXE_2_MEM.v new file mode 100644 index 0000000000000000000000000000000000000000..212141415b39e85ae8355879bcbe9fe89cce6cdf --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/EXE_2_MEM.v @@ -0,0 +1,27 @@ +module EXE2MEM ( + input clk, + input [15:0] valueFromALU_IN, valueFromReg_IN, immIN, PCIN, + input [2:0] RdIN, + input [7:0] MEM_signals_IN, + output reg [15:0] valueFromALU, valueFromReg , imm, PC, + output reg [2:0] Rd, + output reg [7:0] MEM_signals +); + + + always @ (posedge clk) begin + + + valueFromALU <= valueFromALU_IN; + valueFromReg <= valueFromReg_IN; + imm <= immIN; + PC <= PCIN; + Rd <= RdIN; + MEM_signals = MEM_signals_IN; + + + end + + + +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/ID_2_EXE.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/ID_2_EXE.v new file mode 100644 index 0000000000000000000000000000000000000000..1e54e0c7702a85ddb40cb021a24e83e0acf0d89b --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/ID_2_EXE.v @@ -0,0 +1,29 @@ +module ID2EXE ( + input clk,stall, + input [15:0] valueAIN, valueBIN, immIN, PCIN, + input [2:0] RdIN, + input [10:0] EXE_signals_IN, + output reg [15:0] valueA, valueB , imm, PC, + output reg [2:0] Rd, + output reg [10:0] EXE_signals +); + + + always @ (posedge clk) begin + + if (stall) begin + EXE_signals <= 0; + end + else begin + valueA <= valueAIN; + valueB <= valueBIN; + imm <= immIN; + PC <= PCIN; + Rd <= RdIN; + EXE_signals = EXE_signals_IN; + end + + end + + +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/IF_2_ID.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/IF_2_ID.v new file mode 100644 index 0000000000000000000000000000000000000000..bd8441cb910211d93ffa48687b06a14396857cff --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/IF_2_ID.v @@ -0,0 +1,16 @@ +module IF2ID( + input clk,stall, + input [15:0] PCIN, instructionIN, + output reg [15:0] PC, instruction +); + + + always @ (posedge clk) begin + + if (~stall) begin + instruction <= instructionIN; + PC <= PCIN; + end + + end +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/MEM_2_WB.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/MEM_2_WB.v new file mode 100644 index 0000000000000000000000000000000000000000..535bf661153de0f079da9d2fa366a9265e5b0b01 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register/MEM_2_WB.v @@ -0,0 +1,21 @@ +module MEM2WB ( + input clk, + input [15:0] DataWB_IN, + input [2:0] Rd_IN, + input WB_signal_IN, + output reg [15:0] DataWB, + output reg [2:0] Rd, + output reg WB_signal +); + + + always @ (posedge clk) begin + + + DataWB <= DataWB_IN; + Rd <= Rd_IN; + WB_signal = WB_signal_IN; + + end + +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register_file/RegisterFile.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register_file/RegisterFile.v new file mode 100644 index 0000000000000000000000000000000000000000..7f63802aeca395709dca72dfa5caba5f15b0d40f --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/register_file/RegisterFile.v @@ -0,0 +1,123 @@ +module RegisterFile( + input clk, + input wire [2:0] RA, RB, RW, + input wire enableWrite, + input wire [15:0] BusW , + output reg [15:0] BusA, BusB +); + + + reg [15:0] registersArray [0:7]; + + + // read registers always + + + always @(negedge clk) begin + if (enableWrite && (RW != 3'b000)) begin + registersArray[RW] = BusW; + end + end + + + assign BusA = registersArray[RA]; + assign BusB = registersArray[RB]; + assign R7 = registersArray[7]; + + + initial begin + registersArray[0] <= 16'h0000; + registersArray[1] <= 16'h0001; + registersArray[2] <= 16'h0003; + registersArray[3] <= 16'h0000; + registersArray[4] <= 16'h0000; + registersArray[5] <= 16'h0002; + registersArray[6] <= 16'h0007; + registersArray[7] <= 16'h0002; + end + + initial begin + $monitor("%0t ==> R0=%b , R1=%b , R2=%b , R3=%b ",$time,registersArray[0],registersArray[1],registersArray[2],registersArray[3]); + $monitor("%0t ==> R4=%b , R5=%b , R6=%b , R7=%b ",$time,registersArray[4],registersArray[5],registersArray[6],registersArray[7]); + end + +endmodule + +module RegisterFile_TB; + + // Inputs + reg clk; + reg [2:0] RA; + reg [2:0] RB; + reg [2:0] RW; + reg enableWrite; + reg [15:0] BusW; + + // Outputs + wire [15:0] BusA; + wire [15:0] BusB; + + // Instantiate the Unit Under Test (UUT) + RegisterFile uut ( + .clk(clk), + .RA(RA), + .RB(RB), + .RW(RW), + .enableWrite(enableWrite), + .BusW(BusW), + .BusA(BusA), + .BusB(BusB) + ); + + // Clock generation + initial begin + clk = 0; + forever #5 clk = ~clk; // 10 ns period + end + + initial begin + // Initialize Inputs + RA = 0; + RB = 0; + RW = 0; + enableWrite = 0; + BusW = 0; + + // Wait for global reset to finish + #10; + + // Test sequence + + // Read initial values + RA = 3'b000; RB = 3'b001; #10; // Read R0 and R1 + RA = 3'b010; RB = 3'b011; #10; // Read R2 and R3 + RA = 3'b100; RB = 3'b101; #10; // Read R4 and R5 + RA = 3'b110; RB = 3'b111; #10; // Read R6 and R7 + + // Write to registers + enableWrite = 1; + RW = 3'b001; BusW = 16'hAAAA; #10; // Write 0xAAAA to R1 + RW = 3'b010; BusW = 16'hBBBB; #10; // Write 0xBBBB to R2 + RW = 3'b011; BusW = 16'hCCCC; #10; // Write 0xCCCC to R3 + RW = 3'b100; BusW = 16'hDDDD; #10; // Write 0xDDDD to R4 + RW = 3'b111; BusW = 16'hEEEE; #10; // Write 0xEEEE to R7 + + // Disable writing + enableWrite = 0; + + // Read back written values + RA = 3'b001; RB = 3'b010; #10; // Read R1 and R2 + RA = 3'b011; RB = 3'b100; #10; // Read R3 and R4 + RA = 3'b000; RB = 3'b111; #10; // Read R0 and R7 + + // End of simulation + $finish; + end + + // Display register file contents for debugging + initial begin + $monitor("At time %t, RA = %b, BusA = %h, RB = %b, BusB = %h", $time, RA, BusA, RB, BusB); + end + +endmodule + diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/EXEStage.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/EXEStage.v new file mode 100644 index 0000000000000000000000000000000000000000..3cee75a58cd10b95e395418228bdb146b0cd381d --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/EXEStage.v @@ -0,0 +1,107 @@ +module EXEStage ( + input wire clk, + input wire [15:0] immediate_EXE, + input wire [15:0] valueA_EXE, + input wire [15:0] valueB_EXE, + input wire [2:0] signals, // AluSRC ALUOP{2} + output reg [15:0] AluResult_EXE +); + + // Internal wires + wire signed [15:0] ALU_in_B,ALU_output; + + // ALU input selection based on ALUsrc + assign ALU_in_B = signals[2] ? immediate_EXE : valueB_EXE; + + + // ALU instance + ALU alu ( + .A(valueA_EXE), + .B(ALU_in_B), + .Output(AluResult_EXE), + .ALUop(signals[1:0]) + ); + +endmodule + + + + +module EXEStage_TB; + + // Inputs + reg clk; + reg [15:0] immediate_EXE; + reg [15:0] valueA_EXE; + reg [15:0] valueB_EXE; + reg [2:0] signals; + + // Outputs + wire [15:0] AluResult_EXE; + + // Instantiate the EXEStage + EXEStage uut ( + .clk(clk), + .immediate_EXE(immediate_EXE), + .valueA_EXE(valueA_EXE), + .valueB_EXE(valueB_EXE), + .signals(signals), + .AluResult_EXE(AluResult_EXE) + ); + + // Clock generation + initial begin + clk = 0; + forever #5 clk = ~clk; // 10ns period + end + + // Test sequence + initial begin + // Initialize inputs + immediate_EXE = 16'd0; + valueA_EXE = -16'sd10; + valueB_EXE = 16'd0; + signals = 3'b000; + + // Wait for global reset + #10; + + // Test 1: AND operation with ALUsrc = 0 (use B) + immediate_EXE = 16'd5; + valueA_EXE = 16'd15; + valueB_EXE = -16'sd10; + signals = 3'b000; // ALUop = 00 (AND), ALUsrc = 0 + #10; + + // Test 2: ADD operation with ALUsrc = 0 (use B) + signals = 3'b001; // ALUop = 01 (ADD), ALUsrc = 0 + #10; + + // Test 3: SUB operation with ALUsrc = 0 (use B) + signals = 3'b010; // ALUop = 10 (SUB), ALUsrc = 0 + #10; + + // Test 4: AND operation with ALUsrc = 1 (use Immediate1) + signals = 3'b100; // ALUop = 00 (AND), ALUsrc = 1 + #10; + + // Test 5: ADD operation with ALUsrc = 1 (use Immediate1) + signals = 3'b101; // ALUop = 01 (ADD), ALUsrc = 1 + #10; + + // Test 6: SUB operation with ALUsrc = 1 (use Immediate1) + signals = 3'b110; // ALUop = 10 (SUB), ALUsrc = 1 + #10; + + // Finish simulation + $stop; + end + + // Monitor values + initial begin + $monitor("%0t, valueA_EXE = %d, valueB_EXE = %d, immediate_EXE = %d, signals = %b, AluResult_EXE = %d", + $time, valueA_EXE, valueB_EXE, immediate_EXE, signals, AluResult_EXE); + end + +endmodule + diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/IDStage.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/IDStage.v new file mode 100644 index 0000000000000000000000000000000000000000..8540b97c59cdeb8747061c4ad9e948c9b25f2de9 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/IDStage.v @@ -0,0 +1,207 @@ +module IDStage ( + input clk, + input [1:0] ForwardA, + input [1:0] ForwardB, + input WB_signals, + input [5:0] signals, // SRC1{2} SRC2 RegDst ExtOp ExtPlace + input [15:0] inst_ID, + input [15:0] PC_ID, + input [15:0] AluResult_EXE,DataWB_MEM,DataWB_WB, + input [2:0] DestinationRegister, + output reg [15:0] I_TypeImmediate, + output reg [15:0] J_TypeImmediate, + output reg [15:0] ReturnAddress, + output reg [15:0] immediate_ID, + output reg [15:0] valueA_ID, + output reg [15:0] valueB_ID, + output reg [2:0] Rd_ID,Ra_ID,Rb_ID, + output reg gt, + output reg lt, + output reg eq, +); + + + // Internal wires for extended immediate values + wire [15:0] extended_imm; + wire [15:0] BusA, BusB; + + + assign Ra_ID = (signals[5:4]==2'b00) ? inst_ID[8:6] : + (signals[5:4]==2'b01) ? 3'b000 : + (signals[5:4]==2'b10) ? 3'b111 :3'bxxx ; + + assign Rb_ID = signals[3] ? inst_ID[5:3] : inst_ID[11:9]; + assign Rd_ID = signals[2] ? 3'b111 : inst_ID[11:9]; + + // Instance of the extender module for immediate values + Extender imm_extender ( + .in(inst_ID[7:0]), + .ExtOp(signals[1]), + .ExtPlace(signals[0]), + .out(extended_imm) + ); + + + // Register file instance + RegisterFile reg_file ( + .clk(clk), + .RA(Ra_ID), + .RB(Rb_ID), + .RW(DestinationRegister), + .enableWrite(WB_signals), + .BusW(DataWB_WB), + .BusA(BusA), + .BusB(BusB) + ); + + + assign I_TypeImmediate = extended_imm+PC_ID; + assign J_TypeImmediate = {PC_ID[15:12],inst_ID[11:0]}; + assign ReturnAddress = valueA_ID; + assign immediate_ID = extended_imm; + + mux_4 #(.LENGTH(16)) mux_ForwardA ( + .in1(BusA), + .in2(AluResult_EXE), + .in3(DataWB_MEM), + .in4(DataWB_WB), + .sel(ForwardA), + .out(valueA_ID) + ); + + + mux_4 #(.LENGTH(16)) mux_ForwardB ( + .in1(BusB), + .in2(AluResult_EXE), + .in3(DataWB_MEM), + .in4(DataWB_WB), + .sel(ForwardB), + .out(valueB_ID) + ); + + // Instance of the Compare module + Compare comp ( + .A(valueA_ID), + .B(valueB_ID), + .gt(gt), + .lt(lt), + .eq(eq) + ); + + + initial begin + + $monitor("%0t ==> I_TypeImmediate from decode= %b",$time,I_TypeImmediate); + $monitor("%0t ==> J_TypeImmediate from decode= %b",$time,J_TypeImmediate); + $monitor("%0t ==> PC_ID = %b",$time,PC_ID); + $monitor("%0t ==> extended_imm= %b",$time,extended_imm); + end + + +endmodule + + + +module IDStage_TB; + + // Inputs + reg clk; + reg [1:0] ForwardA; + reg [1:0] ForwardB; + reg WB_signals; + reg [5:0] signals; + reg [15:0] inst_ID; + reg [15:0] PC_ID; + reg [15:0] AluResult_EXE; + reg [15:0] DataWB_MEM; + reg [15:0] DataWB_WB; + reg [2:0] DestinationRegister; + + // Outputs + wire [15:0] I_TypeImmediate; + wire [15:0] J_TypeImmediate; + wire [15:0] ReturnAddress; + wire [15:0] immediate_ID; + wire [15:0] valueA_ID; + wire [15:0] valueB_ID; + wire [2:0] Rd_ID; + wire [2:0] Ra_ID; + wire [2:0] Rb_ID; + wire gt; + wire lt; + wire eq; + + // Instantiate the Unit Under Test (UUT) + IDStage uut ( + .clk(clk), + .ForwardA(ForwardA), + .ForwardB(ForwardB), + .WB_signals(WB_signals), + .signals(signals), + .inst_ID(inst_ID), + .PC_ID(PC_ID), + .AluResult_EXE(AluResult_EXE), + .DataWB_MEM(DataWB_MEM), + .DataWB_WB(DataWB_WB), + .DestinationRegister(DestinationRegister), + .I_TypeImmediate(I_TypeImmediate), + .J_TypeImmediate(J_TypeImmediate), + .ReturnAddress(ReturnAddress), + .immediate_ID(immediate_ID), + .valueA_ID(valueA_ID), + .valueB_ID(valueB_ID), + .Rd_ID(Rd_ID), + .Ra_ID(Ra_ID), + .Rb_ID(Rb_ID), + .gt(gt), + .lt(lt), + .eq(eq) + ); + + // Clock generation + always #10 clk = ~clk; + + initial begin + + // Initialize Inputs + clk = 0; + #10 + ForwardA = 0; + ForwardB = 0; + WB_signals = 0; + signals = 6'b0010xx; + inst_ID = 'h09B8; + PC_ID = 'd0 ; + AluResult_EXE = 16'b0000000000000000; + DataWB_MEM = 16'b0000000000000000; + DataWB_WB = 16'b0000000000000000; + DestinationRegister = 3'b000; + + // Apply test vectors + // Test case 1: Simple immediate addition + #20; + inst_ID = 'hD010; // Example instruction + PC_ID = 'd2; // Example PC value + signals = 6'bxxx1xx; // Example control signals + ForwardA = 2'b00; + ForwardB = 2'b00; + AluResult_EXE = 16'b0000000000001000; // Example ALU result from EXE stage + DataWB_MEM = 16'b0000000000010000; // Example data from MEM stage + DataWB_WB = 16'b0000000000100000; // Example data from WB stage + DestinationRegister = 3'b001; + + + + + + #100; + $finish; + end + + // Monitor the outputs + initial begin + $monitor("Time: %0t | I_TypeImmediate: %b | J_TypeImmediate: %b | PC_ID: %b | extended_imm: %b | valueA_ID: %b | valueB_ID: %b | gt: %b | lt: %b | eq: %b", + $time, I_TypeImmediate, J_TypeImmediate, PC_ID, uut.extended_imm, valueA_ID, valueB_ID, gt, lt, eq); + end + +endmodule diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/IFStage.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/IFStage.v new file mode 100644 index 0000000000000000000000000000000000000000..9f9802c57e9e24a2331a17047dca81030450f415 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/IFStage.v @@ -0,0 +1,152 @@ +module IFStage ( + input clk, + input stall,kill, + input wire [1:0] PCsrc, + input[15:0] I_TypeImmediate,J_TypeImmediate,ReturnAddress, + output reg [15:0] NPC, inst_IF +); + + reg [15:0] PC; + wire [15:0] instruction_wire; + + InstructionMemory instructions ( + .clk(clk), + .kill(kill), + .stall(stall), + .address(PC), + .instruction(instruction_wire) + ); + + + mux_2 #(.LENGTH(16)) mux_kill ( + .in1(instruction_wire), + .in2({ADD, R1, R1, R0, 3'b000}), + .sel(kill), + .out(inst_IF) + ); + + always @(posedge clk) begin + if (!stall) begin + PC <= PC + 16'd2; + NPC <= PC + 16'd2; + end + end + + + always @(*) begin + #1fs + if (!stall) + case (PCsrc) + 1: begin + PC = J_TypeImmediate; + NPC = J_TypeImmediate; + end + 2: begin + PC = I_TypeImmediate; + NPC = I_TypeImmediate; + end + 3: begin + PC = ReturnAddress; + NPC = ReturnAddress; + end + endcase + end + + + initial begin + PC = 16'd0; + NPC = 16'd0; + $monitor("%0t ==> kill= %b",$time,kill); + $monitor("%0t ==> I_TypeImmediate= %b",$time,I_TypeImmediate); + $monitor("%0t ==> J_TypeImmediate= %b",$time,J_TypeImmediate); + $monitor("%0t ==> NPC= %b",$time,NPC); + $monitor("%0t ==> PC= %b",$time,PC); + end + +endmodule + + +module IFStage_TB; + + // Inputs + reg clk; + reg stall; + reg kill; + reg [1:0] PCsrc; + reg [15:0] I_TypeImmediate; + reg [15:0] J_TypeImmediate; + reg [15:0] ReturnAddress; + + // Outputs + wire [15:0] NPC; + wire [15:0] inst_IF; + + // Instantiate the Unit Under Test (UUT) + IFStage uut ( + .clk(clk), + .stall(stall), + .kill(kill), + .PCsrc(PCsrc), + .I_TypeImmediate(I_TypeImmediate), + .J_TypeImmediate(J_TypeImmediate), + .ReturnAddress(ReturnAddress), + .NPC(NPC), + .inst_IF(inst_IF) + ); + + // Clock generation + initial begin + clk = 0; + forever #10 clk = ~clk; // 10 time units period clock + end + + // Stimulus + initial begin + // Initialize Inputs + stall = 0; + kill = 0; + PCsrc = 0; + I_TypeImmediate = 16'hA; + J_TypeImmediate = 16'h0; + ReturnAddress = 16'h4; + + // Monitor values + $monitor("Time: %0t | clk: %b | stall: %b | kill: %b | PCsrc: %b | I_TypeImmediate: %h | J_TypeImmediate: %h | ReturnAddress: %h | NPC: %h | inst_IF: %h", + $time, clk, stall, kill, PCsrc, I_TypeImmediate, J_TypeImmediate, ReturnAddress, NPC, inst_IF); + + // Test sequence + #10; + // Test : Normal operation, no stall, no kill + #20; + + // Test : Apply stall + stall = 1; + #21; + stall = 0; + // Test : Change PCsrc to I_TypeImmediate + PCsrc = 2; + kill = 1; + #21; + PCsrc = 0; + kill = 0; + #21; + // Test : Change PCsrc to J_TypeImmediate + PCsrc = 1; + kill = 1; + #21; + PCsrc = 0; + kill = 0; + #21 + // Test 6: Change PCsrc to ReturnAddress + PCsrc = 3; + kill =1; + #21; + PCsrc = 0; + kill = 0; + + // Test complete + #50; + $finish; + end + +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/MEMStage.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/MEMStage.v new file mode 100644 index 0000000000000000000000000000000000000000..714ec8be794ed1e6eee4e308abccf6fa9a172593 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/stages/MEMStage.v @@ -0,0 +1,129 @@ +module MEMStage ( + input wire clk, + input wire [15:0] AluResult_MEM, + input wire [15:0] immediate_MEM, + input wire [15:0] valueB_MEM, + input wire [15:0] PC_MEM, + input wire [6:0] signals, // DataInSrc MemRd MemWr NumOfByte{2} WBdata{2} + output reg [15:0] DataWB_MEM +); + + // Internal wires + wire [15:0] data_in,data_out; + + assign data_in = signals[6] ? valueB_MEM : immediate_MEM; + + + // DataMemory instance + DataMemory data_memory ( + .clk(clk), + .wrEnable(signals[4]), + .rdEnable(signals[5]), + .numberOfByte(signals[3:2]), + .address(AluResult_MEM), + .in(data_in), + .out(data_out) + ); + + mux_3 #(.LENGTH(16)) mux_MemoryResult ( + .in1(PC_MEM), + .in2(AluResult_MEM), + .in3(data_out), + .sel(signals[1:0]), + .out(DataWB_MEM) + ); + + +endmodule + + + +module MEMStage_TB; + + // Test bench signals + reg clk; + reg [15:0] AluResult_MEM; + reg [15:0] immediate_MEM; + reg [15:0] valueB_MEM; + reg [15:0] PC_MEM; + reg [6:0] signals; + wire [15:0] DataWB_MEM; + + // Instantiate the MEMStage module + MEMStage mem_stage ( + .clk(clk), + .AluResult_MEM(AluResult_MEM), + .immediate_MEM(immediate_MEM), + .valueB_MEM(valueB_MEM), + .PC_MEM(PC_MEM), + .signals(signals), + .DataWB_MEM(DataWB_MEM) + ); + + // Clock generation + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + // Test cases + initial begin + // Initialize inputs + AluResult_MEM = 16'h0000; + immediate_MEM = 16'h0000; + valueB_MEM = 16'h0000; + PC_MEM = 16'h0000; + signals = 7'b0000000; + + // Test case 1: Write immediate_MEM to memory + #10; + AluResult_MEM = 16'h0002; + immediate_MEM = 16'h1234; + signals = 7'b0011000; // MemWr, NumOfByte = 2 (16-bit write) + + // Test case 2: Read from memory + #10; + AluResult_MEM = 16'h0002; + signals = 7'b0100010; // MemRd, NumOfByte = 0 (16-bit read) + + + // Test case 3: Write valueB_MEM to memory + #10; + AluResult_MEM = 16'h0004; + valueB_MEM = 16'h5678; + signals = 7'b1010000; // DataInSrc = valueB_MEM, MemWr, NumOfByte = 0 (16-bit write) + + // Test case 4: Read 8-bit value from memory with zero extension + #10; + AluResult_MEM = 16'h0004; + signals = 7'b0100110; // MemRd, NumOfByte = 1 (8-bit read, zero extend) + + + // Test case 5: Read 8-bit value from memory with sign extension + #10; + AluResult_MEM = 16'h0005; + signals = 7'b0101010; // MemRd, NumOfByte = 2 (8-bit read, sign extend) + + + // Test case 6: Write immediate_MEM to memory, single byte + #10; + AluResult_MEM = 16'h0006; + immediate_MEM = 16'h00FF; + signals = 7'b0010100; // MemWr, NumOfByte = 0 (8-bit write) + + + + // Stop simulation + #10; + $finish; + end + + // Monitor signals + initial begin + $monitor("Time: %0t,DataWB_MEM: %h", + $time,DataWB_MEM); + end + + +endmodule + diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/Compare.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/Compare.v new file mode 100644 index 0000000000000000000000000000000000000000..0ea5ecebdee32f43dc235716b67ffdce3fdda022 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/Compare.v @@ -0,0 +1,68 @@ +module Compare( + input wire signed [15:0] A, + input wire signed [15:0] B, + output reg gt, + output reg lt, + output reg eq +); + + always @(A, B) begin + // Initialize all outputs to 0 + gt = 0; + lt = 0; + eq = 0; + + // Compare A and B + if (A > B) begin + lt = 1; + end else if (A < B) begin + gt = 1; + end else begin + eq = 1; + end + end + +endmodule + + + +module Compare_TB; + + reg signed [15:0] A, B; + wire gt; + wire lt; + wire eq; + + Compare comp(A, B, gt, lt, eq); + + initial begin + // Unsigned comparisons + #0 + A <= 16'd3; + B <= 16'd2; + + #10 + A <= 16'd30; + B <= 16'd40; + + #10 + A <= 16'd40; + B <= 16'd40; + + // Signed comparisons + #10 + A <= -16'sd10; + B <= 16'sd10; + + #10 + A <= -16'sd20; + B <= -16'sd30; + + #10 + A <= -16'sd40; + B <= -16'sd40; + + #5 $finish; + end + +endmodule diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/Extender.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/Extender.v new file mode 100644 index 0000000000000000000000000000000000000000..48111b7add305d1b7d652fb7213e105277b23b1f --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/Extender.v @@ -0,0 +1,79 @@ +module Extender ( + input [7:0] in, + input ExtOp, + input ExtPlace, + output reg [15:0] out +); + + always @(*) begin + if (ExtPlace == 1) begin + out <= {8'b0, in}; + end else begin + // Extend from 5-bit position + if (ExtOp) begin + // Signed extension + out <= {{11{in[4]}}, in[4:0]}; + end else begin + // Unsigned extension + out <= {11'b0, in[4:0]}; + end + end + end +endmodule + + +module Extender_TB; + + // Testbench signals + reg [7:0] in; + reg ExtOp; + reg ExtPlace; + wire [15:0] out; + + // Instantiate the Extender module + Extender uut ( + .in(in), + .ExtOp(ExtOp), + .ExtPlace(ExtPlace), + .out(out) + ); + + initial begin + // Display the output + $monitor("in=%b, ExtOp=%b, ExtPlace=%b -> out=%b", in, ExtOp, ExtPlace, out); + + // Test cases + // Test signed extension from MSB + in = 8'b10000000; ExtOp = 0; ExtPlace = 1; + #10; + + // Test unsigned extension from MSB + in = 8'b10000000; ExtOp = 1; ExtPlace = 1; + #10; + + // Test signed extension from 5-bit position + in = 8'b00011100; ExtOp = 0; ExtPlace = 0; + #10; + + // Test unsigned extension from 5-bit position + in = 8'b00011100; ExtOp = 1; ExtPlace = 0; + #10; + + // Add more test cases as needed + in = 8'b01111111; ExtOp = 0; ExtPlace = 1; + #10; + + in = 8'b01111111; ExtOp = 1; ExtPlace = 1; + #10; + + in = 8'b00011111; ExtOp = 0; ExtPlace = 0; + #10; + + in = 8'b00011111; ExtOp = 1; ExtPlace = 0; + #10; + + // Finish the simulation + $finish; + end + +endmodule diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/mux.v b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/mux.v new file mode 100644 index 0000000000000000000000000000000000000000..b9940d39a1218e5d6e154f8b8ef621bf75dd984a --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/utilities/mux.v @@ -0,0 +1,30 @@ +module mux_4 #(parameter integer LENGTH) (in1, in2, in3, in4, sel, out); + input [LENGTH-1:0] in1, in2, in3, in4; + input [1:0] sel; + output [LENGTH-1:0] out; + + assign out = (sel == 2'd0) ? in1 : + (sel == 2'd1) ? in2 : + (sel == 2'd2) ? in3 : in4; +endmodule + + +module mux_3 #(parameter integer LENGTH) (in1, in2, in3, sel, out); + input [LENGTH-1:0] in1, in2, in3; + input [1:0] sel; + output [LENGTH-1:0] out; + + assign out = (sel == 2'd0) ? in1 : + (sel == 2'd1) ? in2 : + (sel == 2'd2) ? in3 : 0; +endmodule + + +module mux_2 #(parameter integer LENGTH) (in1, in2, sel, out); + input [LENGTH-1:0] in1, in2; + input sel; + output [LENGTH-1:0] out; + + assign out = (sel == 0) ? in1 : in2; + +endmodule \ No newline at end of file diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/wave.asdb b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/wave.asdb new file mode 100644 index 0000000000000000000000000000000000000000..d49239b379e45843fd9642058a3426d049cf6bad Binary files /dev/null and b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/src/wave.asdb differ diff --git a/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/synthesis.order b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/synthesis.order new file mode 100644 index 0000000000000000000000000000000000000000..cafbb85f500d303b0f91f5229f706d45550535a8 --- /dev/null +++ b/qossayrida_PipelineProcessorDesign/source/PipelineProcessor/synthesis.order @@ -0,0 +1,22 @@ +i<>.\src\PipelineProcessor.v +i<>.\src\ClockGenerator.v +i<>.\src\parameter.v +i<>.\src\DataMemory.v +i<>.\src\InstructionMemory.v +i<>.\src\RegisterFile.v +i<>.\src\ControlUnit.v +i<>.\src\ALU.v +i<>.\src\DataMemoryTestbench.v +i<>.\src\IFStage.v +i<>.\src\mux.v +i<>.\src\PC.v +i<>.\src\DCStage.v +i<>.\src\Compare.v +i<>.\src\Extender.v +i<>.\src\EXEStage.v +i<>.\src\MEMStage.v +i<>.\src\WBStage.v +i<>.\src\IF_2_ID.v +i<>.\src\ID_2_EXE.v +i<>.\src\EXE_2_MEM.v +i<>.\src\MEM_2_WB.v