diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..b6f2abe3e4e06cc73f4ebc567fb84d9bf0a9be17 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..5141f9132c06a348cf4c83638c4d789aaa9cb4a5 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/Doubly_Linked_List/src/doubly_linked_list.sv ++++ b/Doubly_Linked_List/src/doubly_linked_list.sv +@@ -294,7 +294,7 @@ + end + end + FIND_VALUE: begin +- if(data_rd_buf == data_in) begin ++ if(data_rd_buf != data_in) begin + // update curr pos to invalid + wr_req <= 1'b1; + target_idx <= cur_ptr; diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..78e5ff9dea510607310d4fe449ea4e1396a1bd1f --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "Doubly_Linked_List/src/doubly_linked_list.sv" + ], + "bug_description": "Inverted 'data_rd_buf == data_in' condition in FIND_VALUE state \u2014 delete-by-value now deletes the first node that does NOT match the target value instead of the matching one", + "signals_affected": [ + "data_rd_buf", + "data_in" + ], + "simulation_status": "sim_ok", + "problem_statement": "The delete-by-value operation is not functioning correctly. When attempting to remove a specific node from the list by matching its data field, the operation fails to complete (op_done remains low at t=132000). Additionally, the list state becomes corrupted immediately after a delete-by-value attempt: the empty flag incorrectly asserts to 1, while head and tail both point to address 1000, and length shows 0000, indicating the list thinks it's empty when it shouldn't be. On subsequent operations, the wrong node is deleted from the list\u2014inspection of the waveform shows data_out reads the wrong value (00000000 at t=828000) and pre_node_addr/next_node_addr point to incorrect addresses (1000 at t=828000 and t=876000 respectively). This suggests the comparison logic for matching the target data value is inverted, causing nodes that do NOT match to be selected for deletion instead of the correct matching node. The list structure remains corrupted throughout, with the full flag never asserting as expected and the fault flag remaining inactive even as the list becomes logically invalid.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..bad54b6fcf215d33c047fc073d11a815fc0a1391 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,123 @@ +FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +541000 Addr 0 found at Index 3 +541000 Addr 1 found at Index 2 +541000 Addr 2 found at Index 4 +541000 Addr 3 found at Index 1 +541000 Addr 4 found at Index 0 +541000 Next Addr = 5 +541000 Data Written to Index 1 : 3 +541000 linked_list_exp = 7 3 6 0 3 5 +541000 linked_list_addr = 4 5 3 1 0 2 +541000 OP_Insert_At_Index 2 index, 4 value +685000 Addr 0 found at Index 4 +685000 Addr 1 found at Index 3 +685000 Addr 2 found at Index 5 +685000 Addr 3 found at Index 2 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Next Addr = 6 +685000 Data Written to Index 2 : 4 +685000 linked_list_exp = 7 3 4 6 0 3 5 +685000 linked_list_addr = 4 5 6 3 1 0 2 +685000 OP_Insert_At_Index 8 index, 3 value +733000 Addr 0 found at Index 5 +733000 Addr 1 found at Index 4 +733000 Addr 2 found at Index 6 +733000 Addr 3 found at Index 3 +733000 Addr 4 found at Index 0 +733000 Addr 5 found at Index 1 +733000 Addr 6 found at Index 2 +733000 Next Addr = 7 +733000 Data Written to Back : 3 +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 4 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Read from back 8 times +829000 Data read: 3 +877000 Data read: 5 +925000 Data read: 3 +973000 Data read: 0 +1021000 Data read: 6 +1069000 Data read: 4 +1117000 Data read: 3 +1165000 Data read: 7 +1165000 linked_list_exp = 7 3 4 6 0 3 5 3 +1165000 linked_list_addr = 4 5 6 3 1 0 2 7 +1165000 OP_Insert_At_Index 8 index, 1 value +1213000 Fault flag is asserted correctly +1213000 Queue is full and full flag is asserted correctly +1213000 linked_list_exp = 7 3 4 6 0 3 5 3 +1213000 linked_list_addr = 4 5 6 3 1 0 2 7 +1213000 OP_Insert_At_Index 0 index, 3 value +1261000 Fault flag is asserted correctly +1261000 Queue is full and full flag is asserted correctly +1261000 linked_list_exp = 7 3 4 6 0 3 5 3 +1261000 linked_list_addr = 4 5 6 3 1 0 2 7 +1461000 OP_Read from front 8 times +1501000 Data read: 7 +1549000 Data read: 3 +1597000 Data read: 4 +1645000 Data read: 6 +1693000 Data read: 0 +1741000 Data read: 3 +1789000 Data read: 5 +1837000 Data read: 3 +1837000 linked_list_exp = 7 3 4 6 0 3 5 3 +1837000 linked_list_addr = 4 5 6 3 1 0 2 7 +2337000 OP_Delete_Value 7 value +2413000 Data 7 at Index 0 is Deleted_by_Value +2413000 linked_list_exp = 3 4 6 0 3 5 3 +2413000 linked_list_addr = 5 6 3 1 0 2 7 +2413000 OP_Delete_At_Index 0 index +2485000 Data 3 at Front is Deleted +2485000 linked_list_exp = 4 6 0 3 5 3 +2485000 linked_list_addr = 6 +--- STDERR --- +/tmp/sim4_simsh_fkh0egxi/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_fkh0egxi/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_fkh0egxi/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..8c06990cf4875adf5176473549b3f4b91e0ae91e Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..753e6142e87f4b53aad7cb402f7bfb087d2a1fd7 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/diff.patch @@ -0,0 +1,11 @@ +--- a/Doubly_Linked_List/src/doubly_linked_list.sv ++++ b/Doubly_Linked_List/src/doubly_linked_list.sv +@@ -371,7 +371,7 @@ + data_out <= {DATA_WIDTH{1'b0}}; + next_node_addr <= ADDR_NULL; + pre_node_addr <= ADDR_NULL; +- end else if (op_is_read & (next_state == EXECUTE)) begin ++ end else begin + data_out <= node_data[target_idx]; + next_node_addr <= (addr_in == tail) ? ADDR_NULL : node_next_node_addr[target_idx]; + pre_node_addr <= (addr_in == head) ? ADDR_NULL : node_pre_node_addr[target_idx]; diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..328aba43b4e9b799fbca56cd2a8818de8da404df --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/metadata.json @@ -0,0 +1,18 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "Doubly_Linked_List/src/doubly_linked_list.sv" + ], + "bug_description": "Removed 'op_is_read & (next_state == EXECUTE)' enable condition from the data_out sequential block \u2014 data_out, next_node_addr, and pre_node_addr now update on every clock edge instead of only during a read operation reaching the EXECUTE state", + "signals_affected": [ + "data_out", + "next_node_addr", + "pre_node_addr" + ], + "simulation_status": "sim_ok", + "problem_statement": "During verification of the read operation, we observed that output registers are becoming corrupted with unexpected values at t=108000. The signals `data_out`, `next_node_addr`, and `pre_node_addr` all display unknown/garbage values when they should be maintaining the previously transferred data. This corruption occurs during normal operation when no read transaction should be occurring, suggesting these registers are being unintentionally modified outside their intended update windows. The issue prevents correct data retrieval and appears to affect all three related output signals simultaneously, indicating a shared control issue rather than isolated signal corruption.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..b80508f3905256fdc3af73990e6925aed0d0549c --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_enable/sim_log.txt @@ -0,0 +1,123 @@ +FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +541000 Addr 0 found at Index 3 +541000 Addr 1 found at Index 2 +541000 Addr 2 found at Index 4 +541000 Addr 3 found at Index 1 +541000 Addr 4 found at Index 0 +541000 Next Addr = 5 +541000 Data Written to Index 1 : 3 +541000 linked_list_exp = 7 3 6 0 3 5 +541000 linked_list_addr = 4 5 3 1 0 2 +541000 OP_Insert_At_Index 2 index, 4 value +685000 Addr 0 found at Index 4 +685000 Addr 1 found at Index 3 +685000 Addr 2 found at Index 5 +685000 Addr 3 found at Index 2 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Next Addr = 6 +685000 Data Written to Index 2 : 4 +685000 linked_list_exp = 7 3 4 6 0 3 5 +685000 linked_list_addr = 4 5 6 3 1 0 2 +685000 OP_Insert_At_Index 8 index, 3 value +733000 Addr 0 found at Index 5 +733000 Addr 1 found at Index 4 +733000 Addr 2 found at Index 6 +733000 Addr 3 found at Index 3 +733000 Addr 4 found at Index 0 +733000 Addr 5 found at Index 1 +733000 Addr 6 found at Index 2 +733000 Next Addr = 7 +733000 Data Written to Back : 3 +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 4 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Read from back 8 times +829000 Data read: 3 +877000 Data read: 5 +925000 Data read: 3 +973000 Data read: 0 +1021000 Data read: 6 +1069000 Data read: 4 +1117000 Data read: 3 +1165000 Data read: 7 +1165000 linked_list_exp = 7 3 4 6 0 3 5 3 +1165000 linked_list_addr = 4 5 6 3 1 0 2 7 +1165000 OP_Insert_At_Index 8 index, 1 value +1213000 Fault flag is asserted correctly +1213000 Queue is full and full flag is asserted correctly +1213000 linked_list_exp = 7 3 4 6 0 3 5 3 +1213000 linked_list_addr = 4 5 6 3 1 0 2 7 +1213000 OP_Insert_At_Index 0 index, 3 value +1261000 Fault flag is asserted correctly +1261000 Queue is full and full flag is asserted correctly +1261000 linked_list_exp = 7 3 4 6 0 3 5 3 +1261000 linked_list_addr = 4 5 6 3 1 0 2 7 +1461000 OP_Read from front 8 times +1501000 Data read: 7 +1549000 Data read: 3 +1597000 Data read: 4 +1645000 Data read: 6 +1693000 Data read: 0 +1741000 Data read: 3 +1789000 Data read: 5 +1837000 Data read: 3 +1837000 linked_list_exp = 7 3 4 6 0 3 5 3 +1837000 linked_list_addr = 4 5 6 3 1 0 2 7 +2337000 OP_Delete_Value 7 value +2389000 Data 7 at Index 0 is Deleted_by_Value +2389000 linked_list_exp = 3 4 6 0 3 5 3 +2389000 linked_list_addr = 5 6 3 1 0 2 7 +2389000 OP_Delete_At_Index 0 index +2461000 Data 3 at Front is Deleted +2461000 linked_list_exp = 4 6 0 3 5 3 +2461000 linked_list_addr = 6 +--- STDERR --- +/tmp/sim4_simsh_kilm2m7j/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_kilm2m7j/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_kilm2m7j/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..67351e7e0d3a925a183aa90a50a6e9e22019ca2b Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..3026367618bf400fcc5d4b1faf7343243b8a02b8 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/diff.patch @@ -0,0 +1,16 @@ +--- a/Doubly_Linked_List/src/doubly_linked_list.sv ++++ b/Doubly_Linked_List/src/doubly_linked_list.sv +@@ -365,10 +365,11 @@ + pre_addr_rd_buf <= node_pre_node_addr[target_idx]; + end + end +- ++ ++ initial data_out = {DATA_WIDTH{1'bx}}; ++ + always @ (posedge clk, posedge rst) begin + if (rst) begin +- data_out <= {DATA_WIDTH{1'b0}}; + next_node_addr <= ADDR_NULL; + pre_node_addr <= ADDR_NULL; + end else if (op_is_read & (next_state == EXECUTE)) begin diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..0a8d7ada59a18688434b06a99dcc769f163543d3 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "Doubly_Linked_List/src/doubly_linked_list.sv" + ], + "bug_description": "Removed synchronous reset for 'data_out' register; kept resets for next_node_addr and pre_node_addr intact. Added initial block setting data_out to unknown (x) so the missing reset is observable in simulation.", + "signals_affected": [ + "data_out" + ], + "simulation_status": "sim_ok", + "problem_statement": "Signal `data_out` fails to initialize to a known state at t=0, remaining undefined (xxxxxxxx) throughout the initial reset phase. While other module registers reset as expected, `data_out` appears to lack proper reset handling. This inconsistency could cause unpredictable behavior when the module transitions from reset, as downstream logic may encounter an unknown initial value instead of the expected cleared state.", + "diff_summary": "7 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..5ef4ab0801267d8f0f571cdda40ec3cf0adc54ae --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/missing_reset/sim_log.txt @@ -0,0 +1,123 @@ +FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +541000 Addr 0 found at Index 3 +541000 Addr 1 found at Index 2 +541000 Addr 2 found at Index 4 +541000 Addr 3 found at Index 1 +541000 Addr 4 found at Index 0 +541000 Next Addr = 5 +541000 Data Written to Index 1 : 3 +541000 linked_list_exp = 7 3 6 0 3 5 +541000 linked_list_addr = 4 5 3 1 0 2 +541000 OP_Insert_At_Index 2 index, 4 value +685000 Addr 0 found at Index 4 +685000 Addr 1 found at Index 3 +685000 Addr 2 found at Index 5 +685000 Addr 3 found at Index 2 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Next Addr = 6 +685000 Data Written to Index 2 : 4 +685000 linked_list_exp = 7 3 4 6 0 3 5 +685000 linked_list_addr = 4 5 6 3 1 0 2 +685000 OP_Insert_At_Index 8 index, 3 value +733000 Addr 0 found at Index 5 +733000 Addr 1 found at Index 4 +733000 Addr 2 found at Index 6 +733000 Addr 3 found at Index 3 +733000 Addr 4 found at Index 0 +733000 Addr 5 found at Index 1 +733000 Addr 6 found at Index 2 +733000 Next Addr = 7 +733000 Data Written to Back : 3 +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 4 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Read from back 8 times +829000 Data read: 3 +877000 Data read: 5 +925000 Data read: 3 +973000 Data read: 0 +1021000 Data read: 6 +1069000 Data read: 4 +1117000 Data read: 3 +1165000 Data read: 7 +1165000 linked_list_exp = 7 3 4 6 0 3 5 3 +1165000 linked_list_addr = 4 5 6 3 1 0 2 7 +1165000 OP_Insert_At_Index 8 index, 1 value +1213000 Fault flag is asserted correctly +1213000 Queue is full and full flag is asserted correctly +1213000 linked_list_exp = 7 3 4 6 0 3 5 3 +1213000 linked_list_addr = 4 5 6 3 1 0 2 7 +1213000 OP_Insert_At_Index 0 index, 3 value +1261000 Fault flag is asserted correctly +1261000 Queue is full and full flag is asserted correctly +1261000 linked_list_exp = 7 3 4 6 0 3 5 3 +1261000 linked_list_addr = 4 5 6 3 1 0 2 7 +1461000 OP_Read from front 8 times +1501000 Data read: 7 +1549000 Data read: 3 +1597000 Data read: 4 +1645000 Data read: 6 +1693000 Data read: 0 +1741000 Data read: 3 +1789000 Data read: 5 +1837000 Data read: 3 +1837000 linked_list_exp = 7 3 4 6 0 3 5 3 +1837000 linked_list_addr = 4 5 6 3 1 0 2 7 +2337000 OP_Delete_Value 7 value +2389000 Data 7 at Index 0 is Deleted_by_Value +2389000 linked_list_exp = 3 4 6 0 3 5 3 +2389000 linked_list_addr = 5 6 3 1 0 2 7 +2389000 OP_Delete_At_Index 0 index +2461000 Data 3 at Front is Deleted +2461000 linked_list_exp = 4 6 0 3 5 3 +2461000 linked_list_addr = 6 +--- STDERR --- +/tmp/sim4_simsh_8rbaetq3/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_8rbaetq3/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_8rbaetq3/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..381feb2794d643cc5738b25adeae44afcf5a9d50 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/diff.patch b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..cd28e8ac2b4e3e134539dcd073f8562aec0456bc --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/diff.patch @@ -0,0 +1,11 @@ +--- a/Doubly_Linked_List/src/doubly_linked_list.sv ++++ b/Doubly_Linked_List/src/doubly_linked_list.sv +@@ -240,7 +240,7 @@ + // update pre_node_addr of next post to pre pos + pre_node_addr_idx <= next_addr_rd_buf; + pre_node_addr_in <= pre_addr_rd_buf; +- next_state <= EXECUTE; ++ next_state <= FAULT; + end else if (op_is_insert_at_addr) begin + // insert new pos + wr_req <= 1'b1; diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/metadata.json b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..9fd579cadcea1b21305bcbdbd9df99c40b814194 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/metadata.json @@ -0,0 +1,18 @@ +{ + "bug_type": "state_transition", + "task_type": "behavioral_bug", + "files_modified": [ + "Doubly_Linked_List/src/doubly_linked_list.sv" + ], + "bug_description": "Changed FIND_ADDR\u2192EXECUTE transition to FIND_ADDR\u2192FAULT for op_is_delete_by_addr \u2014 when a valid node is found by address, the FSM incorrectly transitions to FAULT instead of EXECUTE, causing delete_by_addr to always report fault and leaving length/head/tail unmodified", + "signals_affected": [ + "state", + "fault", + "op_done" + ], + "simulation_status": "sim_ok", + "problem_statement": "When executing a delete_by_addr operation to remove a linked-list node at a specific address, the operation fails to complete successfully even when the target node is found. The op_done signal remains low throughout the operation, and the list metadata (length, head, tail) remain unchanged at t=132000, indicating the deletion was never applied. The operation eventually enters a fault state (fault asserts at t=780000), incorrectly flagging this as a fault condition despite the node being successfully located and traversed (as evidenced by pre_node_addr and next_node_addr updates). This prevents delete_by_addr from functioning when a valid address is provided, completely breaking the address-based deletion feature of the linked-list controller.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/sim_log.txt b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..f0be9c9670696a4217914708121d4bdb8363d0b4 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/state_transition/sim_log.txt @@ -0,0 +1,123 @@ +FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +541000 Addr 0 found at Index 3 +541000 Addr 1 found at Index 2 +541000 Addr 2 found at Index 4 +541000 Addr 3 found at Index 1 +541000 Addr 4 found at Index 0 +541000 Next Addr = 5 +541000 Data Written to Index 1 : 3 +541000 linked_list_exp = 7 3 6 0 3 5 +541000 linked_list_addr = 4 5 3 1 0 2 +541000 OP_Insert_At_Index 2 index, 4 value +685000 Addr 0 found at Index 4 +685000 Addr 1 found at Index 3 +685000 Addr 2 found at Index 5 +685000 Addr 3 found at Index 2 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Next Addr = 6 +685000 Data Written to Index 2 : 4 +685000 linked_list_exp = 7 3 4 6 0 3 5 +685000 linked_list_addr = 4 5 6 3 1 0 2 +685000 OP_Insert_At_Index 8 index, 3 value +733000 Addr 0 found at Index 5 +733000 Addr 1 found at Index 4 +733000 Addr 2 found at Index 6 +733000 Addr 3 found at Index 3 +733000 Addr 4 found at Index 0 +733000 Addr 5 found at Index 1 +733000 Addr 6 found at Index 2 +733000 Next Addr = 7 +733000 Data Written to Back : 3 +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 4 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Read from back 8 times +829000 Data read: 3 +877000 Data read: 5 +925000 Data read: 3 +973000 Data read: 0 +1021000 Data read: 6 +1069000 Data read: 4 +1117000 Data read: 3 +1165000 Data read: 7 +1165000 linked_list_exp = 7 3 4 6 0 3 5 3 +1165000 linked_list_addr = 4 5 6 3 1 0 2 7 +1165000 OP_Insert_At_Index 8 index, 1 value +1213000 Fault flag is asserted correctly +1213000 Queue is full and full flag is asserted correctly +1213000 linked_list_exp = 7 3 4 6 0 3 5 3 +1213000 linked_list_addr = 4 5 6 3 1 0 2 7 +1213000 OP_Insert_At_Index 0 index, 3 value +1261000 Fault flag is asserted correctly +1261000 Queue is full and full flag is asserted correctly +1261000 linked_list_exp = 7 3 4 6 0 3 5 3 +1261000 linked_list_addr = 4 5 6 3 1 0 2 7 +1461000 OP_Read from front 8 times +1501000 Data read: 7 +1549000 Data read: 3 +1597000 Data read: 4 +1645000 Data read: 6 +1693000 Data read: 0 +1741000 Data read: 3 +1789000 Data read: 5 +1837000 Data read: 3 +1837000 linked_list_exp = 7 3 4 6 0 3 5 3 +1837000 linked_list_addr = 4 5 6 3 1 0 2 7 +2337000 OP_Delete_Value 7 value +2389000 Data 7 at Index 0 is Deleted_by_Value +2389000 linked_list_exp = 3 4 6 0 3 5 3 +2389000 linked_list_addr = 5 6 3 1 0 2 7 +2389000 OP_Delete_At_Index 0 index +2461000 Data 3 at Front is Deleted +2461000 linked_list_exp = 4 6 0 3 5 3 +2461000 linked_list_addr = 6 +--- STDERR --- +/tmp/sim4_simsh_fwygiove/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_fwygiove/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_fwygiove/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..55bea0efe49c54658d15c242ee577d6b7c7788d8 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/diff.patch b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..0aa4ba68c084f5d54e182381938b04196c7eb453 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/diff.patch @@ -0,0 +1,11 @@ +--- a/Doubly_Linked_List/src/doubly_linked_list.sv ++++ b/Doubly_Linked_List/src/doubly_linked_list.sv +@@ -102,7 +102,7 @@ + assign op_is_insert_at_index = op[2:0] == 3'd5 & op_start; + assign op_is_insert_at_addr = op[2:0] == 3'd1 & op_start; + assign op_is_delete_by_value = op[2:0] == 3'd2 & op_start; +- assign op_is_delete_by_index = op[2:0] == 3'd7 & op_start; ++ assign op_is_delete_by_index = op[2:0] == 2'd7 & op_start; + assign op_is_delete_by_addr = op[2:0] == 3'd3 & op_start; + + always @ (posedge clk or posedge rst) begin diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/metadata.json b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..9029affce942f3a7030c1a030ee36031a2730134 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "width_bit_cutoff", + "task_type": "behavioral_bug", + "files_modified": [ + "Doubly_Linked_List/src/doubly_linked_list.sv" + ], + "bug_description": "Changed '3'd7' to '2'd7' in the op_is_delete_by_index assignment \u2014 2'd7 truncates to decimal 3 (7 mod 4 = 3), so Delete_Index (op=7) is never recognized; instead op=3 (which matches op_is_delete_by_addr) is incorrectly double-matched", + "signals_affected": [ + "op_is_delete_by_index" + ], + "simulation_status": "sim_ok", + "problem_statement": "During verification of delete operations on index values, the design fails to properly handle Delete_Index commands. When executing a delete-by-index operation (op=7), the op_done signal fails to assert at t=132000, and multiple state signals (head, tail, length, empty) retain incorrect values instead of updating. Simultaneously, the fault signal incorrectly asserts at t=780000 and remains stuck, while data_out at t=828000 shows all zeros rather than the expected node data. The traversal signals pre_node_addr and next_node_addr also diverge at t=828000 and t=876000 respectively, both stuck at 1000 instead of progressing through the linked list. Additionally, the full flag incorrectly reads 0 at t=732000 when the structure should be full. These symptoms suggest that delete-by-index operations are not being recognized or executed at all, causing the entire operation pipeline to stall and state management to fail.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/sim_log.txt b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..3c48da2a6b272c0c6f8ecfbeffa0950241300366 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/width_bit_cutoff/sim_log.txt @@ -0,0 +1,122 @@ +FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +541000 Addr 0 found at Index 3 +541000 Addr 1 found at Index 2 +541000 Addr 2 found at Index 4 +541000 Addr 3 found at Index 1 +541000 Addr 4 found at Index 0 +541000 Next Addr = 5 +541000 Data Written to Index 1 : 3 +541000 linked_list_exp = 7 3 6 0 3 5 +541000 linked_list_addr = 4 5 3 1 0 2 +541000 OP_Insert_At_Index 2 index, 4 value +685000 Addr 0 found at Index 4 +685000 Addr 1 found at Index 3 +685000 Addr 2 found at Index 5 +685000 Addr 3 found at Index 2 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Next Addr = 6 +685000 Data Written to Index 2 : 4 +685000 linked_list_exp = 7 3 4 6 0 3 5 +685000 linked_list_addr = 4 5 6 3 1 0 2 +685000 OP_Insert_At_Index 8 index, 3 value +733000 Addr 0 found at Index 5 +733000 Addr 1 found at Index 4 +733000 Addr 2 found at Index 6 +733000 Addr 3 found at Index 3 +733000 Addr 4 found at Index 0 +733000 Addr 5 found at Index 1 +733000 Addr 6 found at Index 2 +733000 Next Addr = 7 +733000 Data Written to Back : 3 +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 4 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Read from back 8 times +829000 Data read: 3 +877000 Data read: 5 +925000 Data read: 3 +973000 Data read: 0 +1021000 Data read: 6 +1069000 Data read: 4 +1117000 Data read: 3 +1165000 Data read: 7 +1165000 linked_list_exp = 7 3 4 6 0 3 5 3 +1165000 linked_list_addr = 4 5 6 3 1 0 2 7 +1165000 OP_Insert_At_Index 8 index, 1 value +1213000 Fault flag is asserted correctly +1213000 Queue is full and full flag is asserted correctly +1213000 linked_list_exp = 7 3 4 6 0 3 5 3 +1213000 linked_list_addr = 4 5 6 3 1 0 2 7 +1213000 OP_Insert_At_Index 0 index, 3 value +1261000 Fault flag is asserted correctly +1261000 Queue is full and full flag is asserted correctly +1261000 linked_list_exp = 7 3 4 6 0 3 5 3 +1261000 linked_list_addr = 4 5 6 3 1 0 2 7 +1461000 OP_Read from front 8 times +1501000 Data read: 7 +1549000 Data read: 3 +1597000 Data read: 4 +1645000 Data read: 6 +1693000 Data read: 0 +1741000 Data read: 3 +1789000 Data read: 5 +1837000 Data read: 3 +1837000 linked_list_exp = 7 3 4 6 0 3 5 3 +1837000 linked_list_addr = 4 5 6 3 1 0 2 7 +2337000 OP_Delete_Value 7 value +2389000 Data 7 at Index 0 is Deleted_by_Value +2389000 linked_list_exp = 3 4 6 0 3 5 3 +2389000 linked_list_addr = 5 6 3 1 0 2 7 +2389000 OP_Delete_At_Index 0 index +ERROR: /tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/tb/sv/tb.sv:353: 2437000 fault flag is asser +--- STDERR --- +/tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/src/doubly_linked_list.sv:105: warning: Numeric constant truncated to 2 bits. +/tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_hleiqk8b/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..74f66ffde0d556bab26316bd2044f2e66db4735a Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..dd1bc5522b091e83057a08b7c06a179cb6e5c769 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/Doubly_Linked_List/src/doubly_linked_list.sv ++++ b/Doubly_Linked_List/src/doubly_linked_list.sv +@@ -81,7 +81,7 @@ + reg valid_wr; + reg [ADDR_WIDTH-1:0] next_addr_rd_buf; + reg [ADDR_WIDTH-1:0] pre_addr_rd_buf; +- reg [DATA_WIDTH-1:0] data_rd_buf; ++ reg [DATA_WIDTH-2:0] data_rd_buf; + reg [ADDR_WIDTH-1:0] target_idx; + reg [ADDR_WIDTH-1:0] next_node_addr_idx; + reg [ADDR_WIDTH-1:0] next_node_addr_in; diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..15463fcb84f49be167ade5b13f640b3b288a4aa0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,5 @@ +{ + "bug_type": "wrong_bitwidth", + "simulation_status": "waveform_identical", + "signals_compared": 10 +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..ca013de737835857d571a564a05884b73a212d29 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,123 @@ +FST info: dumpfile Doubly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +541000 Addr 0 found at Index 3 +541000 Addr 1 found at Index 2 +541000 Addr 2 found at Index 4 +541000 Addr 3 found at Index 1 +541000 Addr 4 found at Index 0 +541000 Next Addr = 5 +541000 Data Written to Index 1 : 3 +541000 linked_list_exp = 7 3 6 0 3 5 +541000 linked_list_addr = 4 5 3 1 0 2 +541000 OP_Insert_At_Index 2 index, 4 value +685000 Addr 0 found at Index 4 +685000 Addr 1 found at Index 3 +685000 Addr 2 found at Index 5 +685000 Addr 3 found at Index 2 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Next Addr = 6 +685000 Data Written to Index 2 : 4 +685000 linked_list_exp = 7 3 4 6 0 3 5 +685000 linked_list_addr = 4 5 6 3 1 0 2 +685000 OP_Insert_At_Index 8 index, 3 value +733000 Addr 0 found at Index 5 +733000 Addr 1 found at Index 4 +733000 Addr 2 found at Index 6 +733000 Addr 3 found at Index 3 +733000 Addr 4 found at Index 0 +733000 Addr 5 found at Index 1 +733000 Addr 6 found at Index 2 +733000 Next Addr = 7 +733000 Data Written to Back : 3 +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 4 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Read from back 8 times +829000 Data read: 3 +877000 Data read: 5 +925000 Data read: 3 +973000 Data read: 0 +1021000 Data read: 6 +1069000 Data read: 4 +1117000 Data read: 3 +1165000 Data read: 7 +1165000 linked_list_exp = 7 3 4 6 0 3 5 3 +1165000 linked_list_addr = 4 5 6 3 1 0 2 7 +1165000 OP_Insert_At_Index 8 index, 1 value +1213000 Fault flag is asserted correctly +1213000 Queue is full and full flag is asserted correctly +1213000 linked_list_exp = 7 3 4 6 0 3 5 3 +1213000 linked_list_addr = 4 5 6 3 1 0 2 7 +1213000 OP_Insert_At_Index 0 index, 3 value +1261000 Fault flag is asserted correctly +1261000 Queue is full and full flag is asserted correctly +1261000 linked_list_exp = 7 3 4 6 0 3 5 3 +1261000 linked_list_addr = 4 5 6 3 1 0 2 7 +1461000 OP_Read from front 8 times +1501000 Data read: 7 +1549000 Data read: 3 +1597000 Data read: 4 +1645000 Data read: 6 +1693000 Data read: 0 +1741000 Data read: 3 +1789000 Data read: 5 +1837000 Data read: 3 +1837000 linked_list_exp = 7 3 4 6 0 3 5 3 +1837000 linked_list_addr = 4 5 6 3 1 0 2 7 +2337000 OP_Delete_Value 7 value +2389000 Data 7 at Index 0 is Deleted_by_Value +2389000 linked_list_exp = 3 4 6 0 3 5 3 +2389000 linked_list_addr = 5 6 3 1 0 2 7 +2389000 OP_Delete_At_Index 0 index +2461000 Data 3 at Front is Deleted +2461000 linked_list_exp = 4 6 0 3 5 3 +2461000 linked_list_addr = 6 +--- STDERR --- +/tmp/sim4_simsh_aa7k8vo0/source/Doubly_Linked_List/tb/sv/tb.sv:98: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_aa7k8vo0/source/Doubly_Linked_List/tb/sv/tb.sv:615: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_aa7k8vo0/source/Doubly_Linked_List/tb/sv/tb.sv:660: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..ca37f89a97beb30a065ba30c26b4cd9d33d80740 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/sim.sh b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..2cbcc6e28d5ed30af638bb2779b2b07e28305105 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/doubly_linked_list__doubly_linked_list/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_doubly_linked_list "$SRCDIR/Doubly_Linked_List/src/doubly_linked_list.sv" "$SRCDIR/Doubly_Linked_List/tb/sv/tb.sv" +vvp /tmp/sim_doubly_linked_list -fst +VCDFILE=Doubly_Linked_List/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..6e61558eec156decb6bb26eb4dfdbbf608ca726a Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..6358339feaadd76cc779bcc68661331d65666ee6 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/Dual_Edge_FF/src/dual_edge_ff.sv ++++ b/Dual_Edge_FF/src/dual_edge_ff.sv +@@ -40,7 +40,7 @@ + always @ (posedge clk or negedge rst_n) begin + if(!rst_n) + q_out_pos[i] <= RESET_VALUE[i]; +- else if(pos_edge_latch_en[i]) ++ else if(!pos_edge_latch_en[i]) + q_out_pos[i] <= d_in_pos[i]; + end + diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..3b5aea14b97f46cc38ad1a95ac2e7e9b859f3403 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "Dual_Edge_FF/src/dual_edge_ff.sv" + ], + "bug_description": "Inverted 'pos_edge_latch_en' condition in positive-edge flip-flop \u2014 q_out_pos now latches when pos_edge_latch_en is deasserted instead of asserted", + "signals_affected": [ + "pos_edge_latch_en" + ], + "simulation_status": "sim_ok", + "problem_statement": "Data output signal data_out fails to update despite pos_edge_latch_en being asserted to enable latching. At t=120000, when the latch enable signal is asserted and new data is available on the input, data_out remains stuck at 00000000 instead of capturing the expected value. The signal continues to hold this value through subsequent clock cycles, indicating that the latch is not responding correctly to the enable control signal. Simulation waveforms show pos_edge_latch_en transitioning as expected, but the data capture mechanism is not functioning properly.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..d5d6178e21199508ec0e08429be01d2e297f49c5 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,51 @@ +FST info: dumpfile Dual_Edge_FF/tb/sv/dump.fst opened for output. +Starting direct operation test +121000 Data out is correctly latched at negedge with value 129 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 133000 Data out is incorrect, should not be updated at posedge, EXP: 129, ACT: 130 + Time: 133000 Scope: tb.direct_test +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:77: 157000 Data out is incorrect at posedge, EXP: 99, ACT: 130 + Time: 157000 Scope: tb.direct_test +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:87: 169000 Data out is incorrect, should not be updated at posedge, EXP: 99, ACT: 130 + Time: 169000 Scope: tb.direct_test +193000 Data out is correctly latched at negedge with value 141 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 205000 Data out is incorrect, should not be updated at posedge, EXP: 141, ACT: 142 + Time: 205000 Scope: tb.direct_test +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:77: 229000 Data out is incorrect at posedge, EXP: 18, ACT: 142 + Time: 229000 Scope: tb.direct_test +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:87: 241000 Data out is incorrect, should not be updated at posedge, EXP: 18, ACT: 142 + Time: 241000 Scope: tb.direct_test +265000 Data out is correctly latched at negedge with value 13 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 277000 Data out is incorrect, should not be updated at posedge, EXP: 13, ACT: 14 + Time: 277000 Scope: tb.direct_test +313000 Data out is correctly latched at negedge with value 61 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 325000 Data out is incorrect at posedge, EXP: 237, ACT: 61 + Time: 325000 Scope: tb.direct_test +361000 Data out is correctly latched at negedge with value 249 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 373000 Data out is incorrect at posedge, EXP: 198, ACT: 249 + Time: 373000 Scope: tb.direct_test +409000 Data out is correctly latched at negedge with value 170 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 421000 Data out is incorrect, should not be updated at posedge, EXP: 170, ACT: 171 + Time: 421000 Scope: tb.direct_test +457000 Data out is correctly latched at negedge with value 119 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 469000 Data out is incorrect at posedge, EXP: 18, ACT: 119 + Time: 469000 Scope: tb.direct_test +505000 Data out is correctly latched at negedge with value 242 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 517000 Data out is incorrect at posedge, EXP: 206, ACT: 242 + Time: 517000 Scope: tb.direct_test +553000 Data out is correctly latched at negedge with value 197 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 565000 Data out is incorrect, should not be updated at posedge, EXP: 197, ACT: 198 + Time: 565000 Scope: tb.direct_test +601000 Data out is correctly latched at negedge with value 189 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:139: 613000 Data out is incorrect at posedge, EXP: 45, ACT: 189 + Time: 613000 Scope: tb.direct_test +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:77: 637000 Data out is incorrect at posedge, EXP: 99, ACT: 189 + Time: 637000 Scope: tb.direct_test +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:87: 649000 Data out is incorrect, should not be updated at posedge, EXP: 99, ACT: 189 + Time: 649000 Scope: tb.direct_test +673000 Data out is correctly latched at negedge with value 128 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:112: 685000 Data out is incorrect, should not be updated at posedge, EXP: 128, ACT: 129 + Time: 685000 Scope: tb.direct_test +721000 Data out is correctly latched at negedge with value 170 +ERROR: /tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/ +--- STDERR --- +/tmp/sim4_simsh_4cdpjsak/source/Dual_Edge_FF/tb/sv/tb.sv:62: warning: task definition for "direct_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..4ed3aa1cffbda4d0f774f6549eafa697ba2b4887 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..faf9ad04fc3ff5bfaf49fb3cf3e2c4833e3cf0f7 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/diff.patch @@ -0,0 +1,11 @@ +--- a/Dual_Edge_FF/src/dual_edge_ff.sv ++++ b/Dual_Edge_FF/src/dual_edge_ff.sv +@@ -40,7 +40,7 @@ + always @ (posedge clk or negedge rst_n) begin + if(!rst_n) + q_out_pos[i] <= RESET_VALUE[i]; +- else if(pos_edge_latch_en[i]) ++ else + q_out_pos[i] <= d_in_pos[i]; + end + diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..3a97252d3d9a54653016c6c56d448bf5a9fe5bc6 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "Dual_Edge_FF/src/dual_edge_ff.sv" + ], + "bug_description": "Removed 'pos_edge_latch_en[i]' enable condition from the posedge clk sequential block \u2014 q_out_pos[i] now updates on every positive clock edge instead of only when pos_edge_latch_en[i] is high", + "signals_affected": [ + "q_out_pos", + "data_out" + ], + "simulation_status": "sim_ok", + "problem_statement": "During verification of the data latch module, we observed that `data_out` is not maintaining stable values across clock cycles as expected. Specifically, at t=120000, `data_out` shows 00000000 when it should have retained the previously latched value based on the pos_edge_latch_en signal control. The `q_out_pos` register appears to be updating on every positive clock edge regardless of the enable signal state, causing `data_out` to be overwritten continuously instead of only updating when pos_edge_latch_en is asserted. This violates the expected behavior where the output should remain constant except when an explicit latch enable pulse is received. The issue prevents proper data capture and holding, breaking the intended control flow of the module.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..0113a7f9cdd929fdf51a0deea206bc3599408ae0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_enable/sim_log.txt @@ -0,0 +1,55 @@ +FST info: dumpfile Dual_Edge_FF/tb/sv/dump.fst opened for output. +Starting direct operation test +121000 Data out is correctly latched at negedge with value 129 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 133000 Data out is incorrect, should not be updated at posedge, EXP: 129, ACT: 130 + Time: 133000 Scope: tb.direct_test +157000 Data out is correctly latched at posedge with value 99 +193000 Data out is correctly latched at negedge with value 141 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 205000 Data out is incorrect, should not be updated at posedge, EXP: 141, ACT: 142 + Time: 205000 Scope: tb.direct_test +229000 Data out is correctly latched at posedge with value 18 +265000 Data out is correctly latched at negedge with value 13 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 277000 Data out is incorrect, should not be updated at posedge, EXP: 13, ACT: 14 + Time: 277000 Scope: tb.direct_test +313000 Data out is correctly latched at negedge with value 61 +325000 Data out is correctly latched at posedge with value 237 +361000 Data out is correctly latched at negedge with value 249 +373000 Data out is correctly latched at posedge with value 198 +409000 Data out is correctly latched at negedge with value 170 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 421000 Data out is incorrect, should not be updated at posedge, EXP: 170, ACT: 171 + Time: 421000 Scope: tb.direct_test +457000 Data out is correctly latched at negedge with value 119 +469000 Data out is correctly latched at posedge with value 18 +505000 Data out is correctly latched at negedge with value 242 +517000 Data out is correctly latched at posedge with value 206 +553000 Data out is correctly latched at negedge with value 197 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 565000 Data out is incorrect, should not be updated at posedge, EXP: 197, ACT: 198 + Time: 565000 Scope: tb.direct_test +601000 Data out is correctly latched at negedge with value 189 +613000 Data out is correctly latched at posedge with value 45 +637000 Data out is correctly latched at posedge with value 99 +673000 Data out is correctly latched at negedge with value 128 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 685000 Data out is incorrect, should not be updated at posedge, EXP: 128, ACT: 129 + Time: 685000 Scope: tb.direct_test +721000 Data out is correctly latched at negedge with value 170 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 733000 Data out is incorrect, should not be updated at posedge, EXP: 170, ACT: 171 + Time: 733000 Scope: tb.direct_test +757000 Data out is correctly latched at posedge with value 150 +805000 Data out is correctly latched at posedge with value 13 +853000 Data out is correctly latched at posedge with value 107 +889000 Data out is correctly latched at negedge with value 2 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 901000 Data out is incorrect, should not be updated at posedge, EXP: 2, ACT: 3 + Time: 901000 Scope: tb.direct_test +937000 Data out is correctly latched at negedge with value 29 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 949000 Data out is incorrect, should not be updated at posedge, EXP: 29, ACT: 30 + Time: 949000 Scope: tb.direct_test +985000 Data out is correctly latched at negedge with value 35 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 997000 Data out is incorrect, should not be updated at posedge, EXP: 35, ACT: 36 + Time: 997000 Scope: tb.direct_test +1033000 Data out is correctly latched at negedge with value 202 +ERROR: /tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:112: 1045000 Data out is incorrect, should not be updated at posedge, EXP: 202, ACT: 203 + Time: 1045000 Scope: tb.direct_test +1069000 Data out is correctly latched at posedge with value 242 +1105000 Data out is cor +--- STDERR --- +/tmp/sim4_simsh_lh7kvlqo/source/Dual_Edge_FF/tb/sv/tb.sv:62: warning: task definition for "direct_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..c8e95f2a28b8c1bc252ec8d52ee352696077d4fc Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..5272dd967f640eb4244f900be85fd63f06be14c6 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/diff.patch @@ -0,0 +1,21 @@ +--- a/Dual_Edge_FF/src/dual_edge_ff.sv ++++ b/Dual_Edge_FF/src/dual_edge_ff.sv +@@ -28,6 +28,7 @@ + reg [DATA_WIDTH-1:0] d_in_neg; + reg [DATA_WIDTH-1:0] q_out_neg; + ++ initial q_out_pos = {DATA_WIDTH{1'bx}}; + + assign clk_n = ~clk; // Invert clock for negative edge latching + +@@ -38,9 +39,7 @@ + + assign d_in_pos[i] = data_in[i] ^ q_out_neg[i]; + always @ (posedge clk or negedge rst_n) begin +- if(!rst_n) +- q_out_pos[i] <= RESET_VALUE[i]; +- else if(pos_edge_latch_en[i]) ++ if(pos_edge_latch_en[i]) + q_out_pos[i] <= d_in_pos[i]; + end + diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..60b81f2524214453841a0bd0dc662f7c1e63b4f5 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "Dual_Edge_FF/src/dual_edge_ff.sv" + ], + "bug_description": "Removed asynchronous reset for 'q_out_pos' register; added initial block setting q_out_pos to unknown (x) to make the missing reset observable in simulation", + "signals_affected": [ + "q_out_pos" + ], + "simulation_status": "sim_ok", + "problem_statement": "Upon simulation startup, the `data_out` signal exhibits undefined values (xxxxxxxx) at t=0, when it should be initialized to a known state following the reset sequence. The output register does not properly initialize to its expected reset value, instead holding unknown bits throughout the initial cycles. This causes the data output bus to drive X-states onto downstream logic immediately at the start of simulation, preventing proper initialization-dependent checks and breaking any verification assertions that depend on known output values after reset de-assertion.", + "diff_summary": "7 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..3df895b95828f7619684766376fb5eb9e9fdd54b --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/missing_reset/sim_log.txt @@ -0,0 +1,68 @@ +FST info: dumpfile Dual_Edge_FF/tb/sv/dump.fst opened for output. +Starting direct operation test +121000 Data out is correctly latched at negedge with value x +157000 Data out is correctly latched at posedge with value x +193000 Data out is correctly latched at negedge with value x +229000 Data out is correctly latched at posedge with value x +265000 Data out is correctly latched at negedge with value x +313000 Data out is correctly latched at negedge with value x +325000 Data out is correctly latched at posedge with value x +361000 Data out is correctly latched at negedge with value x +373000 Data out is correctly latched at posedge with value x +409000 Data out is correctly latched at negedge with value x +457000 Data out is correctly latched at negedge with value x +469000 Data out is correctly latched at posedge with value x +505000 Data out is correctly latched at negedge with value x +517000 Data out is correctly latched at posedge with value x +553000 Data out is correctly latched at negedge with value x +601000 Data out is correctly latched at negedge with value x +613000 Data out is correctly latched at posedge with value x +637000 Data out is correctly latched at posedge with value x +673000 Data out is correctly latched at negedge with value x +721000 Data out is correctly latched at negedge with value x +757000 Data out is correctly latched at posedge with value x +805000 Data out is correctly latched at posedge with value x +853000 Data out is correctly latched at posedge with value x +889000 Data out is correctly latched at negedge with value x +937000 Data out is correctly latched at negedge with value x +985000 Data out is correctly latched at negedge with value x +1033000 Data out is correctly latched at negedge with value x +1069000 Data out is correctly latched at posedge with value x +1105000 Data out is correctly latched at negedge with value x +1117000 Data out is correctly latched at posedge with value x +1153000 Data out is correctly latched at negedge with value x +1165000 Data out is correctly latched at posedge with value x +1201000 Data out is correctly latched at negedge with value x +1213000 Data out is correctly latched at posedge with value x +1249000 Data out is correctly latched at negedge with value x +1285000 Data out is correctly latched at posedge with value x +1321000 Data out is correctly latched at negedge with value x +1333000 Data out is correctly latched at posedge with value x +1369000 Data out is correctly latched at negedge with value x +1417000 Data out is correctly latched at negedge with value x +1465000 Data out is correctly latched at negedge with value x +1477000 Data out is correctly latched at posedge with value x +1513000 Data out is correctly latched at negedge with value x +1525000 Data out is correctly latched at posedge with value x +1561000 Data out is correctly latched at negedge with value x +1597000 Data out is correctly latched at posedge with value x +1633000 Data out is correctly latched at negedge with value x +1645000 Data out is correctly latched at posedge with value x +1681000 Data out is correctly latched at negedge with value x +1729000 Data out is correctly latched at negedge with value x +1741000 Data out is correctly latched at posedge with value x +1777000 Data out is correctly latched at negedge with value x +1789000 Data out is correctly latched at posedge with value x +1825000 Data out is correctly latched at negedge with value x +1873000 Data out is correctly latched at negedge with value x +1885000 Data out is correctly latched at posedge with value x +1921000 Data out is correctly latched at negedge with value x +1957000 Data out is correctly latched at posedge with value x +1993000 Data out is correctly latched at negedge with value x +2041000 Data out is correctly latched at negedge with value x +2077000 Data out is correctly latched at posedge with value x +2125000 Data out is correctly latched at posedge with value x +2173000 Data out is correctly latched at posedge with value x +2221000 Data out is cor +--- STDERR --- +/tmp/sim4_simsh_1_i_5s5y/source/Dual_Edge_FF/tb/sv/tb.sv:62: warning: task definition for "direct_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..f5864e0ba1dae78afaf9c15a92f7f74ab797d50a Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..571a3ebedf5c3fbd6cbd254a7f9635e03e0ae231 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/Dual_Edge_FF/src/dual_edge_ff.sv ++++ b/Dual_Edge_FF/src/dual_edge_ff.sv +@@ -24,7 +24,7 @@ + ); + + reg [DATA_WIDTH-1:0] d_in_pos; +- reg [DATA_WIDTH-1:0] q_out_pos; ++ reg [DATA_WIDTH-3:0] q_out_pos; + reg [DATA_WIDTH-1:0] d_in_neg; + reg [DATA_WIDTH-1:0] q_out_neg; + diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..11a79c6d3024edbe0df71655c839504a614830d5 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "wrong_bitwidth", + "task_type": "behavioral_bug", + "files_modified": [ + "Dual_Edge_FF/src/dual_edge_ff.sv" + ], + "bug_description": "Truncated 'q_out_pos' register from DATA_WIDTH bits to DATA_WIDTH-2 bits, causing upper 2 bits to be stuck at 0 when driving data_out", + "signals_affected": [ + "q_out_pos" + ], + "simulation_status": "sim_ok", + "problem_statement": "The `data_out` signal is not transferring data correctly. At t=0 and throughout simulation, the upper 2 bits remain stuck at 0, while the lower bits show expected transitions. When verifying data transfer operations, the `data_out` output fails to reflect the full value that should be driven from the internal register\u2014specifically, bits that should be set to 1 in the upper positions of the word are consistently observed as 0. This causes mismatches in data integrity checks and prevents correct operation of the data path. The issue appears to affect all data transfers, suggesting a systematic problem with how the output register is connected to the `data_out` port.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..177fff3a31a278bfb43c37b4cc402948e8b1a421 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,68 @@ +FST info: dumpfile Dual_Edge_FF/tb/sv/dump.fst opened for output. +Starting direct operation test +121000 Data out is correctly latched at negedge with value X +157000 Data out is correctly latched at posedge with value X +193000 Data out is correctly latched at negedge with value X +229000 Data out is correctly latched at posedge with value X +265000 Data out is correctly latched at negedge with value X +313000 Data out is correctly latched at negedge with value X +325000 Data out is correctly latched at posedge with value X +361000 Data out is correctly latched at negedge with value X +373000 Data out is correctly latched at posedge with value X +409000 Data out is correctly latched at negedge with value X +457000 Data out is correctly latched at negedge with value X +469000 Data out is correctly latched at posedge with value X +505000 Data out is correctly latched at negedge with value X +517000 Data out is correctly latched at posedge with value X +553000 Data out is correctly latched at negedge with value X +601000 Data out is correctly latched at negedge with value X +613000 Data out is correctly latched at posedge with value X +637000 Data out is correctly latched at posedge with value X +673000 Data out is correctly latched at negedge with value X +721000 Data out is correctly latched at negedge with value X +757000 Data out is correctly latched at posedge with value X +805000 Data out is correctly latched at posedge with value X +853000 Data out is correctly latched at posedge with value X +889000 Data out is correctly latched at negedge with value X +937000 Data out is correctly latched at negedge with value X +985000 Data out is correctly latched at negedge with value X +1033000 Data out is correctly latched at negedge with value X +1069000 Data out is correctly latched at posedge with value X +1105000 Data out is correctly latched at negedge with value X +1117000 Data out is correctly latched at posedge with value X +1153000 Data out is correctly latched at negedge with value X +1165000 Data out is correctly latched at posedge with value X +1201000 Data out is correctly latched at negedge with value X +1213000 Data out is correctly latched at posedge with value X +1249000 Data out is correctly latched at negedge with value X +1285000 Data out is correctly latched at posedge with value X +1321000 Data out is correctly latched at negedge with value X +1333000 Data out is correctly latched at posedge with value X +1369000 Data out is correctly latched at negedge with value X +1417000 Data out is correctly latched at negedge with value X +1465000 Data out is correctly latched at negedge with value X +1477000 Data out is correctly latched at posedge with value X +1513000 Data out is correctly latched at negedge with value X +1525000 Data out is correctly latched at posedge with value X +1561000 Data out is correctly latched at negedge with value X +1597000 Data out is correctly latched at posedge with value X +1633000 Data out is correctly latched at negedge with value X +1645000 Data out is correctly latched at posedge with value X +1681000 Data out is correctly latched at negedge with value X +1729000 Data out is correctly latched at negedge with value X +1741000 Data out is correctly latched at posedge with value X +1777000 Data out is correctly latched at negedge with value X +1789000 Data out is correctly latched at posedge with value X +1825000 Data out is correctly latched at negedge with value X +1873000 Data out is correctly latched at negedge with value X +1885000 Data out is correctly latched at posedge with value X +1921000 Data out is correctly latched at negedge with value X +1957000 Data out is correctly latched at posedge with value X +1993000 Data out is correctly latched at negedge with value X +2041000 Data out is correctly latched at negedge with value X +2077000 Data out is correctly latched at posedge with value X +2125000 Data out is correctly latched at posedge with value X +2173000 Data out is correctly latched at posedge with value X +2221000 Data out is cor +--- STDERR --- +/tmp/sim4_simsh_hhfr_x00/source/Dual_Edge_FF/tb/sv/tb.sv:62: warning: task definition for "direct_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..8f74a41b392c671d2e5f3fe79823f3afc903d700 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/sim.sh b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..707cd01c2bf32b047064f3eb37fe4a9ad1131d9d --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/dual_edge_ff__dual_edge_ff/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_dual_edge_ff "$SRCDIR/Dual_Edge_FF/src/dual_edge_ff.sv" "$SRCDIR/Dual_Edge_FF/tb/sv/tb.sv" +vvp /tmp/sim_dual_edge_ff -fst +VCDFILE=Dual_Edge_FF/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..8018e0bbb4f728a099226167c22c87d6134d1bf7 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/diff.patch b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..64f05a91b27fd3c41e9ef22fc1b14ab2e66dd2b0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/diff.patch @@ -0,0 +1,11 @@ +--- a/FIFO/src/fifo.sv ++++ b/FIFO/src/fifo.sv +@@ -31,7 +31,7 @@ + if(rst) begin + {wr_gray_pointer_sync[1], wr_gray_pointer_sync[0]} <= {(2*CNTR_WIDTH){1'b0}}; + end else begin +- {wr_gray_pointer_sync[1], wr_gray_pointer_sync[0]} <= {wr_gray_pointer_sync[0], wr_gray_pointer}; ++ {wr_gray_pointer_sync[1], wr_gray_pointer_sync[0]} <= {wr_gray_pointer, wr_gray_pointer_sync[0]}; + end + end + diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/metadata.json b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..b3e5063ce1a7049d31b81b703febb758ae6796b4 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "concat_swap", + "task_type": "behavioral_bug", + "files_modified": [ + "FIFO/src/fifo.sv" + ], + "bug_description": "Reordered concatenation {wr_gray_pointer_sync[0], wr_gray_pointer} to {wr_gray_pointer, wr_gray_pointer_sync[0]} in the wr_gray_pointer synchronizer shift register \u2014 the new write-pointer value is loaded into sync[1] instead of sync[0], breaking the two-stage synchronizer so wr_gray_pointer_sync[1] immediately reflects the unsynchronized write pointer rather than the properly delayed version", + "signals_affected": [ + "wr_gray_pointer_sync" + ], + "simulation_status": "sim_ok", + "problem_statement": "During FIFO cross-clock-domain verification, the `fifo_empty` signal exhibits incorrect behavior at t=16000, transitioning to 'x' when it should reflect a valid logic state. The write-side gray pointer synchronizer (`wr_gray_pointer_sync`) appears to be responding too quickly to write-pointer changes, suggesting the multi-stage synchronization pipeline is not functioning as designed. This causes the FIFO empty flag calculation to become unstable and unreliable across clock domain crossings. The issue manifests consistently when write pointer updates occur, indicating a systematic failure in the synchronization mechanism rather than a transient metastability event. Further investigation of the pointer synchronizer path is needed to restore proper FIFO operation.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/sim_log.txt b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..dac736a78a78c134c34175ce8e30a15f627ce5f4 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/concat_swap/sim_log.txt @@ -0,0 +1,77 @@ +FST info: dumpfile FIFO/tb/sv/dump.fst opened for output. + +100000 FIFO WRITE BURST SEQ +110000 Data written = 146, FIFO entry = 1 +130000 Data written = 64, FIFO entry = 2 +150000 Data written = 4, FIFO entry = 3 +170000 Data written = 49, FIFO entry = 4 +190000 Data written = 134, FIFO entry = 5 +210000 Data written = 198, FIFO entry = 6 +230000 Data written = 50, FIFO entry = 7 +250000 Data written = 9, FIFO entry = 8 +270000 Data written = 128, FIFO entry = 9 +290000 Data written = 134, FIFO entry = 10 +310000 Data written = 187, FIFO entry = 11 +330000 Data written = 158, FIFO entry = 12 +351000 FIFO is full, fifo_full flag is asserted correctly +371000 FIFO is full, fifo_full flag is asserted correctly +391000 FIFO is full, fifo_full flag is asserted correctly + +1410000 FIFO READ BURST SEQ +1458000 Data read = 146, FIFO entry = 11 +1490000 Data read = 64, FIFO entry = 10 +1522000 Data read = 4, FIFO entry = 9 +1554000 Data read = 49, FIFO entry = 8 +1586000 Data read = 134, FIFO entry = 7 +1618000 Data read = 198, FIFO entry = 6 +1650000 Data read = 50, FIFO entry = 5 +1682000 Data read = 9, FIFO entry = 4 +1714000 Data read = 128, FIFO entry = 3 +1746000 Data read = 134, FIFO entry = 2 +1778000 Data read = 187, FIFO entry = 1 +1810000 Data read = 158, FIFO entry = 0 +1841000 FIFO is empty, fifo_empty flag is asserted correctly +1873000 FIFO is empty, fifo_empty flag is asserted correctly +1905000 FIFO is empty, fifo_empty flag is asserted correctly + +2905000 FIFO RANDOM READ WRITE SEQ +2910000 Data written = 85, FIFO entry = 1 +2930000 Data written = 242, FIFO entry = 2 +2950000 Data written = 59, FIFO entry = 3 +2970000 Data written = 9, FIFO entry = 4 +2990000 Data written = 199, FIFO entry = 5 +3130000 Data written = 116, FIFO entry = 6 +3150000 Data written = 98, FIFO entry = 7 +3170000 Data written = 174, FIFO entry = 8 +3346000 Data read = 85, FIFO entry = 7 +3474000 Data read = 242, FIFO entry = 6 +3570000 Data written = 144, FIFO entry = 7 +3710000 Data written = 78, FIFO entry = 8 +4466000 Data read = 59, FIFO entry = 7 + +5558000 FIFO SIMULTANEOUS RANDOM READ WRITE SEQ +5618000 Data read = 9, FIFO entry = 6 +5650000 Data read = 199, FIFO entry = 5 +5682000 Data read = 116, FIFO entry = 4 +5714000 Data read = 98, FIFO entry = 3 +5746000 Data read = 174, FIFO entry = 2 +5778000 Data read = 144, FIFO entry = 1 +5810000 Data read = 78, FIFO entry = 0 +5830000 Data written = 101, FIFO entry = 1 +5850000 Data written = 30, FIFO entry = 2 +5870000 Data written = 250, FIFO entry = 3 +5890000 Data written = 197, FIFO entry = 4 +5910000 Data written = 161, FIFO entry = 5 +5930000 Data written = 108, FIFO entry = 6 +5950000 Data written = 188, FIFO entry = 7 +5970000 Data written = 68, FIFO entry = 8 +5990000 Data written = 246, FIFO entry = 9 +6010000 Data written = 219, FIFO entry = 10 +6030000 Data written = 228, FIFO entry = 11 +6050000 Data written = 215, FIFO entry = 12 + +7070000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_al8_3h79/source/FIFO/tb/sv/tb.sv:165: warning: task definition for "fifo_read_write_rand_simul" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..a3e0727a1699e0a92a4a2ec32ec10a0d1d74a6cf Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..b8cf1f2b03066b65ee6c8193ba6f8a4a78f70509 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/FIFO/src/fifo.sv ++++ b/FIFO/src/fifo.sv +@@ -64,7 +64,7 @@ + if(rst) begin + for (i = 0; i < DEPTH; i = i + 1) + fifo_stored[i] <= {DATA_WIDTH{1'b0}}; +- end else if (wr_en & !fifo_full) begin ++ end else if (wr_en & fifo_full) begin + fifo_stored[wr_binary_pointer] <= data_wr; + end + end diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..f0400882834c1658b27344c03e0b7e97da3df8fc --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "FIFO/src/fifo.sv" + ], + "bug_description": "Inverted '!fifo_full' condition in write data block \u2014 FIFO now writes data only when full instead of when not full, corrupting written data output", + "signals_affected": [ + "fifo_full" + ], + "simulation_status": "sim_ok", + "problem_statement": "During verification testing, the `data_rd` output shows undefined/corrupted values (X) starting at t=16000 after multiple write operations to the FIFO. The expected behavior is that written data should be available on `data_rd` during corresponding read cycles, but instead we observe invalid data on the output. This corruption occurs even when `fifo_full` indicates the FIFO is not at capacity. The write control logic requires investigation to ensure data is being correctly loaded into the FIFO and subsequently retrieved during reads.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..5665faaea6d83694f4e37784da0ade529dbeafa1 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,62 @@ +FST info: dumpfile FIFO/tb/sv/dump.fst opened for output. + +100000 FIFO WRITE BURST SEQ +110000 Data written = 146, FIFO entry = 1 +130000 Data written = 64, FIFO entry = 2 +150000 Data written = 4, FIFO entry = 3 +170000 Data written = 49, FIFO entry = 4 +190000 Data written = 134, FIFO entry = 5 +210000 Data written = 198, FIFO entry = 6 +230000 Data written = 50, FIFO entry = 7 +250000 Data written = 9, FIFO entry = 8 +270000 Data written = 128, FIFO entry = 9 +290000 Data written = 134, FIFO entry = 10 +310000 Data written = 187, FIFO entry = 11 +330000 Data written = 158, FIFO entry = 12 +351000 FIFO is full, fifo_full flag is asserted correctly +371000 FIFO is full, fifo_full flag is asserted correctly +391000 FIFO is full, fifo_full flag is asserted correctly + +1410000 FIFO READ BURST SEQ +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1458000 Data read mismatch, ACT = 0, EXP = 146, FIFO entry = 11 + Time: 1458000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1490000 Data read mismatch, ACT = 0, EXP = 64, FIFO entry = 10 + Time: 1490000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1522000 Data read mismatch, ACT = 0, EXP = 4, FIFO entry = 9 + Time: 1522000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1554000 Data read mismatch, ACT = 0, EXP = 49, FIFO entry = 8 + Time: 1554000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1586000 Data read mismatch, ACT = 0, EXP = 134, FIFO entry = 7 + Time: 1586000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1618000 Data read mismatch, ACT = 0, EXP = 198, FIFO entry = 6 + Time: 1618000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1650000 Data read mismatch, ACT = 0, EXP = 50, FIFO entry = 5 + Time: 1650000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1682000 Data read mismatch, ACT = 0, EXP = 9, FIFO entry = 4 + Time: 1682000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1714000 Data read mismatch, ACT = 0, EXP = 128, FIFO entry = 3 + Time: 1714000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1746000 Data read mismatch, ACT = 0, EXP = 134, FIFO entry = 2 + Time: 1746000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1778000 Data read mismatch, ACT = 0, EXP = 187, FIFO entry = 1 + Time: 1778000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 1810000 Data read mismatch, ACT = 252, EXP = 158, FIFO entry = 0 + Time: 1810000 Scope: tb.fifo_read_burst +1841000 FIFO is empty, fifo_empty flag is asserted correctly +1873000 FIFO is empty, fifo_empty flag is asserted correctly +1905000 FIFO is empty, fifo_empty flag is asserted correctly + +2905000 FIFO RANDOM READ WRITE SEQ +2910000 Data written = 85, FIFO entry = 1 +2930000 Data written = 242, FIFO entry = 2 +2950000 Data written = 59, FIFO entry = 3 +2970000 Data written = 9, FIFO entry = 4 +2990000 Data written = 199, FIFO entry = 5 +3130000 Data written = 116, FIFO entry = 6 +3150000 Data written = 98, FIFO entry = 7 +3170000 Data written = 174, FIFO entry = 8 +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 3346000 Data read mismatch, ACT = 0, EXP = 85, FIFO entry = 7 + Time: 3346000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:118: 3474000 Data read +--- STDERR --- +/tmp/sim4_simsh_s5hmrvxe/source/FIFO/tb/sv/tb.sv:165: warning: task definition for "fifo_read_write_rand_simul" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..170a87f6db84dab68199c8703ac1a0a9aed61faa Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..21d429debc45d1fba6e2d46c7937941c1a0d4b97 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/diff.patch @@ -0,0 +1,11 @@ +--- a/FIFO/src/fifo.sv ++++ b/FIFO/src/fifo.sv +@@ -64,7 +64,7 @@ + if(rst) begin + for (i = 0; i < DEPTH; i = i + 1) + fifo_stored[i] <= {DATA_WIDTH{1'b0}}; +- end else if (wr_en & !fifo_full) begin ++ end else begin + fifo_stored[wr_binary_pointer] <= data_wr; + end + end diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..866f601aacc8d4465c9f1e2999d4fb9f5d76b9d3 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "FIFO/src/fifo.sv" + ], + "bug_description": "Removed 'wr_en & !fifo_full' enable condition from the FIFO write block \u2014 fifo_stored now updates on every clock edge regardless of wr_en or fifo_full status", + "signals_affected": [ + "fifo_stored" + ], + "simulation_status": "sim_ok", + "problem_statement": "The FIFO read data output (`data_rd`) is returning undefined values starting at t=16000, indicating corrupted read operations. The issue appears to be that the FIFO is not correctly tracking its internal state \u2014 specifically, the `fifo_stored` count seems to be incrementing unexpectedly even when no valid write operation has been requested. When the FIFO counter reaches an invalid state, subsequent reads return garbage data instead of the expected FIFO contents. The read data remains corrupted (all Xs) after this point, preventing correct data retrieval from the FIFO. This suggests the FIFO's write logic is not properly gating updates to its internal storage counter based on the write enable signal and full status.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..fa22b858efa51327396382f9da2f8f34411e1b40 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_enable/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile FIFO/tb/sv/dump.fst opened for output. + +100000 FIFO WRITE BURST SEQ +110000 Data written = 146, FIFO entry = 1 +130000 Data written = 64, FIFO entry = 2 +150000 Data written = 4, FIFO entry = 3 +170000 Data written = 49, FIFO entry = 4 +190000 Data written = 134, FIFO entry = 5 +210000 Data written = 198, FIFO entry = 6 +230000 Data written = 50, FIFO entry = 7 +250000 Data written = 9, FIFO entry = 8 +270000 Data written = 128, FIFO entry = 9 +290000 Data written = 134, FIFO entry = 10 +310000 Data written = 187, FIFO entry = 11 +330000 Data written = 158, FIFO entry = 12 +351000 FIFO is full, fifo_full flag is asserted correctly +371000 FIFO is full, fifo_full flag is asserted correctly +391000 FIFO is full, fifo_full flag is asserted correctly + +1410000 FIFO READ BURST SEQ +1458000 Data read = 146, FIFO entry = 11 +1490000 Data read = 64, FIFO entry = 10 +1522000 Data read = 4, FIFO entry = 9 +1554000 Data read = 49, FIFO entry = 8 +1586000 Data read = 134, FIFO entry = 7 +1618000 Data read = 198, FIFO entry = 6 +1650000 Data read = 50, FIFO entry = 5 +1682000 Data read = 9, FIFO entry = 4 +1714000 Data read = 128, FIFO entry = 3 +1746000 Data read = 134, FIFO entry = 2 +1778000 Data read = 187, FIFO entry = 1 +ERROR: /tmp/sim4_simsh_ss5z242o/source/FIFO/tb/sv/tb.sv:118: 1810000 Data read mismatch, ACT = 252, EXP = 158, FIFO entry = 0 + Time: 1810000 Scope: tb.fifo_read_burst +1841000 FIFO is empty, fifo_empty flag is asserted correctly +1873000 FIFO is empty, fifo_empty flag is asserted correctly +1905000 FIFO is empty, fifo_empty flag is asserted correctly + +2905000 FIFO RANDOM READ WRITE SEQ +2910000 Data written = 85, FIFO entry = 1 +2930000 Data written = 242, FIFO entry = 2 +2950000 Data written = 59, FIFO entry = 3 +2970000 Data written = 9, FIFO entry = 4 +2990000 Data written = 199, FIFO entry = 5 +3130000 Data written = 116, FIFO entry = 6 +3150000 Data written = 98, FIFO entry = 7 +3170000 Data written = 174, FIFO entry = 8 +3346000 Data read = 85, FIFO entry = 7 +3474000 Data read = 242, FIFO entry = 6 +3570000 Data written = 144, FIFO entry = 7 +3710000 Data written = 78, FIFO entry = 8 +4466000 Data read = 59, FIFO entry = 7 + +5558000 FIFO SIMULTANEOUS RANDOM READ WRITE SEQ +5618000 Data read = 9, FIFO entry = 6 +5650000 Data read = 199, FIFO entry = 5 +5682000 Data read = 116, FIFO entry = 4 +5714000 Data read = 98, FIFO entry = 3 +5746000 Data read = 174, FIFO entry = 2 +5778000 Data read = 144, FIFO entry = 1 +5810000 Data read = 78, FIFO entry = 0 +5830000 Data written = 101, FIFO entry = 1 +5850000 Data written = 30, FIFO entry = 2 +5870000 Data written = 250, FIFO entry = 3 +5890000 Data written = 197, FIFO entry = 4 +5910000 Data written = 161, FIFO entry = 5 +5930000 Data written = 108, FIFO entry = 6 +5950000 Data written = 188, FIFO entry = 7 +5970000 Data written = 68, FIFO entry = 8 +5990000 Data written = 246, FIFO entry = 9 +6010000 Data written = 219, FIFO entry = 10 +6030000 Data written = 228, FIFO entry = 11 +6050000 Data written = 215, FIFO entry = 12 + +7070000 TEST FAILED +Error count = 1 + + +--- STDERR --- +/tmp/sim4_simsh_ss5z242o/source/FIFO/tb/sv/tb.sv:165: warning: task definition for "fifo_read_write_rand_simul" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..2581c1a6c24fb64d58d2f3502452bb6cdaae3d95 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..3a976406d896f27c50721a433777dd350217fced --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/diff.patch @@ -0,0 +1,24 @@ +--- a/FIFO/src/fifo.sv ++++ b/FIFO/src/fifo.sv +@@ -24,6 +24,8 @@ + reg [CNTR_WIDTH-1:0] rd_gray_pointer_sync[1:0]; + reg [CNTR_WIDTH-1:0] wr_gray_pointer_sync[1:0]; + wire rdptr_eq_next_wrptr; ++ ++ initial rd_binary_pointer = {CNTR_WIDTH{1'bx}}; + + generate //: POINTER_SYNCHRONIZER + if (ASYNC == 1) begin +@@ -87,10 +89,8 @@ + // data_rd, rd_binary_pointer, rd_gray_pointer + assign rd_binary_pointer_next = (rd_binary_pointer == DEPTH-1) ? {CNTR_WIDTH{1'b0}} : rd_binary_pointer + 1; + +- always @ (posedge rd_clk, posedge rst) begin +- if(rst) begin +- rd_binary_pointer <= {CNTR_WIDTH{1'b0}}; +- end else if (rd_en & !fifo_empty) begin ++ always @ (posedge rd_clk) begin ++ if (rd_en & !fifo_empty) begin + rd_binary_pointer <= rd_binary_pointer_next; + end + end diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..9f781b33f05dd593350fd242b5a649a08349efd4 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "FIFO/src/fifo.sv" + ], + "bug_description": "Removed synchronous reset for 'rd_binary_pointer' register; the always block no longer resets it on rst assertion, and an initial block sets it to X to make the missing reset observable in simulation", + "signals_affected": [ + "rd_binary_pointer" + ], + "simulation_status": "sim_ok", + "problem_statement": "After reset de-assertion, the FIFO exhibits undefined behavior with its control signals and output data. Specifically, at t=10000ps, the `fifo_full` signal transitions to an unknown state (X), indicating the full flag logic is not functioning correctly. Subsequently, at t=16000ps, both the `data_rd` output and `fifo_empty` signal also collapse to unknown states (X), suggesting a systemic failure in the read pointer logic affecting both empty flag generation and data output multiplexing. The FIFO read side appears to be uninitialized or corrupted after reset, preventing reliable operation. This issue occurs consistently across multiple test vectors and requires investigation into the read-side pointer initialization and the flags' dependence on this pointer state.", + "diff_summary": "10 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..827be2eb8759060fa29ea060e1881e2392ab749d --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/missing_reset/sim_log.txt @@ -0,0 +1,58 @@ +FST info: dumpfile FIFO/tb/sv/dump.fst opened for output. + +100000 FIFO WRITE BURST SEQ +110000 Data written = 146, FIFO entry = 1 +130000 Data written = 64, FIFO entry = 2 +150000 Data written = 4, FIFO entry = 3 +170000 Data written = 49, FIFO entry = 4 +190000 Data written = 134, FIFO entry = 5 +210000 Data written = 198, FIFO entry = 6 +230000 Data written = 50, FIFO entry = 7 +250000 Data written = 9, FIFO entry = 8 +270000 Data written = 128, FIFO entry = 9 +290000 Data written = 134, FIFO entry = 10 +310000 Data written = 187, FIFO entry = 11 +330000 Data written = 158, FIFO entry = 12 +351000 FIFO is full, fifo_full flag is asserted correctly +371000 FIFO is full, fifo_full flag is asserted correctly +391000 FIFO is full, fifo_full flag is asserted correctly + +1410000 FIFO READ BURST SEQ +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1458000 Data read mismatch, ACT = 0, EXP = 146, FIFO entry = 11 + Time: 1458000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1490000 Data read mismatch, ACT = 0, EXP = 64, FIFO entry = 10 + Time: 1490000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1522000 Data read mismatch, ACT = 0, EXP = 4, FIFO entry = 9 + Time: 1522000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1554000 Data read mismatch, ACT = 0, EXP = 49, FIFO entry = 8 + Time: 1554000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1586000 Data read mismatch, ACT = 0, EXP = 134, FIFO entry = 7 + Time: 1586000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1618000 Data read mismatch, ACT = 0, EXP = 198, FIFO entry = 6 + Time: 1618000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1650000 Data read mismatch, ACT = 0, EXP = 50, FIFO entry = 5 + Time: 1650000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1682000 Data read mismatch, ACT = 0, EXP = 9, FIFO entry = 4 + Time: 1682000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1714000 Data read mismatch, ACT = 0, EXP = 128, FIFO entry = 3 + Time: 1714000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1746000 Data read mismatch, ACT = 0, EXP = 134, FIFO entry = 2 + Time: 1746000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1778000 Data read mismatch, ACT = 0, EXP = 187, FIFO entry = 1 + Time: 1778000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:118: 1810000 Data read mismatch, ACT = 0, EXP = 158, FIFO entry = 0 + Time: 1810000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:126: 1841000 FIFO is empty but fifo_empty flag is not asserted + Time: 1841000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:126: 1873000 FIFO is empty but fifo_empty flag is not asserted + Time: 1873000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:126: 1905000 FIFO is empty but fifo_empty flag is not asserted + Time: 1905000 Scope: tb.fifo_read_burst + +2905000 FIFO RANDOM READ WRITE SEQ +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:72: 2910000 FIFO is not full but fifo_full flag is asserted + Time: 2910000 Scope: tb.fifo_write_burst_rand +2910000 Data written = 85, FIFO entry = 1 +ERROR: /tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:72: 2930000 FIFO is not full but +--- STDERR --- +/tmp/sim4_simsh_lu40p89j/source/FIFO/tb/sv/tb.sv:165: warning: task definition for "fifo_read_write_rand_simul" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..b8aadc1cdc55bb061382feb18877177620fb7155 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..641cb20971564ce8d94423ef4cb3f20e62bf17bd --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/FIFO/src/fifo.sv ++++ b/FIFO/src/fifo.sv +@@ -18,7 +18,7 @@ + + reg [CNTR_WIDTH-1:0] rd_gray_pointer, rd_binary_pointer; + wire [CNTR_WIDTH-1:0] rd_binary_pointer_next; +- reg [CNTR_WIDTH-1:0] wr_gray_pointer, wr_binary_pointer; ++ reg [CNTR_WIDTH-2:0] wr_gray_pointer, wr_binary_pointer; + wire [CNTR_WIDTH-1:0] wr_binary_pointer_next; + reg [DATA_WIDTH-1:0] fifo_stored [DEPTH-1:0]; + reg [CNTR_WIDTH-1:0] rd_gray_pointer_sync[1:0]; diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..00b36e6175d9a4f7730582a15a122121f4f6bf7d --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "wrong_bitwidth", + "task_type": "behavioral_bug", + "files_modified": [ + "FIFO/src/fifo.sv" + ], + "bug_description": "Truncated 'wr_gray_pointer' and 'wr_binary_pointer' registers from [CNTR_WIDTH-1:0] to [CNTR_WIDTH-2:0], losing the MSB of the write pointer and causing silent truncation in write address and full-flag comparisons", + "signals_affected": [ + "wr_gray_pointer", + "wr_binary_pointer" + ], + "simulation_status": "sim_ok", + "problem_statement": "The FIFO full detection is failing during normal operation\u2014at t=10000, the `fifo_full` signal shows unexpected behavior when it should be asserting based on write and read pointer comparison. By t=16000, the problem propagates to data integrity, with `data_rd` becoming undefined and `fifo_empty` signal remaining incorrect. The symptoms suggest incorrect pointer tracking or address comparison in the write domain, leading to lost synchronization between the read and write pointers. The FIFO should properly detect full conditions when the write and read pointers compare equal (accounting for gray code conversion), and assert empty when they are identical in the read domain. Current waveforms indicate the write pointer comparison logic is not functioning as specified.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..ff530fe1bc03f21105fbbb9cf81f3f3753bbfdf1 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,56 @@ +FST info: dumpfile FIFO/tb/sv/dump.fst opened for output. + +100000 FIFO WRITE BURST SEQ +110000 Data written = 146, FIFO entry = 1 +130000 Data written = 64, FIFO entry = 2 +150000 Data written = 4, FIFO entry = 3 +170000 Data written = 49, FIFO entry = 4 +190000 Data written = 134, FIFO entry = 5 +210000 Data written = 198, FIFO entry = 6 +230000 Data written = 50, FIFO entry = 7 +250000 Data written = 9, FIFO entry = 8 +270000 Data written = 128, FIFO entry = 9 +290000 Data written = 134, FIFO entry = 10 +310000 Data written = 187, FIFO entry = 11 +330000 Data written = 158, FIFO entry = 12 +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:86: 351000 FIFO is full but fifo_full flag is not asserted + Time: 351000 Scope: tb.fifo_write_burst_rand +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:86: 371000 FIFO is full but fifo_full flag is not asserted + Time: 371000 Scope: tb.fifo_write_burst_rand +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:86: 391000 FIFO is full but fifo_full flag is not asserted + Time: 391000 Scope: tb.fifo_write_burst_rand + +1410000 FIFO READ BURST SEQ +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1458000 Data read mismatch, ACT = 128, EXP = 146, FIFO entry = 11 + Time: 1458000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1490000 Data read mismatch, ACT = 134, EXP = 64, FIFO entry = 10 + Time: 1490000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1522000 Data read mismatch, ACT = 187, EXP = 4, FIFO entry = 9 + Time: 1522000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:106: 1552000 FIFO is not empty but fifo_empty flag is asserted + Time: 1552000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1554000 Data read mismatch, ACT = 187, EXP = 49, FIFO entry = 8 + Time: 1554000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:106: 1584000 FIFO is not empty but fifo_empty flag is asserted + Time: 1584000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1586000 Data read mismatch, ACT = 187, EXP = 134, FIFO entry = 7 + Time: 1586000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:106: 1616000 FIFO is not empty but fifo_empty flag is asserted + Time: 1616000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1618000 Data read mismatch, ACT = 187, EXP = 198, FIFO entry = 6 + Time: 1618000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:106: 1648000 FIFO is not empty but fifo_empty flag is asserted + Time: 1648000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1650000 Data read mismatch, ACT = 187, EXP = 50, FIFO entry = 5 + Time: 1650000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:106: 1680000 FIFO is not empty but fifo_empty flag is asserted + Time: 1680000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1682000 Data read mismatch, ACT = 187, EXP = 9, FIFO entry = 4 + Time: 1682000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:106: 1712000 FIFO is not empty but fifo_empty flag is asserted + Time: 1712000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:118: 1714000 Data read mismatch, ACT = 187, EXP = 128, FIFO entry = 3 + Time: 1714000 Scope: tb.fifo_read_burst +ERROR: /tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:106: 1744000 FIFO is not empty but fifo_empty fla +--- STDERR --- +/tmp/sim4_simsh_o5rfxn6p/source/FIFO/tb/sv/tb.sv:165: warning: task definition for "fifo_read_write_rand_simul" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/fifo__fifo/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..cb55f018e28682416af54fcd5e5fb20476c01689 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/fifo__fifo/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/fifo__fifo/sim.sh b/Weiyet_RTLStructLib/candidates/fifo__fifo/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..fe0aefabfa9f9cd589d892a7c2390e9c304c66de --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/fifo__fifo/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_fifo "$SRCDIR/FIFO/src/fifo.sv" "$SRCDIR/FIFO/tb/sv/tb.sv" +vvp /tmp/sim_fifo -fst +VCDFILE=FIFO/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..e70e687aaf2fbb2316834580cd07cf68a9a6589f Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..681fb252cd8cc8de72c283d0e3071f40cc7514e5 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/Hash_Table/src/hash_table.sv ++++ b/Hash_Table/src/hash_table.sv +@@ -151,7 +151,7 @@ + op_error <= 1; // KEY_NOT_FOUND error + current_state <= OP_DONE; + end +- end else if(key_in == hash_key_stored[get_hash_index(key_in)][search_ptr*KEY_WIDTH +: KEY_WIDTH]) begin ++ end else if(key_in != hash_key_stored[get_hash_index(key_in)][search_ptr*KEY_WIDTH +: KEY_WIDTH]) begin + if(op_sel == 2'b00) begin + current_state <= INSERT; + end else if (op_sel == 2'b01) begin diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..698e78eef5bc07208c689a7e1f989aa724a166ee --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "Hash_Table/src/hash_table.sv" + ], + "bug_description": "Inverted 'key_in == hash_key_stored[...]' condition in SEARCH_KEY state \u2014 key match now triggers the miss branch (insert/delete/read on mismatch) instead of the hit branch", + "signals_affected": [ + "key_in", + "hash_key_stored" + ], + "simulation_status": "sim_ok", + "problem_statement": "When performing key lookups in the hash table, matched keys are not returning the stored values. During a search operation where `key_in` matches an entry in `hash_key_stored`, the `value_out` signal remains at all zeros (t=950000) instead of outputting the associated data value. Additionally, the `op_done` signal fails to assert at the expected time (t=450000), preventing the operation from completing. The `collision_count` stays at zero throughout the test, even when duplicate keys should be detected. The design appears to be executing the incorrect operation path when a key match occurs, causing successful lookups to fail while unintended side effects occur on the hash table state.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..0848984721578ccac9a92d25a8f7c9b3a8b900fc --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,130 @@ +FST info: dumpfile Hash_Table/tb/sv/dump.fst opened for output. +451000 find_first_index: Key 1 is not found +451000 hash_table_insert: Key 2 - Value 1 is inserted to expected index 1 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +1051000 find_first_index: Key 1 is found at Index 1 Chain no 0 +ERROR: /tmp/sim4_simsh__k5ovyky/source/Hash_Table/tb/sv/tb.sv:221: 1051000 hash_table_search: Key 1 - value 0 is mismatched, expeted_value 2 + Time: 1051000 Scope: tb.hash_table_search +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +1551000 find_first_index: Key 3 is not found +1551000 hash_table_insert: Key 2 - Value 3 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2051000 find_first_index: Key 11 is not found +2051000 hash_table_insert: Key 3 - Value 11 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2551000 find_first_index: Key 19 is not found +2551000 hash_table_insert: Key 4 - Value 19 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +3051000 find_first_index: Key 27 is not found +3051000 hash_table_insert: Key 5 - Value 27 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +3551000 find_first_index: Key 35 is not found +ERROR: /tmp/sim4_simsh__k5ovyky/source/Hash_Table/tb/sv/tb.sv:172: 3551000 hash_table_insert: Key 5 - Value 35 is not inserted succesfully, chain is full, op_error is not asserted expectedly + Time: 3551000 Scope: tb.hash_table_insert +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +4051000 find_first_index: Key 43 is not found +ERROR: /tmp/sim4_simsh__k5ovyky/source/Hash_Table/tb/sv/tb.sv:172: 4051000 hash_table_insert: Key 5 - Value 43 is not inserted succesfully, chain is full, op_error is not asserted expectedly + Time: 4051000 Scope: tb.hash_table_insert +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +4651000 find_first_index: Key 1 is found at Index 1 Chain no 0 +4651000 hash_table_delete: Key 1 at index 1 is deleted +4651000 delete_index: Key 1 is deleted at Index 1 Chain no 0 +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5151000 find_first_index: Key 19 is found at Index 3 Chain no 2 +ERROR: /tmp/sim4_simsh__k5ovyky/source/Hash_Table/tb/sv/tb.sv:221: 5151000 hash_table_search: Key 19 - value 5 is mismatched, expeted_value 4 + Time: 5151000 Scope: tb.hash_table_search +Hash Table Index 0: +Hash Table Inde \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..d4278057fecd98e86faae92437dbe39495a10a94 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..e13524e99f3657e66b6b1c6e1ad2e72d2f669d9f --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/diff.patch @@ -0,0 +1,22 @@ +--- a/Hash_Table/src/hash_table.sv ++++ b/Hash_Table/src/hash_table.sv +@@ -80,7 +80,7 @@ + end else begin + case(current_state) + IDLE: begin +- if (op_en) begin ++ begin + case (op_sel) + 2'b00: current_state <= SEARCH_KEY; //INSERT + 2'b01: current_state <= SEARCH_KEY; //DELETE +@@ -91,10 +91,6 @@ + op_error <= 1; // Invalid operation + end + endcase +- end else begin +- current_state <= IDLE; +- op_done <= 0; +- op_error <= 0; + end + search_ptr <= 0; + value_out <= 0; diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..1943e5541712e674a516f81282b69f2bfbf72aa0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/metadata.json @@ -0,0 +1,18 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "Hash_Table/src/hash_table.sv" + ], + "bug_description": "Removed 'op_en' enable condition from the IDLE state \u2014 the state machine now dispatches operations every cycle regardless of op_en, causing unintended transitions out of IDLE even when no operation is requested", + "signals_affected": [ + "current_state", + "op_done", + "op_error" + ], + "simulation_status": "sim_ok", + "problem_statement": "The state machine is dispatching operations without valid enable signals, causing spurious operation completions and errors. Specifically, `op_done` is asserted at t=350000 without a corresponding `op_en` request, and `op_error` is unexpectedly asserted at t=3650000. Additionally, `value_out` contains a non-zero value (0x00000002) at t=750000 and `collision_count` increments to 0x01 at the same cycle, indicating the operation pipeline is executing when it should remain idle. The state machine appears to be transitioning out of the IDLE state and initiating operations autonomously rather than waiting for explicit enable signals from the control interface.", + "diff_summary": "8 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..a4c23830c02fb0c51a518579317024f953925de4 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_enable/sim_log.txt @@ -0,0 +1,148 @@ +FST info: dumpfile Hash_Table/tb/sv/dump.fst opened for output. +351000 find_first_index: Key 1 is not found +351000 hash_table_insert: Key 2 - Value 1 is inserted to expected index 1 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +751000 find_first_index: Key 1 is found at Index 1 Chain no 0 +751000 hash_table_search: Key 1 - value 2 is found +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +1151000 find_first_index: Key 3 is not found +1151000 hash_table_insert: Key 2 - Value 3 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +1651000 find_first_index: Key 11 is not found +1651000 hash_table_insert: Key 3 - Value 11 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2251000 find_first_index: Key 19 is not found +2251000 hash_table_insert: Key 4 - Value 19 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2951000 find_first_index: Key 27 is not found +2951000 hash_table_insert: Key 5 - Value 27 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +3651000 find_first_index: Key 35 is not found +3651000 hash_table_insert: Key 5 - Value 35 is not inserted succesfully, chain is full, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +4351000 find_first_index: Key 43 is not found +4351000 hash_table_insert: Key 5 - Value 43 is not inserted succesfully, chain is full, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +4751000 find_first_index: Key 1 is found at Index 1 Chain no 0 +4751000 hash_table_delete: Key 1 at index 1 is deleted +4751000 delete_index: Key 1 is deleted at Index 1 Chain no 0 +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5351000 find_first_index: Key 19 is found at Index 3 Chain no 2 +5351000 hash_table_search: Key 19 - value 4 is found +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5651000 find_first_index: Key 1 is not found +5651000 hash_table_delete: Key 1 is unfound, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..003bcabffbda83fdab28cef33b5a90b406d09c32 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..e1bd8ead967d2491189124e46b274fc7ef52f2f0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/diff.patch @@ -0,0 +1,21 @@ +--- a/Hash_Table/src/hash_table.sv ++++ b/Hash_Table/src/hash_table.sv +@@ -49,6 +49,9 @@ + localparam READ = 3'b100; + localparam OP_DONE = 3'b101; + ++ initial value_out = {VALUE_WIDTH{1'bx}}; ++ initial collision_count = {$clog2(CHAINING_SIZE-1){1'bx}}; ++ + // Hash function selector + function integer get_hash_index; + input integer key; +@@ -68,8 +71,6 @@ + if(rst) begin + current_state <= IDLE; + search_ptr <= 0; +- value_out <= 0; +- collision_count <= 0; + op_done <= 0; + op_error <= 0; + for (i = 0; i < TOTAL_INDEX; i++) begin diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..4fe994a6ab1f2fa5ed4e72cd9eaf4bcab584034a --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "Hash_Table/src/hash_table.sv" + ], + "bug_description": "Removed synchronous reset for 'value_out' and 'collision_count' registers; added initial blocks setting them to X so the missing reset is observable in simulation", + "signals_affected": [ + "value_out", + "collision_count" + ], + "simulation_status": "sim_ok", + "problem_statement": "After power-on and reset de-assertion, the `value_out` and `collision_count` registers are not being properly initialized. Both signals remain at unknown/undefined (X) values at t=0 instead of reaching their expected reset states. This prevents the design from achieving a known starting state for simulation and would cause verification to fail at any constraint that depends on these signals being in a defined state post-reset. The undefined values propagate through dependent logic, making it impossible to validate the core functionality of the circuit. Verification cannot proceed until these signals properly initialize to their specified reset values.", + "diff_summary": "7 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..fbc51e6a9572fa79d93c3b629404b5709f2e4c0e --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/missing_reset/sim_log.txt @@ -0,0 +1,148 @@ +FST info: dumpfile Hash_Table/tb/sv/dump.fst opened for output. +451000 find_first_index: Key 1 is not found +451000 hash_table_insert: Key 2 - Value 1 is inserted to expected index 1 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +951000 find_first_index: Key 1 is found at Index 1 Chain no 0 +951000 hash_table_search: Key 1 - value 2 is found +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +1451000 find_first_index: Key 3 is not found +1451000 hash_table_insert: Key 2 - Value 3 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2051000 find_first_index: Key 11 is not found +2051000 hash_table_insert: Key 3 - Value 11 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2751000 find_first_index: Key 19 is not found +2751000 hash_table_insert: Key 4 - Value 19 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +3551000 find_first_index: Key 27 is not found +3551000 hash_table_insert: Key 5 - Value 27 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +4351000 find_first_index: Key 35 is not found +4351000 hash_table_insert: Key 5 - Value 35 is not inserted succesfully, chain is full, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5151000 find_first_index: Key 43 is not found +5151000 hash_table_insert: Key 5 - Value 43 is not inserted succesfully, chain is full, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5651000 find_first_index: Key 1 is found at Index 1 Chain no 0 +5651000 hash_table_delete: Key 1 at index 1 is deleted +5651000 delete_index: Key 1 is deleted at Index 1 Chain no 0 +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +6351000 find_first_index: Key 19 is found at Index 3 Chain no 2 +6351000 hash_table_search: Key 19 - value 4 is found +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +6751000 find_first_index: Key 1 is not found +6751000 hash_table_delete: Key 1 is unfound, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..15bd03b90632e206386b56afac4703f2b4950999 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/diff.patch b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..6840e676d9395d6626d947e43ef18682730af46d --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/diff.patch @@ -0,0 +1,11 @@ +--- a/Hash_Table/src/hash_table.sv ++++ b/Hash_Table/src/hash_table.sv +@@ -160,7 +160,7 @@ + current_state <= READ; + end + end else if (search_ptr == hash_chain_count[get_hash_index(key_in)]) begin +- if(op_sel == 2'b00 & (hash_chain_count[get_hash_index(key_in)] < CHAINING_SIZE)) begin ++ if(op_sel == 2'b00 & (hash_chain_count[get_hash_index(key_in)] <= CHAINING_SIZE)) begin + current_state <= INSERT; + end else begin + collision_count <= CHAINING_SIZE; diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/metadata.json b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..d863216110e4e8d80d3b3977ad0645da27019095 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "off_by_one_counter", + "task_type": "behavioral_bug", + "files_modified": [ + "Hash_Table/src/hash_table.sv" + ], + "bug_description": "Changed 'hash_chain_count[get_hash_index(key_in)] < CHAINING_SIZE' to 'hash_chain_count[get_hash_index(key_in)] <= CHAINING_SIZE' \u2014 insert is now allowed even when the chain is already full (count == CHAINING_SIZE), causing an out-of-bounds write one slot past the allocated chain storage", + "signals_affected": [ + "hash_chain_count" + ], + "simulation_status": "sim_ok", + "problem_statement": "Hash table insert operations are failing to complete correctly when chains reach capacity. After multiple insertions that generate collisions, the following issues are observed:\n\n- `op_done` signal never asserts high during insert operations that should trigger chain updates (expected assertion around t=450000, but signal remains low)\n- `value_out` returns all zeros (t=950000) instead of reflecting the inserted or retrieved data\n- `collision_count` register shows incorrect values (read as 00 at t=950000 when collisions have been detected)\n- `op_error` signal does not assert even after attempting multiple inserts to a full chain (remains 0 at t=4350000)\n\nThe behavior suggests the hash table is either silently dropping insertions or corrupting internal state when handling chain-full conditions. This is reproducible when inserting beyond the expected `CHAINING_SIZE` limit for a given hash bucket. Needs investigation into the insert path's handling of chain overflow scenarios.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/sim_log.txt b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..692c32a03850566958f515beae464080c7436a06 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/off_by_one_counter/sim_log.txt @@ -0,0 +1,143 @@ +FST info: dumpfile Hash_Table/tb/sv/dump.fst opened for output. +451000 find_first_index: Key 1 is not found +451000 hash_table_insert: Key 2 - Value 1 is inserted to expected index 1 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +951000 find_first_index: Key 1 is found at Index 1 Chain no 0 +951000 hash_table_search: Key 1 - value 2 is found +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +1451000 find_first_index: Key 3 is not found +1451000 hash_table_insert: Key 2 - Value 3 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2051000 find_first_index: Key 11 is not found +2051000 hash_table_insert: Key 3 - Value 11 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2751000 find_first_index: Key 19 is not found +2751000 hash_table_insert: Key 4 - Value 19 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +3551000 find_first_index: Key 27 is not found +3551000 hash_table_insert: Key 5 - Value 27 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +4451000 find_first_index: Key 35 is not found +ERROR: /tmp/sim4_simsh_6uwj2eg7/source/Hash_Table/tb/sv/tb.sv:172: 4451000 hash_table_insert: Key 5 - Value 35 is not inserted succesfully, chain is full, op_error is not asserted expectedly + Time: 4451000 Scope: tb.hash_table_insert +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5351000 find_first_index: Key 43 is not found +5351000 hash_table_insert: Key 5 - Value 43 is not inserted succesfully, chain is full, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5851000 find_first_index: Key 1 is found at Index 1 Chain no 0 +5851000 hash_table_delete: Key 1 at index 1 is deleted +5851000 delete_index: Key 1 is deleted at Index 1 Chain no 0 +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +6551000 find_first_index: Key 19 is found at Index 3 Chain no 2 +6551000 hash_table_search: Key 19 - value 4 is found +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +6951000 find_first_index: Key 1 is not found +6951000 hash_table_delete: Key 1 is unfound, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table I \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..520ad2b97258751d19fb6d21f66641c6bab97aa6 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/diff.patch b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..4cbfe4e70fad247a2470f2813afcf0904b6168e7 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/diff.patch @@ -0,0 +1,11 @@ +--- a/Hash_Table/src/hash_table.sv ++++ b/Hash_Table/src/hash_table.sv +@@ -157,7 +157,7 @@ + end else if (op_sel == 2'b01) begin + current_state <= DELETE; + end else if (op_sel == 2'b10) begin +- current_state <= READ; ++ current_state <= OP_DONE; + end + end else if (search_ptr == hash_chain_count[get_hash_index(key_in)]) begin + if(op_sel == 2'b00 & (hash_chain_count[get_hash_index(key_in)] < CHAINING_SIZE)) begin diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/metadata.json b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..1c63e9c4869ffd128f8474ef2cbb8fa3d2de35ce --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "state_transition", + "task_type": "behavioral_bug", + "files_modified": [ + "Hash_Table/src/hash_table.sv" + ], + "bug_description": "Changed SEARCH_KEY\u2192READ transition to SEARCH_KEY\u2192OP_DONE when op_sel==2'b10 (Search) and key is found \u2014 FSM skips the READ state, so value_out is never loaded and op_error is never cleared for a successful search", + "signals_affected": [ + "current_state" + ], + "simulation_status": "sim_ok", + "problem_statement": "When executing search operations (op_sel==2'b10), the design fails to properly complete the transaction after successfully finding a matching key. The value_out signal remains stuck at 0x00000000 at t=950000 instead of capturing the found value. Additionally, op_done does not assert at the expected time (t=450000), and op_error fails to transition to the correct state, remaining at 0 at t=4350000. The collision_count similarly stays at 0 at t=950000. These symptoms suggest the search state machine is not executing all necessary transitions to properly load results and finalize the operation.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/sim_log.txt b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..94928a7b1ba9e9a51c7bc0b36f498f40cd5f28fb --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/state_transition/sim_log.txt @@ -0,0 +1,16 @@ +FST info: dumpfile Hash_Table/tb/sv/dump.fst opened for output. +451000 find_first_index: Key 1 is not found +451000 hash_table_insert: Key 2 - Value 1 is inserted to expected index 1 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: + +30000000000 TEST FAILED +SIM TIMEOUT! + diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..5b5868fe438ba6436bfce6358110a4b4cf5b8b64 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..378b64669067cd1b4e0781d31aed05d80f598d68 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/Hash_Table/src/hash_table.sv ++++ b/Hash_Table/src/hash_table.sv +@@ -36,7 +36,7 @@ + reg [2:0] current_state; + //reg [2:0] next_state; + reg [KEY_WIDTH*CHAINING_SIZE-1:0] hash_key_stored [0:TOTAL_INDEX-1]; +- reg [VALUE_WIDTH*CHAINING_SIZE-1:0] hash_value_stored [0:TOTAL_INDEX-1]; ++ reg [VALUE_WIDTH*CHAINING_SIZE-3:0] hash_value_stored [0:TOTAL_INDEX-1]; + reg [CHAINING_SIZE_WIDTH-1:0] hash_chain_count [0:TOTAL_INDEX-1]; // for collision count + reg [CHAINING_SIZE_WIDTH-1:0] search_ptr; // for searching the key in the chain + reg [CHAINING_SIZE_WIDTH-1:0] next_search_ptr; // for searching the key in the chain diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..49010d9cd6bcd26abfdc944736b09ecac3a23eae --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,5 @@ +{ + "bug_type": "wrong_bitwidth", + "simulation_status": "waveform_identical", + "signals_compared": 4 +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..fbc51e6a9572fa79d93c3b629404b5709f2e4c0e --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,148 @@ +FST info: dumpfile Hash_Table/tb/sv/dump.fst opened for output. +451000 find_first_index: Key 1 is not found +451000 hash_table_insert: Key 2 - Value 1 is inserted to expected index 1 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +951000 find_first_index: Key 1 is found at Index 1 Chain no 0 +951000 hash_table_search: Key 1 - value 2 is found +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +1451000 find_first_index: Key 3 is not found +1451000 hash_table_insert: Key 2 - Value 3 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2051000 find_first_index: Key 11 is not found +2051000 hash_table_insert: Key 3 - Value 11 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +2751000 find_first_index: Key 19 is not found +2751000 hash_table_insert: Key 4 - Value 19 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +3551000 find_first_index: Key 27 is not found +3551000 hash_table_insert: Key 5 - Value 27 is inserted to expected index 3 +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +4351000 find_first_index: Key 35 is not found +4351000 hash_table_insert: Key 5 - Value 35 is not inserted succesfully, chain is full, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5151000 find_first_index: Key 43 is not found +5151000 hash_table_insert: Key 5 - Value 43 is not inserted succesfully, chain is full, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Key: 1, Value: 2 +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +5651000 find_first_index: Key 1 is found at Index 1 Chain no 0 +5651000 hash_table_delete: Key 1 at index 1 is deleted +5651000 delete_index: Key 1 is deleted at Index 1 Chain no 0 +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +6351000 find_first_index: Key 19 is found at Index 3 Chain no 2 +6351000 hash_table_search: Key 19 - value 4 is found +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: +Hash Table Index 6: +Hash Table Index 7: +6751000 find_first_index: Key 1 is not found +6751000 hash_table_delete: Key 1 is unfound, op_error is asserted correctly +Hash Table Index 0: +Hash Table Index 1: +Hash Table Index 2: +Hash Table Index 3: +Key: 3, Value: 2 +Key: 11, Value: 3 +Key: 19, Value: 4 +Key: 27, Value: 5 +Hash Table Index 4: +Hash Table Index 5: \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..bed6be75655fc555586be9aefd35d557d9a9287a Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/hash_table__hash_table/sim.sh b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..3cd72c61aea51df80e01313077554e12d425ab36 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/hash_table__hash_table/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_hash_table "$SRCDIR/Hash_Table/src/hash_table.sv" "$SRCDIR/Hash_Table/tb/sv/tb.sv" +vvp /tmp/sim_hash_table -fst +VCDFILE=Hash_Table/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..7d0a7aad933addd89b30a960572997f1d51e1c41 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..1b61f724641542afe46522aaa1f497ab48af8e2f --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/LIFO/src/lifo.sv ++++ b/LIFO/src/lifo.sv +@@ -64,7 +64,7 @@ + lifo_full <= 1'b0; + end else if(rd_op) begin + lifo_full <= 1'b0; +- end else if(pointer == (DEPTH-1) & wr_op) begin ++ end else if(pointer != (DEPTH-1) & wr_op) begin + lifo_full <= 1'b1; + end + end diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..8cea1d56a4cac813690f3e986fc3b0c184565ae3 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "LIFO/src/lifo.sv" + ], + "bug_description": "Inverted 'pointer == (DEPTH-1)' condition in lifo_full flag logic \u2014 lifo_full now asserts when pointer does NOT equal DEPTH-1 during a write, causing premature full assertion", + "signals_affected": [ + "pointer", + "lifo_full" + ], + "simulation_status": "sim_ok", + "problem_statement": "During LIFO buffer operation, the lifo_full flag unexpectedly asserts at t=10000ns while the buffer should still have available capacity. This premature assertion blocks write operations and causes data_rd to output invalid data (xxxxxxxx). Simultaneously, the lifo_empty flag transitions to an indeterminate state (x), indicating corrupted status flags. According to the LIFO specification, the full condition should only trigger when the write pointer reaches DEPTH-1, ensuring the buffer is fully utilized before blocking writes. The current behavior incorrectly restricts buffer capacity and prevents normal read/write operations.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..cdc70895b277cafcc67303d791b4adbbe1d2ffad --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,55 @@ +FST info: dumpfile LIFO/tb/sv/dump.fst opened for output. +Seed number: 0 +200000 LIFO Write 4 times +211000 Data written = 4, entry = 1 +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 231000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 231000 Scope: tb.lifo_write +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 251000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 251000 Scope: tb.lifo_write +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 271000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 271000 Scope: tb.lifo_write +290000 LIFO Read 1 times +331000 Data read = 4, FIFO entry = 0 +331000 LIFO Write 4 times +351000 Data written = 4, entry = 1 +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 371000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 371000 Scope: tb.lifo_write +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 391000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 391000 Scope: tb.lifo_write +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 411000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 411000 Scope: tb.lifo_write +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 431000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 431000 Scope: tb.lifo_write +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 451000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 451000 Scope: tb.lifo_write +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 471000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 471000 Scope: tb.lifo_write +ERROR: /tmp/sim4_simsh_lrh5y1ul/source/LIFO/tb/sv/tb.sv:71: 491000 LIFO is not full but lifo_full flag is asserted incorrectly + Time: 491000 Scope: tb.lifo_write +510000 LIFO Simul Read Write 2 times +551000 Simultaneous Data read/write = 4, FIFO entry = 1 +571000 Simultaneous Data read/write = 49, FIFO entry = 1 +591000 Simultaneous Data read/write = 134, FIFO entry = 1 +611000 Simultaneous Data read/write = 198, FIFO entry = 1 +631000 Simultaneous Data read/write = 187, FIFO entry = 1 +651000 Simultaneous Data read/write = 158, FIFO entry = 1 +671000 Simultaneous Data read/write = 246, FIFO entry = 1 +691000 Simultaneous Data read/write = 198, FIFO entry = 1 +711000 Simultaneous Data read/write = 98, FIFO entry = 1 +731000 Simultaneous Data read/write = 85, FIFO entry = 1 +731000 LIFO Simul Read Write 1 times +771000 Simultaneous Data read/write = 4, FIFO entry = 1 +791000 Simultaneous Data read/write = 49, FIFO entry = 1 +811000 Simultaneous Data read/write = 134, FIFO entry = 1 +831000 Simultaneous Data read/write = 198, FIFO entry = 1 +851000 Simultaneous Data read/write = 187, FIFO entry = 1 +871000 Simultaneous Data read/write = 158, FIFO entry = 1 +891000 Simultaneous Data read/write = 246, FIFO entry = 1 +911000 Simultaneous Data read/write = 198, FIFO entry = 1 +931000 Simultaneous Data read/write = 98, FIFO entry = 1 +951000 Simultaneous Data read/write = 85, FIFO entry = 1 +971000 Simultaneous Data read/write = 59, FIFO entry = 1 + +1971000 TEST FAILED +Error count = 10 + diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..68159918c3d11df2d57c99a613730b5609cac704 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..9815b6ecd1a45ce7b0a67f95287eef85259606c2 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/diff.patch @@ -0,0 +1,11 @@ +--- a/LIFO/src/lifo.sv ++++ b/LIFO/src/lifo.sv +@@ -41,7 +41,7 @@ + if(rst) begin + for (i = 0; i < DEPTH; i = i + 1) + lifo_stored[i] <= {DATA_WIDTH{1'b0}}; +- end else if (wr_op & !lifo_full) begin ++ end else begin + lifo_stored[pointer] <= data_wr; + end + end diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..c884814c391f101cf5356ed2cebfce2cee8dad2d --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/metadata.json @@ -0,0 +1,5 @@ +{ + "bug_type": "missing_enable", + "simulation_status": "waveform_identical", + "signals_compared": 3 +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..c4d95c5ca7892f9fc8c323b90eccf5cd48b5a34f --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_enable/sim_log.txt @@ -0,0 +1,44 @@ +FST info: dumpfile LIFO/tb/sv/dump.fst opened for output. +Seed number: 0 +200000 LIFO Write 4 times +211000 Data written = 4, entry = 1 +231000 Data written = 49, entry = 2 +251000 Data written = 134, entry = 3 +271000 Data written = 198, entry = 4 +290000 LIFO Read 1 times +331000 Data read = 198, FIFO entry = 3 +331000 LIFO Write 4 times +351000 Data written = 4, entry = 4 +371000 Data written = 49, entry = 5 +391000 Data written = 134, entry = 6 +411000 Data written = 198, entry = 7 +431000 Data written = 187, entry = 8 +451000 Data written = 158, entry = 9 +471000 Data written = 246, entry = 10 +491000 Data written = 198, entry = 11 +510000 LIFO Simul Read Write 2 times +551000 Simultaneous Data read/write = 4, FIFO entry = 11 +571000 Simultaneous Data read/write = 49, FIFO entry = 11 +591000 Simultaneous Data read/write = 134, FIFO entry = 11 +611000 Simultaneous Data read/write = 198, FIFO entry = 11 +631000 Simultaneous Data read/write = 187, FIFO entry = 11 +651000 Simultaneous Data read/write = 158, FIFO entry = 11 +671000 Simultaneous Data read/write = 246, FIFO entry = 11 +691000 Simultaneous Data read/write = 198, FIFO entry = 11 +711000 Simultaneous Data read/write = 98, FIFO entry = 11 +731000 Simultaneous Data read/write = 85, FIFO entry = 11 +731000 LIFO Simul Read Write 1 times +771000 Simultaneous Data read/write = 4, FIFO entry = 11 +791000 Simultaneous Data read/write = 49, FIFO entry = 11 +811000 Simultaneous Data read/write = 134, FIFO entry = 11 +831000 Simultaneous Data read/write = 198, FIFO entry = 11 +851000 Simultaneous Data read/write = 187, FIFO entry = 11 +871000 Simultaneous Data read/write = 158, FIFO entry = 11 +891000 Simultaneous Data read/write = 246, FIFO entry = 11 +911000 Simultaneous Data read/write = 198, FIFO entry = 11 +931000 Simultaneous Data read/write = 98, FIFO entry = 11 +951000 Simultaneous Data read/write = 85, FIFO entry = 11 +971000 Simultaneous Data read/write = 59, FIFO entry = 11 + +1971000 TEST PASSED + diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..bea32eb5e4837e760bec9b5fbf492c27996dad04 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..a15d74e3cf207bb18b5a7d56af5d0918be1c33c1 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/diff.patch @@ -0,0 +1,24 @@ +--- a/LIFO/src/lifo.sv ++++ b/LIFO/src/lifo.sv +@@ -25,6 +25,8 @@ + assign rd_op = rd_en & !wr_en; + assign bypass_op = wr_en & rd_en; + ++ initial data_rd = {DATA_WIDTH{1'bx}}; ++ + // pointer logic + always @ (posedge clk, posedge rst) begin + if(rst) begin +@@ -47,10 +49,8 @@ + end + + // data_rd +- always @ (posedge clk, posedge rst) begin +- if(rst) begin +- data_rd <= {DATA_WIDTH{1'b0}}; +- end else if (rd_op & !lifo_empty) begin ++ always @ (posedge clk) begin ++ if (rd_op & !lifo_empty) begin + data_rd <= lifo_stored[pointer-1]; + end else if (bypass_op) begin + data_rd <= data_wr; diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..7c65e292b4a97d5b240359f915974f25c54dd5fd --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "LIFO/src/lifo.sv" + ], + "bug_description": "Removed synchronous reset for 'data_rd' output register; added initial block setting it to X to make the missing reset observable in simulation", + "signals_affected": [ + "data_rd" + ], + "simulation_status": "sim_ok", + "problem_statement": "The output register `data_rd` fails to reset properly following reset de-assertion. In testbench simulations, after the reset signal is cleared, `data_rd` remains in an undefined state (X) at t=10000 instead of being initialized to a known value. This prevents subsequent read operations from returning valid data, causing the entire read path to stall. The issue appears consistently whenever the module is instantiated without explicit external initialization of `data_rd`, suggesting a missing synchronous reset path in the register logic. Verification models expecting `data_rd` to be 0 after reset are failing, and the undefined state is propagating through dependent logic stages.", + "diff_summary": "10 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..c4d95c5ca7892f9fc8c323b90eccf5cd48b5a34f --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/missing_reset/sim_log.txt @@ -0,0 +1,44 @@ +FST info: dumpfile LIFO/tb/sv/dump.fst opened for output. +Seed number: 0 +200000 LIFO Write 4 times +211000 Data written = 4, entry = 1 +231000 Data written = 49, entry = 2 +251000 Data written = 134, entry = 3 +271000 Data written = 198, entry = 4 +290000 LIFO Read 1 times +331000 Data read = 198, FIFO entry = 3 +331000 LIFO Write 4 times +351000 Data written = 4, entry = 4 +371000 Data written = 49, entry = 5 +391000 Data written = 134, entry = 6 +411000 Data written = 198, entry = 7 +431000 Data written = 187, entry = 8 +451000 Data written = 158, entry = 9 +471000 Data written = 246, entry = 10 +491000 Data written = 198, entry = 11 +510000 LIFO Simul Read Write 2 times +551000 Simultaneous Data read/write = 4, FIFO entry = 11 +571000 Simultaneous Data read/write = 49, FIFO entry = 11 +591000 Simultaneous Data read/write = 134, FIFO entry = 11 +611000 Simultaneous Data read/write = 198, FIFO entry = 11 +631000 Simultaneous Data read/write = 187, FIFO entry = 11 +651000 Simultaneous Data read/write = 158, FIFO entry = 11 +671000 Simultaneous Data read/write = 246, FIFO entry = 11 +691000 Simultaneous Data read/write = 198, FIFO entry = 11 +711000 Simultaneous Data read/write = 98, FIFO entry = 11 +731000 Simultaneous Data read/write = 85, FIFO entry = 11 +731000 LIFO Simul Read Write 1 times +771000 Simultaneous Data read/write = 4, FIFO entry = 11 +791000 Simultaneous Data read/write = 49, FIFO entry = 11 +811000 Simultaneous Data read/write = 134, FIFO entry = 11 +831000 Simultaneous Data read/write = 198, FIFO entry = 11 +851000 Simultaneous Data read/write = 187, FIFO entry = 11 +871000 Simultaneous Data read/write = 158, FIFO entry = 11 +891000 Simultaneous Data read/write = 246, FIFO entry = 11 +911000 Simultaneous Data read/write = 198, FIFO entry = 11 +931000 Simultaneous Data read/write = 98, FIFO entry = 11 +951000 Simultaneous Data read/write = 85, FIFO entry = 11 +971000 Simultaneous Data read/write = 59, FIFO entry = 11 + +1971000 TEST PASSED + diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..c8d894000e9aaa38e3b402691b6607bfb4f9fcce Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..de311e3bb0d5833306ddba63a033d4617c470da0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/LIFO/src/lifo.sv ++++ b/LIFO/src/lifo.sv +@@ -13,7 +13,7 @@ + ); + localparam CNTR_WIDTH = $clog2(DEPTH); + +- reg [CNTR_WIDTH-1:0] pointer; ++ reg [CNTR_WIDTH-3:0] pointer; + reg [DATA_WIDTH-1:0] lifo_stored [DEPTH-1:0]; + wire wr_op; + wire rd_op; diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..9bd09e5131ca3fb026ada5d0f3c90bf338fc1a0f --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "wrong_bitwidth", + "task_type": "behavioral_bug", + "files_modified": [ + "LIFO/src/lifo.sv" + ], + "bug_description": "Truncated 'pointer' register from CNTR_WIDTH bits to CNTR_WIDTH-2 bits, causing the stack pointer to wrap around prematurely and corrupt LIFO addressing for deeper entries", + "signals_affected": [ + "pointer" + ], + "simulation_status": "sim_ok", + "problem_statement": "After filling the LIFO stack beyond 2^(CNTR_WIDTH-2) entries, the stack pointer wraps prematurely instead of continuing to address deeper locations as expected. Starting at t=10000, subsequent read operations return undefined data on `data_rd` while the `lifo_empty` flag becomes metastable, indicating the addressing has become corrupted. The stack works correctly for shallow accesses but fails completely once the pointer should address entries beyond the truncated width, suggesting the counter register is not wide enough to represent the full stack depth. This causes data integrity failures and unpredictable behavior in any application relying on deep LIFO operations.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..0e34af37c24edcf3010255b7960e487d892108e0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,48 @@ +FST info: dumpfile LIFO/tb/sv/dump.fst opened for output. +Seed number: 0 +200000 LIFO Write 4 times +211000 Data written = 4, entry = 1 +231000 Data written = 49, entry = 2 +251000 Data written = 134, entry = 3 +271000 Data written = 198, entry = 4 +290000 LIFO Read 1 times +ERROR: /tmp/sim4_simsh_rl68gvcy/source/LIFO/tb/sv/tb.sv:99: 330000 LIFO is not empty but lifo_empty flag is asserted incorrectly + Time: 330000 Scope: tb.lifo_read +ERROR: /tmp/sim4_simsh_rl68gvcy/source/LIFO/tb/sv/tb.sv:108: 331000 Data read mismatch, ACT = 0, EXP = 198, FIFO entry = 3 + Time: 331000 Scope: tb.lifo_read +331000 LIFO Write 4 times +351000 Data written = 4, entry = 4 +371000 Data written = 49, entry = 5 +391000 Data written = 134, entry = 6 +411000 Data written = 198, entry = 7 +431000 Data written = 187, entry = 8 +451000 Data written = 158, entry = 9 +471000 Data written = 246, entry = 10 +491000 Data written = 198, entry = 11 +510000 LIFO Simul Read Write 2 times +551000 Simultaneous Data read/write = 4, FIFO entry = 11 +571000 Simultaneous Data read/write = 49, FIFO entry = 11 +591000 Simultaneous Data read/write = 134, FIFO entry = 11 +611000 Simultaneous Data read/write = 198, FIFO entry = 11 +631000 Simultaneous Data read/write = 187, FIFO entry = 11 +651000 Simultaneous Data read/write = 158, FIFO entry = 11 +671000 Simultaneous Data read/write = 246, FIFO entry = 11 +691000 Simultaneous Data read/write = 198, FIFO entry = 11 +711000 Simultaneous Data read/write = 98, FIFO entry = 11 +731000 Simultaneous Data read/write = 85, FIFO entry = 11 +731000 LIFO Simul Read Write 1 times +771000 Simultaneous Data read/write = 4, FIFO entry = 11 +791000 Simultaneous Data read/write = 49, FIFO entry = 11 +811000 Simultaneous Data read/write = 134, FIFO entry = 11 +831000 Simultaneous Data read/write = 198, FIFO entry = 11 +851000 Simultaneous Data read/write = 187, FIFO entry = 11 +871000 Simultaneous Data read/write = 158, FIFO entry = 11 +891000 Simultaneous Data read/write = 246, FIFO entry = 11 +911000 Simultaneous Data read/write = 198, FIFO entry = 11 +931000 Simultaneous Data read/write = 98, FIFO entry = 11 +951000 Simultaneous Data read/write = 85, FIFO entry = 11 +971000 Simultaneous Data read/write = 59, FIFO entry = 11 + +1971000 TEST FAILED +Error count = 1 + diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/lifo__lifo/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..7783d56cb435e067c6b2ddb5a086ee5a405d744a Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/lifo__lifo/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/lifo__lifo/sim.sh b/Weiyet_RTLStructLib/candidates/lifo__lifo/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..c9d377fba61101ee688a809fec693b7b18d7df74 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/lifo__lifo/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_lifo "$SRCDIR/LIFO/src/lifo.sv" "$SRCDIR/LIFO/tb/sv/tb.sv" +vvp /tmp/sim_lifo -fst +VCDFILE=LIFO/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..d55a0924eed200a0b00b77bd25940d7f0fa8da01 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..c2e1d00b0af388ff10607ae7a470742f4391db33 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/adder.sv ++++ b/List/src/adder.sv +@@ -74,7 +74,7 @@ + sum_result <= sum_result + data_in_unpacked[cur_ptr]; + cur_ptr <= cur_ptr + 'b1; + sum_in_progress <= 1'b1; +- end else if(sum_en & !sum_done & cur_ptr == (LENGTH-1))begin //last element ++ end else if(sum_en & !sum_done & cur_ptr != (LENGTH-1))begin //last element + sum_result <= sum_result + data_in_unpacked[cur_ptr]; + sum_done <= 1'b1; + sum_in_progress <= 1'b0; diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..83fe5f3ae17b9c1edeb5e243232ce9eeff71de93 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/adder.sv" + ], + "bug_description": "Inverted 'cur_ptr == (LENGTH-1)' condition in sequential sum \u2014 last element accumulation now triggers when cur_ptr is NOT at the last position instead of when it is", + "signals_affected": [ + "cur_ptr" + ], + "simulation_status": "sim_ok", + "problem_statement": "The sequential accumulator fails to complete its intended operation. When attempting to process a series of input values, the op_done signal never asserts (observed remaining low at t=132000ps), indicating that the operation did not reach completion. The data_out output similarly remains stuck at all zeros instead of reflecting the accumulated sum across all input elements. The circuit appears to skip processing during the final accumulation cycle, preventing the completion condition from ever being triggered even though cur_ptr advances through the entire input sequence.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..9414a0270b8ffdfb217d70b02dd52b664961578a --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_iarrp1z1/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_iarrp1z1/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_iarrp1z1/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_iarrp1z1/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_iarrp1z1/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..9e76c7ab166117c025b85130a5fca075629c739e Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..6c0ee4d3a3970fccff7008a9cf5b4b292122deed --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/adder.sv ++++ b/List/src/adder.sv +@@ -70,7 +70,7 @@ + sum_done <= 1'b0; + sum_in_progress <= 1'b0; + cur_ptr <= 'b0; +- end else if(sum_en & cur_ptr < (LENGTH-1)) begin ++ end else if(cur_ptr < (LENGTH-1)) begin + sum_result <= sum_result + data_in_unpacked[cur_ptr]; + cur_ptr <= cur_ptr + 'b1; + sum_in_progress <= 1'b1; diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..b34216beeb0f077fac35364acfeac0bbba444567 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/metadata.json @@ -0,0 +1,18 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/adder.sv" + ], + "bug_description": "Removed 'sum_en &' enable condition from the sequential sum (SUM_METHOD==1) accumulation branch \u2014 sum_result and cur_ptr now advance whenever cur_ptr < (LENGTH-1) regardless of whether sum_en is asserted", + "signals_affected": [ + "sum_result", + "cur_ptr", + "sum_in_progress" + ], + "simulation_status": "sim_ok", + "problem_statement": "During sequential sum operation verification, the op_done signal fails to assert at t=132000 when completion is expected, remaining at 0. The data_out output is stuck at all zeros throughout the test sequence. Most critically, the sum_result and cur_ptr counters advance unconditionally rather than only when sum_en is asserted, causing the accumulation loop to progress regardless of control inputs. The sum_in_progress flag does not behave as specified, and the operation fails to complete or hand off control as intended.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..f618d27d761d2493ae351ea2a181246564841b5f --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_enable/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_bthl_k8b/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_bthl_k8b/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_bthl_k8b/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_bthl_k8b/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_bthl_k8b/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..d3135602e98744ea44be3e7829d3c20660904974 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..d174af9867e6abfbc9762803901865d4a037a36b --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/diff.patch @@ -0,0 +1,25 @@ +--- a/List/src/adder.sv ++++ b/List/src/adder.sv +@@ -60,9 +60,9 @@ + sum_in_progress = 1'b0; + end + end else if(SUM_METHOD == 1) begin //: sequential sum ( ++ initial sum_result = {(LENGTH_WIDTH+DATA_WIDTH){1'bx}}; + always @(posedge clk, posedge rst) begin + if(rst) begin +- sum_result <= 'd0; + cur_ptr <= 'b0; + sum_done <= 1'b0; + sum_in_progress <= 1'b0; +@@ -109,10 +109,10 @@ + end + end + ++ initial sum_result = {(LENGTH_WIDTH+DATA_WIDTH){1'bx}}; + always @ (posedge clk, posedge rst) begin + if(rst) begin + stg_ptr <= 'b0; +- sum_result <= 'd0; + sum_done <= 1'b0; + sum_in_progress <= 1'b0; + end else if(!sum_en) begin diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..6fdbd7e5cb3612e7918cc1a8ddcdfe730fe10969 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/adder.sv" + ], + "bug_description": "Removed synchronous reset for 'sum_result' register in both sequential (SUM_METHOD==1) and adder tree (SUM_METHOD==2) always blocks; added initial blocks setting sum_result to x to make the missing reset observable in simulation", + "signals_affected": [ + "sum_result" + ], + "simulation_status": "sim_ok", + "problem_statement": "During simulation of the arithmetic unit, `data_out` is stuck at all zeros (00000000000) from the start of operation, and `op_done` fails to pulse at t=132000 when the operation should complete. The output remains incorrect regardless of input values, and the completion signal never asserts, blocking downstream logic from processing the results. This suggests the accumulator is not properly initialized or clearing its state between operations, or the operation completion detection is broken. The issue occurs consistently across different test vectors.", + "diff_summary": "6 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..28d2ba0107ddefd1ecafa61189572bb40a347f32 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/missing_reset/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_bqr0telh/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_bqr0telh/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_bqr0telh/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_bqr0telh/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_bqr0telh/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..957b20c52cd92a2a18363ef2e6f9b642621a11b9 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/diff.patch b/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..907d85d6424274727f44847a1fc558e44990a582 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/adder.sv ++++ b/List/src/adder.sv +@@ -119,7 +119,7 @@ + stg_ptr <= 'b0; + sum_done <= 1'b0; + sum_in_progress <= 1'b0; +- end else if(sum_en & stg_ptr < (NO_OF_STAGE-1)) begin ++ end else if(sum_en & stg_ptr <= (NO_OF_STAGE-1)) begin + stg_ptr <= stg_ptr + 'b1; + sum_in_progress <= 1'b1; + end else if(sum_en & !sum_done & stg_ptr == (NO_OF_STAGE-1)) begin //last stage diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/metadata.json b/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..362a2e0fa7f98ae68a03167cbde92bac63c4ba09 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "off_by_one_counter", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/adder.sv" + ], + "bug_description": "Changed 'stg_ptr < (NO_OF_STAGE-1)' to 'stg_ptr <= (NO_OF_STAGE-1)' in the adder tree stg_ptr increment condition \u2014 the stage pointer now increments one extra cycle, causing it to skip the final sum_done assignment condition and never assert sum_done", + "signals_affected": [ + "stg_ptr" + ], + "simulation_status": "sim_ok", + "problem_statement": "The adder tree pipeline appears to stall during execution. After providing input operands and allowing the simulation to run for multiple cycles, the output signal `data_out` remains stuck at 00000000000 instead of reflecting the accumulated sum, and the completion signal `op_done` never asserts. Even after 132000 cycles\u2014well beyond the expected latency for a pipelined adder tree of this depth\u2014the pipeline fails to produce either a valid result or a completion indication. This suggests the stage advancement logic may not be correctly progressing through all pipeline stages, preventing both the final sum computation and the completion handshake from occurring.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..596d95dd7e98c284136f782b58b432e8e45d64e7 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/off_by_one_counter/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_p1r53r3j/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_p1r53r3j/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_p1r53r3j/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_p1r53r3j/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_p1r53r3j/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..57c58524426a36949094f49ed5e86cb999e7a493 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..20043d0c4c10d82631bec029bcde1a44edf9e6ba --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/adder.sv ++++ b/List/src/adder.sv +@@ -33,7 +33,7 @@ + reg [DATA_WIDTH-1:0] data_in_unpacked [LENGTH-1:0]; + reg [LENGTH_WIDTH-1:0] cur_ptr; + reg [STG_PTR_WIDTH-1:0] stg_ptr; +- reg [DATA_WIDTH-1:0] output_stage [NO_OF_STAGE-1:0][TOTAL_INPUT_INT-1:0]; ++ reg [DATA_WIDTH-3:0] output_stage [NO_OF_STAGE-1:0][TOTAL_INPUT_INT-1:0]; + integer i,j; + + // icarus does not support stream unpacking, so we need to do it mannually diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..225b75842fca5cd7a9365710c09d3d18c61098c7 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "wrong_bitwidth", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/adder.sv" + ], + "bug_description": "Truncated 'output_stage' register from [DATA_WIDTH-1:0] to [DATA_WIDTH-3:0], reducing each adder tree node by 2 bits so upper bits are silently lost during accumulation", + "signals_affected": [ + "output_stage" + ], + "simulation_status": "sim_ok", + "problem_statement": "When running the accumulator testbench, the `data_out` signal remains all zeros throughout simulation, and the `op_done` signal fails to assert at t=132000 as expected, remaining stuck low. This occurs even with valid inputs being processed through the adder tree. Inspection of intermediate accumulation results suggests that computed sums are not being properly captured or propagated to the final output stage. The silent loss of upper bits during multi-cycle accumulation appears to be corrupting the running total, resulting in incorrect final values that fail to trigger completion logic. This needs investigation into the output path and register width assumptions.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..f1dfd7faf70b30ea0c1d66d53b07a8e8dfc7503b --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_m6721rp8/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_m6721rp8/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_m6721rp8/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_m6721rp8/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_m6721rp8/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__adder/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/list__adder/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..ca37f89a97beb30a065ba30c26b4cd9d33d80740 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__adder/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__adder/sim.sh b/Weiyet_RTLStructLib/candidates/list__adder/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..0bd110a6da0e370dffde372afcfe284801f742b8 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__adder/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_list "$SRCDIR/List/src/list.sv" "$SRCDIR/List/src/sorter.sv" "$SRCDIR/List/src/adder.sv" "$SRCDIR/List/tb/sv/tb.sv" +vvp /tmp/sim_list -fst +VCDFILE=List/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..a5b38222ec372079415e8a386e7eb75e340ea775 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/diff.patch b/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..e5ba0f49f46a6d4b37e64d00ac3b435bbe5fb5b3 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/list.sv ++++ b/List/src/list.sv +@@ -179,7 +179,7 @@ + op_error <= 1'b1; + end else begin + current_state <= ACCESS_DONE; +- data_out <= {{LENGTH_WIDTH{1'b0}},data_stored[index_in]}; ++ data_out <= {data_stored[index_in],{LENGTH_WIDTH{1'b0}}}; + op_done <= 1'b1; + op_error <= 1'b0; + end diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/metadata.json b/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..b92f017a4c4dd805b168a28943a2bf8b4b532cf8 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "concat_swap", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/list.sv" + ], + "bug_description": "Reordered concatenation {{LENGTH_WIDTH{1'b0}}, data_stored[index_in]} to {data_stored[index_in], {LENGTH_WIDTH{1'b0}}} in the read operation \u2014 the data bits are now placed in the upper positions and the zero-padding in the lower positions of data_out, causing incorrect read values", + "signals_affected": [ + "data_out" + ], + "simulation_status": "sim_ok", + "problem_statement": "During read operations from the memory module, `data_out` consistently returns incorrect values with the actual data bits shifted to unexpected bit positions. For example, after initiating a read of previously stored data, the output appears with the data content in the upper bit positions and zeros in the lower positions, which does not match the stored value or the expected output format. Additionally, the `op_done` signal fails to assert at t=132000 as expected after the read operation completes, indicating a potential issue with either the data alignment or the completion signaling logic. This behavior suggests that the concatenation or data routing in the read path may not be correctly ordering the output bits according to the specification.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..c3426ba71e0adeb6d74669774d6dcee3fff9e72d --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/concat_swap/sim_log.txt @@ -0,0 +1,95 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:137: 493000 Data read: 1168, Data Exp: 146 + Time: 493000 Scope: tb.read + +517000 OP_Read at index 1 +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:137: 565000 Data read: 512, Data Exp: 64 + Time: 565000 Scope: tb.read + +589000 OP_Read at index 2 +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:137: 637000 Data read: 1168, Data Exp: 146 + Time: 637000 Scope: tb.read + +661000 OP_Read at index 3 +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:137: 709000 Data read: 32, Data Exp: 4 + Time: 709000 Scope: tb.read + +733000 OP_Read at index 4 +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:137: 781000 Data read: 32, Data Exp: 4 + Time: 781000 Scope: tb.read + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 1453000 Data read: 32, Data Exp: 4 + Time: 1453000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 1500000 Data read: 32, Data Exp: 4 + Time: 1500000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 1548000 Data read: 512, Data Exp: 64 + Time: 1548000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 1596000 Data read: 1168, Data Exp: 146 + Time: 1596000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 1644000 Data read: 1168, Data Exp: 146 + Time: 1644000 Scope: tb.read_n_burst + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 2197000 Data read: 1168, Data Exp: 146 + Time: 2197000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 2244000 Data read: 1168, Data Exp: 146 + Time: 2244000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 2292000 Data read: 512, Data Exp: 64 + Time: 2292000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 2340000 Data read: 32, Data Exp: 4 + Time: 2340000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:177: 2388000 Data read: 32, Data Exp: 4 + Time: 2388000 Scope: tb.read_n_burst + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST FAILED +Error count = 15 + + +--- STDERR --- +/tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_k9omo67h/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..f94b1790b6318a6a2a514fdee1f0a392d26ca8ac Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..a83d941a5cb083114b9f4b33d2067c3f1aeec55b --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/list.sv ++++ b/List/src/list.sv +@@ -255,7 +255,7 @@ + end + end + SEARCH_1ST: begin +- if(data_stored[cur_ptr] == data_in) begin ++ if(data_stored[cur_ptr] != data_in) begin + current_state <= ACCESS_DONE; + data_out <= {{DATA_WIDTH{1'b0}},cur_ptr}; + op_done <= 1'b1; diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..963362f45266c6c761cef972b0951f57d89a7f27 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/metadata.json @@ -0,0 +1,18 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/list.sv" + ], + "bug_description": "Inverted 'data_stored[cur_ptr] == data_in' condition in SEARCH_1ST state \u2014 module now reports a match when data does NOT equal the search target, causing incorrect search results", + "signals_affected": [ + "data_stored", + "cur_ptr", + "data_in" + ], + "simulation_status": "sim_ok", + "problem_statement": "The search module fails to correctly identify matching data elements. When performing a search operation through the data array, the module does not report a match when the stored data at the current pointer matches the search input value. This causes `op_done` to remain asserted low indefinitely (observed at t=132000), while `data_out` remains stuck at zero instead of returning the expected match result. The module appears to be exhibiting inverted match detection logic\u2014either failing to recognize valid matches or incorrectly flagging mismatches. This prevents proper completion of search operations and causes downstream logic to stall waiting for the operation completion signal.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..8638c281bb03b4980d7708ec93958f13b937eaa1 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,81 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +ERROR: /tmp/sim4_simsh_zce2qkts/source/List/tb/sv/tb.sv:366: 2532000 First index of value 146 is 2, Expected: 0 + Time: 2532000 Scope: tb.find_1st_index + +2557000 OP_Find_all_index for value 64 +2677000 Value 64 is found at index 2 + +3701000 TEST FAILED +Error count = 1 + + +--- STDERR --- +/tmp/sim4_simsh_zce2qkts/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_zce2qkts/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_zce2qkts/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_zce2qkts/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_zce2qkts/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..018e3da29248b11ce80c9edc634280c6f2621f04 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..fcfeb1ed85d9f2249ff325449c0a637d3b84f208 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/diff.patch @@ -0,0 +1,23 @@ +--- a/List/src/list.sv ++++ b/List/src/list.sv +@@ -239,19 +239,10 @@ + op_done <= 1'b1; + op_error <= 1'b0; + end +- end else if(op_en) begin // OP selected is not available : OP_ERROR ++ end else begin // OP selected is not available : OP_ERROR + current_state <= ACCESS_DONE; + op_done <= 1'b1; + op_error <= 1'b0; +- end else begin +- current_state <= IDLE; +- op_done <= 1'b0; +- op_error <= 1'b0; +- op_in_progress <= 1'b0; +- sum_en <= 1'b0; +- sort_en <= 1'b0; +- found <= 1'b0; +- cur_ptr <= 'b0; + end + end + SEARCH_1ST: begin diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..cd9d84d8361a2f67cf7d86d0acfdf40dc4e40db1 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/metadata.json @@ -0,0 +1,18 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/list.sv" + ], + "bug_description": "Removed 'op_en' enable condition from IDLE state \u2014 the final else-if(op_en) branch that gated the error response now runs unconditionally as a plain else, causing op_done and op_error to be asserted on every idle cycle when no valid op is selected, even without op_en being high", + "signals_affected": [ + "op_done", + "op_error", + "current_state" + ], + "simulation_status": "sim_ok", + "problem_statement": "During verification, operation completion signal `op_done` is unexpectedly asserted at t=108000 when the state machine is in IDLE with no operation selected. Additionally, output data signal `data_out` remains at all zeros throughout the simulation, failing to capture any valid operation results. The `op_done` signal continues to assert on subsequent idle cycles regardless of the `op_en` enable condition, violating the expected behavior where completion should only occur for enabled, valid operations. These spurious completion assertions are breaking transaction protocols and preventing correct data flow through the design.", + "diff_summary": "13 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..33e8e32d9a61b01e0ec0bbc1ad38a9dc844b5431 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_enable/sim_log.txt @@ -0,0 +1,81 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +181000 OP_Insert at index 1, value 64 +146 64 + +277000 OP_Insert at index 2, value 4 +146 64 4 + +373000 OP_Insert at index 3, value 4 +146 64 4 4 + +469000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +565000 OP_Read at index 0 +636000 Data read: 146 + +661000 OP_Read at index 1 +732000 Data read: 64 + +757000 OP_Read at index 2 +828000 Data read: 146 + +853000 OP_Read at index 3 +924000 Data read: 4 + +949000 OP_Read at index 4 +1020000 Data read: 4 + +1045000 OP_Read at index 5 +1116000 Data read out of bound, fault flag is asserted correctly + +1141000 OP_Sum Request +1212000 Sum: 364 + +1237000 OP_Sort_Asc Request +1692000 OP_Sort_Asc Complete +1692000 OP_Sort_Asc Complete +1692000 OP_Sort_Asc Complete +1692000 OP_Sort_Asc Complete +4 4 64 146 146 + +1717000 OP_Read burst 5 time +1788000 Data read: 4 +1836000 Data read: 4 +1884000 Data read: 64 +1932000 Data read: 146 +1980000 Data read: 146 + +2005000 OP_Sort_Des Request +2484000 OP_Sort_Des Complete +146 146 64 4 4 + +2509000 OP_Read burst 5 time +2580000 Data read: 146 +2628000 Data read: 146 +2676000 Data read: 64 +2724000 Data read: 4 +2772000 Data read: 4 + +2797000 OP_Find_1st_index for value 146 +2892000 First index of value 146 is 0 + +2917000 OP_Find_all_index for value 64 +ERROR: /tmp/sim4_simsh_bcpww9dc/source/List/tb/sv/tb.sv:417: 2965000 OP_Find_all_index All index is not found yet, but op_in_progress is deasserted incorrectly + Time: 2965000 Scope: tb.find_all_index + +3989000 TEST FAILED +Error count = 1 + + +--- STDERR --- +/tmp/sim4_simsh_bcpww9dc/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_bcpww9dc/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_bcpww9dc/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_bcpww9dc/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_bcpww9dc/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..94b49a2913f496a772af2dfa855a9382abf4487e Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..1e7ff142dafeeda36a76787b01719562ee28a712 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/diff.patch @@ -0,0 +1,19 @@ +--- a/List/src/list.sv ++++ b/List/src/list.sv +@@ -69,6 +69,8 @@ + reg [DATA_WIDTH-1:0] data_sorted [LENGTH-1:0]; + + integer i; ++ ++ initial data_out = 'hx; + + assign op_is_read = (op_sel == 3'b000) & op_en; + assign op_is_insert = (op_sel == 3'b001) & op_en; +@@ -134,7 +136,6 @@ + op_done <= 1'b0; + op_in_progress <= 1'b0; + op_error <= 1'b0; +- data_out <= 'd0; + cur_ptr <= 'b0; + found <= 1'b0; + data_count <= {(LENGTH_WIDTH){1'b0}}; diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..b7bc1b898b3604a35896290b57a58f30e63ea0c6 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/list.sv" + ], + "bug_description": "Removed synchronous reset for 'data_out' register; added initial block setting it to 'hx to make the missing reset observable in simulation", + "signals_affected": [ + "data_out" + ], + "simulation_status": "sim_ok", + "problem_statement": "The `data_out` register initializes to unknown values (X) at t=0 instead of the expected reset state, indicating it is not being properly initialized during simulation startup. This undefined initialization propagates through the design, causing the `op_done` output signal to remain stuck at 0 when it should transition during normal operation (expected transition around t=132000). The data path appears unable to clear and establish valid state after a system reset, preventing correct operation of the data output and completion signaling. Verification tests expecting valid data on `data_out` after reset fail with unexpected X values.", + "diff_summary": "5 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..30c0172fefcf20b208950ee23ac19d47ca868ddb --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/missing_reset/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_in5i7fkm/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_in5i7fkm/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_in5i7fkm/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_in5i7fkm/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_in5i7fkm/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..7b284a2db1b3684430cd33ec351e3c9d37da8945 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/diff.patch b/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..ac4506da92d9bf25d1ab5e4716dd77d74143b62c --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/list.sv ++++ b/List/src/list.sv +@@ -261,7 +261,7 @@ + op_done <= 1'b1; + op_in_progress <= 1'b0; + op_error <= 1'b0; +- end else if(cur_ptr == (data_count-1)) begin ++ end else if(cur_ptr == data_count) begin + current_state <= ACCESS_DONE; + op_done <= 1'b1; + op_error <= 1'b1; diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/metadata.json b/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..cda1b94acbee2ff918bfbb8585668da2bee66eac --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "off_by_one_counter", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/list.sv" + ], + "bug_description": "Changed 'cur_ptr == (data_count-1)' to 'cur_ptr == data_count' in SEARCH_1ST state \u2014 the not-found condition now triggers one iteration too late, causing the search to run one cycle too long before reporting an error", + "signals_affected": [ + "cur_ptr", + "data_count" + ], + "simulation_status": "sim_ok", + "problem_statement": "The search operation is not completing as expected. Signal `op_done` remains at 0 until well after the search should have terminated\u2014at t=132000, `op_done` is still low despite the search having iterated through all data elements. The counter `cur_ptr` and `data_count` comparison logic appears to be off by one cycle, causing the not-found condition to trigger one iteration later than specified. This delays the assertion of `op_done` by one clock cycle, breaking the expected timing of search completion. Additionally, `data_out` remains at all zeros from the start when it should reflect the search results or error state. The search state machine needs to be examined for boundary condition errors in the element-not-found detection logic.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..e8e2d5c96712b91a5f4e3ac6a2ed6260b650b16f --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/off_by_one_counter/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_uaenxabq/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_uaenxabq/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_uaenxabq/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_uaenxabq/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_uaenxabq/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..dabdc12880701cb0ba2639cdbfe6c7175b2b5ae1 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/diff.patch b/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..878b869af2d53cfef0ca5ab1f4bf397fbc6a9f82 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/list.sv ++++ b/List/src/list.sv +@@ -303,7 +303,7 @@ + sort_en <= 1'b0; + end + SUM: if(sum_done) begin +- current_state <= ACCESS_DONE; ++ current_state <= IDLE; + data_out <= sum_result; + op_done <= 1'b1; + op_in_progress <= 1'b0; diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/metadata.json b/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..79f25437ac31be25c6d91c90067b17a351ecd789 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "state_transition", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/list.sv" + ], + "bug_description": "Changed SUM\u2192ACCESS_DONE transition to SUM\u2192IDLE \u2014 when sequential/adder-tree sum completes, the FSM skips ACCESS_DONE and goes directly to IDLE, causing op_done and sum results to be cleared one cycle early without the proper ACCESS_DONE handshake", + "signals_affected": [ + "current_state" + ], + "simulation_status": "sim_ok", + "problem_statement": "The sequential adder sum operation completes, but `op_done` fails to assert at the expected time (t=132000), and the sum results in `data_out` are not available as specified by the protocol. The FSM appears to be bypassing the ACCESS_DONE handshake state when returning from SUM, causing the result buffer to be cleared before the processor has a chance to latch the output. Expected behavior: once the sum computation finishes, the FSM should enter an ACCESS_DONE state where `op_done` is asserted for at least one cycle and `data_out` holds the result, allowing downstream logic to capture the value. Instead, the operation appears to complete prematurely with `op_done=0` and `data_out` remaining at 00000000000, indicating the results were invalidated before being properly exposed to the output interface.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..b6dd0d6eed3e03cadaa886d720f8a8e25f7d3a2e --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/state_transition/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_ykzqgfz_/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_ykzqgfz_/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_ykzqgfz_/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_ykzqgfz_/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_ykzqgfz_/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..4a098d42e61585ac75d2bd85221f8d76c09850bb Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/diff.patch b/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..ed35a1f5f3b842296ef5343fc740e52005d19735 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/list.sv ++++ b/List/src/list.sv +@@ -114,7 +114,7 @@ + .sort_order(sort_order), + .sort_done(sort_done), + .sort_in_progress(sort_in_progress), +- .data_sorted(data_sorted_packed)); ++ .data_sorted()); + + // icarus does not support streaming unpacking, so we need to do it manually + // always @ (*) begin diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/metadata.json b/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..305924a1711af6aae3cbedde91f84d3d44daca80 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "unconnected_port", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/list.sv" + ], + "bug_description": "Disconnected 'data_sorted' output port of u_sorter instantiation \u2014 'data_sorted_packed' wire is now floating/undriven", + "signals_affected": [ + "data_sorted_packed" + ], + "simulation_status": "sim_ok", + "problem_statement": "The sorter module is failing to produce valid output in simulation. The `data_out` signal remains at all zeros (00000000000) from the start of simulation, and the `op_done` signal fails to assert at the expected completion time (t=132000), instead remaining low. This indicates the sorter is not processing data or signaling completion as specified. The sorted data should be driven to `data_out` after the sorting operation completes, but instead we observe constant zero values and no completion handshake. Verification tests that depend on valid sorted output and the `op_done` handshake are failing as a result. This appears to be a fundamental connectivity or initialization issue within the sorter instantiation that is preventing normal operation.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..f507222a75112611edfaab0d3656fe0cff7f57bd --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/unconnected_port/sim_log.txt @@ -0,0 +1,70 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +ERROR: /tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:177: 1453000 Data read: X, Data Exp: 4 + Time: 1453000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:177: 1500000 Data read: X, Data Exp: 4 + Time: 1500000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:177: 1548000 Data read: X, Data Exp: 64 + Time: 1548000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:177: 1596000 Data read: X, Data Exp: 146 + Time: 1596000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:177: 1644000 Data read: X, Data Exp: 146 + Time: 1644000 Scope: tb.read_n_burst + +1669000 OP_Sort_Des Request + +500000000 TEST FAILED +SIM TIMEOUT! + + +--- STDERR --- +/tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_o1duybti/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..41bac3530e23d3489b1895afa0e1e01f4ad026f9 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..fe781461807fe6510bdd4428f6d3e88f5fbed4f0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/list.sv ++++ b/List/src/list.sv +@@ -44,7 +44,7 @@ + reg [DATA_WIDTH*LENGTH-1:0] data_stored_packed; + reg [DATA_WIDTH*LENGTH-1:0] data_sorted_packed; + reg [DATA_WIDTH-1:0] data_sorted_unpacked [LENGTH-1:0]; // could implement with RAM for large size of data +- reg [LENGTH_WIDTH-1:0] cur_ptr; ++ reg [LENGTH_WIDTH-3:0] cur_ptr; + reg [2:0] current_state; + reg found; + reg last_key_done; diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..9e65c96f394eb9a625d1af24deb298951fef9bbe --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "wrong_bitwidth", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/list.sv" + ], + "bug_description": "Truncated 'cur_ptr' register from LENGTH_WIDTH bits to LENGTH_WIDTH-2 bits, causing index truncation during search operations", + "signals_affected": [ + "cur_ptr" + ], + "simulation_status": "sim_ok", + "problem_statement": "The `data_out` signal remains at all zeros throughout the simulation, and `op_done` fails to assert at t=132000 where it should complete a search operation. The search operation appears to stall, unable to locate the expected data. Investigation shows that `cur_ptr` cannot properly index through the full address space during the search sequence, resulting in the operation timing out without returning valid results. The issue is reproducible when performing searches that require the pointer to reach addresses beyond a certain range. Without proper pointer width, the design loses address information and cannot complete search operations that depend on accessing the full memory space.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..f64a3e8d3c5366cc6fbf4156d8ec357945807a2c --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 + +500000000 TEST FAILED +SIM TIMEOUT! + + +--- STDERR --- +/tmp/sim4_simsh_uh6eh6bj/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_uh6eh6bj/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_uh6eh6bj/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_uh6eh6bj/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_uh6eh6bj/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__list/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/list__list/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..ca37f89a97beb30a065ba30c26b4cd9d33d80740 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__list/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__list/sim.sh b/Weiyet_RTLStructLib/candidates/list__list/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..0bd110a6da0e370dffde372afcfe284801f742b8 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__list/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_list "$SRCDIR/List/src/list.sv" "$SRCDIR/List/src/sorter.sv" "$SRCDIR/List/src/adder.sv" "$SRCDIR/List/tb/sv/tb.sv" +vvp /tmp/sim_list -fst +VCDFILE=List/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..75a7210e23b0d28f7c182e70730f0e902f1fd74e Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..22643ba8c2bb185147492f404fc8785063c14379 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/sorter.sv ++++ b/List/src/sorter.sv +@@ -95,7 +95,7 @@ + end + + NEXT_KEY: begin +- if(key_ptr < (len-1)) begin ++ if(key_ptr >= (len-1)) begin + key_ptr <= key_ptr + 1; + temp <= data_in_unpacked[key_ptr + 1]; + cur_ptr <= key_ptr + 1 - 'd1; diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..8c71ebc130fe9e2592c6c056cacce4be8a53183b --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/sorter.sv" + ], + "bug_description": "Inverted 'key_ptr < (len-1)' condition in NEXT_KEY state \u2014 sort now terminates early and continues iterating past the boundary, swapping the done/continue branches", + "signals_affected": [ + "key_ptr", + "len" + ], + "simulation_status": "sim_ok", + "problem_statement": "The sorting operation fails to complete correctly. The `op_done` signal never asserts high (remains 0 at t=132000), indicating the module does not signal completion of the sort operation. Additionally, `data_out` remains stuck at all zeros (00000000000 at t=0) instead of returning the sorted result. The `key_ptr` appears to either terminate prematurely or continue iterating beyond the valid boundary, preventing proper traversal of the data during the NEXT_KEY state. This suggests a logic error in the boundary condition that controls iteration through the data array, causing the sort algorithm to exit in an invalid state without producing output.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..58b3348788c8f11031bd2107685d9eaeb3927f8e --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,88 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1068000 OP_Sort_Asc Complete +1068000 OP_Sort_Asc Complete +1068000 OP_Sort_Asc Complete +1068000 OP_Sort_Asc Complete +4 4 64 146 146 + +1093000 OP_Read burst 5 time +ERROR: /tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:177: 1141000 Data read: 146, Data Exp: 4 + Time: 1141000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:177: 1188000 Data read: 64, Data Exp: 4 + Time: 1188000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:177: 1236000 Data read: 146, Data Exp: 64 + Time: 1236000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:177: 1284000 Data read: 4, Data Exp: 146 + Time: 1284000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:177: 1332000 Data read: 4, Data Exp: 146 + Time: 1332000 Scope: tb.read_n_burst + +1357000 OP_Sort_Des Request +1476000 OP_Sort_Des Complete +146 146 64 4 4 + +1501000 OP_Read burst 5 time +1549000 Data read: 146 +ERROR: /tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:177: 1596000 Data read: 64, Data Exp: 146 + Time: 1596000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:177: 1644000 Data read: 146, Data Exp: 64 + Time: 1644000 Scope: tb.read_n_burst +1692000 Data read: 4 +1740000 Data read: 4 + +1765000 OP_Find_1st_index for value 146 +1836000 First index of value 146 is 0 + +1861000 OP_Find_all_index for value 64 +ERROR: /tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:411: 1957000 Value 64 should be found at index 2 but index 1 is reported by DUT + Time: 1957000 Scope: tb.find_all_index + +2981000 TEST FAILED +Error count = 8 + + +--- STDERR --- +/tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_9nd_ocis/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..9db0145c3d074f2c64bd58f212eeb04e75fc88c2 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..7af85c49a030ac38a5507e456ad7f05624b1a07c --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/diff.patch @@ -0,0 +1,35 @@ +--- a/List/src/sorter.sv ++++ b/List/src/sorter.sv +@@ -76,22 +76,17 @@ + end else begin + case(current_state) + IDLE:begin +- if(sort_en) begin +- current_state <= NEXT_KEY; +- key_ptr <= 'd0; +- cur_ptr <= 'd0; +- // icarus does not support direct assignment of 2d array.... +- //data_sorted_unpacked <= data_in_unpacked; +- for (i = 0; i < LENGTH; i = i + 1) begin +- data_sorted_unpacked[i] <= data_in_unpacked[i]; +- end +- // icarus does not support direct assignment of 2d array.... +- sort_in_progress <= 1'b1; +- sort_done <= 1'b0; +- end else begin +- sort_in_progress <= 1'b0; +- sort_done <= 1'b0; ++ current_state <= NEXT_KEY; ++ key_ptr <= 'd0; ++ cur_ptr <= 'd0; ++ // icarus does not support direct assignment of 2d array.... ++ //data_sorted_unpacked <= data_in_unpacked; ++ for (i = 0; i < LENGTH; i = i + 1) begin ++ data_sorted_unpacked[i] <= data_in_unpacked[i]; + end ++ // icarus does not support direct assignment of 2d array.... ++ sort_in_progress <= 1'b1; ++ sort_done <= 1'b0; + end + + NEXT_KEY: begin diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..262e9870c6da71948c390b7dd5968c8a913a6dd9 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/metadata.json @@ -0,0 +1,21 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/sorter.sv" + ], + "bug_description": "Removed 'sort_en' enable condition from the IDLE state in the sequential block \u2014 the sorter now begins sorting unconditionally on every clock cycle when in IDLE state, ignoring the sort_en signal", + "signals_affected": [ + "current_state", + "key_ptr", + "cur_ptr", + "data_sorted_unpacked", + "sort_in_progress", + "sort_done" + ], + "simulation_status": "sim_ok", + "problem_statement": "During verification, the sorter module is observed to begin operation unconditionally on every clock cycle when in the IDLE state, regardless of the sort_en signal's state. The `data_out` signal remains at 0 from the beginning of simulation (t=0), and the `op_done` signal fails to transition to 1 at t=132000 as expected upon completion of the sort operation. The internal state machine correctly transitions through `current_state` and the pointer signals (`key_ptr`, `cur_ptr`) are updating, but sorting appears to be proceeding without the sort_en enable signal being asserted. This suggests the sorter is not respecting the enable control, resulting in corrupted output data and an inability to signal operation completion. The `sort_in_progress` and `sort_done` flags are not behaving as expected in response to the sort_en control signal.", + "diff_summary": "27 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..da0e08e5aab8a7c5a77583921bc5c223e5b70464 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_enable/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1332000 OP_Sort_Asc Complete +1332000 OP_Sort_Asc Complete +1332000 OP_Sort_Asc Complete +1332000 OP_Sort_Asc Complete +4 4 64 146 146 + +1357000 OP_Read burst 5 time +1405000 Data read: 4 +1452000 Data read: 4 +1500000 Data read: 64 +1548000 Data read: 146 +1596000 Data read: 146 + +1621000 OP_Sort_Des Request +2004000 OP_Sort_Des Complete +146 146 64 4 4 + +2029000 OP_Read burst 5 time +2077000 Data read: 146 +2124000 Data read: 146 +2172000 Data read: 64 +2220000 Data read: 4 +2268000 Data read: 4 + +2293000 OP_Find_1st_index for value 146 +2364000 First index of value 146 is 0 + +2389000 OP_Find_all_index for value 64 +2509000 Value 64 is found at index 2 + +3533000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_dyn84_zt/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_dyn84_zt/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_dyn84_zt/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_dyn84_zt/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_dyn84_zt/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..04b55163d3068fd9906816b462c101cabf071bbb Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..70591abbf57d254fbd55f8cf3b536da55daf36ed --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/diff.patch @@ -0,0 +1,10 @@ +--- a/List/src/sorter.sv ++++ b/List/src/sorter.sv +@@ -41,6 +41,7 @@ + reg [DATA_WIDTH-1:0] temp; + reg [2:0] current_state; + ++ initial temp = {DATA_WIDTH{1'bx}}; + + // icarus does not support stream unpacking, so we need to do it manually + // always @ (*) begin diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..606ef28c6e4bbb8b2d1f7b651ce7ac379c2a3242 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/sorter.sv" + ], + "bug_description": "Removed reset initialization for the 'temp' register in the sorter module by omitting it from the reset branch and adding an initial block that sets it to unknown (x)", + "signals_affected": [ + "temp" + ], + "simulation_status": "sim_ok", + "problem_statement": "The sorter module is failing to complete sort operations correctly. In simulation, `data_out` initializes to all zeros (00000000000) at t=0, and the `op_done` signal never asserts\u2014it remains 0 even at t=132000 when the operation should have completed. This suggests the sorter's internal state is not being properly initialized, causing the pipeline to enter an invalid state and preventing the operation from progressing to completion. Verification against the sorter specification expects `op_done` to pulse high once sorting is finished, but the module appears to hang indefinitely with corrupt or uninitialized data on the output bus.", + "diff_summary": "3 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..1042bd16310d54f0e2bddcd932c3c00ba2c39e7a --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/missing_reset/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_x5f9r2d2/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_x5f9r2d2/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_x5f9r2d2/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_x5f9r2d2/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_x5f9r2d2/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..2ab1c6dcb2917711c0d8e34e8ae36bffee39d08c Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/diff.patch b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..8f3d765549abe6e5b231e35cde95afc1d1381fe9 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/sorter.sv ++++ b/List/src/sorter.sv +@@ -101,7 +101,7 @@ + cur_ptr <= key_ptr + 1 - 'd1; + current_state <= COMP_AND_SWAP; + end else begin +- current_state <= SORT_DONE; ++ current_state <= IDLE; + // icarus does not support direct assignment of 2d array.... + //data_sorted_unpacked <= data_sorted_unpacked; + for (i = 0; i < LENGTH; i = i + 1) begin diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/metadata.json b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..c277f8ca0769098f2fe058799c6d8aef2ad51d9c --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "state_transition", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/sorter.sv" + ], + "bug_description": "Changed NEXT_KEY\u2192SORT_DONE transition to NEXT_KEY\u2192IDLE \u2014 when sorting completes (key_ptr reaches end), the FSM skips the SORT_DONE state and goes directly to IDLE, causing sort_done to be asserted for only one cycle before immediately being cleared in IDLE on the next cycle, which may cause the parent module to miss the sort_done signal", + "signals_affected": [ + "current_state", + "sort_done" + ], + "simulation_status": "sim_ok", + "problem_statement": "After the sorter completes processing the final key and reaches the end of the key pointer, the op_done signal asserts high for only a single cycle at t=132000ns before immediately clearing to low. This brief pulse prevents the parent module from reliably detecting the sort completion, as it expects either op_done to remain asserted until acknowledged or to be held long enough for synchronous capture. The current_state signal appears to skip the expected completion acknowledgment state when transitioning at the end of sorting, causing op_done to be de-asserted on the very next clock cycle. This one-cycle assertion window makes the signal susceptible to being missed by edge-triggered or level-sensitive capture logic in downstream modules, causing sort operations to appear incomplete even though the data has finished being sorted.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..a78689dec962ebbc57e699fa3b70512412ee02a3 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/state_transition/sim_log.txt @@ -0,0 +1,79 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +1453000 Data read: 4 +1500000 Data read: 4 +1548000 Data read: 64 +1596000 Data read: 146 +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +2197000 Data read: 146 +2244000 Data read: 146 +2292000 Data read: 64 +2340000 Data read: 4 +2388000 Data read: 4 + +2413000 OP_Find_1st_index for value 146 +2484000 First index of value 146 is 0 + +2509000 OP_Find_all_index for value 64 +2629000 Value 64 is found at index 2 + +3653000 TEST PASSED + + +--- STDERR --- +/tmp/sim4_simsh_53tcr7ls/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_53tcr7ls/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_53tcr7ls/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_53tcr7ls/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_53tcr7ls/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..0a55d5fc82bb6afb3458f94c82132a19279467a0 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..1912f2242e1958cb255f428e8a9e594ca96822cc --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/List/src/sorter.sv ++++ b/List/src/sorter.sv +@@ -38,7 +38,7 @@ + reg [DATA_WIDTH-1:0] data_in_unpacked [LENGTH-1:0]; + reg [LENGTH_WIDTH-1:0] key_ptr; + reg [LENGTH_WIDTH-1:0] cur_ptr; +- reg [DATA_WIDTH-1:0] temp; ++ reg [DATA_WIDTH-3:0] temp; + reg [2:0] current_state; + + diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..52d27f9d46f825b3b13a2a2253a28298cce8a9ba --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "wrong_bitwidth", + "task_type": "behavioral_bug", + "files_modified": [ + "List/src/sorter.sv" + ], + "bug_description": "Truncated 'temp' register from DATA_WIDTH bits to DATA_WIDTH-2 bits, causing upper 2 bits of comparison keys to be lost during insertion sort swaps", + "signals_affected": [ + "temp" + ], + "simulation_status": "sim_ok", + "problem_statement": "During insertion sort operation verification, the op_done signal fails to assert even after 132 \u00b5s, indicating the sorting operation stalls and never completes. The data_out signal remains at 0x000 instead of transitioning to the sorted result after the algorithm finishes. The stall suggests data corruption occurs during the comparison and swap operations within the sort pipeline. Analysis indicates that upper bits of comparison keys are being lost during element swaps, which violates the sorting invariant and causes the algorithm to hang indefinitely trying to reach a valid sorted state.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..0d8067d1b2bdb5c8c2ed487d120e49dae258adbc --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,88 @@ +FST info: dumpfile List/tb/sv/dump.fst opened for output. +Starting direct operation test + +100000 OP_Insert at index 0, value 146 +146 + +157000 OP_Insert at index 1, value 64 +146 64 + +229000 OP_Insert at index 2, value 4 +146 64 4 + +301000 OP_Insert at index 3, value 4 +146 64 4 4 + +373000 OP_Insert at index 2, value 146 +146 64 146 4 4 + +445000 OP_Read at index 0 +493000 Data read: 146 + +517000 OP_Read at index 1 +565000 Data read: 64 + +589000 OP_Read at index 2 +637000 Data read: 146 + +661000 OP_Read at index 3 +709000 Data read: 4 + +733000 OP_Read at index 4 +781000 Data read: 4 + +805000 OP_Read at index 5 +853000 Data read out of bound, fault flag is asserted correctly + +877000 OP_Sum Request +925000 Sum: 364 + +949000 OP_Sort_Asc Request +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +1380000 OP_Sort_Asc Complete +4 4 64 146 146 + +1405000 OP_Read burst 5 time +ERROR: /tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:177: 1453000 Data read: 0, Data Exp: 4 + Time: 1453000 Scope: tb.read_n_burst +1500000 Data read: 4 +ERROR: /tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:177: 1548000 Data read: 4, Data Exp: 64 + Time: 1548000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:177: 1596000 Data read: 18, Data Exp: 146 + Time: 1596000 Scope: tb.read_n_burst +1644000 Data read: 146 + +1669000 OP_Sort_Des Request +2124000 OP_Sort_Des Complete +146 146 64 4 4 + +2149000 OP_Read burst 5 time +ERROR: /tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:177: 2197000 Data read: 18, Data Exp: 146 + Time: 2197000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:177: 2244000 Data read: 18, Data Exp: 146 + Time: 2244000 Scope: tb.read_n_burst +ERROR: /tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:177: 2292000 Data read: 4, Data Exp: 64 + Time: 2292000 Scope: tb.read_n_burst +2340000 Data read: 4 +ERROR: /tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:177: 2388000 Data read: 0, Data Exp: 4 + Time: 2388000 Scope: tb.read_n_burst + +2413000 OP_Find_1st_index for value 146 +2580000 First index of value 146 is 0 + +2605000 OP_Find_all_index for value 64 +ERROR: /tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:411: 2797000 Value 64 should be found at index 2 but index 0 is reported by DUT + Time: 2797000 Scope: tb.find_all_index + +3821000 TEST FAILED +Error count = 8 + + +--- STDERR --- +/tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:92: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:267: warning: task definition for "sort_acending" has an empty port declaration list! +/tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:295: warning: task definition for "sort_desending" has an empty port declaration list! +/tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:325: warning: task definition for "sum" has an empty port declaration list! +/tmp/sim4_simsh_23223d_x/source/List/tb/sv/tb.sv:433: warning: task definition for "direct_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/list__sorter/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..ca37f89a97beb30a065ba30c26b4cd9d33d80740 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/list__sorter/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/list__sorter/sim.sh b/Weiyet_RTLStructLib/candidates/list__sorter/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..0bd110a6da0e370dffde372afcfe284801f742b8 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/list__sorter/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_list "$SRCDIR/List/src/list.sv" "$SRCDIR/List/src/sorter.sv" "$SRCDIR/List/src/adder.sv" "$SRCDIR/List/tb/sv/tb.sv" +vvp /tmp/sim_list -fst +VCDFILE=List/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..913022a6289e4795d8c5aa283a69cf9b0831eefa Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/diff.patch b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..43c7bde24655a2a9e43ca5a8ae8b754f4294c62c --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/diff.patch @@ -0,0 +1,11 @@ +--- a/Singly_Linked_List/src/singly_linked_list.sv ++++ b/Singly_Linked_List/src/singly_linked_list.sv +@@ -237,7 +237,7 @@ + FIND_VALUE: begin + // if (!valid_rd_buf) begin + // next_state <= FAULT; +- if(data_rd_buf == data_in) begin ++ if(data_rd_buf != data_in) begin + // update curr pos to invalid + wr_req <= 1'b1; + target_idx <= cur_ptr; diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/metadata.json b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..ae3e6856b236c16fcb8de50d7dc4ec2ae41dca1b --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "inverted_condition", + "task_type": "behavioral_bug", + "files_modified": [ + "Singly_Linked_List/src/singly_linked_list.sv" + ], + "bug_description": "Inverted 'data_rd_buf == data_in' condition in FIND_VALUE state \u2014 delete-by-value now deletes a node whose data does NOT match the target value instead of one that does", + "signals_affected": [ + "data_rd_buf", + "data_in" + ], + "simulation_status": "sim_ok", + "problem_statement": "When attempting to delete a node with a specific data value from the linked list, the operation fails to complete properly\u2014op_done remains low at t=132000ns and never asserts. More critically, the list structure becomes corrupted immediately following the delete command: length collapses to zero, both head and tail register unexpected values (1000 each), and the empty flag is asserted despite the list containing valid data. The state divergences at t=132000ns and subsequent operations (full signal dropping at t=684000ns, data_out reading zero at t=1068000ns) suggest that the operation is deleting the wrong node or incorrectly manipulating the list pointers. The unit appears to be removing a node that does not match the target value, leaving the data structure in an invalid state.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/sim_log.txt b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..40cc8b030f60f53a5943f6b946e6d35fb1851e16 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/inverted_condition/sim_log.txt @@ -0,0 +1,118 @@ +FST info: dumpfile Singly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +517000 Addr 0 found at Index 3 +517000 Addr 1 found at Index 2 +517000 Addr 2 found at Index 4 +517000 Addr 3 found at Index 1 +517000 Addr 4 found at Index 0 +517000 Next Addr = 5 +517000 Data Written to Index 1 : 3 +517000 linked_list_exp = 7 3 6 0 3 5 +517000 linked_list_addr = 4 5 3 1 0 2 +517000 OP_Insert_At_Index 2 index, 4 value +637000 Addr 0 found at Index 4 +637000 Addr 1 found at Index 3 +637000 Addr 2 found at Index 5 +637000 Addr 3 found at Index 2 +637000 Addr 4 found at Index 0 +637000 Addr 5 found at Index 1 +637000 Next Addr = 6 +637000 Data Written to Index 2 : 4 +637000 linked_list_exp = 7 3 4 6 0 3 5 +637000 linked_list_addr = 4 5 6 3 1 0 2 +637000 OP_Insert_At_Index 8 index, 3 value +685000 Addr 0 found at Index 5 +685000 Addr 1 found at Index 4 +685000 Addr 2 found at Index 6 +685000 Addr 3 found at Index 3 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Addr 6 found at Index 2 +685000 Next Addr = 7 +685000 Data Written to Back : 3 +685000 Queue is full and full flag is asserted correctly +685000 linked_list_exp = 7 3 4 6 0 3 5 3 +685000 linked_list_addr = 4 5 6 3 1 0 2 7 +685000 OP_Insert_At_Index 8 index, 4 value +733000 Fault flag is asserted correctly +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 1 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Insert_At_Index 0 index, 3 value +829000 Fault flag is asserted correctly +829000 Queue is full and full flag is asserted correctly +829000 linked_list_exp = 7 3 4 6 0 3 5 3 +829000 linked_list_addr = 4 5 6 3 1 0 2 7 +1029000 OP_Read 8 times +1069000 Data read: 7 +1117000 Data read: 3 +1165000 Data read: 4 +1213000 Data read: 6 +1261000 Data read: 0 +1309000 Data read: 3 +1357000 Data read: 5 +1405000 Data read: 3 +1405000 linked_list_exp = 7 3 4 6 0 3 5 3 +1405000 linked_list_addr = 4 5 6 3 1 0 2 7 +1905000 OP_Delete_Value 7 value +1981000 Data 7 at Index 0 is Deleted_by_Value +1981000 linked_list_exp = 3 4 6 0 3 5 3 +1981000 linked_list_addr = 5 6 3 1 0 2 7 +1981000 OP_Delete_At_Index 0 index +2053000 Data 3 at Front is Deleted +2053000 linked_list_exp = 4 6 0 3 5 3 +2053000 linked_list_addr = 6 3 1 0 2 7 +2053000 OP_Delete_At_Index 0 index +2125000 Data 4 at Front is Deleted +2125000 linked_list_exp = 6 0 3 5 3 +2125000 linked_list_addr = 3 1 0 2 7 +2125000 OP_Delete_Value 2 value +ERROR: /tmp/sim4_simsh_b_1fwajf/source/Singly_Linked_List/tb/sv/tb.sv:228: 2197000 Data delete out of bound, fault f +--- STDERR --- +/tmp/sim4_simsh_b_1fwajf/source/Singly_Linked_List/tb/sv/tb.sv:96: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_b_1fwajf/source/Singly_Linked_List/tb/sv/tb.sv:528: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_b_1fwajf/source/Singly_Linked_List/tb/sv/tb.sv:571: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..365441b8fc2f9ee35d5dc07d11fd4b6967d17de4 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/diff.patch b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..1ff71923196ebf76f986367a4381051ea8384c10 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/diff.patch @@ -0,0 +1,11 @@ +--- a/Singly_Linked_List/src/singly_linked_list.sv ++++ b/Singly_Linked_List/src/singly_linked_list.sv +@@ -302,7 +302,7 @@ + if (rst) begin + data_out <= {DATA_WIDTH{1'b0}}; + next_node_addr <= {ADDR_WIDTH{1'b0}}; +- end else if (op_is_read & (next_state == EXECUTE)) begin ++ end else begin + data_out <= node_data[target_idx]; + next_node_addr <= node_next_node_addr[target_idx]; + end diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/metadata.json b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..f49b38b515bce57757eb4e4149f56f2e022ae686 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "missing_enable", + "task_type": "behavioral_bug", + "files_modified": [ + "Singly_Linked_List/src/singly_linked_list.sv" + ], + "bug_description": "Removed 'op_is_read & (next_state == EXECUTE)' enable condition from the sequential block controlling data_out and next_node_addr \u2014 these output registers now update on every clock edge instead of only during a read operation reaching the EXECUTE state", + "signals_affected": [ + "data_out", + "next_node_addr" + ], + "simulation_status": "sim_ok", + "problem_statement": "During verification of the memory interface module, unexpected transitions are appearing on output signals outside their intended control windows. At t=108000, `next_node_addr` transitions to 1000 without an active read operation in the EXECUTE state, and at t=156000, `data_out` updates to 00000011 when no read should be occurring. These output registers appear to be updating on every clock cycle rather than remaining stable between actual read transactions. The data and address values are becoming stale and incorrect, breaking the expected read transaction protocol where outputs should only change when a complete read operation enters the EXECUTE state.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/sim_log.txt b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..6727c5a6d3e03bfc7110c543b53755312603820b --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_enable/sim_log.txt @@ -0,0 +1,120 @@ +FST info: dumpfile Singly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +517000 Addr 0 found at Index 3 +517000 Addr 1 found at Index 2 +517000 Addr 2 found at Index 4 +517000 Addr 3 found at Index 1 +517000 Addr 4 found at Index 0 +517000 Next Addr = 5 +517000 Data Written to Index 1 : 3 +517000 linked_list_exp = 7 3 6 0 3 5 +517000 linked_list_addr = 4 5 3 1 0 2 +517000 OP_Insert_At_Index 2 index, 4 value +637000 Addr 0 found at Index 4 +637000 Addr 1 found at Index 3 +637000 Addr 2 found at Index 5 +637000 Addr 3 found at Index 2 +637000 Addr 4 found at Index 0 +637000 Addr 5 found at Index 1 +637000 Next Addr = 6 +637000 Data Written to Index 2 : 4 +637000 linked_list_exp = 7 3 4 6 0 3 5 +637000 linked_list_addr = 4 5 6 3 1 0 2 +637000 OP_Insert_At_Index 8 index, 3 value +685000 Addr 0 found at Index 5 +685000 Addr 1 found at Index 4 +685000 Addr 2 found at Index 6 +685000 Addr 3 found at Index 3 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Addr 6 found at Index 2 +685000 Next Addr = 7 +685000 Data Written to Back : 3 +685000 Queue is full and full flag is asserted correctly +685000 linked_list_exp = 7 3 4 6 0 3 5 3 +685000 linked_list_addr = 4 5 6 3 1 0 2 7 +685000 OP_Insert_At_Index 8 index, 4 value +733000 Fault flag is asserted correctly +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 1 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Insert_At_Index 0 index, 3 value +829000 Fault flag is asserted correctly +829000 Queue is full and full flag is asserted correctly +829000 linked_list_exp = 7 3 4 6 0 3 5 3 +829000 linked_list_addr = 4 5 6 3 1 0 2 7 +1029000 OP_Read 8 times +1069000 Data read: 7 +1117000 Data read: 3 +1165000 Data read: 4 +1213000 Data read: 6 +1261000 Data read: 0 +1309000 Data read: 3 +1357000 Data read: 5 +1405000 Data read: 3 +1405000 linked_list_exp = 7 3 4 6 0 3 5 3 +1405000 linked_list_addr = 4 5 6 3 1 0 2 7 +1905000 OP_Delete_Value 7 value +1957000 Data 7 at Index 0 is Deleted_by_Value +1957000 linked_list_exp = 3 4 6 0 3 5 3 +1957000 linked_list_addr = 5 6 3 1 0 2 7 +1957000 OP_Delete_At_Index 0 index +2029000 Data 3 at Front is Deleted +2029000 linked_list_exp = 4 6 0 3 5 3 +2029000 linked_list_addr = 6 3 1 0 2 7 +2029000 OP_Delete_At_Index 0 index +2101000 Data 4 at Front is Deleted +2101000 linked_list_exp = 6 0 3 5 3 +2101000 linked_list_addr = 3 1 0 2 7 +2101000 OP_Delete_Value 2 value +2269000 Data delete out of bound, fault flag is asserted correctly +2269000 linked_list_exp = 6 0 3 5 3 +2269000 link +--- STDERR --- +/tmp/sim4_simsh_9ty0hwt_/source/Singly_Linked_List/tb/sv/tb.sv:96: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_9ty0hwt_/source/Singly_Linked_List/tb/sv/tb.sv:528: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_9ty0hwt_/source/Singly_Linked_List/tb/sv/tb.sv:571: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..95aa8ec58896367755c5a7d14652c7ac78491850 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/diff.patch b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..64fda7c12e0edfbe121ba3f1c8a2e72a2ac48f79 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/diff.patch @@ -0,0 +1,19 @@ +--- a/Singly_Linked_List/src/singly_linked_list.sv ++++ b/Singly_Linked_List/src/singly_linked_list.sv +@@ -297,12 +297,12 @@ + next_addr_rd_buf <= node_next_node_addr[target_idx]; + end + end ++ ++ initial data_out = {DATA_WIDTH{1'bx}}; ++ initial next_node_addr = {ADDR_WIDTH{1'bx}}; + + always @ (posedge clk, posedge rst) begin +- if (rst) begin +- data_out <= {DATA_WIDTH{1'b0}}; +- next_node_addr <= {ADDR_WIDTH{1'b0}}; +- end else if (op_is_read & (next_state == EXECUTE)) begin ++ if (op_is_read & (next_state == EXECUTE)) begin + data_out <= node_data[target_idx]; + next_node_addr <= node_next_node_addr[target_idx]; + end diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/metadata.json b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..6fe8d79112ac87602f95b22b2ece96bff8362996 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "missing_reset", + "task_type": "behavioral_bug", + "files_modified": [ + "Singly_Linked_List/src/singly_linked_list.sv" + ], + "bug_description": "Removed synchronous reset for 'data_out' and 'next_node_addr' output registers; added initial blocks setting them to x to make the missing reset observable in simulation", + "signals_affected": [ + "data_out", + "next_node_addr" + ], + "simulation_status": "sim_ok", + "problem_statement": "After power-up and reset de-assertion, the output signals `data_out` and `next_node_addr` are not properly initialized. At t=0, both signals show undefined values (X) instead of their expected known state, causing unpredictable behavior in downstream logic. This initialization failure violates the interface contract and makes the design unsuitable for synthesis and place-and-route. Investigation shows that these output registers are not being driven to a valid state during the reset sequence, leaving them in an undefined condition that persists until other logic writes to them. The data corruption at startup breaks verification and prevents reliable operation in hardware.", + "diff_summary": "10 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/sim_log.txt b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..39db7736dfd40f6bcd2820730a7f30b2d96472ab --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/missing_reset/sim_log.txt @@ -0,0 +1,120 @@ +FST info: dumpfile Singly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +517000 Addr 0 found at Index 3 +517000 Addr 1 found at Index 2 +517000 Addr 2 found at Index 4 +517000 Addr 3 found at Index 1 +517000 Addr 4 found at Index 0 +517000 Next Addr = 5 +517000 Data Written to Index 1 : 3 +517000 linked_list_exp = 7 3 6 0 3 5 +517000 linked_list_addr = 4 5 3 1 0 2 +517000 OP_Insert_At_Index 2 index, 4 value +637000 Addr 0 found at Index 4 +637000 Addr 1 found at Index 3 +637000 Addr 2 found at Index 5 +637000 Addr 3 found at Index 2 +637000 Addr 4 found at Index 0 +637000 Addr 5 found at Index 1 +637000 Next Addr = 6 +637000 Data Written to Index 2 : 4 +637000 linked_list_exp = 7 3 4 6 0 3 5 +637000 linked_list_addr = 4 5 6 3 1 0 2 +637000 OP_Insert_At_Index 8 index, 3 value +685000 Addr 0 found at Index 5 +685000 Addr 1 found at Index 4 +685000 Addr 2 found at Index 6 +685000 Addr 3 found at Index 3 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Addr 6 found at Index 2 +685000 Next Addr = 7 +685000 Data Written to Back : 3 +685000 Queue is full and full flag is asserted correctly +685000 linked_list_exp = 7 3 4 6 0 3 5 3 +685000 linked_list_addr = 4 5 6 3 1 0 2 7 +685000 OP_Insert_At_Index 8 index, 4 value +733000 Fault flag is asserted correctly +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 1 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Insert_At_Index 0 index, 3 value +829000 Fault flag is asserted correctly +829000 Queue is full and full flag is asserted correctly +829000 linked_list_exp = 7 3 4 6 0 3 5 3 +829000 linked_list_addr = 4 5 6 3 1 0 2 7 +1029000 OP_Read 8 times +1069000 Data read: 7 +1117000 Data read: 3 +1165000 Data read: 4 +1213000 Data read: 6 +1261000 Data read: 0 +1309000 Data read: 3 +1357000 Data read: 5 +1405000 Data read: 3 +1405000 linked_list_exp = 7 3 4 6 0 3 5 3 +1405000 linked_list_addr = 4 5 6 3 1 0 2 7 +1905000 OP_Delete_Value 7 value +1957000 Data 7 at Index 0 is Deleted_by_Value +1957000 linked_list_exp = 3 4 6 0 3 5 3 +1957000 linked_list_addr = 5 6 3 1 0 2 7 +1957000 OP_Delete_At_Index 0 index +2029000 Data 3 at Front is Deleted +2029000 linked_list_exp = 4 6 0 3 5 3 +2029000 linked_list_addr = 6 3 1 0 2 7 +2029000 OP_Delete_At_Index 0 index +2101000 Data 4 at Front is Deleted +2101000 linked_list_exp = 6 0 3 5 3 +2101000 linked_list_addr = 3 1 0 2 7 +2101000 OP_Delete_Value 2 value +2269000 Data delete out of bound, fault flag is asserted correctly +2269000 linked_list_exp = 6 0 3 5 3 +2269000 link +--- STDERR --- +/tmp/sim4_simsh_0g8m75iy/source/Singly_Linked_List/tb/sv/tb.sv:96: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_0g8m75iy/source/Singly_Linked_List/tb/sv/tb.sv:528: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_0g8m75iy/source/Singly_Linked_List/tb/sv/tb.sv:571: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..dfa244e7961274ff574dbbe972cd2a5672b7b1c4 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/diff.patch b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..9e186479fd58fd4390e7ef2a4c0af76ae36d31ac --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/diff.patch @@ -0,0 +1,11 @@ +--- a/Singly_Linked_List/src/singly_linked_list.sv ++++ b/Singly_Linked_List/src/singly_linked_list.sv +@@ -224,7 +224,7 @@ + // update next_node_addr of pre pos to next pos + next_node_addr_idx <= cur_ptr; + next_node_addr_in <= find_next_ptr(valid_bits); +- next_state <= INSERT_STG1; ++ next_state <= EXECUTE; + end + end else if (index >= (length - 1)) begin + next_state <= FAULT; diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/metadata.json b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..92f6c50109e637e09bec0815999cf8b3cda67e83 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/metadata.json @@ -0,0 +1,17 @@ +{ + "bug_type": "state_transition", + "task_type": "behavioral_bug", + "files_modified": [ + "Singly_Linked_List/src/singly_linked_list.sv" + ], + "bug_description": "Changed FIND_ADDR\u2192INSERT_STG1 transition to FIND_ADDR\u2192EXECUTE for insert operations \u2014 FSM skips the INSERT_STG1 stage, so the newly inserted node's next pointer is never set to point to the node that was previously at that position, corrupting the linked list chain", + "signals_affected": [ + "next_state", + "state" + ], + "simulation_status": "sim_ok", + "problem_statement": "After inserting nodes into the linked list, subsequent operations return incorrect data and the internal list state becomes corrupted. At t=132000, following an insert operation, the `empty` flag unexpectedly asserts while `head` and `tail` simultaneously hold non-zero values (1000), creating an inconsistent state. Further operations trigger unexpected behavior: the `full` flag asserts at t=636000 despite the list not being at capacity, and a fault condition is raised at t=684000. When attempting to read data from the list at t=1020000, `data_out` contains 00000111 and `next_node_addr` shows 0101, neither of which correspond to the inserted values, indicating the linked list chain has been corrupted and nodes are not properly linked.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/sim_log.txt b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..6cf48654074eee091a2922879596db88b1def628 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/state_transition/sim_log.txt @@ -0,0 +1,108 @@ +FST info: dumpfile Singly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +493000 Addr 0 found at Index 3 +493000 Addr 1 found at Index 2 +493000 Addr 2 found at Index 4 +493000 Addr 3 found at Index 1 +493000 Addr 4 found at Index 0 +493000 Next Addr = 5 +493000 Data Written to Index 1 : 3 +493000 linked_list_exp = 7 3 6 0 3 5 +493000 linked_list_addr = 4 5 3 1 0 2 +493000 OP_Insert_At_Index 2 index, 4 value +589000 Addr 0 found at Index 4 +589000 Addr 1 found at Index 3 +589000 Addr 2 found at Index 5 +589000 Addr 3 found at Index 2 +589000 Addr 4 found at Index 0 +589000 Addr 5 found at Index 1 +589000 Next Addr = 6 +589000 Data Written to Index 2 : 4 +589000 linked_list_exp = 7 3 4 6 0 3 5 +589000 linked_list_addr = 4 5 6 3 1 0 2 +589000 OP_Insert_At_Index 8 index, 3 value +637000 Addr 0 found at Index 5 +637000 Addr 1 found at Index 4 +637000 Addr 2 found at Index 6 +637000 Addr 3 found at Index 3 +637000 Addr 4 found at Index 0 +637000 Addr 5 found at Index 1 +637000 Addr 6 found at Index 2 +637000 Next Addr = 7 +637000 Data Written to Back : 3 +637000 Queue is full and full flag is asserted correctly +637000 linked_list_exp = 7 3 4 6 0 3 5 3 +637000 linked_list_addr = 4 5 6 3 1 0 2 7 +637000 OP_Insert_At_Index 8 index, 4 value +685000 Fault flag is asserted correctly +685000 Queue is full and full flag is asserted correctly +685000 linked_list_exp = 7 3 4 6 0 3 5 3 +685000 linked_list_addr = 4 5 6 3 1 0 2 7 +685000 OP_Insert_At_Index 8 index, 1 value +733000 Fault flag is asserted correctly +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 0 index, 3 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +981000 OP_Read 8 times +1021000 Data read: 7 +1069000 Data read: 3 +1117000 Data read: 4 +ERROR: /tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/sv/tb.sv:180: 1117000 Next Addr: 8, Addr Exp: 3 + Time: 1117000 Scope: tb.read_n +ERROR: /tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/sv/tb.sv:173: 1165000 Data read: 4, Data Exp: 6 + Time: 1165000 Scope: tb.read_n +ERROR: /tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/sv/tb.sv:180: 1165000 Next Addr: 8, Addr Exp: 1 + Time: 1165000 Scope: tb.read_n +ERROR: /tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/sv/tb.sv:173: 1213000 Data read: 4, Data Exp: 0 + Time: 1213000 Scope: tb.read_n +ERROR: /tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/sv/tb.sv:180: 1213000 Next Addr: 8, Addr Exp: 0 + Time: 1213000 Scope: tb.read_n +ERROR: /tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/ +--- STDERR --- +/tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/sv/tb.sv:96: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/sv/tb.sv:528: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_5wd9aqsm/source/Singly_Linked_List/tb/sv/tb.sv:571: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..c18c38a4389d3c776c90100645fc4691c29532d1 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/diff.patch b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..722384f35826c5ecfce2496f3f31d79aabd3fa85 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/diff.patch @@ -0,0 +1,11 @@ +--- a/Singly_Linked_List/src/singly_linked_list.sv ++++ b/Singly_Linked_List/src/singly_linked_list.sv +@@ -93,7 +93,7 @@ + assign op_is_insert_at_addr = op[2:0] == 3'd1 & op_start; + assign op_is_insert_at_index = op[2:0] == 3'd5 & op_start; + assign op_is_delete_by_value = op[2:0] == 3'd2 & op_start; +- assign op_is_delete_by_index = op[2:0] == 3'd7 & op_start; ++ assign op_is_delete_by_index = op[2:0] == 2'd7 & op_start; + assign op_is_delete_by_addr = op[2:0] == 3'd3 & op_start; + + always @ (posedge clk or posedge rst) begin diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/metadata.json b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..91f845f02bd645551137d696e6bd7467b7e1f6a0 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/metadata.json @@ -0,0 +1,16 @@ +{ + "bug_type": "width_bit_cutoff", + "task_type": "behavioral_bug", + "files_modified": [ + "Singly_Linked_List/src/singly_linked_list.sv" + ], + "bug_description": "Changed '3'd7' to '2'd7' in the op_is_delete_by_index assignment \u2014 decimal 7 (3-bit) truncates to decimal 3 in 2 bits (7 mod 4 = 3), so Delete_At_Index now incorrectly triggers when op=3 (which is Delete_At_Addr) instead of op=7", + "signals_affected": [ + "op_is_delete_by_index" + ], + "simulation_status": "sim_ok", + "problem_statement": "During functional verification of the linked list controller, I observed unexpected behavior in delete operations that suggests incorrect operation decoding. When executing a sequence of operations including Delete_At_Index (op=7) and Delete_At_Addr (op=3), the state machine appears to conflate these two distinct operations, causing list structure corruption.\n\nSpecifically, at t=132000ns, the empty flag unexpectedly asserts and the head/tail pointers are incorrectly updated (head=1000, tail=1000) during a delete sequence where they should remain at different values. Simultaneously, length goes to 0000 and op_done does not assert as expected, suggesting the operation never completes properly. This corruption cascades: by t=684000ns, the full flag diverges from expected behavior, and by t=1068000ns, the data_out and next_node_addr signals diverge from the correct values (both going to 0). The fault signal also unexpectedly asserts at t=732000ns, indicating the controller detected internal inconsistency.\n\nThe root cause appears to be in the operation selector logic that differentiates between Delete_At_Index and Delete_At_Addr. These operations are being incorrectly decoded and conflated, causing the list metadata to become invalid.", + "diff_summary": "4 changed lines", + "buggy_waveform": "buggy_waveform.fst", + "golden_waveform": "golden_waveform.fst" +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/sim_log.txt b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..5954c2dc499509f00543a645831f1c82b038add3 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/width_bit_cutoff/sim_log.txt @@ -0,0 +1,117 @@ +FST info: dumpfile Singly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +517000 Addr 0 found at Index 3 +517000 Addr 1 found at Index 2 +517000 Addr 2 found at Index 4 +517000 Addr 3 found at Index 1 +517000 Addr 4 found at Index 0 +517000 Next Addr = 5 +517000 Data Written to Index 1 : 3 +517000 linked_list_exp = 7 3 6 0 3 5 +517000 linked_list_addr = 4 5 3 1 0 2 +517000 OP_Insert_At_Index 2 index, 4 value +637000 Addr 0 found at Index 4 +637000 Addr 1 found at Index 3 +637000 Addr 2 found at Index 5 +637000 Addr 3 found at Index 2 +637000 Addr 4 found at Index 0 +637000 Addr 5 found at Index 1 +637000 Next Addr = 6 +637000 Data Written to Index 2 : 4 +637000 linked_list_exp = 7 3 4 6 0 3 5 +637000 linked_list_addr = 4 5 6 3 1 0 2 +637000 OP_Insert_At_Index 8 index, 3 value +685000 Addr 0 found at Index 5 +685000 Addr 1 found at Index 4 +685000 Addr 2 found at Index 6 +685000 Addr 3 found at Index 3 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Addr 6 found at Index 2 +685000 Next Addr = 7 +685000 Data Written to Back : 3 +685000 Queue is full and full flag is asserted correctly +685000 linked_list_exp = 7 3 4 6 0 3 5 3 +685000 linked_list_addr = 4 5 6 3 1 0 2 7 +685000 OP_Insert_At_Index 8 index, 4 value +733000 Fault flag is asserted correctly +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 1 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Insert_At_Index 0 index, 3 value +829000 Fault flag is asserted correctly +829000 Queue is full and full flag is asserted correctly +829000 linked_list_exp = 7 3 4 6 0 3 5 3 +829000 linked_list_addr = 4 5 6 3 1 0 2 7 +1029000 OP_Read 8 times +1069000 Data read: 7 +1117000 Data read: 3 +1165000 Data read: 4 +1213000 Data read: 6 +1261000 Data read: 0 +1309000 Data read: 3 +1357000 Data read: 5 +1405000 Data read: 3 +1405000 linked_list_exp = 7 3 4 6 0 3 5 3 +1405000 linked_list_addr = 4 5 6 3 1 0 2 7 +1905000 OP_Delete_Value 7 value +1957000 Data 7 at Index 0 is Deleted_by_Value +1957000 linked_list_exp = 3 4 6 0 3 5 3 +1957000 linked_list_addr = 5 6 3 1 0 2 7 +1957000 OP_Delete_At_Index 0 index +ERROR: /tmp/sim4_simsh_3kpfdw_4/source/Singly_Linked_List/tb/sv/tb.sv:266: 2005000 fault flag is asserted incorrectly + Time: 2005000 Scope: tb.delete_at_index +2005000 Data 3 at Front is Deleted +2005000 linked_list_exp = 4 6 0 3 5 3 +2005000 linked_list_addr = 6 3 1 0 2 7 +2005000 OP_Delete_At_Index 0 index +ERROR: /tmp/sim4_simsh_3kpfdw_4/source/Singly_Linked_List/tb/sv/tb.sv:266: 2053000 fault flag +--- STDERR --- +/tmp/sim4_simsh_3kpfdw_4/source/Singly_Linked_List/src/singly_linked_list.sv:96: warning: Numeric constant truncated to 2 bits. +/tmp/sim4_simsh_3kpfdw_4/source/Singly_Linked_List/tb/sv/tb.sv:96: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_3kpfdw_4/source/Singly_Linked_List/tb/sv/tb.sv:528: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_3kpfdw_4/source/Singly_Linked_List/tb/sv/tb.sv:571: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/buggy_waveform.fst b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/buggy_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..a4a2496ed2e9449a1761124cc20cf0c258b60d99 Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/buggy_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/diff.patch b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/diff.patch new file mode 100644 index 0000000000000000000000000000000000000000..ecc30ea55c5c8398dcf5b1cc95498d00581a054d --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/diff.patch @@ -0,0 +1,11 @@ +--- a/Singly_Linked_List/src/singly_linked_list.sv ++++ b/Singly_Linked_List/src/singly_linked_list.sv +@@ -75,7 +75,7 @@ + reg valid_rd_buf; + reg valid_wr; + reg [ADDR_WIDTH-1:0] next_addr_rd_buf; +- reg [DATA_WIDTH-1:0] data_rd_buf; ++ reg [DATA_WIDTH-3:0] data_rd_buf; + reg [ADDR_WIDTH-1:0] target_idx; + reg [ADDR_WIDTH-1:0] next_node_addr_idx; + reg [ADDR_WIDTH-1:0] next_node_addr_in; diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/metadata.json b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/metadata.json new file mode 100644 index 0000000000000000000000000000000000000000..d1559dafe36103101c84359439cc793163f31b64 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/metadata.json @@ -0,0 +1,5 @@ +{ + "bug_type": "wrong_bitwidth", + "simulation_status": "waveform_identical", + "signals_compared": 9 +} \ No newline at end of file diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/sim_log.txt b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/sim_log.txt new file mode 100644 index 0000000000000000000000000000000000000000..46bf9142d85920378fe7a2ade26991970ffa1855 --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/bugs/wrong_bitwidth/sim_log.txt @@ -0,0 +1,120 @@ +FST info: dumpfile Singly_Linked_List/tb/sv/dump.fst opened for output. + +====================================== +Direct Index Op Test +====================================== +100000 OP_Insert_At_Index 0 index, 3 value +133000 Next Addr = 0 +133000 Data Written to Front : 3 +133000 linked_list_exp = 3 +133000 linked_list_addr = 0 +133000 OP_Insert_At_Index 0 index, 0 value +181000 Addr 0 found at Index 0 +181000 Next Addr = 1 +181000 Data Written to Front : 0 +181000 linked_list_exp = 0 3 +181000 linked_list_addr = 1 0 +281000 OP_Insert_At_Index 4 index, 5 value +325000 Addr 0 found at Index 1 +325000 Addr 1 found at Index 0 +325000 Next Addr = 2 +325000 Data Written to Back : 5 +325000 linked_list_exp = 0 3 5 +325000 linked_list_addr = 1 0 2 +325000 OP_Insert_At_Index 0 index, 6 value +373000 Addr 0 found at Index 1 +373000 Addr 1 found at Index 0 +373000 Addr 2 found at Index 2 +373000 Next Addr = 3 +373000 Data Written to Front : 6 +373000 linked_list_exp = 6 0 3 5 +373000 linked_list_addr = 3 1 0 2 +373000 OP_Insert_At_Index 0 index, 7 value +421000 Addr 0 found at Index 2 +421000 Addr 1 found at Index 1 +421000 Addr 2 found at Index 3 +421000 Addr 3 found at Index 0 +421000 Next Addr = 4 +421000 Data Written to Front : 7 +421000 linked_list_exp = 7 6 0 3 5 +421000 linked_list_addr = 4 3 1 0 2 +421000 OP_Insert_At_Index 1 index, 3 value +517000 Addr 0 found at Index 3 +517000 Addr 1 found at Index 2 +517000 Addr 2 found at Index 4 +517000 Addr 3 found at Index 1 +517000 Addr 4 found at Index 0 +517000 Next Addr = 5 +517000 Data Written to Index 1 : 3 +517000 linked_list_exp = 7 3 6 0 3 5 +517000 linked_list_addr = 4 5 3 1 0 2 +517000 OP_Insert_At_Index 2 index, 4 value +637000 Addr 0 found at Index 4 +637000 Addr 1 found at Index 3 +637000 Addr 2 found at Index 5 +637000 Addr 3 found at Index 2 +637000 Addr 4 found at Index 0 +637000 Addr 5 found at Index 1 +637000 Next Addr = 6 +637000 Data Written to Index 2 : 4 +637000 linked_list_exp = 7 3 4 6 0 3 5 +637000 linked_list_addr = 4 5 6 3 1 0 2 +637000 OP_Insert_At_Index 8 index, 3 value +685000 Addr 0 found at Index 5 +685000 Addr 1 found at Index 4 +685000 Addr 2 found at Index 6 +685000 Addr 3 found at Index 3 +685000 Addr 4 found at Index 0 +685000 Addr 5 found at Index 1 +685000 Addr 6 found at Index 2 +685000 Next Addr = 7 +685000 Data Written to Back : 3 +685000 Queue is full and full flag is asserted correctly +685000 linked_list_exp = 7 3 4 6 0 3 5 3 +685000 linked_list_addr = 4 5 6 3 1 0 2 7 +685000 OP_Insert_At_Index 8 index, 4 value +733000 Fault flag is asserted correctly +733000 Queue is full and full flag is asserted correctly +733000 linked_list_exp = 7 3 4 6 0 3 5 3 +733000 linked_list_addr = 4 5 6 3 1 0 2 7 +733000 OP_Insert_At_Index 8 index, 1 value +781000 Fault flag is asserted correctly +781000 Queue is full and full flag is asserted correctly +781000 linked_list_exp = 7 3 4 6 0 3 5 3 +781000 linked_list_addr = 4 5 6 3 1 0 2 7 +781000 OP_Insert_At_Index 0 index, 3 value +829000 Fault flag is asserted correctly +829000 Queue is full and full flag is asserted correctly +829000 linked_list_exp = 7 3 4 6 0 3 5 3 +829000 linked_list_addr = 4 5 6 3 1 0 2 7 +1029000 OP_Read 8 times +1069000 Data read: 7 +1117000 Data read: 3 +1165000 Data read: 4 +1213000 Data read: 6 +1261000 Data read: 0 +1309000 Data read: 3 +1357000 Data read: 5 +1405000 Data read: 3 +1405000 linked_list_exp = 7 3 4 6 0 3 5 3 +1405000 linked_list_addr = 4 5 6 3 1 0 2 7 +1905000 OP_Delete_Value 7 value +1957000 Data 7 at Index 0 is Deleted_by_Value +1957000 linked_list_exp = 3 4 6 0 3 5 3 +1957000 linked_list_addr = 5 6 3 1 0 2 7 +1957000 OP_Delete_At_Index 0 index +2029000 Data 3 at Front is Deleted +2029000 linked_list_exp = 4 6 0 3 5 3 +2029000 linked_list_addr = 6 3 1 0 2 7 +2029000 OP_Delete_At_Index 0 index +2101000 Data 4 at Front is Deleted +2101000 linked_list_exp = 6 0 3 5 3 +2101000 linked_list_addr = 3 1 0 2 7 +2101000 OP_Delete_Value 2 value +2269000 Data delete out of bound, fault flag is asserted correctly +2269000 linked_list_exp = 6 0 3 5 3 +2269000 link +--- STDERR --- +/tmp/sim4_simsh_e0c5goz4/source/Singly_Linked_List/tb/sv/tb.sv:96: warning: task definition for "list_print_contents" has an empty port declaration list! +/tmp/sim4_simsh_e0c5goz4/source/Singly_Linked_List/tb/sv/tb.sv:528: warning: task definition for "direct_index_op_test" has an empty port declaration list! +/tmp/sim4_simsh_e0c5goz4/source/Singly_Linked_List/tb/sv/tb.sv:571: warning: task definition for "direct_addr_op_test" has an empty port declaration list! diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/golden_waveform.fst b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/golden_waveform.fst new file mode 100644 index 0000000000000000000000000000000000000000..d3e2199ffe51b034f7692215813caaee4ea8294a Binary files /dev/null and b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/golden_waveform.fst differ diff --git a/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/sim.sh b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/sim.sh new file mode 100644 index 0000000000000000000000000000000000000000..535629ad5b6ebbf3fa45657fcae2e7deb5d5785a --- /dev/null +++ b/Weiyet_RTLStructLib/candidates/singly_linked_list__singly_linked_list/sim.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -euo pipefail +SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +iverilog -g2012 -o /tmp/sim_singly_linked_list "$SRCDIR/Singly_Linked_List/src/singly_linked_list.sv" "$SRCDIR/Singly_Linked_List/tb/sv/tb.sv" +vvp /tmp/sim_singly_linked_list -fst +VCDFILE=Singly_Linked_List/tb/sv/dump.fst +VCDLEVEL=0 diff --git a/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/cocotb/Makefile b/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/cocotb/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..f6387abd59791acc73bc03a8de690a61e8548076 --- /dev/null +++ b/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/cocotb/Makefile @@ -0,0 +1,41 @@ +SIM ?= icarus +TOPLEVEL_LANG ?= verilog +WAVES ?= 1 #set 1 to enable waveform dump. + +PWD=$(shell pwd) + +#export PYTHONPATH := $(PWD)/../model:$(PYTHONPATH) + +VERILOG_SOURCES = $(PWD)/../../src/doubly_linked_list.sv + +# DUT Top +TOPLEVEL = doubly_linked_list +# top python file name +MODULE = tb + +#use , separtor to run multiple TESTCASE, by default all @cocotb.test will be run +#TESTCASE = index_op_test ， addr_op_test + +COMPILE_ARGS = -Ptable_top.DATA_WIDTH=8 # DUT parameter #"-p" (parameter) iverilog command flags +COMPILE_ARGS += -Ptable_top.MAX_NODE=8 # DUT parameter #"-p" (parameter) iverilog command flags +#run make clean before running with new parameter. + +#Set RANDOM_SEED number +#PLUSARGS = +seed=1716033254 +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +ifeq ($(SIM), icarus) + $(shell echo 'module iverilog_dump();' > iverilog_dump.v) + $(shell echo 'initial begin' >> iverilog_dump.v) + $(shell echo ' $$dumpfile("$(TOPLEVEL).vcd");' >> iverilog_dump.v) + $(shell echo ' $$dumpvars(0, $(TOPLEVEL));' >> iverilog_dump.v) + $(shell echo 'end' >> iverilog_dump.v) + $(shell echo 'endmodule' >> iverilog_dump.v) + VERILOG_SOURCES += $(PWD)/iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + + diff --git a/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/cocotb/tb.py b/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/cocotb/tb.py new file mode 100644 index 0000000000000000000000000000000000000000..0742f926d9178f9fb44d4ccd759c8791af2f0a52 --- /dev/null +++ b/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/cocotb/tb.py @@ -0,0 +1,480 @@ +import random +#import asyncio +import math +import cocotb +import cocotb.result +from cocotb.triggers import Timer, RisingEdge, ReadOnly +from cocotb.clock import Clock +from cocotb_bus.drivers import BusDriver +from cocotb_bus.monitors import BusMonitor +from cocotb.binary import BinaryValue + +#BIN string +#BinaryValue(dut.data_wr.value, n_bits=8) ; BinaryValue.integar ; BinaryValue.hex ; BinaryValue.binstr; BinaryValue.signed_integer ; can represent x,z + +DATA_WIDTH = 8 # DUT paramter +MAX_NODE = 8 # DUT paramter + +ADDR_NULL = MAX_NODE + 1 +MAX_DATA = 2**DATA_WIDTH - 1 + +OP_Read = 0b000 +OP_Insert_At_Addr = 0b001 +OP_Insert_At_Index = 0b101 +OP_Delete_Value = 0b010 +OP_Delete_At_Addr = 0b011 +OP_Delete_At_Index = 0b111; + +TB_CLK_PERIOD = 30 # TB clk generator +TB_SIM_TIMEOUT = 30 # TB sim timeout 30ms +TB_TEST_WEIGHT = 1 +err_cnt = 0 + +# doubly_linked_list #(.DATA_WIDTH(DUT_DATA_WIDTH),.MAX_NODE(DUT_MAX_NODE)) DUT +# ( /*input*/ .rst(rst), +# /*input*/ .clk(clk), +# /*input [DATA_WIDTH-1:0]*/ .data_in(data_in), +# /*input [ADDR_WIDTH-1:0]*/ .addr_in(addr_in), +# /*input [1:0]*/ .op(op), // 0: Read(addr_in); 1: Delete_Value(data_in); 2: Push_Back(data_in); 3: Push_front(data_in) +# /*input*/ .op_start(op_start), +# /*output reg [DATA_WIDTH-1:0]*/ .data_out(data_out), +# /*output reg*/ .op_done(op_done), +# /*output wire [ADDR_WIDTH-1:0]*/ .pre_node_addr(pre_node_addr),// Addr of pre node +# /*output wire [ADDR_WIDTH-1:0]*/ .next_node_addr(next_node_addr), // Addr of next node +# // status +# /*output reg [ADDR_WIDTH-1:0]*/ .length(length), +# /*output wire*/ .full(full), +# /*output reg [ADDR_WIDTH-1:0]*/ .head(head), // Addr of head +# /*output reg [ADDR_WIDTH-1:0]*/ .tail(tail), // Addr of head +# /*output wire*/ .empty(empty), +# /*output reg*/ .fault(fault) // Invalid Errors +# ); + +# Actual Python linked_list class: https://www.datacamp.com/tutorial/python-linked-lists +# To mimic harware linked_list, we need to keep track of the address of each node, model in below way also for our ease of debug. +class doubly_linked_list: + def __init__(self, dut): + self.dut = dut + self.linked_list_value = [] + self.linked_list_addr = [] + + def remove(self, index): + self.linked_list_value.pop(index) + self.linked_list_addr.pop(index) + + def find_next_addr(self): + for i in range(len(self.linked_list_addr)+2): + if i not in self.linked_list_addr: + return i + + def insert_by_addr(self, addr, data): + if(addr == -1): + self.linked_list_value.append(data) + self.linked_list_addr.append(self.find_next_addr()) + else: + self.linked_list_value.insert(self.linked_list_addr.index(addr), data) + self.linked_list_addr.insert(self.linked_list_addr.index(addr), self.find_next_addr()) + + def insert_by_index(self, index, data): + if(index == -1): + self.linked_list_value.append(data) + self.linked_list_addr.append(self.find_next_addr()) + else: + self.linked_list_value.insert(index, data) + self.linked_list_addr.insert(index, self.find_next_addr()) + + def delete_by_value(self, data): + self.linked_list_addr.remove(self.linked_list_value.index(data)) + self.linked_list_value.remove(data) + + def delete_by_addr(self, addr): + self.linked_list_value.pop(self.linked_list_addr.index(addr)) + self.linked_list_addr.pop(self.linked_list_addr.index(addr)) + + def read_by_addr(self, addr): + return self.linked_list_value[self.linked_list_addr.index(addr)] + + def print_content(self): + cocotb.log.info(f"Linked List Content: value = {self.linked_list_value}, addr = {self.linked_list_addr}") + +async def read_n_front(dut, list_exp, n): + global err_cnt + cocotb.log.info("OP_Read %0d values", n) + i = 0 + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + dut.op.value = OP_Read + dut.op_start.value = 1 + dut.addr_in.value = dut.head.value + i = i + 1 + while (i <= n): + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + if (dut.op_done.value == 1): + if( (i-1) >= len(list_exp.linked_list_addr)): + if(dut.fault.value == 1): + cocotb.log.info("Data read out of bound, fault flag is asserted correctly") + else: + cocotb.log.error("Data read out of bound, fault flag is not asserted") + err_cnt += 1 + elif (list_exp.linked_list_value[i-1] == dut.data_out.value): + cocotb.log.info("Data read : %0d at Index %0d", dut.data_out.value, i-1) + else: + cocotb.log.error("Data read at Index %0d is Correct, ACT: %0d, EXP: %0d", i-1, dut.data_out.value, list_exp.linked_list_value[i-1]) + err_cnt += 1 + if(i==n): + dut.op_start.value = 0 + dut.addr_in.value = dut.next_node_addr.value + i = i + 1 + list_exp.print_content() + +async def read_n_back(dut, list_exp, n): + global err_cnt + cocotb.log.info("OP_Read %0d values", n) + i = 0 + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + dut.op.value = OP_Read + dut.op_start.value = 1 + dut.addr_in.value = dut.tail.value + i = i + 1 + while (i <= n): + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + if (dut.op_done.value == 1): + if( (i-1) >= len(list_exp.linked_list_addr)): + if(dut.fault.value == 1): + cocotb.log.info("Data read out of bound, fault flag is asserted correctly") + else: + cocotb.log.error("Data read out of bound, fault flag is not asserted") + err_cnt += 1 + elif (list_exp.linked_list_value[-i] == dut.data_out.value): + cocotb.log.info("Data read : %0d at Index %0d", dut.data_out.value, len(list_exp.linked_list_addr)-1-(i-1)) + else: + cocotb.log.error("Data read at Index %0d is Correct, ACT: %0d, EXP: %0d", i-1, dut.data_out.value, list_exp.linked_list_value[-i]) + err_cnt += 1 + if(i==n): + dut.op_start.value = 0 + dut.addr_in.value = dut.pre_node_addr.value + i = i + 1 + list_exp.print_content() + +async def delete_value(dut, list_exp, value): + global err_cnt + cocotb.log.info("OP_Delete_Value %0d value", value) + i = 0 + found = 0 + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + dut.op.value = OP_Delete_Value + dut.data_in.value = value + dut.op_start.value = 1 + await RisingEdge(dut.op_done) + await Timer (1, units = 'ns') + for i in range(len(list_exp.linked_list_addr)): + if list_exp.linked_list_value[i] == value: + cocotb.log.info("Data %0d at Index %0d is Deleted_by_Value", value, i) + list_exp.remove(i) + found = 1 + break + if found == 0: + if(dut.fault.value == 1): + cocotb.log.info("Data delete out of bound, fault flag is asserted correctly") + else: + cocotb.log.error("Data delete out of bound, fault flag is not asserted") + err_cnt += 1 + else: + if(dut.fault.value == 1): + cocotb.log.error("Data delete in bound, fault flag is asserted incorrectly") + err_cnt += 1 + dut.op_start.value = 0 + list_exp.print_content() + +async def delete_at_index(dut, list_exp, index): + global err_cnt + cocotb.log.info("OP_Delete_At_Index %0d index", index) + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + dut.op.value = OP_Delete_At_Index + dut.addr_in.value = index + dut.op_start.value = 1 + await RisingEdge(dut.op_done) + await Timer (1, units = 'ns') + if (index >= len(list_exp.linked_list_addr)): + if(dut.fault.value == 1): + cocotb.log.info("Data delete out of bound, fault flag is asserted correctly") + else: + cocotb.log.error("Data delete out of bound, fault flag is not asserted") + err_cnt += 1 + elif (index == 0): + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + cocotb.log.info("Data %0d at Front is Deleted_by_Index", list_exp.linked_list_value[0]) + list_exp.remove(0) + else: + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + cocotb.log.info("Data %0d at Index %0d is Deleted_by_Index", list_exp.linked_list_value[index], index) + list_exp.remove(index) + dut.op_start.value = 0 + list_exp.print_content() + +async def insert_at_index(dut, list_exp, index, data): + global err_cnt + cocotb.log.info("OP_Insert_At_Index %0d index, %0d data", index, data) + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + dut.op.value = OP_Insert_At_Index + dut.addr_in.value = index + dut.data_in.value = data + dut.op_start.value = 1 + await RisingEdge(dut.op_done) + await Timer (1, units = 'ns') + if (len(list_exp.linked_list_value) >= MAX_NODE): + if(dut.fault.value == 1): + cocotb.log.info("Data insert out of bound, fault flag is asserted correctly") + else: + cocotb.log.error("Data insert out of bound, fault flag is not asserted") + err_cnt += 1 + elif (index == 0): + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + list_exp.insert_by_index(0, data) + cocotb.log.info("Data %0d at Front is Inserted_by_Index", data) + elif (index >= len(list_exp.linked_list_value)): + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + list_exp.insert_by_index(-1, data) + cocotb.log.info("Data %0d at End is Inserted_by_Index", data) + else: + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + list_exp.insert_by_index(index, data) + cocotb.log.info("Data %0d at Index %0d is Inserted_by_Index", data, index) + if(len(list_exp.linked_list_value) >= MAX_NODE): + if(dut.full.value == 1): + cocotb.log.info("Full flag is asserted correctly") + else: + cocotb.log.error("Full flag is not asserted") + err_cnt += 1 + elif (dut.full.value == 1): + cocotb.log.error("Full flag is asserted incorrectly") + err_cnt += 1 + dut.op_start.value = 0 + list_exp.print_content() + +async def delete_at_addr (dut, list_exp, addr): + global err_cnt + cocotb.log.info("OP_Delete_At_Addr %0d addr", addr) + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + dut.op.value = OP_Delete_At_Addr + dut.addr_in.value = addr + dut.op_start.value = 1 + pre_head = int(dut.head.value) + pre_tail = int(dut.tail.value) + + await RisingEdge(dut.op_done) + await Timer (1, units = 'ns') + if (addr >= ADDR_NULL): + if(dut.fault.value == 1): + cocotb.log.info("Data delete out of bound, fault flag is asserted correctly") + else: + cocotb.log.error("Data delete out of bound, fault flag is not asserted") + err_cnt += 1 + elif (addr == pre_head): + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + cocotb.log.info("Data %0d at Front is Deleted_by_Addr", list_exp.linked_list_value[0]) + list_exp.remove(0) + elif (addr == pre_tail): + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + cocotb.log.info("Data %0d at Back is Deleted_by_Addr", list_exp.linked_list_value[0]) + list_exp.remove(-1) + else: + if(addr not in list_exp.linked_list_addr): + if(dut.fault.value == 0): + cocotb.log.error("Fault flag is not asserted") + err_cnt += 1 + else: + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + cocotb.log.info("Data %0d at Addr %0d is Inserted_by_Addr", list_exp.linked_list_value[list_exp.linked_list_addr.index(addr)], addr) + list_exp.delete_by_addr(addr) + if(len(list_exp.linked_list_value) == 0): + if(dut.empty.value == 1): + cocotb.log.info("Full flag is asserted correctly") + else: + cocotb.log.error("Full flag is not asserted") + err_cnt += 1 + elif (dut.empty.value == 1): + cocotb.log.error("Full flag is asserted incorrectly") + err_cnt += 1 + dut.op_start.value = 0 + list_exp.print_content() + +async def insert_at_addr(dut, list_exp, addr, data): + global err_cnt + cocotb.log.info("OP_Insert_At_Addr %0d addr, %0d data", addr, data) + await RisingEdge(dut.clk) + await Timer (1, units = 'ns') + dut.op.value = OP_Insert_At_Addr + dut.addr_in.value = addr + dut.data_in.value = data + dut.op_start.value = 1 + pre_head = int(dut.head.value) + pre_tail = int(dut.tail.value) + + await RisingEdge(dut.op_done) + await Timer (1, units = 'ns') + if (len(list_exp.linked_list_value) >= MAX_NODE): + if(dut.fault.value == 1): + cocotb.log.info("Data insert out of bound, fault flag is asserted correctly") + else: + cocotb.log.error("Data insert out of bound, fault flag is not asserted") + err_cnt += 1 + elif (addr >= ADDR_NULL): + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + list_exp.insert_by_addr(-1, data) + cocotb.log.info("Data %0d at End is Inserted_by_Addr", data) + elif (addr == pre_head): + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + list_exp.insert_by_addr(addr, data) + cocotb.log.info("Data %0d at Front is Inserted_by_Addr", data) + elif (addr == pre_tail): + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + list_exp.insert_by_index(len(list_exp.linked_list_value)-1, data) + cocotb.log.info("Data %0d at End is Inserted_by_Addr", data) + else: + if(addr not in list_exp.linked_list_addr): + if(dut.fault.value == 0): + cocotb.log.error("Fault flag is not asserted") + err_cnt += 1 + else: + if(dut.fault.value == 1): + cocotb.log.error("Fault flag is asserted incorrectly") + err_cnt += 1 + list_exp.insert_by_addr(addr, data) + cocotb.log.info("Data %0d at Addr %0d is Inserted_by_Addr", data, addr) + if(len(list_exp.linked_list_value) >= MAX_NODE): + if(dut.full.value == 1): + cocotb.log.info("Full flag is asserted correctly") + else: + cocotb.log.error("Full flag is not asserted") + err_cnt += 1 + elif (dut.full.value == 1): + cocotb.log.error("Full flag is asserted incorrectly") + err_cnt += 1 + dut.op_start.value = 0 + list_exp.print_content() + +async def dut_init(dut): + global DATA_WIDTH # DUT paramter + global MAX_NODE # DUT paramter + global ADDR_NULL + global MAX_DATA + DATA_WIDTH = dut.DATA_WIDTH.value + MAX_NODE = dut.MAX_NODE.value + ADDR_NULL = MAX_NODE + MAX_DATA = 2**DATA_WIDTH - 1 + await cocotb.start(Clock(dut.clk, TB_CLK_PERIOD, units="ns").start()) + dut.data_in.value = 0 + dut.addr_in.value = 0 + dut.op.value = 0 + dut.op_start.value = 0 + dut.rst.value = 1 + await(Timer(100,'ns')) + dut.rst.value = 0 + await(Timer(100,'ns')) + +@cocotb.test() +async def index_op_test(dut): + await dut_init(dut) + list_exp = doubly_linked_list(dut) + cocotb.log.info("SEED NUMBER = %d",cocotb.RANDOM_SEED) + await insert_at_index(dut,list_exp,0,3) + await insert_at_index(dut,list_exp,0,0) + await Timer(200, units = 'ns') + await insert_at_index(dut,list_exp,4,5) + await insert_at_index(dut,list_exp,0,6) + await insert_at_index(dut,list_exp,0,7) + await insert_at_index(dut,list_exp,1,3) + await insert_at_index(dut,list_exp,2,4) + await insert_at_index(dut,list_exp,ADDR_NULL,3) + await insert_at_index(dut,list_exp,ADDR_NULL,4) + await insert_at_index(dut,list_exp,ADDR_NULL,1) + await insert_at_index(dut,list_exp,0,3) + await Timer(200, units = 'ns') + await read_n_front(dut,list_exp,len(list_exp.linked_list_value)) + await read_n_back(dut,list_exp,len(list_exp.linked_list_value)) + await Timer(200, units = 'ns') + await delete_value(dut,list_exp,7) + await delete_at_index(dut,list_exp,0) + await delete_at_index(dut,list_exp,0) + await delete_value(dut,list_exp,2) + await delete_value(dut,list_exp,4) + await delete_at_index(dut,list_exp,0) + await delete_at_index(dut,list_exp,7) + await delete_at_index(dut,list_exp,dut.length.value-1) + await delete_at_index(dut,list_exp,dut.length.value-1) + await delete_at_index(dut,list_exp,0) + await delete_at_index(dut,list_exp,0) + await delete_at_index(dut,list_exp,0) + await Timer(200, units = 'ns') + + if (err_cnt > 0): + cocotb.log.error("Errors count = %d",err_cnt) + cocotb.result.TestFailure() #FIX ME + +@cocotb.test() +async def addr_op_test(dut): + await dut_init(dut) + list_exp = doubly_linked_list(dut) + cocotb.log.info("SEED NUMBER = %d",cocotb.RANDOM_SEED) + await insert_at_addr(dut, list_exp, int(dut.head.value), 3) + await insert_at_addr(dut, list_exp, int(dut.head.value), 0) + await Timer(100, units='ns') + await insert_at_addr(dut, list_exp, int(dut.head.value), 5) + await insert_at_addr(dut, list_exp, int(dut.head.value), 6) + await insert_at_addr(dut, list_exp, list_exp.linked_list_addr[2], 7) + await insert_at_addr(dut, list_exp, 0, 3) + await insert_at_addr(dut, list_exp, int(dut.head.value), 4) + await insert_at_addr(dut, list_exp, int(dut.tail.value), 3) + await insert_at_addr(dut, list_exp, ADDR_NULL, 4) + await insert_at_addr(dut, list_exp, ADDR_NULL, 1) + await insert_at_addr(dut, list_exp, 0, 3) + await Timer(200, units='ns') + await read_n_front(dut, list_exp, len(list_exp.linked_list_value)) + await read_n_back(dut, list_exp, len(list_exp.linked_list_value)) + await Timer(500, units='ns') + await delete_value(dut, list_exp, 7) + await delete_at_addr(dut, list_exp, 0) + await delete_at_addr(dut, list_exp, 0) + await delete_value(dut, list_exp, 2) + await read_n_front(dut, list_exp, len(list_exp.linked_list_value)) + await delete_value(dut, list_exp, 4) + await delete_at_addr(dut, list_exp, 0) + await delete_at_addr(dut, list_exp, 7) + await delete_at_addr(dut, list_exp, int(dut.head.value)) + await delete_at_addr(dut, list_exp, int(dut.tail.value)-1) + await delete_at_addr(dut, list_exp, 0) + await Timer(500, units='ns') + + if (err_cnt > 0): + cocotb.log.error("Errors count = %d",err_cnt) + cocotb.result.TestError() #FIX ME diff --git a/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/sv/Makefile b/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/sv/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..97b6bb6aa2000f25a5287711e75721c537a02d38 --- /dev/null +++ b/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/sv/Makefile @@ -0,0 +1,38 @@ + +DUT ?= doubly_linked_list +SIM_OPTS ?= ../../src/doubly_linked_list.sv +SEED ?= $$(shuf -i 1-10000 -n 1) + +# DUT parameter #"-p" iverilog command flags +# COMPILE_ARGS = -P tb.DUT_DATA_WIDTH=8 +# COMPILE_ARGS += -P tb.DUT_MAX_NODE=8 +# COMPILE_ARGS += -P tb.TB_CLK_PERIOD=25 +# COMPILE_ARGS += -P tb.TB_TEST_WEIGHT=1 +# COMPILE_ARGS += -P tb.TB_CLK_PERIOD=100 +# COMPILE_ARGS += -P tb.SIM_TIMEOUT=500000 + +XILINX_LIB_URL ?= https://github.com/Xilinx/XilinxUnisimLibrary.git +XILINX_LIB_DIR ?= XilinxUnisimLibrary/verilog/src + +sim: gen_sim + ./${DUT}.sim +VCDFILE=sim.vcd +VCDLEVEL=0 +SEED=${SEED} | tee sim.log + +gen_sim: tb.sv ${SIM_OPTS} # to generate executable file by using iverilator + iverilog -g2012 -s tb ${COMPILE_ARGS} -o ${DUT}.sim $^ + +synth: ${SIM_OPTS} + yosys -p synth_xilinx ${SIM_OPTS} -L synth.log -o ${DUT}.netlist.v + #timeout + +netlist_sim: gen_netlist_sim + ./${DUT}.netlist.sim +VCDFILE=netlist_sim.vcd +VCDLEVEL=0 +SEED=${SEED} | tee netlist_sim.log + +gen_netlist_sim: tb.sv ${DUT}.netlist.v | ${XILINX_LIBS_DIR}/.got + iverilog -g2012 -s tb -y ${XILINX_LIB_DIR} -y ${XILINX_LIB_DIR}/unisims -DXILINX_GLS ${COMPILE_ARGS} -o ${DUT}.netlist.sim $^ + +${XILINX_LIBS_DIR}/.git: + git clone ${XILINX_LIB_URL} + +clean: + rm -f ${DUT}_sim sim.log sim.vcd + rm -f ${DUT}.netlist.v synth.log diff --git a/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/sv/tb.sv b/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/sv/tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..7f5955d4d07d16950c2bb1e74f6f3d8dedfa8d87 --- /dev/null +++ b/Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/sv/tb.sv @@ -0,0 +1,744 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Create Date: 09/22/2024 01:42:52 PM +// Module Name: tb +// Description: Supported Operation +// 0. Read_Addr(addr_in) -> data_out +// 1. Insert_At_Addr(addr_in, data_in) +// 5. Insert_At_Index(addr_in, data_in) +// 2. Delete_Value(data_in) +// 3. Delete_At_Addr(addr_in) +// 7. Delete_At_Index(addr_in) +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb( + ); + // DUT parameter + localparam DUT_DATA_WIDTH = 8; + localparam DUT_MAX_NODE = 8; + // TB parameter + localparam TB_CLK_PERIOD = 25; + localparam ADDR_WIDTH = $clog2(DUT_MAX_NODE+1); // Reserve {ADDR_WIDTH(1'b1)} as NULL/INVALID ADDR + localparam MAX_DATA = 2**DUT_DATA_WIDTH - 1; + localparam TB_TEST_WEIGHT = 1; + localparam SIM_TIMEOUT = 500000; + +localparam ADDR_NULL = (DUT_MAX_NODE); + +localparam OP_Read = 3'b000; +localparam OP_Insert_At_Addr = 3'b001; +localparam OP_Insert_At_Index = 3'b101; +localparam OP_Delete_Value = 3'b010; +localparam OP_Delete_At_Addr = 3'b011; +localparam OP_Delete_At_Index = 3'b111; + +integer err_cnt = 0; + +// input +reg clk = 0; +reg rst = 0; +reg [DUT_DATA_WIDTH-1:0] data_in = 0; +reg [ADDR_WIDTH-1:0] addr_in = 0; +reg [2:0] op = 0; +reg op_start = 0; +// output +wire [DUT_DATA_WIDTH-1:0] data_out; +wire op_done; +wire [ADDR_WIDTH-1:0] pre_node_addr; +wire [ADDR_WIDTH-1:0] next_node_addr; +wire [ADDR_WIDTH-1:0] length; +wire [ADDR_WIDTH-1:0] head; // Addr of head +reg [ADDR_WIDTH-1:0] pre_head; +wire [ADDR_WIDTH-1:0] tail; // Addr of tail +reg [ADDR_WIDTH-1:0] pre_tail; // Addr of tail +wire full; +wire empty; +wire fault; + +`ifdef XILINX_GLS + // for xilinx gate sim + glbl glbl(); +`endif + + doubly_linked_list #(.DATA_WIDTH(DUT_DATA_WIDTH),.MAX_NODE(DUT_MAX_NODE)) DUT + ( /*input*/ .rst(rst), + /*input*/ .clk(clk), + /*input [DATA_WIDTH-1:0]*/ .data_in(data_in), + /*input [ADDR_WIDTH-1:0]*/ .addr_in(addr_in), + /*input [1:0]*/ .op(op), // 0: Read(addr_in); 1: Delete_Value(data_in); 2: Push_Back(data_in); 3: Push_front(data_in) + /*input*/ .op_start(op_start), + /*output reg [DATA_WIDTH-1:0]*/ .data_out(data_out), + /*output reg*/ .op_done(op_done), + /*output wire [ADDR_WIDTH-1:0]*/ .pre_node_addr(pre_node_addr),// Addr of pre node + /*output wire [ADDR_WIDTH-1:0]*/ .next_node_addr(next_node_addr), // Addr of next node + // status + /*output reg [ADDR_WIDTH-1:0]*/ .length(length), + /*output wire*/ .full(full), + /*output reg [ADDR_WIDTH-1:0]*/ .head(head), // Addr of head + /*output reg [ADDR_WIDTH-1:0]*/ .tail(tail), // Addr of head + /*output wire*/ .empty(empty), + /*output reg*/ .fault(fault) // Invalid Errors + ); + +always #(TB_CLK_PERIOD/2) clk = ~clk; + +integer linked_list_exp[$]; +integer linked_list_addr[$]; // corresponding to linked_list_exp. +integer data_wr[$]; +integer i = 0; +integer next; +int dummy[$]; +int temp[$]; +integer temp2; + + +task list_print_contents(); + $write("%0t linked_list_exp = ", $realtime); + for (int i = 0; i < linked_list_exp.size(); i = i + 1) begin + $write("%0d ", linked_list_exp[i]); + end + $write("\n%0t linked_list_addr = ", $realtime); + for (int i = 0; i < linked_list_addr.size(); i = i + 1) begin + $write("%0d ", linked_list_addr[i]); + end + $write("\n"); +endtask + +task find_first_index (input integer addr); // input integer list[$], ref integer addr[$]); icarus does not support ref. +begin + temp = {}; + for (integer i = 0; i < linked_list_addr.size(); i = i + 1) begin + if(addr == linked_list_addr[i]) begin + temp.push_back(i); + $display("%0t Addr %0d found at Index %0d", $realtime, addr, i); + end + end +end +endtask + +task find_first_index2 (input integer addr); //avoid temp output conflict +begin + dummy = {}; + for (integer i = 0; i < linked_list_addr.size(); i = i + 1) begin + if(addr == linked_list_addr[i]) begin + dummy.push_back(i); + $display("%0t Addr %0d found at Index %0d", $realtime, addr, i); + end + end +end +endtask + +task find_next_addr (output integer next_addr); +begin + next_addr = 0; + for (int i = 0; i < (linked_list_addr.size()+1); i = i + 1) begin + dummy = {}; + //dummy = (linked_list_addr.find_first_index(x) with ( x == i )); // icarus does not support built in find_first_index method, so used workaround below. + find_first_index2(i); + if(dummy.size() == 0) begin + next_addr = i; + //break; //icarus does not support break statement, so used workaround below. + i = linked_list_addr.size()+1; + end + end + $display("%0t Next Addr = %0d", $realtime, next_addr); +end +endtask + +task read_n_front(input integer count); +begin + $display("%0t OP_Read from front %0d times", $realtime,count); + i = 0; + @(posedge (clk)); + #1 + op = OP_Read; + op_start = 1; + addr_in = head; + i = i + 1; + while (i<=count) begin + @(posedge (clk)); + #1 + if(op_done) begin + if( (i-1) >= linked_list_exp.size()) begin + if(fault) begin + $display("%0t Data read out of bound, fault flag is asserted correctly",$realtime); + end else begin + $error("%0t Data read out of bound, fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else if(data_out == linked_list_exp[i-1]) begin + $display("%0t Data read: %0d",$realtime,data_out); + end else begin + $error("%0t Data read: %0d, Data Exp: %0d", $realtime, data_out, linked_list_exp[i-1]); + err_cnt = err_cnt + 1; + end + if(i == count) begin + op_start = 0; + end else if ( ((i-1) == 0) && ((i-1) < linked_list_exp.size()-2) ) begin + if(next_node_addr != linked_list_addr[i]) begin + $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, linked_list_addr[i]); + err_cnt = err_cnt + 1; + end + if(pre_node_addr != ADDR_NULL) begin + $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, ADDR_NULL); + err_cnt = err_cnt + 1; + end + end else if ( ((i-1) > 0) && ((i-1) < linked_list_exp.size()-2) ) begin + if(next_node_addr != linked_list_addr[i]) begin + $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, linked_list_addr[i]); + err_cnt = err_cnt + 1; + end + if(pre_node_addr != linked_list_addr[i-2]) begin + $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, linked_list_addr[i-2]); + err_cnt = err_cnt + 1; + end + end else if ( (i-1) == linked_list_exp.size()-1) begin + if(next_node_addr != ADDR_NULL) begin + $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, ADDR_NULL); + err_cnt = err_cnt + 1; + end + if(pre_node_addr != linked_list_addr[i-2]) begin + $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, linked_list_addr[i-2]); + err_cnt = err_cnt + 1; + end + end + addr_in = next_node_addr; + i = i + 1; + end + end + // icarus does not support %p concanation, so used workaround below. + list_print_contents(); + //$display("%0t Complete OP_Read from front %0d times, linked_list_exp = %p", $realtime,count,linked_list_exp[0:(linked_list_exp.size()-1)]); + //$display("%0t Complete OP_Read from front %0d times, linked_list_addr = %p\n", $realtime,count,linked_list_addr[0:(linked_list_addr.size()-1)]); +end +endtask + +task read_n_back(input integer count); +begin + $display("%0t OP_Read from back %0d times", $realtime,count); + i = 0; + @(posedge (clk)); + #1 + op = OP_Read; + op_start = 1; + addr_in = tail; + i = i + 1; + while (i<=count) begin + @(posedge (clk)); + #1 + if(op_done) begin + if( (i-1) >= linked_list_exp.size()) begin + if(fault) begin + $display("%0t Data read out of bound, fault flag is asserted correctly",$realtime); + end else begin + $error("%0t Data read out of bound, fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else if(data_out == linked_list_exp[linked_list_exp.size()-1-(i-1)]) begin + $display("%0t Data read: %0d",$realtime,data_out); + end else begin + $error("%0t Data read: %0d, Data Exp: %0d", $realtime, data_out, linked_list_exp[linked_list_exp.size()-1-(i-1)]); + err_cnt = err_cnt + 1; + end + if(i == count) begin + op_start = 0; + end else if ( ((i-1) == 0) && ((i-1) < linked_list_exp.size()-2) ) begin + if(next_node_addr != ADDR_NULL) begin + $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, ADDR_NULL); + err_cnt = err_cnt + 1; + end + if(pre_node_addr != linked_list_addr[linked_list_exp.size()-1-(i-2)]) begin + $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, linked_list_addr[linked_list_exp.size()-1-(i-2)]); + err_cnt = err_cnt + 1; + end else if ( ((i-1) > 0) && ((i-1) < linked_list_exp.size()-2) ) begin + if(next_node_addr != linked_list_addr[linked_list_exp.size()-1-(i)]) begin + $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, linked_list_addr[linked_list_exp.size()-1-(i)]); + err_cnt = err_cnt + 1; + end + if(pre_node_addr != linked_list_addr[linked_list_exp.size()-1-(i-2)]) begin + $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, linked_list_addr[linked_list_exp.size()-1-(i-2)]); + err_cnt = err_cnt + 1; + end + end else if ( (i-1) == linked_list_exp.size()-1) begin + if(next_node_addr != linked_list_addr[linked_list_exp.size()-1-(i)]) begin + $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, linked_list_addr[linked_list_exp.size()-1-(i)]); + err_cnt = err_cnt + 1; + end + if(pre_node_addr != ADDR_NULL) begin + $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, ADDR_NULL); + err_cnt = err_cnt + 1; + end + end + end + addr_in = pre_node_addr; + i = i + 1; + end + end + // icarus does not support %p concanation, so used workaround below. + list_print_contents(); + // $display("%0t Complete OP_Read from back %0d times, linked_list_exp = %p", $realtime,count,linked_list_exp[0:(linked_list_exp.size()-1)]); + // $display("%0t Complete OP_Read from back %0d times, linked_list_addr = %p\n", $realtime,count,linked_list_addr[0:(linked_list_addr.size()-1)]); +end +endtask + +bit found = 0; + +task delete_value(input integer value); +begin + $display("%0t OP_Delete_Value %0d value", $realtime,value); + i = 0; + found = 0; + @(posedge (clk)); + #1 + op = OP_Delete_Value; + data_in = value; + op_start = 1; + wait (op_done) + #1 + for (int j = 0; j < linked_list_exp.size(); j=j+1) begin + if(value == linked_list_exp[j]) begin + $display("%0t Data %0d at Index %0d is Deleted_by_Value", $realtime, linked_list_exp[j],j); + linked_list_exp.delete(j); + linked_list_addr.delete(j); + found = 1; + //break; + j = linked_list_exp.size() + 1; + end + end + if (!found) begin + if(fault) begin + $display("%0t Data delete out of bound, fault flag is asserted correctly",$realtime); + end else begin + $error("%0t Data delete out of bound, fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else begin + if(fault) begin + $error("%0t fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + end + op_start = 0; + // icarus does not support %p concanation, so used workaround below. + list_print_contents(); + //$display("%0t Complete OP_Delete_Value %0d value, linked_list_exp = %p", $realtime,value,linked_list_exp[0:(linked_list_exp.size()-1)]); + //$display("%0t Complete OP_Delete_Value %0d value, linked_list_addr = %p\n", $realtime,value,linked_list_addr[0:(linked_list_addr.size()-1)]); +end +endtask + +task delete_at_index (input integer addr); +begin + $display("%0t OP_Delete_At_Index %0d index", $realtime,addr); + i = 0; + @(posedge (clk)); + #1 + op = OP_Delete_At_Index; + addr_in = addr; + op_start = 1; + + wait (op_done) + #1 + if( addr >= linked_list_exp.size()) begin + if(fault) begin + $display("%0t Data delete out of bound, fault flag is asserted correctly",$realtime); + end else begin + $error("%0t Data delete out of bound, fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else if ( addr == 0 ) begin + if(fault) begin + $error("%0t fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + $display("%0t Data %0d at Front is Deleted", $realtime, linked_list_exp[0]); + temp2 = linked_list_exp.pop_front(); + temp2 = linked_list_addr.pop_front(); + end else begin + if(fault) begin + $error("%0t fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + $display("%0t Data %0d at Index %0d is Deleted", $realtime, linked_list_exp[addr],addr); + linked_list_exp.delete(addr); + linked_list_addr.delete(addr); + end + if(linked_list_exp.size() == 0) begin + if(empty) begin + $display("%0t Queue is empty and empty flag is asserted correctly",$realtime); + end else begin + $error("%0t Queue is empty but empty flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else if(empty) begin + $error("%0t Empty flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + op_start = 0; + // icarus does not support %p concanation, so used workaround below. + list_print_contents(); + //$display("%0t Complete OP_Delete_At_Index %0d index, linked_list_exp = %p", $realtime,addr,linked_list_exp[0:(linked_list_exp.size()-1)]); + //$display("%0t Complete OP_Delete_At_Index %0d index, linked_list_addr = %p\n", $realtime,addr,linked_list_addr[0:(linked_list_addr.size()-1)]); +end +endtask + +task insert_at_index (input integer addr, input integer value); +begin + $display("%0t OP_Insert_At_Index %0d index, %0d value", $realtime,addr,value); + i = 0; + @(posedge (clk)); + #1 + op = OP_Insert_At_Index; + addr_in = addr; + data_in = value; + op_start = 1; + wait (op_done) + #1 + if(linked_list_exp.size() >= DUT_MAX_NODE) begin + if(!fault) begin + $error("%0t Fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end else begin + $display("%0t Fault flag is asserted correctly",$realtime); + end + end else if( addr == 0 ) begin + if(fault) begin + $error("%0t Fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + linked_list_exp.push_front(value); + find_next_addr(next); + linked_list_addr.push_front(next); + $display("%0t Data Written to Front : %0d",$realtime,value); + end else if ( addr >= linked_list_exp.size() ) begin + if(fault) begin + $error("%0t Fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + linked_list_exp.push_back(value); + find_next_addr(next); + linked_list_addr.push_back(next); + $display("%0t Data Written to Back : %0d",$realtime,value); + end else begin + if(fault) begin + $error("%0t Fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + linked_list_exp.insert(addr, value); + find_next_addr(next); + linked_list_addr.insert(addr, next); + $display("%0t Data Written to Index %0d : %0d",$realtime,addr,value); + end + if(linked_list_exp.size() >= (DUT_MAX_NODE)) begin + if(full) begin + $display("%0t Queue is full and full flag is asserted correctly",$realtime); + end else begin + $error("%0t Queue is full but full flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else if(full) begin + $error("%0t Full flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + op_start = 0; + // icarus does not support %p concanation, so used workaround below. + list_print_contents(); + //$display("%0t Complete OP_Insert_At_Index %0d index %0d value, linked_list_exp = %p", $realtime,addr,value,linked_list_exp[0:(linked_list_exp.size()-1)]); + //$display("%0t Complete OP_Insert_At_Index %0d index %0d value, linked_list_addr = %p\n", $realtime,addr,value,linked_list_addr[0:(linked_list_addr.size()-1)]); +end +endtask + +task delete_at_addr (input int addr); +begin + $display("%0t OP_Delete_At_Addr %0d Addr", $realtime,addr); + i = 0; + @(posedge (clk)); + #1 + op = OP_Delete_At_Addr; + addr_in = addr; + op_start = 1; + pre_head = head; + pre_tail = tail; + + wait (op_done) + #1 + if( addr >= ADDR_NULL) begin + if(fault) begin + $display("%0t Data delete out of bound, fault flag is asserted correctly",$realtime); + end else begin + $error("%0t Data delete out of bound, fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else if ( addr == pre_head ) begin + if(fault) begin + $error("%0t fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + $display("%0t Data %0d at Front is Deleted", $realtime, linked_list_exp[0]); + temp2 = linked_list_exp.pop_front(); + temp2 = linked_list_addr.pop_front(); + end else if ( addr == pre_tail ) begin + if(fault) begin + $error("%0t fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + $display("%0t Data %0d at Back is Deleted", $realtime, linked_list_exp[0]); + temp2 = linked_list_exp.pop_back(); + temp2 = linked_list_addr.pop_back(); + end else begin + temp = {}; + // for (int j = 0; j <1; j = j+1) begin + // temp = (linked_list_addr.find_first_index(x) with (x == addr)); + // end + find_first_index(addr); + if (temp.size() == 0) begin + if(!fault) begin + $error("%0t Fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end else begin + $display("%0t Fault flag is asserted correctly",$realtime); + end + end else begin + $display("%0t Data %0d at Addr %0d is Deleted", $realtime, linked_list_exp[temp[0]],linked_list_addr[temp[0]]); + linked_list_exp.delete(temp[0]); + linked_list_addr.delete(temp[0]); + end + end + if(linked_list_exp.size() == 0) begin + if(empty) begin + $display("%0t Queue is empty and empty flag is asserted correctly",$realtime); + end else begin + $error("%0t Queue is empty but empty flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else if(empty) begin + $error("%0t Empty flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + op_start = 0; + // icarus does not support %p concanation, so used workaround below. + list_print_contents(); + //$display("%0t Complete OP_Delete_At_Addr %0d addr, linked_list_exp = %p", $realtime,addr,linked_list_exp[0:(linked_list_exp.size()-1)]); + //$display("%0t Complete OP_Delete_At_Addr %0d addr, linked_list_addr = %p\n", $realtime,addr,linked_list_addr[0:(linked_list_addr.size()-1)]); +end +endtask + +task insert_at_addr (input int addr, input integer value); +begin + $display("%0t OP_Insert_At_Addr %0d addr, %0d value", $realtime,addr,value); + i = 0; + @(posedge (clk)); + #1 + op = OP_Insert_At_Addr; + addr_in = addr; + data_in = value; + op_start = 1; + pre_head = head; + pre_tail = tail; + wait (op_done) + #1 + if(linked_list_exp.size() >= DUT_MAX_NODE) begin + if(!fault) begin + $error("%0t Fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end else begin + $display("%0t Fault flag is asserted correctly",$realtime); + end + end else if( addr == pre_head ) begin + if(fault) begin + $error("%0t Fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + linked_list_exp.push_front(value); + find_next_addr(next); + linked_list_addr.push_front(next); + $display("%0t Data Written to Front : %0d",$realtime,value); + end else if( addr == pre_tail ) begin + if(fault) begin + $error("%0t Fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + linked_list_exp.insert(linked_list_exp.size()-1, value); + find_next_addr(next); + linked_list_addr.insert(linked_list_addr.size()-1, next); + $display("%0t Data Written to Back : %0d",$realtime,value); + end else if ( addr >= ADDR_NULL ) begin + if(fault) begin + $error("%0t Fault flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + linked_list_exp.push_back(value); + find_next_addr(next); + linked_list_addr.push_back(next); + $display("%0t Data Written to Back : %0d",$realtime,value); + end else begin + temp = {}; + // for (int j = 0; j <1; j = j+1) begin + // temp = (linked_list_addr.find_first_index(x) with (x == addr)); + // end + find_first_index(addr); + if (temp.size() == 0) begin + if(!fault) begin + $error("%0t Fault flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end else begin + $display("%0t Fault flag is asserted correctly",$realtime); + end + end else begin + linked_list_exp.insert(temp[0], value); + find_next_addr(next); + linked_list_addr.insert(temp[0], next); + $display("%0t Data Written to Addr %0d : %0d",$realtime,addr,value); + end + end + if(linked_list_exp.size() >= (DUT_MAX_NODE)) begin + if(full) begin + $display("%0t Queue is full and full flag is asserted correctly",$realtime); + end else begin + $error("%0t Queue is full but full flag is not asserted",$realtime); + err_cnt = err_cnt + 1; + end + end else if(full) begin + $error("%0t Full flag is asserted incorrectly",$realtime); + err_cnt = err_cnt + 1; + end + op_start = 0; + // icarus does not support %p concanation, so used workaround below. + list_print_contents(); + //$display("%0t Complete OP_Insert_At_Addr %0d addr %0d value, linked_list_exp = %p", $realtime,addr,value,linked_list_exp[0:(linked_list_exp.size()-1)]); + //$display("%0t Complete OP_Insert_At_Addr %0d addr %0d value, linked_list_addr = %p\n", $realtime,addr,value,linked_list_addr[0:(linked_list_addr.size()-1)]); +end +endtask + +task direct_index_op_test(); +begin + $display("\n======================================"); + $display("Direct Index Op Test"); + $display("======================================"); + //DIRECT TEST Index Mode + rst = 1'b1; + #100 + rst = 1'b0; + linked_list_exp = {}; + linked_list_addr = {}; + insert_at_index(0,3); + insert_at_index(0,0); + #100 + insert_at_index(4,5); + insert_at_index(0,6); + insert_at_index(0,7); + insert_at_index(1,3); + insert_at_index(2,4); + insert_at_index(ADDR_NULL,3); + insert_at_index(ADDR_NULL,4); + read_n_back(linked_list_exp.size()); + insert_at_index(ADDR_NULL,1); + insert_at_index(0,3); + #200 + read_n_front(linked_list_exp.size()); + #500 + delete_value(7); + delete_at_index(0); + read_n_back(linked_list_exp.size()); + delete_at_index(0); + delete_value(2); + delete_value(4); + delete_at_index(0); + read_n_front(linked_list_exp.size()); + delete_at_index(7); + delete_at_index(length-1); + delete_at_index(length-1); + delete_at_index(0); + delete_at_index(0); + delete_at_index(0); + #500; +end +endtask + +task direct_addr_op_test(); +begin + //DIRECT TEST Index Mode + $display("\n======================================"); + $display("Direct Address Op Test"); + $display("======================================"); + rst = 1'b1; + #100 + rst = 1'b0; + linked_list_exp = {}; + linked_list_addr = {}; + insert_at_addr(head,3); + insert_at_addr(head,0); + #100 + insert_at_addr(0,5); + insert_at_addr(head,6); + insert_at_addr(linked_list_addr[2],7); + insert_at_addr(tail,3); + insert_at_addr(head,4); + read_n_back(linked_list_exp.size()); + insert_at_addr(ADDR_NULL,3); + insert_at_addr(ADDR_NULL,4); + insert_at_addr(ADDR_NULL,1); + insert_at_addr(0,3); + #200 + read_n_front(linked_list_exp.size()); + #500 + delete_value(7); + read_n_front(linked_list_exp.size()); + delete_at_addr(0); + delete_at_addr(head); + delete_value(2); + read_n_front(linked_list_exp.size()); + read_n_back(linked_list_exp.size()); + delete_value(4); + read_n_front(linked_list_exp.size()); + delete_at_addr(head); + delete_at_addr(7); + delete_at_addr(tail); + delete_at_addr(tail-1); + delete_at_addr(0); + #500; +end +endtask + +initial begin + string vcdfile; + int vcdlevel; + int seed; + int temp; + + rst = 1'b1; + if ($value$plusargs("VCDFILE=%s",vcdfile)) + $dumpfile(vcdfile); + if ($value$plusargs("VCDLEVEL=%d",vcdlevel)) + $dumpvars(vcdlevel,tb); + if ($value$plusargs("SEED=%d",seed)) begin + temp = $urandom(seed); + $display("Seed = %d",seed); + end + + direct_index_op_test(); + + #1000; + + direct_addr_op_test(); + + //DIRECT TEST Index Mode + + if (err_cnt > 0) begin + $display("\n%0t TEST FAILED",$realtime); + $display("Error count = %d\n", err_cnt); + end else + $display("\n%0t TEST PASSED\n", $realtime); + $finish; +end + +initial begin + #(SIM_TIMEOUT) + $display("\n%0t TEST FAILED", $realtime); + $display("SIM TIMEOUT!\n"); + $finish; +end + +endmodule diff --git a/Weiyet_RTLStructLib/source/Doubly_Linked_List/vip/pyuvm/tests/__init__.py b/Weiyet_RTLStructLib/source/Doubly_Linked_List/vip/pyuvm/tests/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..80abe2d7cf1249f1c6ce871e4888ecc0b1422983 --- /dev/null +++ b/Weiyet_RTLStructLib/source/Doubly_Linked_List/vip/pyuvm/tests/__init__.py @@ -0,0 +1,13 @@ +""" +Doubly Linked List VIP Tests Package +Contains test classes for Doubly Linked List VIP +""" + +from .dll_vip_base_test import BaseTest +from .dll_vip_simple_test import SimpleTest, RandomTest + +__all__ = [ + 'BaseTest', + 'SimpleTest', + 'RandomTest', +] diff --git a/ttchisholm_10g-low-latency-ethernet/source/.gitignore b/ttchisholm_10g-low-latency-ethernet/source/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..3a9a2d2ee8668ec8b40944829afee4edb53ebb80 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/.gitignore @@ -0,0 +1,9 @@ +vivado_project/* +msim/* +*.log +doc/ +notes +.sv*.toml +.vscode/ +TODO +.Xil/ \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/.gitmodules b/ttchisholm_10g-low-latency-ethernet/source/.gitmodules new file mode 100644 index 0000000000000000000000000000000000000000..5cb5c00fc11bb934e098fe0655f3c7cfa7e7f1f0 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/.gitmodules @@ -0,0 +1,3 @@ +[submodule "src/ip/slicing_crc"] + path = src/lib/slicing_crc + url = git@github.com:ttchuk/slicing_crc.git diff --git a/ttchisholm_10g-low-latency-ethernet/source/.vscode/launch.json b/ttchisholm_10g-low-latency-ethernet/source/.vscode/launch.json new file mode 100644 index 0000000000000000000000000000000000000000..bd9eb70503d055bcbeb6b7b5ebf3f041ffe6314d --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/.vscode/launch.json @@ -0,0 +1,24 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "Python: Remote Attach", + "type": "python", + "request": "attach", + "connect": { + "host": "localhost", + "port": 5678 + }, + "pathMappings": [ + { + "localRoot": "${workspaceFolder}", + "remoteRoot": "${workspaceFolder}" + } + ], + "justMyCode": false + } + ] +} \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/LICENSE b/ttchisholm_10g-low-latency-ethernet/source/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..fc0f70f9bc9c5f88260f34d75b9219e7a38b6a09 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2023 Tom Chisholm + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/README.md b/ttchisholm_10g-low-latency-ethernet/source/README.md new file mode 100644 index 0000000000000000000000000000000000000000..15e472049bd65c09d38f3bffb5979d5b5409082a --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/README.md @@ -0,0 +1,58 @@ +# 10G Low Latency Ethernet + +[![cocotb-test](https://github.com/ttchisholm/10g-low-latency-ethernet/actions/workflows/cocotb-test.yaml/badge.svg?branch=master)](https://github.com/ttchisholm/10g-low-latency-ethernet/actions/workflows/cocotb-test.yaml) + +## Overview + +For more information, refer to my blog series for this project - [Designing a Low Latency 10G Ethernet Core - Part 1 (Introduction)](https://ttchisholm.github.io/ethernet/2023/05/01/designing-10g-eth-1.html) + +This repository contains: +- A low latency 10G Ethernet MAC/PCS, written in SystemVerilog and tested with pyuvm/cocotb +- An integrated low latency 10G Ethernet core, with MAC/PCS and GTY wrapper/IP for Xilinx UltraScale+ +- An example design containing packet latency measurement in loopback + +Repository structure: + +``` +.github/ # GitHub workflow +example/ # Example design +src/ # Ethernet core source + hdl/ # HDL source + ip/ # IP generation + lib/ # Submodules + tb/ # Testbenches +``` + +## Example Design + +**Building the example design:** + +1. Clone the slicing_crc submodule + +```console +git submodule update --init --recursive +``` + +2. Generate GTY IP. Set the FPGA part and GTY channel in *src/ip/gen_eth_10g_ip.sh* and run + +```console +cd src/ip +./gen_eth_10g_ip.sh +``` + +3. Modify the constraints file *example/constraints/example_10g_eth.xdc* with appropriate pin assignments. The design requires a 100MHz clock input for initialisation and a low-jitter 156.25MHz clock for the transceivers + +4. Build the example design. Set the FPGA part again in *example/build_example.sh* + +```console +cd example +./build_example.sh +Vivado> all +``` +**Running the example design:** + +1. Program the device in Vivado Hardware Manager +2. Add the VIOs +3. De-assert *core_reset* in *hw_vio1 (u_core_reset_vio)* +4. De-assert *packet_gen_reset* in *hw_vio3 (u_packet_control_vio)* +5. Capture on *hw_ila_2 (tx_packet_ila)* to observe latency \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/example/.gitignore b/ttchisholm_10g-low-latency-ethernet/source/example/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..000d41ef3166e8053d3484274a3185e2bd8aa606 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/example/.gitignore @@ -0,0 +1 @@ +build*/ \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/example/build_example.sh b/ttchisholm_10g-low-latency-ethernet/source/example/build_example.sh new file mode 100644 index 0000000000000000000000000000000000000000..b284c2808804975af5fa79842d26c43a78382d9f --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/example/build_example.sh @@ -0,0 +1,28 @@ +# !/bin/sh + +# Ensure IP is built using src/ip/gen_eth_10g_ip and part matches below. + +# Default build parameters +export FPGA_PART=xczu49dr-ffvf1760-2-e +export SCRAMBLER_BYPASS=0 +export EXTERNAL_GEARBOX=0 +export TX_XVER_BUFFER=0 +export INIT_CLK_FREQ=100.0 + +# get arguments k=v +build_config="" +for ARGUMENT in "$@" +do + KEY=$(echo $ARGUMENT | cut -f1 -d=) + + KEY_LENGTH=${#KEY} + VALUE="${ARGUMENT:$KEY_LENGTH+1}" + + export "$KEY"="$VALUE" + + build_config="${build_config}-${KEY}_${VALUE}" +done + +mkdir -p build$build_config +cd build$build_config +vivado -mode tcl -source ../example_10g_eth_build.tcl -notrace \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/example/example_10g_eth_build.tcl b/ttchisholm_10g-low-latency-ethernet/source/example/example_10g_eth_build.tcl new file mode 100644 index 0000000000000000000000000000000000000000..e7633d878741f101c2040a9535298f81b70a5b82 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/example/example_10g_eth_build.tcl @@ -0,0 +1,174 @@ +# Vivado build script + + +set module_vars {SCRAMBLER_BYPASS EXTERNAL_GEARBOX TX_XVER_BUFFER INIT_CLK_FREQ} +set build_vars [concat {FPGA_PART} $module_vars] + +foreach x $build_vars { + if {[info exists env($x)]} { + set $x $env($x) + puts "$x = $env($x)" + + } else { + puts "Environment variable $x not set, generate IP from shell script." + exit 1 + } +} + +global output_dir +global src_dir +global ip_dir +global flatten_hierarchy + +set project_name example_10g_eth +set output_dir ./out +set src_dir ../ + +set ip_dir ../../src/ip/gen +set core_src_dir ../../src +set core_src_include_dir ../../src/hdl/include +set lib_src_dir ../../src/lib + +set flatten_hierarchy none +set directive PerformanceOptimized +set fanout_limit 512 +set use_retiming 1 + +proc init {} { + + set_part $::FPGA_PART + set_property target_language Verilog [current_project] + + set_property source_mgmt_mode All [current_project] +} + +proc add_sources {} { + + read_verilog [glob $::src_dir/hdl/*.sv] -sv + read_verilog [glob $::core_src_dir/hdl/*.sv] -sv + read_verilog [glob $::core_src_dir/hdl/**/*.sv] -sv + read_verilog [glob $::core_src_dir/hdl/**/*.v] + read_verilog [glob $::lib_src_dir/**/**/*.sv] + + read_ip [glob $::ip_dir/**/*.xci] + + read_xdc [glob $::src_dir/constraints/*.xdc] + + set params "" + foreach x $::module_vars { + global $x + set params [concat $params "$x=[expr $$x]"] + } + set_property generic $params [current_fileset] +} + +proc gen_ip {} { + + # Out-Of-Context synthesis for IPs + foreach ip [get_ips] { + set ip_filename [get_property IP_FILE $ip] + set ip_dcp [file rootname $ip_filename] + append ip_dcp ".dcp" + set ip_xml [file rootname $ip_filename] + append ip_xml ".xml" + + if {([file exists $ip_dcp] == 0) || [expr {[file mtime $ip_filename ] > [file mtime $ip_dcp ]}]} { + + # re-generate the IP + generate_target all -force $ip + set_property generate_synth_checkpoint true [get_files $ip_filename] + synth_ip -force $ip + } + } +} + +proc synth {} { + + if { $::use_retiming == 1 } { + synth_design -top $::project_name -flatten_hierarchy $::flatten_hierarchy -directive $::directive \ + -include_dirs $::core_src_include_dir -retiming + } else { + synth_design -top $::project_name -flatten_hierarchy $::flatten_hierarchy -directive $::directive \ + -include_dirs $::core_src_include_dir + } + + + write_checkpoint -force $::output_dir/post_synth.dcp + report_timing_summary -file $::output_dir/post_synth_timing_summary.rpt + report_utilization -file $::output_dir/post_synth_util.rpt +} + +proc impl {} { + + # ensure debug hub connected to free running clock + connect_debug_port dbg_hub/clk [get_nets i_init_clk] + + opt_design -hier_fanout_limit $::fanout_limit + # opt_design + place_design + report_clock_utilization -file $::output_dir/clock_util.rpt + + #get timing violations and run optimizations if needed + if {[get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] < 0} { + puts "Found setup timing violations => running physical optimization" + phys_opt_design + } + write_checkpoint -force $::output_dir/post_place.dcp + report_utilization -file $::output_dir/post_place_util.rpt + report_timing_summary -file $::output_dir/post_place_timing_summary.rpt + + #Route design and generate bitstream + route_design -directive Explore + + # Re-run phys_opt if timing violations found + if {[get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] < 0} { + puts "Found setup timing violations => running physical optimization" + if { $::use_retiming == 1 } { + phys_opt_design -directive AddRetime + } else { + phys_opt_design + } + + } + + + write_checkpoint -force $::output_dir/post_route.dcp + report_route_status -file $::output_dir/post_route_status.rpt + report_timing_summary -file $::output_dir/post_route_timing_summary.rpt + report_power -file $::output_dir/post_route_power.rpt + report_drc -file $::output_dir/post_imp_drc.rpt +} + +proc output {} { + write_verilog -force $::output_dir/cpu_impl_netlist.v -mode timesim -sdf_anno true + write_debug_probes -force $::output_dir/$::project_name.ltx + + write_bitstream -force $::output_dir/$::project_name + write_bitstream -bin_file -force $::output_dir/$::project_name +} + +proc all {} { + init + add_sources + gen_ip + synth + impl + output +} + +proc start_synth {} { + init + add_sources + gen_ip + synth +} + +proc impl_out {} { + impl + output +} + +puts "Build options: " +puts " 'all' : Full build" +puts " 'start_synth' : Initialise, add sources and run synthesis" +puts " 'impl_out' : Run implementation and bitstream generation" diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/hdl/eth_10g.sv b/ttchisholm_10g-low-latency-ethernet/source/src/hdl/eth_10g.sv new file mode 100644 index 0000000000000000000000000000000000000000..3e8718681e26d6abfea1b369b61f404d949c8697 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/hdl/eth_10g.sv @@ -0,0 +1,198 @@ +// MIT License + +// Copyright (c) 2023 Tom Chisholm + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + +/* +* Module: eth_10g +* +* Description: Top-level low-latency 10G Ethernet Core. Includes MAC, PCS and Xilinx +* GTY instantiation. +* +* Note: +* A non-standard implementation of TUSER is used for the AXIS master. +* If TUSER is not asserted with TLAST, this indicates a packet was recieved with +* incorrect CRC. However, TLAST/TUSER can be asserted when all TKEEP == 0, this is to +* provide data for processing ASAP. This may cause TUSER to be dropped if routing +* the AXIS interface through interconnect. +* +*/ + +`timescale 1ns/1ps +`default_nettype none + +module eth_10g #( + parameter bit SCRAMBLER_BYPASS = 0, + parameter bit EXTERNAL_GEARBOX = 0, + parameter bit TX_XVER_BUFFER = 0, + parameter real INIT_CLK_FREQ = 100.0 +) ( + // Reset + initiliaszation + input wire i_reset, + input wire i_init_clk, + + // Differential reference clock inputs + input wire i_mgtrefclk0_x0y3_p, + input wire i_mgtrefclk0_x0y3_n, + + /* svlint off prefix_input */ + /* svlint off prefix_output */ + // Tx AXIS + output wire s00_axis_aclk, + input wire [31:0] s00_axis_tdata, + input wire [3:0] s00_axis_tkeep, + input wire s00_axis_tvalid, + output logic s00_axis_tready, + input wire s00_axis_tlast, + + // Rx AXIS + output wire m00_axis_aclk, + output logic [31:0] m00_axis_tdata, + output logic [3:0] m00_axis_tkeep, + output logic m00_axis_tvalid, + output logic m00_axis_tlast, + output logic m00_axis_tuser, + /* svlint on prefix_input */ + /* svlint on prefix_output */ + + // Serial data ports for transceiver channel 0 + input wire i_ch0_gtyrxn, + input wire i_ch0_gtyrxp, + output wire o_ch0_gtytxn, + output wire o_ch0_gtytxp, + + // Output tx/rx mac/pcs i_reset ports + output wire o_mac_pcs_tx_reset, + output wire o_mac_pcs_rx_reset +); + + // MAC/PCS i_reset + wire gtwiz_tx_ready; + wire gtwiz_rx_ready; + + assign o_mac_pcs_tx_reset = !gtwiz_tx_ready; + assign o_mac_pcs_rx_reset = !gtwiz_rx_ready; + + // Datapath + logic [31:0] pcs_xver_tx_data, xver_tx_data; + logic [1:0] pcs_xver_tx_header, xver_tx_header; + wire [31:0] pcs_xver_rx_data; + wire [1:0] pcs_xver_rx_header; + + // Clock + wire gtwiz_tx_usrclk2; + wire gtwiz_rx_usrclk2; + + // Gearbox + logic [5:0] pcs_xver_tx_gearbox_sequence, xver_tx_gearbox_sequence; + wire pcs_xver_rx_data_valid; + wire pcs_xver_rx_header_valid; + wire pcs_xver_rx_gearbox_slip; + + assign m00_axis_aclk = gtwiz_rx_usrclk2; + assign s00_axis_aclk = gtwiz_tx_usrclk2; + + mac_pcs #( + .SCRAMBLER_BYPASS(SCRAMBLER_BYPASS), + .EXTERNAL_GEARBOX(EXTERNAL_GEARBOX) + ) u_mac_pcs ( + .i_tx_reset(o_mac_pcs_tx_reset), + .i_rx_reset(o_mac_pcs_rx_reset), + .s00_axis_tdata(s00_axis_tdata), + .s00_axis_tkeep(s00_axis_tkeep), + .s00_axis_tvalid(s00_axis_tvalid), + .s00_axis_tready(s00_axis_tready), + .s00_axis_tlast(s00_axis_tlast), + .m00_axis_tdata(m00_axis_tdata), + .m00_axis_tkeep(m00_axis_tkeep), + .m00_axis_tvalid(m00_axis_tvalid), + .m00_axis_tlast(m00_axis_tlast), + .m00_axis_tuser(m00_axis_tuser), + .i_xver_rx_clk(gtwiz_rx_usrclk2), + .i_xver_rx_data(pcs_xver_rx_data), + .i_xver_rx_header(pcs_xver_rx_header), + .i_xver_rx_data_valid(pcs_xver_rx_data_valid), + .i_xver_rx_header_valid(pcs_xver_rx_header_valid), + .o_xver_rx_gearbox_slip(pcs_xver_rx_gearbox_slip), + .i_xver_tx_clk(gtwiz_tx_usrclk2), + .o_xver_tx_data(pcs_xver_tx_data), + .o_xver_tx_header(pcs_xver_tx_header), + .o_xver_tx_gearbox_sequence(pcs_xver_tx_gearbox_sequence) + ); + + + generate if (TX_XVER_BUFFER == 1) begin: l_tx_xver_buffer + always_ff @(posedge gtwiz_tx_usrclk2) + if (o_mac_pcs_tx_reset) begin + xver_tx_data <= '0; + xver_tx_header <= '0; + xver_tx_gearbox_sequence <= '0; + end else begin + xver_tx_data <= pcs_xver_tx_data; + xver_tx_header <= pcs_xver_tx_header; + xver_tx_gearbox_sequence <= pcs_xver_tx_gearbox_sequence; + end + end else begin: l_tx_xver_nobuf + assign xver_tx_data = pcs_xver_tx_data; + assign xver_tx_header = pcs_xver_tx_header; + assign xver_tx_gearbox_sequence = pcs_xver_tx_gearbox_sequence; + end + endgenerate + + gtwizard_wrapper #( + .INIT_CLK_FREQ(INIT_CLK_FREQ), + .EXTERNAL_GEARBOX(EXTERNAL_GEARBOX) + ) u_gtwizard_wrapper ( + + // Differential reference clock inputs + .mgtrefclk0_x0y3_p(i_mgtrefclk0_x0y3_p), + .mgtrefclk0_x0y3_n(i_mgtrefclk0_x0y3_n), + + // Serial data ports for transceiver channel 0 + .ch0_gtyrxn_in(i_ch0_gtyrxn), + .ch0_gtyrxp_in(i_ch0_gtyrxp), + .ch0_gtytxn_out(o_ch0_gtytxn), + .ch0_gtytxp_out(o_ch0_gtytxp), + + // User-provided ports for i_reset helper block(s) + .hb_gtwiz_reset_clk_freerun_in(i_init_clk), + .hb_gtwiz_reset_all_in(i_reset), + + // User data ports + .hb0_gtwiz_userdata_tx_int(xver_tx_data), + .hb0_gtwiz_header_tx(xver_tx_header), + .hb0_gtwiz_userdata_rx_int(pcs_xver_rx_data), + .hb0_gtwiz_header_rx(pcs_xver_rx_header), + + .hb0_gtwiz_rx_gearbox_slip(pcs_xver_rx_gearbox_slip), + .hb0_gtwiz_rx_data_valid(pcs_xver_rx_data_valid), + .hb0_gtwiz_rx_header_valid(pcs_xver_rx_header_valid), + .hb0_gtwiz_tx_gearbox_sequence(xver_tx_gearbox_sequence), + + // Transceiver user clock outputs + .hb0_gtwiz_userclk_tx_usrclk2(gtwiz_tx_usrclk2), + .hb0_gtwiz_userclk_rx_usrclk2(gtwiz_rx_usrclk2), + + // Transceiver ready/error outputs + .tx_ready(gtwiz_tx_ready), + .rx_ready(gtwiz_rx_ready) + ); + +endmodule diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/hdl/mac_pcs.sv b/ttchisholm_10g-low-latency-ethernet/source/src/hdl/mac_pcs.sv new file mode 100644 index 0000000000000000000000000000000000000000..8205c8cd033a5b4beb3c55f5bac4571be2ecfe98 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/hdl/mac_pcs.sv @@ -0,0 +1,155 @@ +// MIT License + +// Copyright (c) 2023 Tom Chisholm + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + +/* +* Module: mac_pcs +* +* Description: Integrated 10G MAC and PCS with AXIS user I/O. +* +* Note: +* A non-standard implementation of TUSER is used for the AXIS master. +* If TUSER is not asserted with TLAST, this indicates a packet was recieved with +* incorrect CRC. However, TLAST/TUSER can be asserted when all TKEEP == 0, this is to +* provide data for processing ASAP. This may cause TUSER to be dropped if routing +* the AXIS interface through interconnect. +*/ + +`timescale 1ns/1ps +`default_nettype none + +module mac_pcs #( + parameter bit SCRAMBLER_BYPASS = 0, + parameter bit EXTERNAL_GEARBOX = 0, + localparam int DATA_WIDTH = 32, + + localparam int DATA_NBYTES = DATA_WIDTH / 8 +) ( + input wire i_tx_reset, + input wire i_rx_reset, + + /* svlint off prefix_input */ + /* svlint off prefix_output */ + // Tx AXIS + input wire [DATA_WIDTH-1:0] s00_axis_tdata, + input wire [DATA_NBYTES-1:0] s00_axis_tkeep, + input wire s00_axis_tvalid, + output logic s00_axis_tready, + input wire s00_axis_tlast, + + // Rx AXIS + output logic [DATA_WIDTH-1:0] m00_axis_tdata, + output logic [DATA_NBYTES-1:0] m00_axis_tkeep, + output logic m00_axis_tvalid, + output logic m00_axis_tlast, + output logic m00_axis_tuser, + /* svlint on prefix_input */ + /* svlint on prefix_output */ + + // Rx XVER + input wire i_xver_rx_clk, + input wire [DATA_WIDTH-1:0] i_xver_rx_data, + input wire [1:0] i_xver_rx_header, + input wire i_xver_rx_data_valid, + input wire i_xver_rx_header_valid, + output wire o_xver_rx_gearbox_slip, + + // TX XVER + input wire i_xver_tx_clk, + output wire [DATA_WIDTH-1:0] o_xver_tx_data, + output wire [1:0] o_xver_tx_header, + output wire [5:0] o_xver_tx_gearbox_sequence +); + + wire [DATA_WIDTH-1:0] xgmii_rx_data, xgmii_tx_data; + wire [DATA_NBYTES-1:0] xgmii_rx_ctl, xgmii_tx_ctl; + wire phy_rx_valid, phy_tx_ready; + wire [DATA_NBYTES-1:0] term_loc; + + mac u_mac ( + .i_tx_reset(i_tx_reset), + .i_rx_reset(i_rx_reset), + + // Tx PHY + .i_tx_clk(i_xver_tx_clk), + .o_xgmii_tx_data(xgmii_tx_data), + .o_xgmii_tx_ctl(xgmii_tx_ctl), + .i_phy_tx_ready(phy_tx_ready), + + // Tx AXIS + .s00_axis_tdata(s00_axis_tdata), + .s00_axis_tkeep(s00_axis_tkeep), + .s00_axis_tvalid(s00_axis_tvalid), + .s00_axis_tready(s00_axis_tready), + .s00_axis_tlast(s00_axis_tlast), + + // Rx PHY + .i_rx_clk(i_xver_rx_clk), + .i_xgmii_rx_data(xgmii_rx_data), + .i_xgmii_rx_ctl(xgmii_rx_ctl), + .i_phy_rx_valid(phy_rx_valid), + .i_term_loc(term_loc), + + // Rx AXIS + .m00_axis_tdata(m00_axis_tdata), + .m00_axis_tkeep(m00_axis_tkeep), + .m00_axis_tvalid(m00_axis_tvalid), + .m00_axis_tlast(m00_axis_tlast), + .m00_axis_tuser(m00_axis_tuser) + ); + + + pcs #( + .SCRAMBLER_BYPASS(SCRAMBLER_BYPASS), + .EXTERNAL_GEARBOX(EXTERNAL_GEARBOX), + .ENCODER_OCODE_SUPPORT(0) // Mac doesn't generate OCODES, disable to relieve timing pressure + ) u_pcs ( + + // Reset logic + .i_tx_reset(i_tx_reset), + .i_rx_reset(i_rx_reset), + + // Rx from tranceiver + .i_xver_rx_clk(i_xver_rx_clk), + .i_xver_rx_data(i_xver_rx_data), + .i_xver_rx_header(i_xver_rx_header), + .i_xver_rx_data_valid(i_xver_rx_data_valid), + .i_xver_rx_header_valid(i_xver_rx_header_valid), + .o_xver_rx_gearbox_slip(o_xver_rx_gearbox_slip), + + //Rx interface out + .o_xgmii_rx_data(xgmii_rx_data), + .o_xgmii_rx_ctl(xgmii_rx_ctl), + .o_xgmii_rx_valid(phy_rx_valid), // Non standard XGMII - required for no CDC + .o_term_loc(term_loc), + + .i_xver_tx_clk(i_xver_tx_clk), + .i_xgmii_tx_data(xgmii_tx_data), + .i_xgmii_tx_ctl(xgmii_tx_ctl), + .o_xgmii_tx_ready(phy_tx_ready), // Non standard XGMII - required for no CDC + + // TX Interface out + .o_xver_tx_data(o_xver_tx_data), + .o_xver_tx_header(o_xver_tx_header), + .o_xver_tx_gearbox_sequence(o_xver_tx_gearbox_sequence) + ); + +endmodule diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/ip/.gitignore b/ttchisholm_10g-low-latency-ethernet/source/src/ip/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..44adb22c29d9df7919e98ee0a1a81683901de6e3 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/ip/.gitignore @@ -0,0 +1,2 @@ +vivado_project/ +gen/ \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/ip/eth_10g_ip.tcl b/ttchisholm_10g-low-latency-ethernet/source/src/ip/eth_10g_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..ac40aab50686b04ea60843b1a1d8fea9be4f41c1 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/ip/eth_10g_ip.tcl @@ -0,0 +1,67 @@ +if {[info exists env(ETH10G_FPGA_PART)]} { + set FPGA_PART $env(ETH10G_FPGA_PART) + puts "FPGA_PART = ${FPGA_PART}" +} else { + puts "Environment variable ETH10G_FPGA_PART not set, generate IP from shell script." + exit 1 +} + +if {[info exists env(ETH10G_CHANNEL)]} { + set CHANNEL $env(ETH10G_CHANNEL) + puts "CHANNEL = ${CHANNEL}" +} else { + puts "Environment variable ETH10G_CHANNEL not set, generate IP from shell script." + exit 1 +} + +# IP project setup +create_project -in_memory -part $FPGA_PART +set_property target_language Verilog [current_project] +set_property source_mgmt_mode All [current_project] + +# Transceiver - with gearbox +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -version 1.7 -module_name gtwizard_ultrascale_inc_gearbox -dir . -force +set_property -dict [list CONFIG.CHANNEL_ENABLE ${CHANNEL} CONFIG.TX_MASTER_CHANNEL ${CHANNEL} CONFIG.RX_MASTER_CHANNEL ${CHANNEL} \ + CONFIG.TX_REFCLK_FREQUENCY {156.25} CONFIG.TX_DATA_ENCODING {64B66B} CONFIG.TX_USER_DATA_WIDTH {32} \ + CONFIG.TX_BUFFER_MODE {0} CONFIG.TX_OUTCLK_SOURCE {TXPROGDIVCLK} CONFIG.RX_REFCLK_FREQUENCY {156.25} \ + CONFIG.RX_DATA_DECODING {64B66B} CONFIG.RX_USER_DATA_WIDTH {32} CONFIG.RX_INT_DATA_WIDTH {32} \ + CONFIG.RX_BUFFER_MODE {0} CONFIG.RX_REFCLK_SOURCE {} CONFIG.TX_REFCLK_SOURCE {} \ + CONFIG.LOCATE_TX_USER_CLOCKING {CORE} CONFIG.LOCATE_RX_USER_CLOCKING {CORE} \ + CONFIG.TXPROGDIV_FREQ_ENABLE {false} CONFIG.FREERUN_FREQUENCY {100} CONFIG.ENABLE_OPTIONAL_PORTS {loopback_in}] [get_ips gtwizard_ultrascale_inc_gearbox] +generate_target all [get_ips gtwizard_ultrascale_inc_gearbox] + +# Transceiver - without gearbox +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -version 1.7 -module_name gtwizard_ultrascale_raw -dir . -force +set_property -dict [list CONFIG.CHANNEL_ENABLE ${CHANNEL} CONFIG.TX_MASTER_CHANNEL ${CHANNEL} CONFIG.RX_MASTER_CHANNEL ${CHANNEL} \ + CONFIG.TX_REFCLK_FREQUENCY {156.25} CONFIG.TX_DATA_ENCODING {RAW} CONFIG.TX_USER_DATA_WIDTH {32} \ + CONFIG.TX_BUFFER_MODE {0} CONFIG.TX_OUTCLK_SOURCE {TXPROGDIVCLK} CONFIG.RX_REFCLK_FREQUENCY {156.25} \ + CONFIG.RX_DATA_DECODING {RAW} CONFIG.RX_USER_DATA_WIDTH {32} CONFIG.RX_INT_DATA_WIDTH {32} \ + CONFIG.RX_BUFFER_MODE {0} CONFIG.RX_REFCLK_SOURCE {} CONFIG.TX_REFCLK_SOURCE {} \ + CONFIG.LOCATE_TX_USER_CLOCKING {CORE} CONFIG.LOCATE_RX_USER_CLOCKING {CORE} \ + CONFIG.TXPROGDIV_FREQ_ENABLE {false} CONFIG.FREERUN_FREQUENCY {100} CONFIG.ENABLE_OPTIONAL_PORTS {loopback_in}] [get_ips gtwizard_ultrascale_raw] +generate_target all [get_ips gtwizard_ultrascale_raw] + + +# Transceiver bringup VIO + +create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name gtwizard_ultrascale_0_vio_0 -dir . -force +set_property -dict [list CONFIG.C_PROBE_IN7_WIDTH {2} CONFIG.C_PROBE_IN6_WIDTH {2} CONFIG.C_PROBE_IN5_WIDTH {2} CONFIG.C_PROBE_IN4_WIDTH {2} \ + CONFIG.C_PROBE_IN3_WIDTH {4} CONFIG.C_PROBE_OUT6_INIT_VAL {0x2} CONFIG.C_PROBE_OUT6_WIDTH {3} \ + CONFIG.C_NUM_PROBE_OUT {7} CONFIG.C_NUM_PROBE_IN {14} \ + CONFIG.Component_Name {gtwizard_ultrascale_0_vio_0}] [get_ips gtwizard_ultrascale_0_vio_0] +generate_target all [get_ips gtwizard_ultrascale_0_vio_0] + + +# Example core control VIO + +create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name eth_core_control_vio -dir . -force +set_property -dict [list CONFIG.C_PROBE_OUT2_INIT_VAL {0xBEEF0000} CONFIG.C_PROBE_OUT1_INIT_VAL {0x100} CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} CONFIG.C_PROBE_OUT2_WIDTH {32} CONFIG.C_PROBE_OUT1_WIDTH {16} CONFIG.C_NUM_PROBE_OUT {3} CONFIG.C_EN_PROBE_IN_ACTIVITY {0} CONFIG.C_NUM_PROBE_IN {0}] [get_ips eth_core_control_vio] +generate_target all [get_ips eth_core_control_vio] + +# Packet monitor ILAs + +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name example_packet_ila -dir . -force +set_property -dict [list CONFIG.C_DATA_DEPTH {131072} CONFIG.C_NUM_OF_PROBES {7} CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {4} CONFIG.C_PROBE5_WIDTH {16}] [get_ips example_packet_ila] +generate_target all [get_ips example_packet_ila] + +exit 0 \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/ip/gen_eth_10g_ip.sh b/ttchisholm_10g-low-latency-ethernet/source/src/ip/gen_eth_10g_ip.sh new file mode 100644 index 0000000000000000000000000000000000000000..ad74ead52ae79cbd75e3b146f80bf987da3a2efb --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/ip/gen_eth_10g_ip.sh @@ -0,0 +1,8 @@ +# !/bin/sh + +export ETH10G_FPGA_PART=xczu49dr-ffvf1760-2-e +export ETH10G_CHANNEL=X0Y12 + +mkdir -p gen +cd gen +vivado -mode tcl -source ../eth_10g_ip.tcl \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/.gitignore b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..f2825ef1f93228c2bda15b9102cbd5a8eb750195 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/.gitignore @@ -0,0 +1,6 @@ +__pycache__ +sim_build +*.fst* +*.vcd +*.xml +iverilog_dump.v \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/Makefile b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e6401783e3c6b1e51d88c8c2d385c58b57eb3ba6 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/Makefile @@ -0,0 +1,53 @@ +# Makefile + +# defaults +SIM ?= icarus +TOPLEVEL_LANG ?= verilog +WAVES ?= 1 + +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/rx_gearbox.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/tx_gearbox.sv + + +# MODULE is the basename of the Python test file +MODULE ?= test_rx_gearbox + + +ifeq ($(MODULE), test_tx_gearbox) + TOPLEVEL ?= tx_gearbox +endif + +ifeq ($(MODULE), test_rx_gearbox) + TOPLEVEL ?= rx_gearbox +endif + +export REGISTER_OUTPUT ?= 0 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += -P $(TOPLEVEL).REGISTER_OUTPUT=$(REGISTER_OUTPUT) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif + +endif + +# include cocotb's make rules to take care of the simulator setup +include $(shell cocotb-config --makefiles)/Makefile.sim + + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf crc32.mem + @rm -rf dump.fst $(TOPLEVEL).fst \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/gearbox_model.ipynb b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/gearbox_model.ipynb new file mode 100644 index 0000000000000000000000000000000000000000..c234863d6b7a0c04bd329d08c144074da96d308f --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/gearbox_model.ipynb @@ -0,0 +1,214 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "import numpy as np\n", + "from gearbox_model import RxGearboxModel, TxGearboxModel\n", + "import matplotlib.pyplot as plt" + ] + }, + { + "attachments": {}, + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Tx Gearbox" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "\n", + "n_frames = 200\n", + "header = [[f'{y:02d}-H0{x}' for x in range(2)] for y in range(n_frames)]\n", + "data = [[f'{y:02d}-D{x:02d}' for x in range(64)] for y in range(n_frames)]\n", + "\n", + "\n", + "txg = TxGearboxModel('str')\n", + "txg_odata = []\n", + "\n", + "print(txg.get_state_header())\n", + "\n", + "for h, d in zip(header, data):\n", + " for _ in range(2):\n", + " idata = d[32:] if txg.get_frame_word() else d[:32]\n", + " ret = txg.next(h, idata)\n", + " txg_odata.append(ret['data'])\n", + " print(txg.get_state())\n", + "\n", + " if (ret['pause']):\n", + " ret = txg.next(h, idata)\n", + " txg_odata.append(ret['data'])\n", + " print(txg.get_state())" + ] + }, + { + "attachments": {}, + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Rx Gearbox - no slip" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "rxg = RxGearboxModel('str')\n", + "\n", + "rxg_oheader =[]\n", + "rxg_odata = []\n", + "\n", + "for id in txg_odata:\n", + " ret = rxg.next(id)\n", + " print(rxg.get_state())\n", + "\n", + " if ret['header_valid']:\n", + " rxg_oheader.append(ret['header'])\n", + "\n", + " if ret['data_valid']:\n", + " rxg_odata.append(ret['data'])" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "# check the data\n", + "\n", + "# stitch the data back together in to frames\n", + "\n", + "\n", + "\n", + "oframes = [list(np.concatenate([x,y])) for x,y in zip(rxg_odata[::2], rxg_odata[1::2])]\n", + "\n", + "\n", + "head_match = [ih == oh for ih, oh in zip(header, rxg_oheader)]\n", + "data_match = [id == od for id, od in zip(data, oframes)]\n", + "\n", + "plt.plot(head_match)\n", + "plt.plot(data_match)" + ] + }, + { + "attachments": {}, + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Rx Gearbox - half slip needed" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "# try with 1 slip out\n", + "rx_idata = txg_odata.copy()\n", + "rx_idata = [item for sublist in rx_idata for item in sublist]\n", + "for _ in range(1): rx_idata.insert(0, 'XXX')\n", + "\n", + "def chunks(lst, n):\n", + " \"\"\"Yield successive n-sized chunks from lst.\"\"\"\n", + " for i in range(0, len(lst), n):\n", + " yield lst[i:i + n]\n", + "\n", + "rx_idata = list(chunks(rx_idata, 32))[:-1]" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "rxg = RxGearboxModel('str')\n", + "slip_next = False\n", + "\n", + "rxg_oheader = []\n", + "rxg_odata = []\n", + "aligned_idx = 0\n", + "aligned = False\n", + "\n", + "for i, id in enumerate(rx_idata):\n", + " ret = rxg.next(id, slip_next)\n", + " print(rxg.get_state())\n", + "\n", + " if not aligned:\n", + " aligned = ('H00' in ret['header'][0] and 'H01' in ret['header'][1]) and ret['header_valid'] \n", + "\n", + " slip_next = ret['header_valid'] and not aligned and not slip_next \n", + "\n", + " if ret['header_valid'] and aligned:\n", + " rxg_oheader.append(ret['header'])\n", + " rxg_odata.append([]) # append data placeholder\n", + "\n", + " if ret['data_valid'] and aligned:\n", + " rxg_odata[-1] = list(np.concatenate([rxg_odata[-1], ret['data']]))\n" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [ + "start_offset = 20 # if half slip, miss frame when first aligning\n", + "\n", + "# align the rx / test data\n", + "\n", + "start_idx = 0\n", + "for i in range(len(header)):\n", + " if header[i] == rxg_oheader[start_offset]:\n", + " start_idx = i\n", + " print(f'Aligned at {i}')\n", + "\n", + "head_match = [ih == oh for ih, oh in zip(header[start_idx:], rxg_oheader[start_offset:])]\n", + "data_match = [id == od for id, od in zip(data[start_idx:], rxg_odata[start_offset:])]\n", + "plt.plot(head_match)\n", + "plt.plot(data_match)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "metadata": {}, + "outputs": [], + "source": [] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.8.10" + }, + "orig_nbformat": 4 + }, + "nbformat": 4, + "nbformat_minor": 2 +} diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/gearbox_model.py b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/gearbox_model.py new file mode 100644 index 0000000000000000000000000000000000000000..c6f782d2b9d9aa3ef681a2501a12c2846cb31663 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/gearbox_model.py @@ -0,0 +1,165 @@ + + +class RxGearboxModel: + def __init__(self, type='int'): + if type == 'str': + self.obuf = ['XXX' for _ in range(67)] # Extra bit for half slip + else: + self.obuf = [0 for _ in range(67)] + self.cycle = 0 + self.half_slip = 0 + + + def next(self, idata, slip=False): + + self.slip = slip + self.count = int(self.cycle % 33) + + + if not self.half_slip: + self.valid = self.count != 0 + self.frame_word = int(self.count % 2 == 0) + self.output_header = int(self.count % 2 == 1) + else: + self.valid = self.count != 31 + self.frame_word = int(self.count % 2 == 0) and self.count != 32 + self.output_header = (int(self.count % 2 == 1) or self.count == 32) and self.valid + + data_idxs = [00,32,64,30,62,28,60,26,58,24,56,22,54,20,52,18,50,16,48,14,46,12,44,10,42,8,40,6,38,4,36,2,34] + + # if self.count % 2 == 0: + # idata_idx = (66 - self.count) % 66 + # obuf[idata_idx:66] = idata[0 : self.count] + # obuf[0:32-self.count] = idata[self.count:] + + # else: + # idata_idx = ((66 - self.count - 32) - 1) % 66 + # obuf[idata_idx : self.idata_idx + 32] = idata + + # bit select method + + for bit in range(len(self.obuf)): + + self.idata_idx = data_idxs[self.count] + + if self.count % 2 == 0: + if self.idata_idx != 0 and bit >= self.idata_idx and bit < 66: + self.obuf[bit] = idata[bit-self.idata_idx] + elif bit < 32 - self.count: + self.obuf[bit] = idata[self.count + bit] + else: + if bit >= self.idata_idx and bit < self.idata_idx + 32: + self.obuf[bit] = idata[bit - self.idata_idx] + + self.obuf[66] = self.obuf[0] + + if self.half_slip % 2 == 0: + self.odata = self.obuf[2 : 34] if self.frame_word == 0 else self.obuf[34:66] + self.oheader = self.obuf[0:2] + else: + self.odata = self.obuf[3 : 35] if self.frame_word == 0 else self.obuf[35:67] + self.oheader = self.obuf[1:3] + + ret = { + 'data' : self.odata, + 'header' : self.oheader, + 'data_valid' : self.valid, + 'header_valid' : self.output_header, + 'obuf' : self.obuf, + 'cycle' : self.cycle, + 'count' : self.count, + 'frame_word' : self.frame_word + } + + if not self.slip: + self.cycle = self.cycle + 1 + + if slip: + self.half_slip = (self.half_slip + 1) % 2 + + return ret + + + + + def get_state(self): + + return f'{self.count:03d}\t{self.slip:b}\t{self.valid}\t{int(self.output_header)}\t{self.idata_idx:02d}\t{self.oheader}\t{self.odata}' + + +class TxGearboxModel: + def __init__(self, type='int'): + if type == 'str': + self.obuf = ['XXX' for _ in range(66)] + else: + self.obuf = [0 for _ in range(66)] + self.cycle = 0 + self.half_slip = 0 + self.count = int(self.cycle % 33) + self.pause = self.count == 32 + + + + def next(self, iheader, idata): + + self.count = int(self.cycle % 33) + self.pause = self.count == 32 + self.frame_word = int(self.count % 2 == 1) + self.load_header = int(self.count % 2 == 0) + self.header_idx = self.count if self.load_header else -1 + self.data_idx = self.count + 2 if self.load_header else self.count + 1 + + + + # obuf[0:32] = obuf[32:64] + # if not self.pause: + # if self.load_header: + # obuf[self.header_idx:self.header_idx+2] = header + # obuf[self.data_idx:self.data_idx+32] = data[self.frame_word*32 : 32 + self.frame_word*32] + + # odata.append(obuf[0:32]) + + # bit select method + for bit in range(len(self.obuf)): + if bit < 32: + self.obuf[bit] = self.obuf[bit+32] + + if not self.pause: + if self.load_header: + if bit >= self.header_idx and bit < self.header_idx + 2: + self.obuf[bit] = iheader[bit-self.header_idx] + + if bit >= self.data_idx and bit < self.data_idx + 32: + self.obuf[bit] = idata[bit - self.data_idx] + + self.odata = self.obuf[:32] + + self.cycle = self.cycle + 1 + + return { + 'data' : self.odata, + 'pause' : self.pause, + 'obuf' : self.obuf, + 'cycle' : self.cycle + } + + def get_frame_word(self): + self.count = int(self.cycle % 33) + self.frame_word = int(self.count % 2 == 1) + return self.frame_word + + def get_pause(self): + self.count = int(self.cycle % 33) + self.pause = self.count == 32 + return self.pause + + def get_count(self): + self.count = int(self.cycle % 33) + return self.count + + def get_state(self): + + return f'{self.count:03d}\t{self.pause}\t{int(self.load_header)}\t{self.header_idx:02d}\t{self.data_idx:02d}\t{int(self.frame_word)}\t{self.odata}' + + def get_state_header(self): + return f'count\tpause\theader?\theader_idx\tdata_idx\tframe_word\todata' \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_gearboxes.py b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_gearboxes.py new file mode 100644 index 0000000000000000000000000000000000000000..e12315677c5bb5df160d08f7a18ffe9eb5e5585c --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_gearboxes.py @@ -0,0 +1,48 @@ +import pytest +import os + +from cocotb_test.simulator import run + +@pytest.mark.parametrize( + "parameters", [ + {"REGISTER_OUTPUT": "0"}, + ]) +def test_rx_gearbox(parameters): + + sim_build = "./sim_build/rx_gearbox" + os.makedirs(sim_build, exist_ok=True) + + run( + verilog_sources=['../../hdl/pcs/rx_gearbox.sv'], + toplevel="rx_gearbox", + + module="test_rx_gearbox", + simulator="icarus", + verilog_compile_args=["-g2012"], + includes=["../hdl", "../../", "../../../"], + parameters=parameters, + extra_env=parameters, + sim_build=sim_build + ) + +@pytest.mark.parametrize( + "parameters", [ + {"REGISTER_OUTPUT": "0"}, + ]) +def test_tx_gearbox(parameters): + + sim_build = "./sim_build/tx_gearbox" + os.makedirs(sim_build, exist_ok=True) + + run( + verilog_sources=['../../hdl/pcs/tx_gearbox.sv'], + toplevel="tx_gearbox", + + module="test_tx_gearbox", + simulator="icarus", + verilog_compile_args=["-g2012"], + includes=["../hdl", "../../", "../../../"], + parameters=parameters, + extra_env=parameters, + sim_build=sim_build + ) \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_rx_gearbox.py b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_rx_gearbox.py new file mode 100644 index 0000000000000000000000000000000000000000..59f81d1eaad1660f86b59ae60aaf13bf136d11d8 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_rx_gearbox.py @@ -0,0 +1,163 @@ +from asyncore import loop +import asyncio +import enum +import cocotb +import numpy as np +from gearbox_model import RxGearboxModel + +from cocotb.triggers import Timer, RisingEdge, FallingEdge, Edge, NextTimeStep +from cocotb.clock import Clock + +import debugpy + + +class RxGearboxTb: + def __init__(self, dut): + self.dut = dut + + self.clk_period = round(1 / (10.3125 / 32), 2) # ps precision + cocotb.start_soon(Clock(dut.i_clk, self.clk_period, units="ns").start()) + self.dut.i_reset.value = 1 + self.dut.i_slip.value = 0 + self.dut.i_data.value = 0 + + + async def reset(self): + self.dut.i_reset.value = 0 + await RisingEdge(self.dut.i_clk) + self.dut.i_reset.value = 1 + await RisingEdge(self.dut.i_clk) + self.dut.i_reset.value = 0 + + +@cocotb.test() +async def rx_gearbox_test_no_slip(dut): + + # debugpy.listen(5678) + # debugpy.wait_for_client() + # debugpy.breakpoint() + + + tb = RxGearboxTb(dut) + + await tb.reset() + + # Generate random data + gen_idata = [np.random.randint(0,2,32) for _ in range(100)] + + # Create ref model + model = RxGearboxModel() + + + tb.dut.i_data.value=0 + + for id in gen_idata: + for i in range(len(id)): + tb.dut.i_data[i].value = int(id[i]) + + await FallingEdge(tb.dut.i_clk) # Give the sim a tick to update the comb outputs + + dut_odata = str(tb.dut.o_data.value)[::-1] + dut_oheader = str(tb.dut.o_header.value)[::-1] + dut_odata_valid = str(tb.dut.o_data_valid.value) + dut_oheader_valid = str(tb.dut.o_header_valid.value) + dut_obuf = str(tb.dut.next_obuf.value)[::-1] + + await RisingEdge(tb.dut.i_clk) + + ret = model.next(id) + + model_odata = ''.join([str(x) for x in ret['data']]) + model_oheader = ''.join([str(x) for x in ret['header']]) + model_odata_valid = str(int(ret['data_valid'])) + model_oheader_valid = str(int(ret['header_valid'])) + model_obuf = ''.join([str(x) for x in ret['obuf']]) + + + all_eq = model_odata == dut_odata and \ + model_oheader == dut_oheader and \ + model_odata_valid == dut_odata_valid and \ + model_oheader_valid == dut_oheader_valid + + if not all_eq: + print('dut data: ', dut_odata_valid, dut_odata) + print('model data: ', model_odata_valid, model_odata) + print('dut header: ', dut_oheader_valid, dut_oheader) + print('model header:', model_oheader_valid, model_oheader) + print('dut buf: ', dut_obuf) + print('model buf:', model_obuf) + print('dut cycle: ', tb.dut.gearbox_seq.value) + print('model cycle: ', ret['cycle']) + print('input data: ', str(tb.dut.i_data.value)[::-1]) + assert all_eq + +@cocotb.test() +async def rx_gearbox_test_slip(dut): + + # debugpy.listen(5678) + # debugpy.wait_for_client() + # debugpy.breakpoint() + + for n_slips in list(range(34)): + + tb = RxGearboxTb(dut) + + await tb.reset() + + # Generate random data + gen_idata = [np.random.randint(0,2,32) for _ in range(1000)] + + # Create ref model + model = RxGearboxModel() + + tb.dut.i_data.value=0 + + for i, id in enumerate(gen_idata): + + slip = i < n_slips and np.random.randint(0,20) == 0 + + for i in range(len(id)): + tb.dut.i_data[i].value = int(id[i]) + + tb.dut.i_slip.value = int(slip) + + await FallingEdge(tb.dut.i_clk) + + dut_odata = str(tb.dut.o_data.value)[::-1] + dut_oheader = str(tb.dut.o_header.value)[::-1] + dut_odata_valid = str(tb.dut.o_data_valid.value) + dut_oheader_valid = str(tb.dut.o_header_valid.value) + dut_obuf = str(tb.dut.next_obuf.value)[::-1] + + await RisingEdge(tb.dut.i_clk) + + ret = model.next(id, slip) + + model_odata = ''.join([str(x) for x in ret['data']]) + model_oheader = ''.join([str(x) for x in ret['header']]) + model_odata_valid = str(int(ret['data_valid'])) + model_oheader_valid = str(int(ret['header_valid'])) + model_obuf = ''.join([str(x) for x in ret['obuf']]) + + + all_eq = model_odata == dut_odata and \ + model_oheader == dut_oheader and \ + model_odata_valid == dut_odata_valid and \ + model_oheader_valid == dut_oheader_valid + + if not all_eq: + print('dut data: ', dut_odata_valid, dut_odata) + print('model data: ', model_odata_valid, model_odata) + print('dut header: ', dut_oheader_valid, dut_oheader) + print('model header:', model_oheader_valid, model_oheader) + print('dut buf: ', dut_obuf) + print('model buf:', model_obuf) + print('dut cycle: ', tb.dut.gearbox_seq.value) + print('model cycle: ', ret['cycle']) + print('input data: ', str(tb.dut.i_data.value)[::-1]) + assert all_eq + + + + + \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_tx_gearbox.py b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_tx_gearbox.py new file mode 100644 index 0000000000000000000000000000000000000000..1ff0dc7c6e0ccb3c7e618cbcb98bdd9092130a80 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/gearbox/test_tx_gearbox.py @@ -0,0 +1,112 @@ +from asyncore import loop +import asyncio +import enum +import cocotb +import numpy as np +from gearbox_model import TxGearboxModel + +from cocotb.triggers import Timer, RisingEdge, FallingEdge, Edge, NextTimeStep +from cocotb.clock import Clock + +import debugpy + +class TxGearboxTb: + def __init__(self, dut): + self.dut = dut + + self.clk_period = round(1 / (10.3125 / 32), 2) # ps precision + cocotb.start_soon(Clock(dut.i_clk, self.clk_period, units="ns").start()) + self.dut.i_reset.value = 1 + self.dut.i_data.value = 0 + self.dut.i_header.value = 0 + + + async def reset(self): + self.dut.i_reset.value = 0 + await RisingEdge(self.dut.i_clk) + self.dut.i_reset.value = 1 + await RisingEdge(self.dut.i_clk) + self.dut.i_reset.value = 0 + + + +@cocotb.test() +async def tx_gearbox_test(dut): + + # debugpy.listen(5678) + # debugpy.wait_for_client() + # debugpy.breakpoint() + + + tb = TxGearboxTb(dut) + + await tb.reset() + + # Generate random data + np.random.seed(0) + gen_idata = [np.random.randint(0,2,64) for _ in range(200)] + gen_iheader = [np.random.randint(0,2,2) for _ in range(200)] + + # gen_iheader = [[f'{y:02d}-H0{x}' for x in range(2)] for y in range(20)] + # gen_idata = [[f'{y:02d}-D{x:02d}' for x in range(64)] for y in range(20)] + + # Create ref model + model = TxGearboxModel('str') + + + async def run_cycle(iheader, idata): + + for i in range(len(iheader)): + tb.dut.i_header[i].value = int(iheader[i]) + + for i in range(len(idata)): + tb.dut.i_data[i].value = int(idata[i]) + + tb.dut.i_gearbox_seq.value = model.get_count() + tb.dut.i_pause.value = model.get_pause() + + await FallingEdge(tb.dut.i_clk) # Give the sim a tick to update the comb outputs + + dut_odata = str(tb.dut.o_data.value)[::-1] + dut_obuf = str(tb.dut.next_obuf.value)[::-1] + + await RisingEdge(tb.dut.i_clk) + + ret = model.next(iheader, idata) + + model_odata = ''.join([str(x) for x in ret['data']]) + model_obuf = ''.join([str(x) for x in ret['obuf']]) + + all_eq = model_odata == dut_odata + + if not all_eq: + print('OK' if all_eq else 'FAIL') + print('seq: ', int(tb.dut.i_gearbox_seq.value)) + print('pause: ', tb.dut.i_pause.value) + print('dut data: ', dut_odata) + print('model data: ', model_odata) + print('input data: ', str(tb.dut.i_data.value)[::-1]) + print('input header: ', str(tb.dut.i_header.value)[::-1]) + + assert all_eq + + return ret + + + + tb.dut.i_data.value = 0 + + for ih, id in zip(gen_iheader, gen_idata): + for _ in range(2): + + idata = id[32:] if model.get_frame_word() else id[:32] + + ret = await run_cycle(ih, idata) + + if (ret['pause']): # do another cycle with same data + ret = await run_cycle(ih, idata) + + + + + \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/.gitignore b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..4b61a22bec243c7a737f43fe2fe1e38b5d02bf69 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/.gitignore @@ -0,0 +1,7 @@ +__pycache__ +sim_build +*.fst +*.vcd +*.xml +iverilog_dump.v +crc_tables.mem \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/Makefile b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..90217fbb11956341d0a2d072e56b1fc97e7db5c3 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/Makefile @@ -0,0 +1,62 @@ +# Makefile + +# defaults +SIM ?= icarus +TOPLEVEL_LANG ?= verilog +WAVES ?= 1 + +VERILOG_SOURCES += $(PWD)/../../hdl/include/code_defs_pkg.svh +VERILOG_SOURCES += $(PWD)/../../hdl/mac/mac.sv +VERILOG_SOURCES += $(PWD)/../../hdl/mac/tx_mac.sv +VERILOG_SOURCES += $(PWD)/../../hdl/mac/rx_mac.sv +VERILOG_SOURCES += $(PWD)/../../lib/slicing_crc/hdl/slicing_crc.sv + + + +CUSTOM_SIM_DEPS += crc_tables.mem + + +# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file +TOPLEVEL = mac + +# MODULE is the basename of the Python test file +MODULE = test_mac + + + +# module parameters +export DATA_WIDTH ?= 32 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(DATA_WIDTH) + COMPILE_ARGS += -I $(PWD)/../../hdl/include + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif + +endif + +# include cocotb's make rules to take care of the simulator setup +include $(shell cocotb-config --makefiles)/Makefile.sim + + + +crc_tables.mem: $(PWD)/../../lib/slicing_crc/hdl/crc_tables.mem + cp $< $@ + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf crc32.mem + @rm -rf dump.fst $(TOPLEVEL).fst \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/test_mac.py b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/test_mac.py new file mode 100644 index 0000000000000000000000000000000000000000..042463758c1f85d0b27c82990ccb740fe7aa29b7 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac/test_mac.py @@ -0,0 +1,215 @@ +from asyncore import loop +import asyncio +import enum +import cocotb +from cocotb.triggers import Timer, RisingEdge, FallingEdge, Edge, NextTimeStep +from cocotb.clock import Clock +from cocotb.result import TestFailure + +import debugpy + + +class MAC_TB: + def __init__(self, dut, loopback=False): + self.dut = dut + + self.data_width = len(self.dut.o_xgmii_tx_data) + self.data_nbytes = self.data_width // 8 + self.clk_period = round(1 / (10.3125 / self.data_width), 2) # ps precision + + cocotb.start_soon(Clock(dut.i_tx_clk, self.clk_period, units="ns").start()) + cocotb.start_soon(Clock(dut.i_rx_clk, self.clk_period, units="ns").start()) + + if loopback: + cocotb.start_soon(self.loopback('o_xgmii_tx_data', 'i_xgmii_rx_data')) + cocotb.start_soon(self.loopback('o_xgmii_tx_ctl', 'i_xgmii_rx_ctl')) + + + + self.dut.s00_axis_tvalid.value = 0 + self.dut.s00_axis_tdata.value = 0 + self.dut.s00_axis_tkeep.value = 0 + self.dut.s00_axis_tlast.value = 0 + + + async def change_reset(self, val): + self.dut.i_tx_reset.value = val + self.dut.i_rx_reset.value = val + + await RisingEdge(self.dut.i_tx_clk) + await RisingEdge(self.dut.i_rx_clk) + + + async def reset(self): + await self.change_reset(0) + await self.change_reset(1) + self.dut.i_tx_reset.value = 0 + self.dut.i_rx_reset.value = 0 + + async def loopback(self, output, input): + while True: + await Edge(getattr(self.dut, output)) + getattr(self.dut, input).value = getattr(self.dut, output).value + + + +@cocotb.test() +async def tx_test(dut): + tb = MAC_TB(dut, True) + + dut.i_phy_tx_ready.value = 1 + + await tb.reset() + + dut.s00_axis_tkeep.value = int(2**tb.data_nbytes - 1) + await RisingEdge(dut.i_tx_clk) + + test_vectors = [ + [ + int("0x00", 16), int("0x10", 16), int("0xA4", 16), int("0x7B", 16), int("0xEA", 16), + ], + [ + int("0x00", 16), int("0x10", 16), int("0xA4", 16), int("0x7B", 16), int("0xEA", 16), int("0x80", 16), + int("0x00", 16), int("0x12", 16), int("0x34", 16), int("0x56", 16), int("0x78", 16), int("0x90", 16), + int("0x08", 16), int("0x00", 16), int("0x45", 16), int("0x00", 16), int("0x00", 16), int("0x2E", 16), + int("0xB3", 16), int("0xFE", 16), int("0x00", 16), int("0x00", 16), int("0x80", 16), int("0x11", 16), + int("0x05", 16), int("0x40", 16), int("0xC0", 16), int("0xA8", 16), int("0x00", 16), int("0x2C", 16), + int("0xC0", 16), int("0xA8", 16), int("0x00", 16), int("0x04", 16), int("0x04", 16), int("0x00", 16), + int("0x04", 16), int("0x00", 16), int("0x00", 16), int("0x1A", 16), int("0x2D", 16), int("0xE8", 16), + int("0x00", 16), int("0x01", 16), int("0x02", 16), int("0x03", 16), int("0x04", 16), int("0x05", 16), + int("0x06", 16), int("0x07", 16), int("0x08", 16), int("0x09", 16), int("0x0A", 16), int("0x0B", 16), + int("0x0C", 16), int("0x0D", 16), int("0x0E", 16), int("0x0F", 16), int("0x10", 16), int("0x11", 16) + ], + [ int("0x08", 16), int("0x00", 16), int("0x20", 16), int("0x77", 16), int("0x05", 16), int("0x38", 16), int("0x0e", 16), int("0x8b", 16), + int("0x00", 16), int("0x00", 16), int("0x00", 16), int("0x00", 16), int("0x08", 16), int("0x00", 16), int("0x45", 16), int("0x00", 16), + int("0x00", 16), int("0x28", 16), int("0x1c", 16), int("0x66", 16), int("0x00", 16), int("0x00", 16), int("0x1b", 16), int("0x06", 16), + int("0x9e", 16), int("0xd7", 16), int("0x00", 16), int("0x00", 16), int("0x59", 16), int("0x4d", 16), int("0x00", 16), int("0x00", 16), + int("0x68", 16), int("0xd1", 16), int("0x39", 16), int("0x28", 16), int("0x4a", 16), int("0xeb", 16), int("0x00", 16), int("0x00", 16), + int("0x30", 16), int("0x77", 16), int("0x00", 16), int("0x00", 16), int("0x7a", 16), int("0x0c", 16), int("0x50", 16), int("0x12", 16), + int("0x1e", 16), int("0xd2", 16), int("0x62", 16), int("0x84", 16), int("0x00", 16), int("0x00", 16), int("0x00", 16), int("0x00", 16), + int("0x00", 16), int("0x00", 16), int("0x00", 16), int("0x00", 16) + ], + [ int("0x08", 16), int("0xdd", 16), int("0x20", 16), int("0x77", 16), int("0x05", 16), int("0x38", 16), int("0x0e", 16), int("0x8b", 16), + int("0xd3", 16), int("0xd4", 16), int("0xd5", 16), int("0xd6", 16), int("0x08", 16), int("0xdd", 16), int("0x45", 16), int("0xdd", 16), + int("0xdd", 16), int("0x28", 16), int("0x1c", 16), int("0x66", 16), int("0xd8", 16), int("0xda", 16), int("0x1b", 16), int("0x06", 16), + int("0x9e", 16), int("0xd7", 16), int("0x08", 16), int("0xdd", 16), int("0x20", 16), int("0x77", 16), int("0x05", 16), int("0x38", 16), int("0x0e", 16), int("0x8b", 16), + int("0xd3", 16), int("0xd4", 16), int("0xd5", 16), int("0xd6", 16), int("0x08", 16), int("0xdd", 16), int("0x45", 16), int("0xdd", 16), + int("0xdd", 16), int("0x28", 16), int("0x1c", 16), int("0x66", 16), int("0xd8", 16), int("0xda", 16), int("0x1b", 16), int("0x06", 16), + int("0x9e", 16), int("0xd7", 16), int("0xd8", 16) + ] + ] + + # concatonate the test vector to match the input width + # https://stackoverflow.com/questions/434287/how-to-iterate-over-a-list-in-chunks + def chunker(seq, size): + return (seq[pos:pos + size] for pos in range(0, len(seq), size)) + + # debugpy.listen(5678) + # debugpy.wait_for_client() + # debugpy.breakpoint() + + async def print_out(): + while(True): + await RisingEdge(dut.i_tx_clk) + print(f'{int(tb.dut.o_xgmii_tx_data.value):08x}') + + cocotb.start_soon(print_out()) + + + for tv in test_vectors: + + timeout = 0 + + tvc = list(chunker(tv, tb.data_nbytes)) + + for i, ivalues in enumerate(tvc): + + while tb.dut.s00_axis_tready.value == 0: + tb.dut.s00_axis_tvalid.value = 0 + timeout += 1 + await RisingEdge(dut.i_tx_clk) + assert timeout < 40, 'Waiting for tx ready timed out' + + ivalue = 0 + ivalid = 0 + for k, v in enumerate(ivalues): + ivalue = ivalue | (v << (k * 8)) + ivalid = ivalid | (1 << k) + + tb.dut.s00_axis_tdata.value = ivalue + tb.dut.s00_axis_tkeep.value = ivalid + tb.dut.s00_axis_tvalid.value = 1 + tb.dut.s00_axis_tlast.value = int(i == len(tvc) - 1) + + await RisingEdge(dut.i_tx_clk) + + + tb.dut.s00_axis_tvalid.value = 0 + tb.dut.s00_axis_tdata.value = 0 + tb.dut.s00_axis_tlast.value = 0 + + await RisingEdge(dut.i_tx_clk) + + for _ in range(20): + await RisingEdge(dut.i_tx_clk) + +@cocotb.test() +async def rx_test(dut): + tb = MAC_TB(dut) + + eg_xgmii_data = {64: [ + (int("0b11111111", 2), int("0x0707070707070707", 16)), + (int("0b00000001", 2), int("0xd5555555555555fb", 16)), + (int("0b00000000", 2), int("0x8b0e380577200008", 16)), + (int("0b00000000", 2), int("0x0045000800000000", 16)), + (int("0b00000000", 2), int("0x061b0000661c2800", 16)), + (int("0b00000000", 2), int("0x00004d590000d79e", 16)), + (int("0b00000000", 2), int("0x0000eb4a2839d168", 16)), + (int("0b00000000", 2), int("0x12500c7a00007730", 16)), + (int("0b00000000", 2), int("0x000000008462d21e", 16)), + (int("0b00000000", 2), int("0x79f7eb9300000000", 16)), + (int("0b11111111", 2), int("0x07070707070707fd", 16)), + (int("0b11111111", 2), int("0x0707070707070707", 16)) + ], + 32: [ + (int("0b1111", 2), int("0x07070707", 16)), + (int("0b1111", 2), int("0x07070707", 16)), + (int("0b0001", 2), int("0x555555fb", 16)), + (int("0b0000", 2), int("0xd5555555", 16)), + (int("0b0000", 2), int("0x77200008", 16)), + (int("0b0000", 2), int("0x8b0e3805", 16)), + (int("0b0000", 2), int("0x00000000", 16)), + (int("0b0000", 2), int("0x00450008", 16)), + (int("0b0000", 2), int("0x661c2800", 16)), + (int("0b0000", 2), int("0x061b0000", 16)), + (int("0b0000", 2), int("0x0000d79e", 16)), + (int("0b0000", 2), int("0x00004d59", 16)), + (int("0b0000", 2), int("0x2839d168", 16)), + (int("0b0000", 2), int("0x0000eb4a", 16)), + (int("0b0000", 2), int("0x00007730", 16)), + (int("0b0000", 2), int("0x12500c7a", 16)), + (int("0b0000", 2), int("0x8462d21e", 16)), + (int("0b0000", 2), int("0x00000000", 16)), + (int("0b0000", 2), int("0x00000000", 16)), + (int("0b0000", 2), int("0x79f7eb93", 16)), + (int("0b1111", 2), int("0x070707fd", 16)), + (int("0b1111", 2), int("0x07070707", 16)), + (int("0b1111", 2), int("0x07070707", 16)), + (int("0b1111", 2), int("0x07070707", 16)) + ]} + + + + tb.dut.i_xgmii_rx_data.value = 0 + tb.dut.i_xgmii_rx_ctl.value = 0 + tb.dut.i_phy_rx_valid.value = 1 + + await tb.reset() + + for (ctl, data) in eg_xgmii_data[tb.data_width]: + tb.dut.i_xgmii_rx_data.value = data + tb.dut.i_xgmii_rx_ctl.value = ctl + + await RisingEdge(dut.i_rx_clk) + + diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/.gitignore b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..aaa0a149c35828146e198b9e2e7f010dbd45ad14 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/.gitignore @@ -0,0 +1,14 @@ +__pycache__ +sim_build +*.fst +*.vcd +*.xml +iverilog_dump.v +crc_tables.mem +*.hier + +transcript +modelsim.ini +vsim.wlf +*.ucdb +covhtmlreport \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/Makefile b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..bffde1591523f74581bfcdb5d5bf89b9c619168f --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/Makefile @@ -0,0 +1,92 @@ +# Makefile + +# defaults +SIM ?= icarus +TOPLEVEL_LANG ?= verilog +WAVES ?= 1 + +VERILOG_SOURCES += $(PWD)/../../hdl/include/code_defs_pkg.svh +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/pcs.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/decoder.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/encoder.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/rx_gearbox.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/tx_gearbox.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/gearbox_seq.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/lock_state.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/scrambler.sv + +VERILOG_SOURCES += $(PWD)/../../hdl/mac/mac.sv +VERILOG_SOURCES += $(PWD)/../../hdl/mac/tx_mac.sv +VERILOG_SOURCES += $(PWD)/../../hdl/mac/rx_mac.sv + +VERILOG_SOURCES += $(PWD)/../../hdl/mac_pcs.sv + +VERILOG_SOURCES += $(PWD)/../../lib/slicing_crc/hdl/slicing_crc.sv + + +CUSTOM_SIM_DEPS += crc_tables.mem + + +# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file +TOPLEVEL = mac_pcs + +# MODULE is the basename of the Python test file +MODULE = test_mac_pcs + +# module parameters +export SCRAMBLER_BYPASS ?= 0 +export EXTERNAL_GEARBOX ?= 0 +export DATA_WIDTH ?= 32 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += -P $(TOPLEVEL).SCRAMBLER_BYPASS=$(SCRAMBLER_BYPASS) + COMPILE_ARGS += -P $(TOPLEVEL).EXTERNAL_GEARBOX=$(EXTERNAL_GEARBOX) + COMPILE_ARGS += -I $(PWD)/../../hdl/include + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), modelsim) + COMPILE_ARGS += "+incdir+$(PWD)/../../hdl/include" + COMPILE_ARGS += +cover=sbceft + + SIM_ARGS += -GSCRAMBLER_BYPASS=$(SCRAMBLER_BYPASS) + SIM_ARGS += -GEXTERNAL_GEARBOX=$(EXTERNAL_GEARBOX) + + SIM_ARGS += -coverage + SIM_ARGS += -no_autoacc + SIM_ARGS += -do \" coverage save -onexit $(TOPLEVEL).ucdb; run -all;exit\" +endif +# "Veriliator currently does not work with cocotb verilog-axi" +# else ifeq ($(SIM), verilator) + +# COMPILE_ARGS += -GSCRAMBLER_BYPASS=$(SCRAMBLER_BYPASS) +# COMPILE_ARGS += -GEXTERNAL_GEARBOX=$(EXTERNAL_GEARBOX) +# COMPILE_ARGS += -I$(PWD)/../../hdl/include + +# ifeq ($(WAVES), 1) +# COMPILE_ARGS += --trace-fst --trace-structs +# endif +# endif + +# include cocotb's make rules to take care of the simulator setup +include $(shell cocotb-config --makefiles)/Makefile.sim + +crc_tables.mem: $(PWD)/../../lib/slicing_crc/hdl/crc_tables.mem + cp $< $@ + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf crc_tables.mem + @rm -rf dump.fst $(TOPLEVEL).fst \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/mac_pcs_bfm.py b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/mac_pcs_bfm.py new file mode 100644 index 0000000000000000000000000000000000000000..38448564f757336dc6495022c108b1be1f56f7c8 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/mac_pcs_bfm.py @@ -0,0 +1,240 @@ +# MIT License + +# Copyright (c) 2023 Tom Chisholm + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +""" + mac_pcs_bfm.py + + Pyuvm Bus Fuctional Model (BFM) for mac_pcs module. + +""" + +import logging +import debugpy + +import cocotb +from cocotb.triggers import RisingEdge, FallingEdge, Edge +from cocotb.queue import QueueEmpty, Queue +from cocotb.clock import Clock + +from cocotbext.axi import (AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamMonitor) + +from pyuvm import * + +class MacPcsBfm(metaclass=utility_classes.Singleton): + def __init__(self): + self.dut = cocotb.top + self.config = ConfigDB().get(None, "", 'run_config') + self.tx_driver_queue = Queue(maxsize=1) + self.tx_monitor_queue = Queue(maxsize=0) + self.rx_monitor_queue = Queue(maxsize=0) + + self.tx_axis_source = AxiStreamSource(AxiStreamBus.from_prefix(self.dut, "s00_axis"), + self.dut.i_xver_tx_clk, self.dut.i_rx_reset) + + + self.tx_axis_monitor = AxiStreamMonitor(AxiStreamBus.from_prefix(self.dut, "s00_axis"), + self.dut.i_xver_tx_clk, self.dut.i_rx_reset) + + + self.rx_axis_monitor = AxiStreamMonitor(AxiStreamBus.from_prefix(self.dut, "m00_axis"), + self.dut.i_xver_rx_clk, self.dut.i_tx_reset) + + + def set_axis_log(self, enable): + self.tx_axis_source.log.propagate = enable + self.tx_axis_monitor.log.propagate = enable + self.rx_axis_monitor.log.propagate = enable + + async def loopback(self, cycle_delay, bit_delay): + async def capture_outputs(self, q, cycle_delay, bit_delay): + for _ in range(cycle_delay): await q.put([0, 0, 0, 0]) + prev_tx_gearbox_seq = 0 + prev_data_bits = 0 + + while True: + await RisingEdge(self.dut.i_xver_tx_clk) + + o_xver_tx_data = self.dut.o_xver_tx_data.value + o_xver_tx_header = self.dut.o_xver_tx_header.value + xver_tx_data_valid = self.dut.o_xver_tx_gearbox_sequence.value != self.gearbox_pause_val + + xver_tx_header_valid = self.dut.o_xver_tx_gearbox_sequence.value != prev_tx_gearbox_seq and xver_tx_data_valid + prev_tx_gearbox_seq = self.dut.o_xver_tx_gearbox_sequence.value + + # As we don't fully model external gearbox, only support bit slips for internal + if bit_delay > 0 and self.dut.EXTERNAL_GEARBOX.value == 0: + tx_data_noslip = o_xver_tx_data + o_xver_tx_data = ((o_xver_tx_data << bit_delay) | prev_data_bits) & 0xFFFFFFFF + prev_data_bits = (tx_data_noslip >> (32 - bit_delay)) & ((1 << bit_delay) - 1) + + await q.put([o_xver_tx_data, o_xver_tx_header, xver_tx_data_valid, xver_tx_header_valid]) + + async def apply_input(self, q): + while True: + await RisingEdge(self.dut.i_xver_rx_clk) + [o_xver_tx_data, o_xver_tx_header, xver_tx_data_valid, xver_tx_header_valid] = await q.get() + + self.dut.i_xver_rx_data.value = o_xver_tx_data + if self.dut.EXTERNAL_GEARBOX.value: + self.dut.i_xver_rx_header.value = o_xver_tx_header + self.dut.i_xver_rx_data_valid.value = xver_tx_data_valid + self.dut.i_xver_rx_header_valid.value = xver_tx_header_valid + else: + self.dut.i_xver_rx_header.value = 0 + self.dut.i_xver_rx_data_valid.value = 0 + self.dut.i_xver_rx_header_valid.value = 0 + + q = Queue() + cocotb.start_soon(capture_outputs(self, q, cycle_delay, bit_delay)) + cocotb.start_soon(apply_input(self, q)) + + async def send_tx_packet(self, packet): + await self.tx_driver_queue.put(packet) + + async def reset(self): + self.dut.i_tx_reset.value = 1 + self.dut.i_rx_reset.value = 1 + self.dut.i_xver_rx_clk.value = 0 + self.dut.i_xver_rx_data.value = 0 + self.dut.i_xver_tx_clk.value = 0 + await RisingEdge(self.dut.i_xver_rx_clk) + await RisingEdge(self.dut.i_xver_tx_clk) + await FallingEdge(self.dut.i_xver_rx_clk) + await FallingEdge(self.dut.i_xver_tx_clk) + self.dut.i_tx_reset.value = 0 + self.dut.i_rx_reset.value = 0 + await RisingEdge(self.dut.i_xver_rx_clk) + await RisingEdge(self.dut.i_xver_tx_clk) + + async def pause(self, cycles): + for _ in range(cycles): + await RisingEdge(self.dut.i_xver_tx_clk) + + async def driver_bfm(self): + while True: + packet = await self.tx_driver_queue.get() + await self.tx_axis_source.send(packet.tobytes()) + await self.tx_axis_source.wait() + + + async def tx_monitor_bfm(self): + while True: + packet = await self.tx_axis_monitor.recv() + self.tx_monitor_queue.put_nowait(packet) + + async def rx_monitor_bfm(self): + while True: + packet = await self.rx_axis_monitor.recv(compact=False) + packet = self.compact_axis_no_tuser(packet) + self.rx_monitor_queue.put_nowait(packet) + + async def get_tx_frame(self): + return await self.tx_monitor_queue.get() + + async def get_rx_frame(self): + return await self.rx_monitor_queue.get() + + + async def start_bfm(self): + self.data_width = len(self.dut.xgmii_tx_data) + self.data_nbytes = self.data_width // 8 + self.gearbox_pause_val = 32 + self.clk_period = round(1 / (10.3125 / self.data_width), 2) # ps precision + + cocotb.start_soon(Clock(self.dut.i_xver_tx_clk, self.clk_period, units="ns").start()) + cocotb.start_soon(Clock(self.dut.i_xver_rx_clk, self.clk_period, units="ns").start()) + + + await self.reset() + cocotb.start_soon(self.loopback(self.config['loopback_cycle_slip'], self.config['loopback_bit_slip'])) + + # manual slip for idles - debugging w/out scrambler + if self.config['dbg_manual_gearbox_slip']: + print('Performing manual gearbox sync') + conseq = 0 + for i in range(10000): + + if self.dut.xgmii_rx_data.value == int('0x07070707', 16) and \ + self.dut.u_pcs.l_rx_int_gearbox.u_rx_gearbox.o_header.value != 0: + conseq += 1 + else: + conseq = 0 + + if conseq > 40: + print('aligned') + break + + if i % 50 == 0: + self.dut.u_pcs.rx_gearbox_slip.value = 1 + else: + self.dut.u_pcs.rx_gearbox_slip.value = 0 + await RisingEdge(self.dut.i_xver_rx_clk) + + + cocotb.start_soon(self.driver_bfm()) + cocotb.start_soon(self.tx_monitor_bfm()) + cocotb.start_soon(self.rx_monitor_bfm()) + + + # A copy of AxiStreamFrame::compact but does not remvove tuser when tkeep = 0 + @staticmethod + def compact_axis_no_tuser(frame): + if len(frame.tkeep): + # remove tkeep=0 bytes + for k in range(len(frame.tdata)-1, -1, -1): + if not frame.tkeep[k]: + if k < len(frame.tdata): + del frame.tdata[k] + if k < len(frame.tkeep): + del frame.tkeep[k] + if k < len(frame.tid): + del frame.tid[k] + if k < len(frame.tdest): + del frame.tdest[k] + + # remove tkeep + frame.tkeep = None + + # clean up other sideband signals + # either remove or consolidate if values are identical + if len(frame.tid) == 0: + frame.tid = None + elif all(frame.tid[0] == i for i in frame.tid): + frame.tid = frame.tid[0] + + if len(frame.tdest) == 0: + frame.tdest = None + elif all(frame.tdest[0] == i for i in frame.tdest): + frame.tdest = frame.tdest[0] + + if len(frame.tuser) == 0: + frame.tuser = None + elif all(frame.tuser[0] == i for i in frame.tuser): + frame.tuser = frame.tuser[0] + + return frame + + + + + + \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/mac_pcs_config.yaml b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/mac_pcs_config.yaml new file mode 100644 index 0000000000000000000000000000000000000000..118845189d8f4ba3e64b92581d5209a51cc07e70 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/mac_pcs_config.yaml @@ -0,0 +1,8 @@ +debug: False +print_axis: False +seed: 0 +startup_pause: 5000 +tx_seq_length: 100 +loopback_cycle_slip: 1 +loopback_bit_slip: 3 +dbg_manual_gearbox_slip : False \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/requirements.txt b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/requirements.txt new file mode 100644 index 0000000000000000000000000000000000000000..d9996393906eaeb91d7a3ee3c95c8bec5064f428 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/requirements.txt @@ -0,0 +1,9 @@ +cocotb==1.7.2 +cocotb-bus==0.2.1 +cocotb-test==0.2.4 +cocotbext-axi==0.1.18 +debugpy==1.6.3 +numpy==1.23.5 +pytest==7.1.3 +pyuvm==2.9.0 +PyYAML==6.0 diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/test_mac_pcs.py b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/test_mac_pcs.py new file mode 100644 index 0000000000000000000000000000000000000000..43e87118459bbb70763a465a5431213cc3b35bae --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/mac_pcs/test_mac_pcs.py @@ -0,0 +1,275 @@ +# MIT License + +# Copyright (c) 2023 Tom Chisholm + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +"""test_mac_pcs.py + + Pyuvm testbench for mac_pcs module. + + This testbench implements a single test with random packets, tested in loopback. + Received packets are checked for correctness and for CRC match flag (TUSER) set. + +""" + +import random +import debugpy +import yaml +import pytest +import numpy as np +import os +import glob +from shutil import copyfile + +from cocotb.triggers import RisingEdge, FallingEdge +from cocotb.queue import QueueEmpty, Queue +from cocotb.clock import Clock +from cocotb_test.simulator import run + +from pyuvm import * +import pyuvm + +from mac_pcs_bfm import MacPcsBfm + +class EthTxSeqItem(uvm_sequence_item): + def __init__(self, name, packet_size): + super().__init__(name) + self.packet_size = packet_size + self.packet = np.random.randint(0, 255, packet_size, dtype=np.uint8) + + def __eq__(self, other): + return self.packet == other.packet + + def __str__(self): + return f'{self.get_name()} : Size = {len(self.packet)}, Data = {self.packet}' + +class EthTxSeqRandom(uvm_sequence): + + def __init__(self, name, length): + super().__init__(name) + self.length = length + + async def body(self): + for i in range(self.length): + seq_item = EthTxSeqItem(f'p{i}', np.random.randint(16, 256, 1)) + await self.start_item(seq_item) + await self.finish_item(seq_item) + +class EthTxAllSeq(uvm_sequence): + async def body(self): + self.config = ConfigDB().get(None, "", 'run_config') + seqr = ConfigDB().get(None, "", "SEQR") + random = EthTxSeqRandom("random", self.config['tx_seq_length']) + await random.start(seqr) + +class TxDriver(uvm_driver): + def build_phase(self): + self.config = ConfigDB().get(self, "", 'run_config') + self.ap = uvm_analysis_port('ap', self) + + def start_of_simulation_phase(self): + self.bfm = MacPcsBfm() + + async def launch_tb(self): + await self.bfm.start_bfm() + await self.bfm.pause(self.config['startup_pause']) + + async def run_phase(self): + await self.launch_tb() + while True: + seq_item = await self.seq_item_port.get_next_item() + await self.bfm.send_tx_packet(seq_item.packet) + self.seq_item_port.item_done() + +class Monitor(uvm_component): + def __init__(self, name, parent, method_name): + super().__init__(name, parent) + self.method_name = method_name + + def build_phase(self): + self.ap = uvm_analysis_port("ap", self) + self.bfm = MacPcsBfm() + self.get_method = getattr(self.bfm, self.method_name) + + async def run_phase(self): + while True: + datum = await self.get_method() + self.logger.debug(f"MONITORED {datum}") + self.ap.write(datum) + +class Scoreboard(uvm_component): + def build_phase(self): + self.tx_frame_fifo = uvm_tlm_analysis_fifo("tx_frame_fifo", self) + self.rx_frame_fifo = uvm_tlm_analysis_fifo("rx_frame_fifo", self) + self.tx_frame_port = uvm_get_port("tx_frame_port", self) + self.rx_frame_port = uvm_get_port("rx_frame_port", self) + self.tx_frame_export = self.tx_frame_fifo.analysis_export + self.rx_frame_export = self.rx_frame_fifo.analysis_export + + def connect_phase(self): + self.tx_frame_port.connect(self.tx_frame_fifo.get_export) + self.rx_frame_port.connect(self.rx_frame_fifo.get_export) + + def check_phase(self): + + had_frame = False + + while self.rx_frame_port.can_get(): + _, rx_frame = self.rx_frame_port.try_get() + tx_success, tx_frame = self.tx_frame_port.try_get() + + had_frame = True + + if not tx_success: + self.logger.critical(f'tx_frame {tx_frame} error') + assert tx_success + else: + + if len(tx_frame.tdata) < 64: + data_eq = rx_frame.tdata[0:len(tx_frame.tdata)] == tx_frame.tdata and \ + all([x == 0 for x in rx_frame.tdata[len(tx_frame.tdata):-4]]) + else: + data_eq = rx_frame.tdata[:-4] == tx_frame.tdata + + try: + iter(rx_frame.tuser) + rx_crc_valid = rx_frame.tuser[-1] == 1 + except TypeError: + rx_crc_valid = False + + + if not data_eq: + self.logger.critical(f"FAILED (Data Not Equal): {rx_frame}, {tx_frame}") + for i, (tx,rx) in enumerate(zip(tx_frame.tdata, rx_frame.tdata)): + if tx != rx: + print(f'Index {i}, tx = 0x{tx:02x}, rx = 0x{rx:02x}') + + elif not rx_crc_valid: + self.logger.critical(f"FAILED (CRC Valid Flag Not Set): {rx_frame}, {tx_frame}") + else: + self.logger.info(f"PASSED: {rx_frame}, {tx_frame}") + + assert data_eq and rx_crc_valid + + if not had_frame: self.logger.critical(f"Didn't recieve any frames") + assert had_frame + + + +class EthEnv(uvm_env): + def build_phase(self): + self.config = ConfigDB().get(self, "", 'run_config') + + self.seqr = uvm_sequencer('seqr', self) + ConfigDB().set(None, '*', 'SEQR', self.seqr) + + self.bfm = MacPcsBfm() + self.bfm.set_axis_log(self.config['print_axis']) + + self.driver = TxDriver.create('driver', self) + self.tx_mon = Monitor("tx_mon", self, "get_tx_frame") + self.rx_mon = Monitor("rx_mon", self, "get_rx_frame") + self.scoreboard = Scoreboard("scoreboard", self) + + def connect_phase(self): + self.driver.seq_item_port.connect(self.seqr.seq_item_export) + self.tx_mon.ap.connect(self.scoreboard.tx_frame_export) + self.rx_mon.ap.connect(self.scoreboard.rx_frame_export) + + +class MacPcsTest(uvm_test): + def build_phase(self): + + with open('mac_pcs_config.yaml', 'r') as f: + self.config = yaml.safe_load(f) + + ConfigDB().set(None, '*', 'run_config', self.config) + + np.random.seed(self.config['seed']) + + if self.config['debug']: + debugpy.listen(5678) + debugpy.wait_for_client() + debugpy.breakpoint() + + self.env = EthEnv("env", self) + + def end_of_elaboration_phase(self): + self.test_random = EthTxAllSeq.create("test_random") + + async def run_phase(self): + self.raise_objection() + await self.test_random.start() + self.drop_objection() + + + +@cocotb.test() +async def run_MacPcsTest(pytestconfig): + # + await uvm_root().run_test(MacPcsTest) + +@pytest.mark.parametrize( + "parameters,config", [ + ({"EXTERNAL_GEARBOX": "0", "SCRAMBLER_BYPASS": "0"}, {"loopback_bit_slip": 0}), + ({"EXTERNAL_GEARBOX": "0", "SCRAMBLER_BYPASS": "0"}, {"loopback_bit_slip": 1}), + ({"EXTERNAL_GEARBOX": "0", "SCRAMBLER_BYPASS": "0"}, {"loopback_bit_slip": 2}), + ({"EXTERNAL_GEARBOX": "0", "SCRAMBLER_BYPASS": "0"}, {"loopback_bit_slip": 3}), + ({"EXTERNAL_GEARBOX": "1", "SCRAMBLER_BYPASS": "0"}, {"loopback_bit_slip": 0}), + ]) +def test_mac_pcs(parameters, config): + + test_variables = {**parameters, **config} + + sim_build = "./sim_build/" + ",".join((f"{key}={str(value)}" for key, value in test_variables.items())) + + os.makedirs(sim_build, exist_ok=True) + + with open('mac_pcs_config.yaml', 'r') as f: + base_config = yaml.safe_load(f) + + base_config.update(config) + + with open(os.path.join(sim_build, "mac_pcs_config.yaml"), 'w') as f: + yaml.dump(base_config, f) + + copyfile("../../lib/slicing_crc/hdl/crc_tables.mem", os.path.join(sim_build, "crc_tables.mem")) + + source_tree = [ + glob.glob('../../hdl/mac_pcs.sv'), + glob.glob('../../hdl/mac/*.sv'), + glob.glob('../../hdl/pcs/*.sv'), + glob.glob('../../lib/slicing_crc/hdl/*.sv') + ] + + sources = [item for sublist in source_tree for item in sublist] + + run( + verilog_sources=sources, + toplevel="mac_pcs", + + module="test_mac_pcs", + simulator="icarus", + verilog_compile_args=["-g2012"], + includes=["../../hdl/include/"], + parameters=parameters, + extra_env=parameters, + sim_build=sim_build + ) \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/pcs/.gitignore b/ttchisholm_10g-low-latency-ethernet/source/src/tb/pcs/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7d2e4a8ade05bf137527ddc5f7054de275255f89 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/pcs/.gitignore @@ -0,0 +1,6 @@ +__pycache__ +sim_build +*.fst +*.vcd +*.xml +iverilog_dump.v \ No newline at end of file diff --git a/ttchisholm_10g-low-latency-ethernet/source/src/tb/pcs/Makefile b/ttchisholm_10g-low-latency-ethernet/source/src/tb/pcs/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..1d6887c155c0d5c32ec3a0dc347a1ddb4715bf46 --- /dev/null +++ b/ttchisholm_10g-low-latency-ethernet/source/src/tb/pcs/Makefile @@ -0,0 +1,62 @@ +# Makefile + +# defaults +SIM ?= icarus +TOPLEVEL_LANG ?= verilog +WAVES ?= 1 + +VERILOG_SOURCES += $(PWD)/../../hdl/include/code_defs_pkg.svh +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/pcs.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/decoder.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/encoder.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/rx_gearbox.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/tx_gearbox.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/gearbox_seq.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/lock_state.sv +VERILOG_SOURCES += $(PWD)/../../hdl/pcs/scrambler.sv +# use VHDL_SOURCES for VHDL files + +# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file +TOPLEVEL = pcs + +# MODULE is the basename of the Python test file +MODULE = test_pcs + + + +# module parameters +export SCRAMBLER_BYPASS ?= 0 +export EXTERNAL_GEARBOX ?= 1 +export DATA_WIDTH ?= 32 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += -P $(TOPLEVEL).SCRAMBLER_BYPASS=$(SCRAMBLER_BYPASS) + COMPILE_ARGS += -P $(TOPLEVEL).EXTERNAL_GEARBOX=$(EXTERNAL_GEARBOX) + COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(DATA_WIDTH) + COMPILE_ARGS += -I $(PWD)/../../hdl/include + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif + +endif + + +# include cocotb's make rules to take care of the simulator setup +include $(shell cocotb-config --makefiles)/Makefile.sim + + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst \ No newline at end of file