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}, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/concat_swap": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/operator_typo": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/unconnected_port": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/concat_swap": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/operator_typo": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/missing_reset": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/operator_typo": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/wrong_bitwidth": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/operator_typo": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/unconnected_port": { "status": "waveform_identical" }, "meiniKi_RV32I_SC_Logisim/mcu__sc_bus/operator_typo": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/concat_swap": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/inverted_condition": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_enable": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_reset": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/operator_typo": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/wrong_bitwidth": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/inverted_condition": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/missing_reset": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/operator_typo": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/state_transition": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_reg__router_reg/inverted_condition": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_enable": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_reset": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_reg__router_reg/operator_typo": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_reg__router_reg/wrong_bitwidth": { "status": "sim_ok" }, "mnmhdanas_Router-1-x-3-/router_sync__router_sync/case_swap": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_sync__router_sync/inverted_condition": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_sync__router_sync/missing_enable": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_sync__router_sync/missing_reset": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_sync__router_sync/operator_typo": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_sync__router_sync/wrong_bitwidth": { "status": "waveform_identical" }, "mnmhdanas_Router-1-x-3-/router_top__router_top/unconnected_port": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__accelerator/unconnected_port": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/concat_swap": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/inverted_condition": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/operator_typo": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/wrong_bitwidth": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/inverted_condition": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/missing_enable": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/missing_reset": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/operator_typo": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/wrong_bitwidth": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/inverted_condition": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/missing_enable": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/missing_reset": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/operator_typo": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/unconnected_port": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/wrong_bitwidth": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__input_mux/operator_typo": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/missing_enable": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/missing_reset": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/operator_typo": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/unconnected_port": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/wrong_bitwidth": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__max_reg/missing_enable": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__max_reg/missing_reset": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__pooler/unconnected_port": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__qmult/concat_swap": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__qmult/operator_typo": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__tanh_lut/operator_typo": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__tanh_lut/wrong_bitwidth": { "status": "waveform_identical" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__variable_shift_reg/missing_enable": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__variable_shift_reg/missing_reset": { "status": "sim_ok" }, "thedatabusdotio_fpga-ml-accelerator/acclerator__variable_shift_reg/wrong_bitwidth": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac__code_defs_pkg/case_swap": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac__code_defs_pkg/operator_typo": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac__mac/missing_enable": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac__mac/missing_reset": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac__mac/unconnected_port": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/case_swap": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/concat_swap": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/inverted_condition": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/missing_enable": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/missing_reset": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/operator_typo": { "status": "sim_ok" }, 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"ttchisholm_10g-low-latency-ethernet/mac__tx_mac/unconnected_port": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/wrong_bitwidth": { "status": "timeout" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/case_swap": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/concat_swap": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/inverted_condition": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/missing_enable": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/missing_reset": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/operator_typo": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/wrong_bitwidth": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/concat_swap": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/inverted_condition": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/missing_enable": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/missing_reset": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/operator_typo": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/wrong_bitwidth": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/inverted_condition": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/missing_reset": { "status": "timeout" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/off_by_one_counter": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/operator_typo": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/inverted_condition": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/missing_reset": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/off_by_one_counter": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/operator_typo": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/state_transition": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/wrong_bitwidth": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__mac_pcs/unconnected_port": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/missing_reset": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/operator_typo": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/unconnected_port": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/wrong_bitwidth": { "status": "waveform_identical" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/concat_swap": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/missing_enable": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/missing_reset": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/operator_typo": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/wrong_bitwidth": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/inverted_condition": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/missing_reset": { "status": "compile_error" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/off_by_one_counter": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/operator_typo": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/wrong_bitwidth": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/concat_swap": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/inverted_condition": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/missing_enable": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/missing_reset": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/operator_typo": { "status": "sim_ok" }, "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/wrong_bitwidth": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/display_pal__display_pal/case_swap": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/display_pal__display_pal/inverted_condition": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/display_pal__display_pal/missing_enable": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/display_pal__display_pal/missing_reset": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/display_pal__display_pal/off_by_one_counter": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/display_pal__display_pal/operator_typo": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/display_pal__display_pal/wrong_bitwidth": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/concat_swap": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/inverted_condition": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/missing_reset": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/off_by_one_counter": { "status": "waveform_identical" }, "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/operator_typo": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/state_transition": { "status": "sim_ok" }, "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/unconnected_port": { "status": "waveform_identical" }, "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/wrong_bitwidth": { "status": "sim_ok" } }, "bug_types_attempted": { "Vaibhav-Gunthe_Verilog-Projects": [ "blocking_nonblocking", "case_swap", "concat_swap" ], "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "phoeniX-Digital-Design_phoeniX": [ "blocking_nonblocking" ], "meiniKi_FazyRV": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "selimsandal_OneShotNPU": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "thejefflarson_little-cpu": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "mnmhdanas_UART-protocol": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "lucky-wfw_IC_System_Design": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "akira2963753_Pipelined-RV32-SoC": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "fcayci_sv-digital-design": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "Fraunhofer-IMS_airisc_core_complex": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "nimanaqavi_Verilog-MathFunctions": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "scarv_xcrypto": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "JN513_Risco-5": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "accomdemy_accomdemy_rv32i": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "chili-chips-ba_wireguard-fpga": [ "blocking_nonblocking", "inverted_condition", "missing_else_latch", "missing_reset", "operator_typo", "signal_typo", "unconnected_port", "wrong_bitwidth" ], "shahsaumya00_Floating-Point-Adder": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "Mr-Bossman_KISC-V": [ "blocking_nonblocking", "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_else_latch", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "signal_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "apfaudio_eurorack-pmod": [ "case_swap", "concat_swap", "delayed_signal", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "ttchisholm_10g-low-latency-ethernet": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "Weiyet_RTLStructLib": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "zhangxin6_iverilog_testbench": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "OrsuVenkataKrishnaiah1235_RTL-Coding": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "thedatabusdotio_fpga-ml-accelerator": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "aditeyabaral_DDCO-Lab-UE18CS207": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "mnmhdanas_Router-1-x-3-": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "meiniKi_RV32I_SC_Logisim": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "defano_digital-design": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "MohamedHussein27_AMPA_APB4_Protocol": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ], "MohamedHussein27_SPI_Slave_With_Single_Port_Memory": [ "case_swap", "concat_swap", "inverted_condition", "missing_enable", "missing_reset", "off_by_one_counter", "operator_typo", "state_transition", "unconnected_port", "width_bit_cutoff", "wrong_bitwidth" ] } }