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+# Hardware-Aware LLM Optimization: CPUs, GPUs, and AWS Trainium
+
+## Lecture one A. What Does “Faster” Mean?
+
+Before optimizing a CPU, GPU, or Trainium chip, decide whose clock matters.
+
+**Time to first token**, abbreviated **TTFT**, measures the delay from sending a request until its first token arrives. **Inter-token latency**, or **ITL**, measures the gaps between subsequent tokens. **Output throughput** counts generated tokens per second across the entire service.
+
+Imagine configuration A delivers forty tokens per second to one user. Configuration B delivers thirty per second to each of ten users: three hundred overall. B completes more work, but each individual stream is slower.
+
+A useful target might be: maximize throughput while keeping first-token delay below one second and token gaps below fifty milliseconds. Those are illustrative requirements, not universal thresholds. Model quality must also remain acceptable.
+
+**The takeaway: faster is a workload requirement, not a hardware property.**
+
+Before changing settings, ask: which user-visible constraint must remain satisfied?
+
+Next, we will separate the two phases that produce those measurements: prefill and decode.
+
+## Lecture one B. Prefill and Decode: Two Different Hardware Problems
+
+Our first lecture separated response latency from service throughput. Now consider why those measurements favor different hardware behavior.
+
+During **prefill**, the model processes known prompt tokens. Within each layer, their projections can form large matrix multiplications, reusing weight tiles across many tokens.
+
+During **decode**, ordinary autoregressive generation processes one new token per active sequence. For one user, projections resemble matrix-vector operations: many weights are read for relatively little arithmetic.
+
+Imagine reading the same weight tile for thirty-two concurrent users. A batched kernel can reuse that tile across thirty-two token calculations instead of just one. This increases arithmetic intensity: useful operations per byte moved.
+
+However, more requests also increase attention-cache traffic. Long contexts can change the balance again.
+
+**The takeaway: prefill is often compute-intensive and decode often bandwidth-limited, but neither label is unconditional.**
+
+Ask: what are my actual batch size and context length?
+
+Next, we will make those conditions explicit in a reproducible benchmark.
+
+## Lecture one C. Build a Benchmark You Can Trust
+
+Suppose an optimization appears to improve throughput by forty percent. Before celebrating, check whether the experiment changed.
+
+Use identical model weights, tokenization, precision, and decoding settings. Hold prompt lengths, output lengths, and the request-arrival pattern constant. Record concurrency: the number of outstanding requests, not necessarily the number executing in one batch.
+
+For a controlled test, use prompts of one thousand twenty-four tokens and outputs of two hundred fifty-six tokens. Later, replay a representative mixture of lengths.
+
+Warm the system before steady-state measurements. Record loading, compilation, and cold-start costs separately rather than pretending they do not exist.
+
+Measure latency distributions, not only averages. **P95**, the ninety-fifth percentile, is the threshold below which ninety-five percent of observations fall. Specify whether those observations are requests or token gaps.
+
+**The takeaway: compare like with like, repeat runs, and preserve quality.**
+
+Ask: could a workload change explain the improvement?
+
+Next, we will calculate the memory budget behind that workload.
+
+## Lecture two A. Build the Memory and Traffic Budgets
+
+Our benchmark now specifies the workload. Before tuning it, separate memory capacity from memory traffic.
+
+First, weights. An illustrative eight-billion-parameter model needs sixteen billion bytes for sixteen-bit weights, before metadata. That is sixteen decimal gigabytes, or about fourteen point nine binary gibibytes.
+
+Second, the **KV cache**, meaning key-value cache. Assume thirty-two layers, eight key-value heads, a head dimension of one hundred twenty-eight, and two bytes per value.
+
+Multiply layers, heads, head dimension, bytes, and two for keys plus values. The result is one hundred twenty-eight kibibytes per cached token.
+
+Four thousand ninety-six tokens require half a gibibyte per request. Sixteen such requests require eight gibibytes, before allocation overhead.
+
+Third, add temporary activations, workspaces, and runtime buffers.
+
+**The takeaway: fitting in memory does not establish how quickly that memory can be read.**
+
+Ask: which tensors must move during each generation step?
+
+Next, we will connect those bytes to arithmetic intensity.
+
+## Lecture two B. Arithmetic Intensity and the Roofline Model
+
+We know the memory footprint. Now ask how much computation each transferred byte supports.
+
+**Arithmetic intensity** means operations performed per byte moved across a specified memory boundary. Here, use external memory to the processor.
+
+Imagine hardware sustaining one hundred trillion operations per second and two trillion bytes per second at the relevant precision. Dividing gives fifty operations per byte: its approximate compute-to-bandwidth crossover.
+
+For a simplified dense eight-billion-parameter model, one decode token involves roughly sixteen billion weight-related operations. Reading sixteen billion weight bytes gives approximately one operation per byte. Ignore attention and other traffic for this first estimate.
+
+Batching sixty-four tokens could raise weight-related intensity toward sixty-four, provided the kernel actually reuses those weights. Additional traffic lowers the full-workload intensity.
+
+**The takeaway: the roofline model gives a ceiling, not a guaranteed performance prediction.**
+
+Ask: should I first reduce bytes moved or improve arithmetic execution?
+
+Next, we will decide which operation is worth optimizing.
+
+## Lecture two C. Amdahl’s Law and the Critical Path
+
+The roofline model identifies a possible resource limit. Amdahl’s law tells us whether improving that resource will matter overall.
+
+Imagine one token takes one hundred milliseconds. An operation occupies twenty milliseconds, while everything else takes eighty. Assume these times are sequential.
+
+Make that operation ten times faster. Its twenty milliseconds become two, giving eighty-two milliseconds overall. Latency falls eighteen percent; throughput for this sequential loop rises about twenty-two percent. Those are different percentages describing the same change.
+
+Even eliminating the operation entirely would leave eighty milliseconds. That limits the total speedup to one point two five times.
+
+Real traces include overlapping work. Adding every kernel’s duration can overstate elapsed time, so inspect dependencies and the critical path: the chain determining completion.
+
+**The takeaway: prioritize time you can actually remove from the request.**
+
+Ask: how much end-to-end improvement could this change possibly deliver?
+
+Next, we will trace the operations inside one decoder block.
+
+## Lecture three A. Follow a Decoder Block Through Its Operations
+
+We now need an execution map, not another transformer introduction.
+
+Take a common decoder block using **RMSNorm**, root mean square normalization. It rescales activations before projections create queries, keys, and values. Positional transformations may follow, depending on the architecture.
+
+During decode, attention compares the current query with cached keys, normalizes scores, and combines cached values. An output projection and residual addition follow. Another normalization leads into the feed-forward network, often with expansion, gating, and contraction.
+
+Group the hardware work into large weight-bearing matrix operations, attention-cache access, and smaller elementwise or reduction operations.
+
+A **kernel** is a low-level implementation of some computation; CPUs have kernels too. One mathematical operator can launch multiple kernels, while one fused kernel can implement several operators.
+
+Writing an intermediate tensor between kernels can create avoidable traffic.
+
+**The takeaway: operator boundaries and execution boundaries are not identical.**
+
+Ask: which intermediate is materialized unnecessarily?
+
+Next, we will locate those decisions in the software stack.
+
+## Lecture three B. Frameworks, Inference Engines, Compilers, and Kernels
+
+Our decoder block becomes executable through several cooperating software layers, not one rigid assembly line.
+
+A **framework**, such as PyTorch, expresses tensor operations and model behavior. An **inference engine**, such as vLLM, coordinates requests, batching, and attention-cache allocation.
+
+A **compiler** transforms supported code into executable implementations. It may fuse operations, specialize shapes, or call existing libraries. Some kernels are compiled beforehand; others are compiled when needed.
+
+The **kernel** performs the actual low-level work. Its layout and arithmetic must match the device.
+
+These responsibilities overlap. An inference engine can contain custom kernels; a compiled graph can call prebuilt kernels without recompiling their internals.
+
+For example, queueing caused by a poor scheduling policy is not automatically fixed by faster multiplication. Conversely, a bad multiplication implementation is not necessarily cured by changing the scheduler.
+
+**The takeaway: place the bottleneck in the correct software layer before intervening.**
+
+Ask: which component controls the wasted time?
+
+Next, we will examine precision across these layers.
+
+## Lecture three C. Precision Is an Execution Contract
+
+The software stack must agree on what a compressed model actually means.
+
+Separate **weight storage precision**, **activation precision**, and **accumulation precision**. Accumulation is the format used while summing products, not simply the format of each multiplication input.
+
+**W4A16** means four-bit weights and sixteen-bit activations. It does not fully specify accumulation or the instructions that execute.
+
+Our eight-billion-parameter model would contain four billion raw weight bytes at four bits each. Scales, offsets, padding, and unquantized tensors add overhead.
+
+A kernel might unpack those weights, apply scales, and convert values before multiplication. An efficient implementation performs this work close to computation instead of expanding the whole model into temporary memory.
+
+Smaller storage can therefore help a bandwidth-limited workload while hurting another workload through conversion overhead.
+
+**The takeaway: choose a numerical format together with a supported, measured kernel.**
+
+Ask: what arithmetic does my backend actually execute?
+
+Next, we begin CPU optimization with vector instructions.
+
+## Lecture four A. CPU SIMD: More Useful Work per Instruction
+
+We move from software layers to the CPU instructions executing a linear layer.
+
+**SIMD** means single instruction, multiple data. One vector instruction performs corresponding operations on several packed values. A dot product can use vector multiplication, accumulation, and a final reduction rather than separate scalar instructions for every pair.
+
+Some CPUs also provide integer dot-product instructions that combine several products and accumulate into wider integer results.
+
+For our quantized model, however, four-bit storage is only the starting point. The kernel must interpret packed values and scales, then arrange operands for supported instructions. That preparation can dominate a poorly implemented loop.
+
+Wider vectors also do not guarantee proportional speedups when memory bandwidth already limits execution.
+
+Imagine cutting arithmetic time in half while weight-read time stays unchanged. The benefit depends on which one sets the critical path.
+
+**The takeaway: maximize useful work, not vector width alone.**
+
+Ask: are arithmetic instructions or operand preparation limiting this kernel?
+
+Next, we examine matrix-oriented CPU instructions.
+
+## Lecture four B. CPU Matrix Engines: Intel AMX and Arm SME
+
+Vector instructions process several values together. Matrix-oriented instructions extend that idea to blocks of computation.
+
+Intel **AMX**, Advanced Matrix Extensions, provides two-dimensional tile registers and matrix multiply-accumulate operations. Available numerical formats depend on the processor generation and supported extensions.
+
+Arm **SME**, Scalable Matrix Extension, introduces two-dimensional accumulator storage called **ZA**, or Z Array. Outer-product instructions multiply elements from two vectors and accumulate the resulting matrix into that storage.
+
+These are related capabilities, not identical hardware designs.
+
+Imagine our model processing a long prompt. Many token rows provide enough matrix work to reuse loaded operands and amortize setup costs. During one-user decoding, much smaller shapes may leave that capability underused.
+
+Batching can improve the fit, but it changes latency and memory requirements. A matrix-capable CPU needs a compatible operating environment and an efficient kernel.
+
+**The takeaway: match precision and matrix shape to the available execution path.**
+
+Ask: does this workload use the matrix engine?
+
+Next, we connect capability to compiled code.
+
+## Lecture four C. CPU Targets, Compilers, and Runtime Dispatch
+
+A CPU can support an instruction that your program never executes.
+
+The **ISA**, instruction set architecture, defines the machine instructions available to software. A compiler target controls which of those instructions generated code may use.
+
+For supported compilers and targets, the option commonly written as “march equals native” selects capabilities of the compilation machine. That can improve specialization, but the binary may fail on an older deployment machine.
+
+Another approach is **runtime dispatch**: ship several kernel implementations and select a compatible one after detecting processor features. A portable binary can therefore still use advanced instructions.
+
+llama.cpp supports CPU-specific build choices and backend variants. Nevertheless, a favorable build flag does not prove that a particular operation selected the desired kernel.
+
+Check build information, runtime reporting, and performance evidence.
+
+**The takeaway: distinguish hardware support, compiled availability, and actual kernel selection.**
+
+Ask: which implementation ran for this tensor shape?
+
+Next, we will arrange data to feed that implementation efficiently.
+
+## Lecture five A. Cache Blocking and Weight Packing
+
+The right instructions still need the right operands at the right time.
+
+**Cache blocking**, also called tiling, divides a matrix operation into pieces sized for useful reuse in registers and cache.
+
+Imagine processing sixteen prompt tokens together. A weight tile can contribute to all sixteen before being displaced. That is more useful than repeatedly fetching it for independent token calculations.
+
+**Weight packing** rearranges values into the layout an optimized kernel expects. For example, values consumed together by a vector or matrix instruction can be stored together rather than gathered from scattered locations.
+
+Because inference weights remain unchanged, a backend can pack them once and reuse the result. Packing still consumes startup time and may require additional memory.
+
+For single-token decoding, a model larger than cache still requires substantial weight traffic.
+
+**The takeaway: blocking creates reuse; packing makes the required access pattern cheaper.**
+
+Ask: am I repacking or reloading something unnecessarily?
+
+Next, we explore how CPU threads compete for those resources.
+
+## Lecture five B. Find the Useful CPU Thread Count
+
+Cache-aware kernels do not mean that every additional thread improves inference.
+
+Imagine a decode test using eight, sixteen, and thirty-two threads. Throughput rises from eight to sixteen, then barely changes at thirty-two.
+
+One hypothesis is memory-bandwidth saturation: sixteen workers already move weights as quickly as the memory system allows. Extra workers add scheduling and synchronization without increasing available bandwidth.
+
+But a plateau alone is not proof. Also check core placement, thread oversubscription, and whether work is large enough to divide efficiently. Multiple software libraries can accidentally create competing thread pools.
+
+Run separate sweeps for prefill and decode. Prefill may benefit from more compute resources even when single-user decode does not.
+
+Keep power settings, model precision, and memory placement fixed during each sweep. Repeat measurements to separate noise from improvement.
+
+**The takeaway: choose thread count from a scaling curve, not the advertised core count.**
+
+Ask: what evidence explains the plateau?
+
+Next, we will examine where those threads and their memory live.
+
+## Lecture five C. NUMA Placement and Thread Affinity
+
+Thread count is only half the CPU placement problem.
+
+**NUMA**, non-uniform memory access, means access cost depends on where memory resides relative to a processor. A multi-socket server commonly has memory attached near each socket.
+
+**Thread affinity** keeps workers on chosen cores. Memory placement determines which locality domain supplies their pages. Pinning threads does not automatically move previously allocated memory.
+
+Imagine weights allocated near socket one while workers execute on socket two. Reads cross the socket interconnect instead of using only local memory paths.
+
+Compare a locally placed single-socket configuration with a deliberately partitioned multi-socket configuration. A larger deployment can expose more aggregate bandwidth, but communication and allocation policy matter.
+
+For two independent replicas, placing one replica and its weights near each socket may avoid unnecessary cross-socket traffic, provided memory capacity permits.
+
+**The takeaway: treat compute placement and data placement as one decision.**
+
+Ask: are my workers reading locally?
+
+Next, we will return to the arithmetic inside quantized CPU kernels.
+
+## Lecture six A. Four-Bit Storage Does Not Specify the Arithmetic
+
+We have placed CPU threads and memory sensibly. Now inspect what a four-bit dot product actually does.
+
+Two four-bit values fit into one byte. The kernel extracts them, interprets their signed or offset representation, and applies the appropriate scale information.
+
+From there, execution paths differ. One kernel converts values into floating point. Another quantizes activations into eight-bit integers, uses integer dot-product instructions, and rescales accumulated results.
+
+Neither path is described completely by saying “the model is four-bit.” Even a weight-only compressed file may execute with additional temporary activation quantization inside its backend.
+
+Imagine two implementations reading identical compressed weights. The faster one might simply require fewer unpacking and conversion instructions, not fewer mathematical multiplications.
+
+Measure the full operation, including preparation, rather than timing only its multiply loop.
+
+**The takeaway: storage format and execution format are separate choices.**
+
+Ask: where are unpacking, activation conversion, and scaling performed?
+
+Next, we will reduce the memory traffic those steps can create.
+
+## Lecture six B. Fuse Dequantization with CPU Computation
+
+Consider two ways to use our four-bit weights on a CPU.
+
+The first expands an entire matrix into sixteen-bit values, stores that temporary matrix, and then multiplies it. During repeated inference, this can add a large write followed by another read.
+
+The second loads a compressed tile, unpacks only the needed values, and consumes them immediately in the dot-product kernel. Intermediate values can stay in registers or nearby working storage instead of becoming a full external-memory tensor.
+
+That is **fused dequantization**: combining reconstruction with useful computation.
+
+It still costs instructions. Excessive live intermediate state can also pressure registers. A fused implementation must be measured, not assumed superior.
+
+For fixed weights and large repeated batches, a separately prepared representation might sometimes repay its storage and preparation costs. The workload decides.
+
+**The takeaway: avoid materializing expanded weights unless reuse justifies it.**
+
+Ask: which temporary writes disappear in the fused path?
+
+Next, we will compare the quantization layouts feeding these kernels.
+
+## Lecture six C. Match Quantization Groups and Layouts to the Kernel
+
+Fusion works best when the compressed layout suits the kernel.
+
+**Group size** describes how many values share quantization metadata, such as a scale. Smaller groups can represent local ranges more accurately, but require more metadata and scaling work.
+
+Consider a deliberately simple format: thirty-two four-bit weights occupy sixteen bytes. Add one two-byte scale, and the group occupies eighteen bytes. Its effective storage is four point five bits per weight, before padding or other metadata.
+
+That is why nominal bit width does not fully describe memory traffic.
+
+Packing order matters too. A layout convenient for one vector instruction may require extra rearrangement on another CPU. Changing group size can also alter which optimized kernels are supported.
+
+Compare formats at an acceptable quality level, measuring prefill and decode separately. Do not assume the smallest file is the fastest deployment.
+
+**The takeaway: evaluate the complete format-kernel pair.**
+
+Ask: am I saving weight bytes but adding expensive preparation?
+
+Next, we assemble a CPU baseline.
+
+## Lecture seven A. Establish a CPU Baseline with llama.cpp
+
+We now have enough theory to run a meaningful CPU experiment.
+
+Start with a known llama.cpp version and a model representation it supports. Record the processor, build options, selected backend, precision, thread count, and memory placement.
+
+Use **llama-bench**, the project’s benchmarking tool, to measure prompt processing and token generation separately. Confirm the meaning of its parameters in the documentation for your version.
+
+Begin with a fixed prompt length and generation length. Warm the workload, run repeated trials, and preserve the raw results rather than only the best run.
+
+A kernel-focused benchmark answers how this model configuration executes under controlled conditions. It does not automatically measure networking, request queueing, tokenization, or tail latency through a real server.
+
+After establishing the baseline, repeat the chosen configuration through your actual serving path.
+
+**The takeaway: a microbenchmark is a diagnostic instrument, not the entire service evaluation.**
+
+Ask: which costs does this measurement exclude?
+
+Next, we will change exactly one variable.
+
+## Lecture seven B. Tune One Variable and Explain the Result
+
+Take the CPU baseline and choose one hypothesis: decode is limited by memory bandwidth, while prefill still benefits from extra threads.
+
+Sweep thread count without changing precision, request lengths, or memory placement. Suppose decode plateaus at sixteen threads, but prefill improves through thirty-two. These are hypothetical results, not a claim about every processor.
+
+Now inspect bandwidth and execution measurements. A flat decode curve with saturated memory traffic supports the hypothesis. A flat curve with mostly idle cores suggests another explanation, such as serialization or insufficient work.
+
+Keep the best configuration for your actual service objective. Some engines allow distinct controls for different phases; verify support rather than assuming it.
+
+Once the thread experiment is complete, you can separately test batch size. Combining both changes immediately would make attribution harder.
+
+**The takeaway: predict, change, measure, and explain before combining optimizations.**
+
+Ask: what observation would falsify my hypothesis?
+
+Next, we will decide whether adding a GPU helps.
+
+## Lecture seven C. When CPU–GPU Offloading Helps
+
+Suppose our model does not fit entirely in GPU memory. A hybrid configuration can keep some layers on the CPU and others on the GPU.
+
+With persistent layer placement, weights remain near the processor executing them. Activations cross the boundary between assigned layer groups. That differs from repeatedly streaming large weight tensors into the GPU during generation.
+
+**PCIe**, Peripheral Component Interconnect Express, is a common host-device connection. Its usable bandwidth and transfer latency must enter the performance budget.
+
+Imagine saving ten milliseconds of CPU computation but adding twelve milliseconds of transfers and synchronization. The offload loses, despite the GPU kernel being faster.
+
+Also account for attention-cache placement and temporary buffers. Some integrated systems share physical memory, so their transfer model differs from a discrete accelerator’s.
+
+**The takeaway: evaluate the complete partition, not the GPU’s isolated speed.**
+
+Ask: what crosses the boundary, how often, and on whose critical path?
+
+Next, we move fully onto GPUs and examine matrix shapes.
+
+## Lecture eight A. Tensor-Core Capability Versus Useful Utilization
+
+On a GPU, arithmetic capability matters only when the workload exposes suitable work.
+
+Compare one-user decode with a batch of sixty-four users. Both use the same weights, but their activation matrices have different numbers of token rows.
+
+A tiny operation may provide too few useful tiles to occupy the device. A larger operation can distribute more tiles and reuse weights across more rows.
+
+Specialized matrix units also have supported shapes and numerical formats. Padding an awkward dimension may make an implementation possible, but some executed arithmetic then contributes nothing to the answer.
+
+This does not mean that every small matrix must avoid tensor cores. Specialized kernels can still be effective; the comparison must use real shapes and include all overhead.
+
+Record useful throughput alongside total execution time rather than trusting peak specifications.
+
+**The takeaway: matrix dimensions are part of the hardware configuration.**
+
+Ask: how many useful tiles does this operation expose?
+
+Next, we will examine how their threads access memory.
+
+## Lecture eight B. Coalesced Access and Tensor Layout
+
+Useful matrix tiles still need efficient memory access.
+
+**Coalescing** means combining nearby threads’ memory requests into an efficient set of memory transactions. It depends on addresses, alignment, and access size, not simply on whether a tensor is contiguous somewhere in memory.
+
+Imagine neighboring threads reading neighboring elements. Now imagine the same threads reading elements separated by a long stride. Both request the same amount of useful data, but the second pattern may require many more transactions.
+
+A tensor layout determines which dimension sits next to which in memory. A layout convenient for one operation can be inconvenient for the next.
+
+Transposing or repacking can repair access patterns, but that transformation also moves data. Prefer a pipeline whose adjacent kernels agree on layout when possible.
+
+Measure the complete chain, including any rearrangement.
+
+**The takeaway: optimize useful bytes per transaction, not just nominal tensor size.**
+
+Ask: are neighboring threads requesting nearby addresses?
+
+Next, we will reuse efficiently loaded data on-chip.
+
+## Lecture eight C. GPU Tiling and On-Chip Reuse
+
+Coalescing makes a transfer efficient. Tiling makes each transferred value useful more than once.
+
+Many datacenter GPUs use **HBM**, high-bandwidth memory. A matrix kernel loads tiles from external memory into on-chip storage, such as shared memory and registers, then reuses them for multiple products.
+
+Imagine multiplying a tile containing sixteen token rows by a weight tile. Reusing each weight across those rows raises useful arithmetic per external byte.
+
+A larger tile may increase reuse, but it also consumes more registers and shared memory. That can reduce the number of simultaneously resident thread blocks. An oversized tile can therefore lose despite reducing some traffic.
+
+Edge tiles introduce another tradeoff: padded or masked elements may consume resources without producing useful outputs.
+
+Try several tile shapes against the actual operation dimensions, including small decode batches and long prefills.
+
+**The takeaway: reuse competes with resource capacity.**
+
+Ask: does this tile save more traffic than the resources it consumes?
+
+Next, we will examine occupancy.
+
+## Lecture nine A. Occupancy Is Not the Same as Speed
+
+Our tile size controls how much work can reside on the GPU at once.
+
+An NVIDIA **SM**, streaming multiprocessor, executes resident thread blocks. **Occupancy** measures resident warps relative to the architectural maximum. It is not the same as useful compute utilization.
+
+More resident warps can hide latency by providing other work when one warp waits. But each block consumes registers, shared memory, and scheduling resources.
+
+Imagine reducing registers per thread to admit more warps. If that forces intermediate values to spill into device-backed local memory, the extra traffic can outweigh improved occupancy.
+
+Conversely, a kernel with moderate occupancy may keep its limiting execution units busy. Increasing occupancy would then solve the wrong problem.
+
+Compare kernel duration, memory behavior, and execution stalls, not occupancy alone. Other GPU architectures use related concepts with different names and resource limits.
+
+**The takeaway: occupancy is evidence, not the objective.**
+
+Ask: what latency or resource limitation would additional resident work actually hide?
+
+Next, we evaluate fusion.
+
+## Lecture nine B. Kernel Fusion and Its Limits
+
+Occupancy explains one reason that combining kernels can both help and hurt.
+
+Imagine a matrix multiplication writing an intermediate tensor, followed by an activation kernel reading it, transforming it, and writing again. A fused implementation may apply the activation before the result leaves the first kernel.
+
+That can remove an intermediate memory round trip and a launch. Similar opportunities occur around normalization, residual additions, and quantization.
+
+However, fusion increases the amount of live state or the complexity of scheduling. It can raise register use, reduce parallelism, or prevent a specialized library kernel from handling the largest operation.
+
+A fused kernel is therefore not automatically the best kernel.
+
+Measure the original chain and the fused chain under identical shapes. Include every conversion or layout change introduced around the replacement.
+
+**The takeaway: fusion should remove more overhead than it introduces.**
+
+Ask: which reads, writes, and launches disappear, and what new resource pressure appears?
+
+Next, we overlap work that still needs to happen.
+
+## Lecture nine C. Overlap Data Movement with Computation
+
+Fusion removes work. **Pipelining** hides some remaining work behind independent computation.
+
+Consider loading tile two while computing on tile one. **Double buffering** reserves separate storage for the tile being consumed and the tile being prepared.
+
+In a simplified example, loading each tile takes eight microseconds and computing takes twenty. Serial execution takes twenty-eight. With ideal independent overlap, the long-run interval can approach twenty, plus startup and drain costs.
+
+That improvement requires real independence. Computation cannot use a tile before its load completes, and a buffer cannot be overwritten while still in use.
+
+Transfers may also compete for bandwidth with other operations. More buffers consume more on-chip storage, potentially reducing residency.
+
+Use a timeline to verify that the intended overlap occurs. An asynchronous instruction permits overlap; it does not guarantee it.
+
+**The takeaway: overlap shortens the critical path only when dependencies and resources allow it.**
+
+Ask: which waits remain exposed?
+
+Next, we apply these ideas to attention.
+
+## Lecture ten A. What FlashAttention Changes
+
+Attention combines our previous lessons about tiling, fusion, and data movement.
+
+A straightforward prefill implementation can materialize a large attention-score matrix in external memory, then read it again for normalization and value aggregation.
+
+**FlashAttention** instead processes tiles and maintains running normalization statistics and partial outputs. Intermediate scores need not become one full external-memory matrix.
+
+The key is an online softmax calculation: updating normalization as new score blocks arrive while preserving the dense attention result mathematically.
+
+Ordinary floating-point rounding can still differ between implementations. “Exact attention” distinguishes the algorithm from an approximation that drops or changes attention interactions.
+
+For dense prefill attention, the underlying arithmetic still grows quadratically with sequence length. FlashAttention primarily changes memory behavior and execution efficiency, not that fundamental count.
+
+Generation with one query per sequence needs its own suitable attention kernel and parallelization choices.
+
+**The takeaway: fewer intermediate bytes can outperform fewer advertised operations.**
+
+Ask: which attention tensors actually reach external memory?
+
+Next, we tackle cache allocation.
+
+## Lecture ten B. What Paged Key-Value Caching Changes
+
+FlashAttention improves attention execution. **Paged key-value caching** addresses a different problem: allocating and sharing cache memory.
+
+Suppose every request reserves one contiguous region large enough for its maximum possible context. Short requests leave much of that reservation unused, limiting how many requests fit.
+
+A paged design divides the cache into fixed-size blocks. A logical sequence maps to physical blocks that need not sit next to each other. Additional blocks can be allocated as the sequence grows.
+
+A compatible attention kernel follows that mapping when reading keys and values. Shared prefixes may also share blocks when the implementation supports safe reuse.
+
+There is still metadata, mapping overhead, and possible waste in the final partly filled block. Paging does not eliminate attention arithmetic or make every cache access cheaper.
+
+**The takeaway: better allocation can enable more useful concurrency without shrinking the model.**
+
+Ask: how much memory is reserved but not serving useful tokens?
+
+Next, we investigate growing context length.
+
+## Lecture ten C. Diagnose Long-Context Decoding
+
+We have improved cache allocation. Now consider the cost of reading the cache itself.
+
+Hold model weights and active batch size constant while increasing context length. For ordinary full-attention decoding, each new query attends over more previous keys and values.
+
+Weight traffic may remain broadly similar per step, while attention computation and cache traffic grow. Eventually, optimizing only the weight kernels can produce diminishing returns.
+
+Possible interventions include a better decode-attention kernel, a lower-precision cache, or a different concurrency limit. Each changes a different part of the budget.
+
+Cache quantization reduces stored bytes but introduces conversion work and potential quality changes. It is separate from quantizing model weights.
+
+Shortening context, restricting the attention window, or evicting tokens may change model behavior; those are not equivalent replacements for exact full attention.
+
+**The takeaway: context length can move the bottleneck into attention.**
+
+Ask: how does attention time change as context grows?
+
+Next, we will locate that time in a profiler.
+
+## Lecture eleven A. Read the GPU Timeline Before the Counters
+
+A slow request needs an explanation in elapsed time before it needs an impressive counter report.
+
+On NVIDIA systems, **Nsight Systems** provides a timeline spanning host activity, device work, and transfers. **Nsight Compute** examines individual kernels and detailed performance measurements.
+
+Begin with the timeline. Are kernels separated by host-side gaps? Is a transfer delaying the next operation? Is the device continuously busy, but on expensive attention work?
+
+Only then inspect the kernel responsible for the limiting region. Examine memory traffic, execution-unit activity, and resource pressure against your hypothesis.
+
+Imagine a multiplication kernel that is already efficient, surrounded by substantial launch gaps. Spending weeks tuning its arithmetic would attack the wrong part of the request.
+
+Profiling itself can perturb execution, particularly when counters require replay. Confirm improvements with ordinary end-to-end benchmarks afterward.
+
+**The takeaway: local efficiency matters only in its execution context.**
+
+Ask: which visible dependency determines completion?
+
+Next, we compare precision choices on specific GPUs.
+
+## Lecture eleven B. Choose Low Precision for a Specific GPU
+
+Our profiler identifies a costly matrix operation. Should we choose a smaller numerical format?
+
+**FP8** means eight-bit floating point. **INT4** means four-bit integer. These labels describe different representations, not interchangeable speed settings.
+
+For a given GPU, check native instruction support, the kernel’s supported operand combination, and the numerical scaling required. Stored four-bit weights may still feed higher-precision arithmetic after conversion.
+
+NVIDIA and AMD devices also use different software ecosystems. AMD’s **ROCm** is its GPU software platform; a tuned NVIDIA kernel is not automatically a tuned AMD implementation.
+
+Imagine four-bit weights improving one-user decode because fewer bytes are read, while an eight-bit floating-point kernel wins during larger prefills because its arithmetic path is more efficient. That is a hypothesis to test, not a universal ranking.
+
+Evaluate representative quality tasks after numerical changes.
+
+**The takeaway: select precision for the exact device, backend, shape, and quality target.**
+
+Ask: where does conversion erase the expected saving?
+
+Next, we address launch overhead.
+
+## Lecture eleven C. Reduce Launch Overhead with Graph Replay
+
+Suppose the GPU timeline shows small kernels separated by host submission overhead.
+
+**CUDA**, Compute Unified Device Architecture, is NVIDIA’s GPU programming platform. **CUDA Graphs** records an execution pattern so work can be submitted with less per-operation host overhead.
+
+Graph replay does not fuse kernels or make the memory system faster. It mainly changes how work is launched and coordinated.
+
+For a stable decode shape, this can reduce gaps around otherwise efficient kernels. Variable workloads may need multiple captures, shape buckets, or partial graph execution, depending on the framework.
+
+Captured work also imposes constraints, such as stable memory addresses in common implementations. Frameworks manage these through prepared buffers and other machinery.
+
+Measure capture costs and extra memory separately from warm replay. A compute-heavy kernel with little launch overhead may barely benefit.
+
+**The takeaway: graph replay targets dispatch overhead, not every kind of inefficiency.**
+
+Ask: did the gaps shrink without worsening memory or shape handling?
+
+Next, we transfer our method to Trainium.
+
+## Lecture twelve A. Trainium: Think in Engines, Not GPU Warps
+
+Our optimization method carries over to **AWS**, Amazon Web Services, Trainium. Our GPU execution model does not transfer unchanged.
+
+A **NeuronCore** contains specialized engines. The Tensor Engine performs matrix-oriented work. Vector and Scalar Engines handle supported operations such as elementwise transforms and reductions. Other facilities handle computation and data movement.
+
+These engine names describe Trainium resources, not a promise that every operation follows an ordinary CPU-style instruction path.
+
+Imagine a matrix multiplication followed by an activation. Accelerating the matrix engine alone cannot eliminate a wait caused by moving its result or preparing the next input.
+
+The useful mental model is a dependency graph mapped onto engines and memory buffers. Independent operations may overlap; dependent ones must respect ordering.
+
+Exact capabilities vary by NeuronCore generation, so use the matching architecture guide.
+
+**The takeaway: optimize the engine schedule and dataflow, not just matrix throughput.**
+
+Ask: which engine or dependency is holding up the next operation?
+
+Next, we inspect the buffers connecting them.
+
+## Lecture twelve B. Trainium’s Explicit On-Chip Buffers
+
+Trainium’s engines communicate through storage that matters directly to kernel design.
+
+**SBUF**, the state buffer, holds on-chip working tensors. **PSUM**, the partial-sum buffer, holds accumulation results for supported operations, notably matrix products.
+
+A common matrix path loads operands from external high-bandwidth memory into SBUF, accumulates matrix results in PSUM, then moves or processes the result before storing it externally.
+
+These are not ordinary CPU caches that transparently rescue arbitrary access patterns. The kernel and compiler must arrange legal layouts, lifetimes, and transfers.
+
+Imagine retaining a weight tile while processing several activation tiles. That reuse saves external reads. But keeping too many tensors live can exceed the available on-chip storage and force additional movement.
+
+A mathematically valid operation can therefore be slow because its buffer schedule is poor.
+
+**The takeaway: manage on-chip residency as deliberately as arithmetic.**
+
+Ask: which tensor should remain live, and which can be released or recomputed?
+
+Next, we identify the exact Trainium configuration.
+
+## Lecture twelve C. Identify the Trainium Generation and Configuration
+
+Before choosing tile sizes, be precise about what “a Trainium device” means.
+
+A **NeuronCore** is a compute unit within a chip. A cloud instance can contain multiple chips. Some configurations combine resources from physical cores into a **logical NeuronCore**, changing the resource view exposed to software.
+
+Trainium2 uses NeuronCore version three; Trainium3 uses version four. Their engine capabilities, buffer capacities, and supported numerical formats differ. A tuning assumption copied from another generation may therefore be wrong.
+
+Build a hardware fact sheet: chip generation, physical and logical core configuration, external-memory capacity, on-chip limits, and device interconnects.
+
+Record the Neuron software version alongside it. A hardware instruction becomes useful only when the selected software path supports it correctly.
+
+Imagine moving a carefully tiled kernel between generations. Recheck its resource limits instead of assuming that successful compilation proves optimal mapping.
+
+**The takeaway: optimize a concrete configuration, not a product-family name.**
+
+Ask: which architectural limits apply here?
+
+Next, we trace the Neuron software stack.
+
+## Lecture thirteen A. The Neuron Framework, Compiler, and Runtime
+
+Our Trainium fact sheet now needs a software path.
+
+**Neuron** is the software stack connecting frameworks and serving engines to Trainium hardware. Its components divide responsibilities rather than acting as one interchangeable package.
+
+Framework integration presents model operations to the backend. The compiler produces device-executable work, applying supported transformations and using appropriate kernels. The runtime loads and executes compiled work, manages device interaction, and supports communication.
+
+Serving software adds request scheduling and cache management around that execution.
+
+Suppose startup is slow because several variants are being compiled. That is different from a warm request being slow because its attention kernel transfers too much data. The same latency number hides different problems.
+
+Track model loading, compilation, initialization, and steady-state serving separately. Preserve compatible compilation artifacts where the chosen path supports reuse.
+
+**The takeaway: locate the problem before changing compiler or runtime settings.**
+
+Ask: am I paying a preparation cost or a repeated execution cost?
+
+Next, we distinguish eager and compiled execution.
+
+## Lecture thirteen B. Eager Versus Compiled Execution on Trainium
+
+Do not assume that every Trainium program must begin as one fully compiled static graph.
+
+**Eager execution** runs operations as the program reaches them. It is convenient for debugging and experimentation. **Compiled execution** transforms supported regions into prepared device work that can be reused.
+
+At this series’ documentation snapshot, **TorchNeuron**, the native PyTorch backend for Trainium2 and Trainium3, supports eager execution and PyTorch’s compile interface. That native backend is documented as a public beta.
+
+This does not mean every existing model or custom GPU kernel transfers unchanged. Operator coverage, numerical behavior, and performance still require verification.
+
+Imagine an experiment with changing control flow. Eager mode can simplify development, while a stable hot region may benefit from compilation. Compare both after separating first-use costs from warm execution.
+
+Older Neuron framework paths also exist and have different constraints.
+
+**The takeaway: name the execution path before discussing its limitations.**
+
+Ask: what does compilation improve for this workload?
+
+Next, we examine shape specialization.
+
+## Lecture thirteen C. Shape Bucketing and Compilation Reuse
+
+Compiled execution often benefits from predictable shapes. Real requests rarely arrive in identical sizes.
+
+**Bucketing** maps variable workloads onto a limited collection of prepared shapes. Padding fills unused positions when necessary; masks preserve the intended computation.
+
+Imagine request lengths near five hundred, one thousand, and four thousand tokens. One maximum-size bucket may waste substantial work on shorter requests. More buckets can reduce padding, but increase preparation costs and the number of variants to maintain.
+
+The relevant shape may describe a prompt, a decode batch, or a context-length range. Those are different tuning dimensions.
+
+In supported Neuron serving paths, decode context-length bucketing can reduce unnecessary attention-cache reads. Compilation caches can reuse compatible artifacts, but changes in configuration or software may invalidate them.
+
+Choose buckets from a measured traffic distribution, not round numbers alone.
+
+**The takeaway: trade padding waste against variant complexity and compilation cost.**
+
+Ask: which bucket receives most real requests?
+
+Next, we consider when a custom kernel is justified.
+
+## Lecture fourteen A. When to Use the Neuron Kernel Interface
+
+Bucketing changes which work executes. Sometimes the costly operation itself needs a better implementation.
+
+**NKI**, Neuron Kernel Interface, lets developers write custom kernels with control over Trainium computation and data movement.
+
+Begin with profiling, not enthusiasm for low-level code. Check the existing optimized kernel library and the compiler-generated implementation first. A mature kernel may already solve your problem.
+
+Choose one expensive operation with stable, representative shapes. Write a correctness reference, then test normal inputs, edge shapes, and the required numerical tolerances.
+
+Imagine a standalone activation between two operations causing an unnecessary external-memory round trip. A custom fused kernel might help, but only if it preserves efficient matrix execution and legal buffer lifetimes.
+
+Include integration, compilation, and maintenance costs in the decision. A faster isolated kernel can still lose after surrounding layout conversions.
+
+**The takeaway: custom kernels need a measured reason to exist.**
+
+Ask: what overhead will this kernel remove?
+
+Next, we learn the layout rules that determine whether it can.
+
+## Lecture fourteen B. Partition Dimensions, Layouts, and Tiles
+
+A custom Trainium kernel must respect the structure of on-chip tensors.
+
+In NKI, SBUF and PSUM tensors have a **partition dimension**, mapping across parallel storage partitions. Their remaining **free dimensions** describe elements within that organization.
+
+This is more than a naming convention. Instructions impose layout requirements, and moving values across partitions can require real data movement rather than a free reinterpretation.
+
+For common matrix instructions, the reduction dimension—the dimension whose products are summed—must match the required partition layout of the operands.
+
+Imagine a tensor loaded in a convenient external-memory order but an inconvenient compute order. A transpose may become necessary before the Tensor Engine can consume it efficiently.
+
+A better design may load directly into an appropriate layout or preserve that layout across adjacent operations. Exact limits depend on the instruction and generation.
+
+**The takeaway: choose layouts for the whole producer-consumer chain.**
+
+Ask: is this reshape metadata-only, or does it physically move values?
+
+Next, we pipeline the required transfers.
+
+## Lecture fourteen C. Pipeline Transfers and Trainium Engine Execution
+
+Once layouts are legal, the next question is when each operation happens.
+
+**DMA**, direct memory access, refers to hardware-managed data transfers. Trainium kernels can arrange transfers and engine work so independent stages overlap when the architecture and compiler allow it.
+
+Imagine loading the next activation tile into SBUF while the Tensor Engine computes the current tile. A later vector operation processes a completed result while another matrix product begins.
+
+This pipeline needs enough buffer capacity and distinct live regions. Reusing storage too early creates a dependency or corrupts data; keeping everything indefinitely creates capacity pressure.
+
+Small fragmented transfers may also be less efficient than larger ones. Combining transfers can help, but must preserve the needed ordering and layout.
+
+Inspect the timeline for exposed waits rather than assuming that separate engines guarantee overlap.
+
+**The takeaway: schedule the transfers, computation, and buffer lifetimes together.**
+
+Ask: which stage sets the steady-state interval between completed tiles?
+
+Next, we choose the arithmetic those engines execute.
+
+## Lecture fifteen A. Choose Native Trainium Arithmetic
+
+An efficient pipeline still needs a numerical format the selected generation handles well.
+
+**BF16**, brain floating point sixteen, is a sixteen-bit floating-point format. Trainium3 also supports matrix operations using **MXFP8** and **MXFP4**: microscaling eight-bit and four-bit floating-point representations.
+
+Microscaling associates small groups of values with shared scale information. It is not the same representation as an arbitrary four-bit integer weight file.
+
+Supported Trainium3 matrix instructions combine these formats with their scale handling. That capability does not imply that every model backend selects the fastest path, or that every model retains acceptable quality.
+
+Imagine importing a compressed checkpoint whose grouping or layout differs from the native kernel’s expectations. Conversion, repacking, or a different execution format may be required.
+
+Compare total operation time, memory traffic, and quality after those steps are included.
+
+**The takeaway: match checkpoint representation to hardware arithmetic through a verified kernel path.**
+
+Ask: what conversions remain inside the repeated execution loop?
+
+Next, we inspect that loop with Neuron Explorer.
+
+## Lecture fifteen B. Profile with Neuron Explorer
+
+Trainium performance analysis follows GPU analysis logic, using different tools.
+
+**Neuron Explorer** provides profiling views for system behavior and device execution. Begin by separating host preparation, device work, transfers, and synchronization.
+
+Then inspect the region controlling request completion. Is the Tensor Engine waiting for an input? Are vector operations extending the tail? Is compilation or host scheduling appearing inside the measurement window?
+
+Imagine a matrix engine that looks active whenever it runs, but sits idle between short bursts. Increasing its arithmetic throughput may barely change the request. Removing an exposed transfer or dependency could matter more.
+
+Conversely, a continuously busy limiting engine suggests a different experiment: improve its work mapping or reduce its required operations.
+
+Form one hypothesis and state what trace change should follow from your intervention. Validate again without intrusive profiling.
+
+**The takeaway: engine activity becomes useful only when connected to elapsed time.**
+
+Ask: which wait can my next change remove?
+
+Next, we run a controlled serving experiment.
+
+## Lecture fifteen C. Run a Controlled Trainium Serving Experiment
+
+We can now connect Trainium architecture to a complete serving test.
+
+Start with a documented model recipe and compatible hardware, Neuron release, and serving-plugin versions. The **vLLM Neuron** plugin provides a supported route; verify its feature matrix for the exact model and execution path.
+
+Use our recurring dense-model workload, preserving prompt distribution, output lengths, concurrency, and quality requirements.
+
+Separate cold preparation from warm serving. Record the selected compilation path and whether existing artifacts were reused.
+
+Change one variable: for example, replace one broad context-length bucket with several narrower buckets. Predict less unnecessary cache traffic, then inspect whether the trace and end-to-end measurements support that prediction.
+
+A faster median is insufficient when the slowest supported shapes regress badly or memory usage becomes unacceptable.
+
+Only combine successful changes after testing them independently.
+
+**The takeaway: a hardware-specific optimization must survive the real request distribution.**
+
+Ask: what improved, what regressed, and why?
+
+Next, we move above individual devices to optimize the request stream.
+
+## Lecture sixteen A. Continuous Batching and Prefill Scheduling
+
+Fast devices can still deliver poor service when requests are scheduled badly.
+
+**Continuous batching** updates the active batch as requests finish and new work becomes eligible. Unlike a fixed batch that waits for every sequence, it can reuse available capacity during generation.
+
+However, a new request also brings prefill work. A long prompt can compete with ongoing decode steps and stretch users’ token gaps.
+
+**Chunked prefill** divides prompt processing into smaller pieces that can be scheduled alongside generation. Smaller chunks may protect streaming latency, while larger chunks may use matrix hardware more efficiently. The tradeoff also affects first-token delay.
+
+Imagine a document arriving while many short conversations are generating. The scheduler must decide how much prompt work to admit without violating their latency requirements.
+
+Keep the workload distribution fixed while varying the token budget per scheduling step.
+
+**The takeaway: optimize admitted work, not just kernel speed.**
+
+Ask: which requests pay for the larger batch?
+
+Next, we avoid repeated prompt computation.
+
+## Lecture sixteen B. Prefix Reuse and Cache-Aware Request Placement
+
+Scheduling decides when prompt work runs. Prefix caching can remove some of that work entirely.
+
+Suppose many requests begin with the same two-thousand-token system prompt. After processing it once, a compatible engine can reuse its cached keys and values for later requests with the identical prefix.
+
+The match must include the relevant model and configuration, not merely text that looks similar. A shared passage appearing after a different prefix is not automatically reusable.
+
+Reuse primarily avoids repeated prefill. Decode still attends to the cached prefix when full attention requires it.
+
+In a multi-replica service, routing toward an existing cache may increase hits. But an overloaded cache-rich worker can be slower than an idle worker that recomputes the prefix.
+
+Retained cache blocks also compete with active requests for memory. Respect isolation requirements when sharing across users.
+
+**The takeaway: value saved computation against queueing and retained memory.**
+
+Ask: does a cache hit reduce actual response time?
+
+Next, we reduce repeated decode work.
+
+## Lecture sixteen C. Speculative Decoding as a Hardware Tradeoff
+
+Prefix reuse accelerates repeated prompts. **Speculative decoding** attacks the sequential cost of generation.
+
+A cheaper draft mechanism proposes several tokens. The target model verifies them together, accepting valid proposals and correcting rejected ones according to the algorithm.
+
+Proper verification can preserve the target model’s sampling distribution. It does not imply every run produces identical text under every random-number implementation.
+
+The hardware opportunity is to replace several small target-model steps with a larger verification operation that reuses weights more effectively.
+
+Imagine ordinary decoding costs twenty milliseconds per token. A complete draft-and-verify round costing forty milliseconds and emitting four tokens averages ten milliseconds per token. Those are hypothetical numbers; include drafting, rejection, synchronization, and cache updates.
+
+A high acceptance rate alone does not prove a speedup. A saturated service may lose throughput to extra draft and verification work.
+
+**The takeaway: measure useful emitted tokens per complete round.**
+
+Ask: does speculation improve my latency-constrained workload?
+
+Next, we distribute work across devices.
+
+## Lecture seventeen A. Tensor Parallelism and Communication
+
+When one device is insufficient, we can distribute a layer itself.
+
+**Tensor parallelism** partitions weight tensors and the corresponding computation across devices. The exact partition determines which activations or partial results must be communicated.
+
+An **all-reduce** combines contributions, such as partial sums, and makes the combined result available to every participant. Other partitions require different collective operations.
+
+Imagine a layer taking eight milliseconds on one device. Four devices might ideally reduce its local computation to two milliseconds. But if exposed communication adds five milliseconds, total time becomes seven, not two.
+
+Some communication can overlap computation; some sits directly on the dependency path. Include the exposed portion rather than blindly adding every transfer duration.
+
+Partitioning can also create smaller, less efficient local matrix shapes. Attention-cache placement depends on the model and implementation.
+
+**The takeaway: dividing arithmetic does not divide latency automatically.**
+
+Ask: how much computation is saved after communication and shape penalties?
+
+Next, we compare splitting layers with running independent replicas.
+
+## Lecture seventeen B. Pipeline Parallelism Versus Independent Replicas
+
+Tensor parallelism splits work inside layers. **Pipeline parallelism** places different groups of layers on different devices.
+
+An activation passes through those stages in order. Different requests or microbatches can occupy different stages simultaneously. A **microbatch** is a smaller group of examples scheduled as a unit.
+
+With insufficient concurrent work, stages wait idle. These gaps are called pipeline bubbles. One token cannot traverse dependent stages simultaneously because more devices exist.
+
+By contrast, **independent replicas** each hold a model and process separate requests. They avoid inter-device communication inside a request, but duplicate weights and require enough memory per replica.
+
+Imagine a model that fits on one device and many unrelated users. Replication is a useful baseline. If the model cannot fit, partitioning may become necessary even before considering speed.
+
+Choose based on capacity, latency, throughput, and the arrival pattern.
+
+**The takeaway: model capacity and request parallelism are different problems.**
+
+Ask: am I distributing one request or many?
+
+Next, we include interconnect topology.
+
+## Lecture seventeen C. Make Parallelism Fit the Interconnect
+
+A parallelism strategy is incomplete until we place its workers on real connections.
+
+**Topology** describes which devices connect directly, the bandwidth of those links, and the paths communication must follow. Link latency matters as well as bandwidth, especially for small repeated collectives.
+
+Imagine two servers, each with four tightly connected accelerators, joined by a slower network. One candidate uses tensor parallelism within each server and pipeline stages across servers. Another runs an independent replica per server.
+
+Neither is automatically best. Compare model fit, local matrix shapes, communication volume, pipeline bubbles, and concurrency.
+
+On Trainium, inspect the relevant NeuronLink and network arrangement. On GPUs, inspect the actual accelerator and network fabric rather than assuming every pair communicates equally well.
+
+Adding devices can improve aggregate capacity while worsening an individual request’s latency.
+
+**The takeaway: map frequent communication onto the links that can support it.**
+
+Ask: which slow link lies on the critical path?
+
+Next, we examine how training changes the optimization budget.
+
+## Lecture eighteen A. Training and Fine-Tuning Need a Different Memory Budget
+
+So far, we have focused on inference. Training adds state that changes the optimization problem.
+
+Beyond weights and working tensors, we need gradients, optimizer state, and activations retained for backward computation. A full-sequence training step does not use the same growing inference-cache pattern as autoregressive serving.
+
+Consider an illustrative layout with two bytes of weights, two bytes of gradients, and eight bytes of optimizer state per parameter. That is twelve bytes before activations: ninety-six decimal gigabytes for eight billion parameters.
+
+Some implementations also retain higher-precision master weights. Actual totals depend on the optimizer, precision policy, and sharding.
+
+**LoRA**, low-rank adaptation, trains small added matrices rather than all base weights. It reduces trainable state, but does not eliminate activation or base-model execution costs.
+
+Measure training tokens per second and time to an acceptable result, not inference streaming latency.
+
+**The takeaway: rebuild the budget when the task changes.**
+
+Ask: which state actually consumes peak memory?
+
+Next, we trade recomputation for activation storage.
+
+## Lecture eighteen B. Activation Checkpointing and Recomputation
+
+Training activations can dominate memory even when model state is carefully managed.
+
+**Activation checkpointing** retains selected boundary values instead of every intermediate needed by the backward pass. Missing intermediates are recomputed when backward computation reaches that region.
+
+It trades additional arithmetic for lower retained memory. This differs from saving a training checkpoint to disk for recovery.
+
+Imagine memory limits us to a very small microbatch. Checkpointing frees enough space for a larger one. Each step may perform more arithmetic, yet useful tokens per second could improve through better hardware utilization or fewer accumulation steps.
+
+Alternatively, recomputation may simply slow an already efficient workload. Compare at the same effective batch and training-quality target.
+
+Selective policies can preserve expensive intermediates while recomputing cheaper ones. Correctness also requires consistent behavior for randomness and stateful operations.
+
+**The takeaway: evaluate the complete memory-throughput tradeoff, not recomputation cost alone.**
+
+Ask: what useful work becomes possible with the freed memory?
+
+Next, we distribute training state across devices.
+
+## Lecture eighteen C. Shard Training State with FSDP
+
+Checkpointing reduces retained activations. Another approach distributes model state itself.
+
+**FSDP**, Fully Sharded Data Parallel, partitions parameters, gradients, and optimizer state across participating workers rather than keeping every copy everywhere.
+
+Before a layer needs full parameters, an **all-gather** collects the required pieces. After backward computation, a **reduce-scatter** combines gradient contributions and distributes the resulting shards.
+
+The exact gathering and resharding schedule depends on configuration. Each worker still needs activations and temporary space for the computation it performs.
+
+Consequently, using eight workers does not guarantee that peak memory becomes exactly one-eighth of the original total. Temporarily gathered parameters and communication buffers also matter.
+
+Imagine a configuration that finally fits but repeatedly waits for parameter gathering. Adjusting grouping or overlap might improve it, while a slower network could erase the benefit.
+
+**The takeaway: state sharding exchanges replication for communication and scheduling complexity.**
+
+Ask: what remains replicated, and which collectives are exposed?
+
+Next, we revisit inference with mixture-of-experts models.
+
+## Lecture nineteen A. Mixture-of-Experts Models and Uneven Work
+
+Our dense-model examples use roughly the same weight structure for every token. **MoE**, mixture of experts, changes that pattern.
+
+A router selects a subset of expert networks for each token. Fewer active parameters can reduce arithmetic, but performance depends on how routed work is distributed.
+
+Imagine eight experts and sixteen tokens, with two experts selected per token. Thirty-two assignments are produced, but they need not divide evenly. Some experts receive tiny batches; others become bottlenecks.
+
+With **expert parallelism**, different devices own different experts. An **all-to-all** exchange can move each token’s activations to its selected experts and return results afterward.
+
+Now small matrix shapes, routing imbalance, and communication can dominate. The full expert weights still need storage even when only a subset is active for one token.
+
+Evaluate routing distributions, not just average active parameter counts.
+
+**The takeaway: sparse arithmetic does not guarantee efficient execution.**
+
+Ask: which expert or communication stage delays the batch?
+
+Next, we separate prefill and decode resources.
+
+## Lecture nineteen B. Separate Prefill and Decode—or Keep Them Together
+
+Prefill and decode favor different execution conditions. **Disaggregated serving** assigns them to separate resources rather than making each worker handle both phases.
+
+This can reduce interference and allow independent scheduling or hardware choices. But the decode worker needs the key-value state produced during prefill.
+
+Imagine transferring one decimal gigabyte over an effective fifty-gigabyte-per-second connection. Payload transfer alone takes twenty milliseconds, before coordination, conversion, contention, or additional copying.
+
+Any latency benefit must survive those costs. Throughput also depends on balancing the two resource pools; an underloaded pool can waste expensive capacity.
+
+Different device types may require compatible cache representations or extra transformation. Moving state is not automatically equivalent to copying a file.
+
+Compare against a well-tuned colocated baseline using the same workload, quality, and total resource budget. Also test traffic shifts that change the prefill-to-decode ratio.
+
+**The takeaway: phase specialization needs an end-to-end break-even calculation.**
+
+Ask: what gain exceeds the transfer and coordination cost?
+
+Next, we compare whole hardware choices.
+
+## Lecture nineteen C. Choose Hardware Using Matched Requirements
+
+We can compare CPUs, GPUs, and Trainium without reducing the decision to peak arithmetic.
+
+Hold the model task, acceptable quality, prompt distribution, output lengths, and latency requirements constant. Each platform may need a different implementation to meet that contract.
+
+Then measure **goodput**: useful service output satisfying the defined constraints. State precisely how you count failed or late requests.
+
+For a hypothetical service costing ten dollars per hour and delivering one thousand qualifying output tokens per second, one million output tokens cost about two dollars and seventy-eight cents. The calculation divides hourly cost by qualifying hourly output.
+
+Include host machines, networking, idle provisioned capacity, and relevant storage costs. Compilation and engineering effort can matter over a deployment’s lifetime.
+
+For energy, divide measured system energy by useful tokens; a chip’s rated power is not that measurement.
+
+**The takeaway: compare complete services at matched requirements.**
+
+Ask: which platform meets the contract most efficiently?
+
+Next, we apply the method to three final diagnosis exercises.
+
+## Lecture twenty A. CPU Capstone: More Cores, Worse Performance
+
+Here is a hypothetical CPU case using our recurring dense model.
+
+Sixteen threads generate twenty-eight tokens per second. Thirty-two generate twenty-four. The larger configuration crosses sockets, and profiling shows increased remote-memory reads. Precision, prompt length, and output length are unchanged.
+
+Do not conclude that thirty-two threads are always bad. Our first hypothesis is that placement is introducing expensive traffic.
+
+Keep the thread count fixed and test a local or correctly partitioned allocation policy. Compare remote traffic, achieved bandwidth, and generation rate. Preserve enough capacity to avoid paging.
+
+If locality improves but throughput does not, investigate bandwidth saturation and synchronization next. That outcome weakens the original explanation rather than proving the experiment failed.
+
+Finally, repeat the chosen configuration for prefill and through the real serving path. A decode-only victory may not satisfy the complete workload.
+
+**The takeaway: change one suspected cause and demand matching evidence.**
+
+Ask: did both the mechanism and the user metric improve?
+
+Next, we diagnose a busy GPU.
+
+## Lecture twenty B. GPU Capstone: High Utilization, Poor Response Times
+
+Consider a hypothetical GPU service reporting ninety-five percent utilization. Users still experience long pauses while answers stream.
+
+Its timeline shows large prefill operations arriving between decode steps. The device is busy, but busy on work that delays ongoing responses.
+
+Our hypothesis is scheduling interference, not an inefficient matrix kernel. Capturing the same workload in a graph would not automatically fix that allocation of time.
+
+Test a smaller prefill chunk budget while keeping the request-arrival trace, model, precision, and hardware unchanged. Predict shorter interruptions between decode steps, possibly at the expense of prompt-processing efficiency or first-token delay.
+
+Measure tail token gaps, first-token latency, and qualifying throughput together. Reject the change if it merely transfers an unacceptable delay from one group of users to another.
+
+Then test whether the improvement persists under different realistic prompt mixtures.
+
+**The takeaway: utilization describes activity, not whether activity serves the right objective.**
+
+Ask: whose latency improved, and who paid for it?
+
+Next, we diagnose Trainium.
+
+## Lecture twenty C. Trainium Capstone: Fast Arithmetic, Slow Serving
+
+Our hypothetical trace shows efficient Trainium matrix operations, yet disappointing decode latency.
+
+Most requests have short contexts, but the serving configuration uses one broad context-length bucket. Profiling shows attention-cache transfers over a much larger prepared region than most requests need.
+
+Our hypothesis is excess bucket-related traffic, not insufficient matrix throughput.
+
+Test a small set of context buckets matched to the observed distribution. Keep model quality, active concurrency, and the arrival trace unchanged. Separate new compilation costs from warm execution.
+
+Look for reduced cache traffic and shorter exposed waits. Then check long-context requests, memory consumption, and first-token latency. If transfers shrink but request time barely changes, another dependency has become dominant.
+
+That is the complete optimization loop: specify the workload, measure, form a hypothesis, intervene, and validate.
+
+**The takeaway: an optimization succeeds only under stated conditions, with evidence explaining why.**
+
+Ask: what is the new bottleneck?
+
+Across CPUs, GPUs, and Trainium, that question—not a favorite tuning flag—is the skill to retain.