// Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // test 2 kinds of loopback // 1. system loopback, any outgoing bits to TX are received through RX // 2. Line loopback, incoming bits (on RX) are forwarded to TX // Flattened from: uart_loopback_vseq -> uart_tx_rx_vseq -> uart_base_vseq class uart_loopback_vseq extends uart_base_vseq; `uvm_object_utils(uart_loopback_vseq) // ==================== Fields from uart_tx_rx_vseq ==================== rand uint num_tx_bytes; rand uint num_rx_bytes; rand uint dly_to_next_rx_trans; rand uint dly_to_next_tx_trans; rand uint dly_to_access_intr; rand bit wait_for_rx_idle; rand bit wait_for_tx_idle; rand uint weight_to_skip_rx_read; rand uint dly_to_rx_read; // ==================== Constraints from uart_tx_rx_vseq ==================== constraint num_trans_c { num_trans inside {[1:20]}; } constraint num_tx_bytes_c { num_tx_bytes dist { 1 :/ 2, [2:10] :/ 5, [11:15] :/ 5, [16:20] :/ 2 }; } constraint num_rx_bytes_c { num_rx_bytes dist { 1 :/ 2, [2:10] :/ 5, [11:15] :/ 5, [16:20] :/ 2 }; } constraint dly_to_next_rx_trans_c { dly_to_next_rx_trans dist { 0 :/ 5, // more back2back transaction [1:100] :/ 5, [100:10000] :/ 2 }; } constraint dly_to_next_tx_trans_c { dly_to_next_tx_trans dist { 0 :/ 5, // more back2back transaction [1:100] :/ 5, [100:10000] :/ 2 }; } constraint dly_to_access_intr_c { dly_to_access_intr dist { 0 :/ 1, [1 :100] :/ 5, [101 :10_000] :/ 3, [10_001 :1_000_000] :/ 1 }; } constraint wait_for_rx_idle_c { wait_for_rx_idle dist { 1 :/ 1, 0 :/ 10 }; } constraint wait_for_tx_idle_c { wait_for_tx_idle dist { 1 :/ 1, 0 :/ 10 }; } constraint weight_to_skip_rx_read_c { // 3: read, 7: skip weight_to_skip_rx_read == 7; } constraint dly_to_rx_read_c { dly_to_rx_read dist {0 :/ 1, [1:100] :/ 1, [100:10000] :/ 2}; } // ==================== Constraints from uart_loopback_vseq ==================== constraint en_tx_c { en_tx == 1; } constraint en_rx_c { en_rx == 1; } `uvm_object_new // ==================== pre_start from uart_tx_rx_vseq ==================== task pre_start(); super.pre_start(); num_trans.rand_mode(0); cfg.m_tl_agent_cfg.a_valid_delay_min = 0; cfg.m_tl_agent_cfg.a_valid_delay_max = 0; endtask // ==================== body from uart_loopback_vseq ==================== task body(); for (int i = 1; i <= num_trans; i++) begin if (cfg.stop_transaction_generators()) break; `DV_CHECK_RANDOMIZE_FATAL(this) uart_init(); randcase 1: drive_system_loopback(); 1: drive_line_loopback(); endcase `uvm_info(`gfn, $sformatf("finished run %0d/%0d", i, num_trans), UVM_LOW) end endtask : body // ==================== post_start from uart_tx_rx_vseq ==================== task post_start(); bit [TL_DW-1:0] intr_status; do_dut_shutdown = 0; if (ral.ctrl.tx.get_mirrored_value() == 0) begin clear_fifos(.clear_tx_fifo(1), .clear_rx_fifo(0)); cfg.clk_rst_vif.wait_clks(1); end super.post_start(); endtask // ==================== drive_system_loopback from uart_loopback_vseq ==================== virtual task drive_system_loopback(); byte unsigned tx_byte; `uvm_info(`gfn, "Start system loopback", UVM_HIGH) ral.ctrl.slpbk.set(1); csr_update(ral.ctrl); `DV_CHECK_STD_RANDOMIZE_FATAL(tx_byte) `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_next_tx_trans) cfg.clk_rst_vif.wait_clks(dly_to_next_tx_trans); // drive tx data and expect to receive it rx fifo send_tx_byte(tx_byte); // wait for loopback to complete spinwait_txidle(); spinwait_rxidle(); csr_rd_check(.ptr(ral.rdata), .compare_value(tx_byte)); // clear TxDone interrupt csr_wr(.ptr(ral.intr_state), .value(1 << TxDone)); // check status is default value csr_rd_check(.ptr(ral.status), .compare_value(ral.status.get_reset())); ral.ctrl.slpbk.set(0); csr_update(ral.ctrl); endtask // ==================== drive_line_loopback from uart_loopback_vseq ==================== // when line loopback is enabled, RX data will be wired to TX w/o any synchronizer // drive RX with random data and random delay, and check same value at TX virtual task drive_line_loopback(); `uvm_info(`gfn, "Start line loopback", UVM_HIGH) ral.ctrl.llpbk.set(1); csr_update(ral.ctrl); // disable monitor, as it can't handle these random data cfg.m_uart_agent_cfg.en_tx_monitor = 0; cfg.m_uart_agent_cfg.en_rx_monitor = 0; fork begin // isolation_fork fork // drive RX with random data and random delay repeat ($urandom_range(100, 1000)) begin cfg.m_uart_agent_cfg.vif.uart_rx = $urandom_range(0, 1); `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(dly_to_next_rx_trans, dly_to_next_rx_trans > 0;) #(dly_to_next_rx_trans * 1ns); end // RX has same value as TX without any synchronizer in the data path forever begin @(cfg.m_uart_agent_cfg.vif.uart_tx || cfg.m_uart_agent_cfg.vif.uart_rx); #1ps; // avoid race condition if (!cfg.under_reset) begin `DV_CHECK_EQ(cfg.m_uart_agent_cfg.vif.uart_tx, cfg.m_uart_agent_cfg.vif.uart_rx) end end join_any disable fork; end // isolation_fork join cfg.m_uart_agent_cfg.vif.uart_rx = 1; // back to default value cfg.m_uart_agent_cfg.en_tx_monitor = 1; cfg.m_uart_agent_cfg.en_rx_monitor = 1; // CDC sync on RX input adds propagation delay, so wait some cycles to ensure the internal RX // value is 1 before disabling line loopback. Otherwise, unexpected value (0) may be propagated // to RX datapath and be falsely interpreted as the beginning of a START bit. cfg.clk_rst_vif.wait_clks(2); // If noise filter is on, need an additional cycle of delay. if (en_noise_filter) cfg.clk_rst_vif.wait_clks(1); ral.ctrl.llpbk.set(0); ral.fifo_ctrl.rxrst.set(1); csr_update(ral.ctrl); csr_update(ral.fifo_ctrl); endtask endclass : uart_loopback_vseq