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| package cpu |
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| |
| const CacheLinePadSize = 128 |
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| func doinit() { |
| options = []option{ |
| {Name: "aes", Feature: &ARM64.HasAES}, |
| {Name: "pmull", Feature: &ARM64.HasPMULL}, |
| {Name: "sha1", Feature: &ARM64.HasSHA1}, |
| {Name: "sha2", Feature: &ARM64.HasSHA2}, |
| {Name: "sha512", Feature: &ARM64.HasSHA512}, |
| {Name: "sha3", Feature: &ARM64.HasSHA3}, |
| {Name: "crc32", Feature: &ARM64.HasCRC32}, |
| {Name: "atomics", Feature: &ARM64.HasATOMICS}, |
| {Name: "cpuid", Feature: &ARM64.HasCPUID}, |
| {Name: "isNeoverse", Feature: &ARM64.IsNeoverse}, |
| } |
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| |
| osInit() |
| } |
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| func getisar0() uint64 |
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| func getpfr0() uint64 |
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| func getMIDR() uint64 |
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| func extractBits(data uint64, start, end uint) uint { |
| return (uint)(data>>start) & ((1 << (end - start + 1)) - 1) |
| } |
|
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| func parseARM64SystemRegisters(isar0, pfr0 uint64) { |
| |
| |
| switch extractBits(isar0, 4, 7) { |
| case 1: |
| ARM64.HasAES = true |
| case 2: |
| ARM64.HasAES = true |
| ARM64.HasPMULL = true |
| } |
|
|
| switch extractBits(isar0, 8, 11) { |
| case 1: |
| ARM64.HasSHA1 = true |
| } |
|
|
| switch extractBits(isar0, 12, 15) { |
| case 1: |
| ARM64.HasSHA2 = true |
| case 2: |
| ARM64.HasSHA2 = true |
| ARM64.HasSHA512 = true |
| } |
|
|
| switch extractBits(isar0, 16, 19) { |
| case 1: |
| ARM64.HasCRC32 = true |
| } |
|
|
| switch extractBits(isar0, 20, 23) { |
| case 2: |
| ARM64.HasATOMICS = true |
| } |
|
|
| switch extractBits(isar0, 32, 35) { |
| case 1: |
| ARM64.HasSHA3 = true |
| } |
|
|
| switch extractBits(pfr0, 48, 51) { |
| case 1: |
| ARM64.HasDIT = true |
| } |
| } |
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