question stringlengths 23 136 | answer stringlengths 294 1.09k | image_path dict | netlist stringlengths 27 549 ⌀ |
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If we double the length and width of a MOSFET, what happens to its intrinsic gain? | The intrinsic gain is `Av,int = gm ro`.
If both `W` and `L` are doubled while the overdrive voltage is kept constant, `W/L` is unchanged, so `gm` is approximately unchanged. The drain current is also approximately unchanged, while `ro = 1/(lambda ID)` increases because `lambda` decreases as `L` increases. Thus `ro` ap... | null | null |
Student A says the transconductance of a MOSFET goes up as the overdrive voltage increases. Student B says it goes down. Who is correct? | Both statements can be true, depending on what is held fixed.
For a long-channel MOSFET in saturation,
`gm = mu Cox (W/L) Vov = 2 ID / Vov`.
If `W/L` is fixed and `Vov` is increased, then `ID` rises as `Vov^2` and `gm` increases linearly with `Vov`; Student A is correct under this condition. If instead `ID` is fixed... | null | null |
Is the small-signal model of a PMOS device identical to that of an NMOS device? | Yes, the small-signal model has the same form after using consistent voltage and current polarities.
A PMOS has `gm`, `gmb`, `ro`, and terminal capacitances analogous to an NMOS. The controlled source direction and sign conventions are reversed if the same absolute node-voltage directions are used, but with source-ref... | null | null |
Sketch IX versus VX in the circuit in Figure 1. | The transistor is diode-connected with its gate and drain tied to `VX`, source at ground. For `VX <= VTH`, the device is off and `IX` is approximately zero.
For `VX > VTH`, the device operates in saturation because `VDS = VGS = VX`, so
`IX ~= (1/2) mu Cox (W/L) (VX - VTH)^2`
ignoring channel-length modulation. The s... | {
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M1 (net7 net7 VSS VSS) nmos |
Sketch IX versus VX in the circuit of Figure 2. | In Figure 2, `VX` is applied to the gate, the source is grounded, and the drain is held at `1 V`. Thus `VGS = VX` and `VDS = 1 V`.
For `VX <= VTH`, the transistor is off and `IX ~= 0`.
For `VTH < VX < VTH + 1 V`, the condition `VDS >= VGS - VTH` is satisfied, so the device is in saturation and
`IX ~= (1/2) mu_n Cox ... | {
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Ix (net8 net9 VSS VSS) nmos
V1 (net8 VSS) vsource |
Can the device shown in Figure 3 act as a current source? | No. The device is diode-connected, so it presents a low small-signal resistance of roughly `1/gm` rather than a high output resistance.
A good current source should maintain nearly constant current while its terminal voltage changes. Here the current is strongly set by the terminal voltage through the diode-connected ... | {
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Analyze the circuit shown in Figure 4. | Figure 4 is a PMOS common-source stage with source degeneration. The source is connected to `VDD` through `RS`, the drain is loaded by `RD`, the input is applied to the gate, and the output is taken at the drain.
For a small-signal analysis with `VDD` as ac ground, the gain magnitude is reduced by the source degenerat... | {
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Rs (VDD net7) resistor
M1 (VO VIN net7 net7) pmos |
Analyze the circuit shown in Figure 5. | Figure 5 is a source follower. The input is applied to the gate, the output is at the source, and `RS` is the source load.
Neglecting body effect and `ro`,
`Av = vout/vin ~= gm RS / (1 + gm RS)`.
The gain is positive and less than unity. The output resistance looking into the source is approximately `1/gm` in parall... | {
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M1 (VDD VIN net9 net9) nmos |
Analyze the circuit shown in Figure 6. | In Figure 6, `Vin` is applied to the source of `M1`, the gate is tied to a dc bias at `VDD` and is therefore ac-grounded, and the output is taken at the drain through `RD`.
This is a common-gate stage, not a common-source stage. Neglecting `ro`, the small-signal input resistance seen at the source is approximately
`R... | {
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M1 (VO VDD VIN VIN) nmos |
Analyze the circuit shown in Figure 7. | In Figure 7, `Vin` is coupled through `C1` to the source node of `M1`, but that same source node is directly shorted to ground. The gate is biased by `Vb`, and the output is taken at the drain through `RD`.
Because the input is applied to a node that is hard-shorted to ground, the ideal small-signal voltage at the sou... | {
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RD (VDD VOUT) resistor
C1 (VIN net_s) capacitor
M1 (VOUT VB net_s VSS) nmos
VSRC_GND (net_s VSS) vsource
ends ckt_common_gate |
How many poles does the circuit of Figure 8 have? | The circuit has two poles in the usual small-signal model.
The capacitors are connected among two independent dynamic nodes: the input/gate-side node and the output/drain-side node. `CGD` couples these two nodes, but it does not by itself create a third independent node.
Thus the number of poles is two. More precisel... | {
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CGS (net12 VSS) capacitor
CSB (VSS VSS) capacitor
RD (VDD VO) resistor
Rs (VIN net12) resistor
CDB (VO VSS) capacitor
CGD (net12 VO) capacitor |
Analyze the circuit shown in Figure 9. | Figure 9 contains negative feedback, but the source of `M1` is not grounded. The input `Vin` is applied to the source of the NMOS, while the gate voltage `VF` is generated by the `R1`-`R2` divider from `Vout`.
The drain/output node is loaded by `RD`. A change in output voltage is divided down to the gate, so the circu... | {
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R2 (net9 VSS) resistor
RD (VDD VO) resistor
M1 (VO net9 VIN VIN) nmos |
Analyze the circuit shown in Figure 10. | Figure 10 is a source follower, not a common-source amplifier with an active load. `M1` receives the input at its gate, and the output is taken from its source. `M2` provides a bias current path to ground.
The small-signal voltage gain is positive and less than unity. Neglecting body effect and output resistances, the... | {
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M2 (VO Vb VSS VSS) nmos |
Analyze the circuit of Figure 11(a). | Figure 11(a) is a CMOS inverter. The PMOS pull-up device connects the output to `VDD` when the input is low, and the NMOS pull-down device connects the output to ground when the input is high.
As an analog stage biased near its switching point, it behaves as a high-gain inverting amplifier with transconductance approx... | {
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M1 (VO VIN VSS VSS) nmos |
Analyze the circuit shown in Figure 11(b). | Figure 11(b) is not a proper CMOS inverter. Compared with the normal inverter in Figure 11(a), the device polarities/source-drain orientations are effectively swapped: the upper device is an NMOS connected to `VDD`, and the lower device is a PMOS connected to ground.
Although both gates are driven by `Vin`, the topolo... | {
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M2 (VO VIN VSS VSS) nmos |
Analyze the circuit of Figure 12. | Figure 12 is a common-source NMOS stage with a diode-connected PMOS load. `M1` is the input transistor and `M2` is diode-connected to `VDD`, providing a nonlinear active load.
The output is at the drain of `M1`, so the stage is inverting. The small-signal load resistance of the diode-connected PMOS is approximately `1... | {
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M1 (VO VIN VSS VSS) nmos |
Analyze the circuit of Figure 13. | Figure 13 has two PMOS devices, not a PMOS stacked on an NMOS. The input `Vin` is applied to the gate of the upper PMOS `M2`, and the output is the common node between `M2` and the lower PMOS `M1`.
The lower device `M1` has its gate and lower terminal tied to ground. With PMOS source-at-higher-potential convention, it... | {
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M1 (VSS VSS VO VO) pmos |
Find Rout in Figure 14. | Figure 14 is a PMOS current-source stack, and the output resistance is measured looking into the drain of the lower device `M1`.
Here `M1`, not `M2`, is the common-gate/cascode device seen from the output port. The upper PMOS `M2` sets the bias current and the intermediate node `X`; the lower PMOS `M1` shields that no... | {
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M1 (net10 Vb1 net8 net8) pmos |
How do we ensure that M2 is in saturation in Figure 14? | To keep `M2` in saturation, the drain-source voltage of `M2` must exceed its overdrive voltage. In the stack of Figure 14 this condition is controlled mainly by the intermediate node `X`, which is set by the lower bias `Vb1` and the current through `M1`.
The bias must leave enough voltage across `M2`. Razavi's conditi... | {
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M1 (net10 Vb1 net8 net8) pmos |
Analyze the circuit shown in Figure 15. | Figure 15 is an NMOS cascode gain stage. `M1` is the input common-source transistor, `M2` is the common-gate cascode transistor biased by `Vb1`, and `I1` is the load current source at the output.
A change in `vin` changes the drain current of `M1`; `M2` conveys this current to the output while holding node `X` relativ... | {
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M2 (VO Vb1 net10 net10) nmos
M1 (net10 VIN VSS VSS) nmos |
Is the circuit of Figure 16 a cascode structure? | No. Figure 16 is not a cascode in the usual sense because the lower device does not operate as a common-source input device feeding a common-gate cascode. Instead, `M1` acts as a source follower.
The output resistance is therefore not the usual cascode value `gm ro1 ro2`. Razavi gives the resistance as approximately
... | {
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RD (VDD VO) resistor
M1 (VSS VIN net10 net10) pmos |
Explain why the Miller effect is less pronounced in a cascode. | In a cascode, the drain of the input common-source transistor is held at a relatively low-impedance node by the common-gate cascode device. Therefore the voltage swing across the input transistor's `Cgd` is much smaller than in a single common-source stage whose drain has a large gain swing.
The Miller multiplication ... | null | null |
Analyze the circuit shown in Figure 17. | Figure 17 is a common-gate NMOS stage with a PMOS current-source load. The input `Vin` is applied at the source side of `M2`, while the gate of `M2` is biased by `Vb1`. `M1`, biased by `Vb2`, provides the PMOS load from `VDD`.
Because the input is at the source of `M2`, the stage is not a gate-driven common-source amp... | {
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M2 (VO Vb1 VIN VIN) nmos |
How many poles does the circuit of Figure 18 have? | The circuit has two independent poles in the shown small-signal model.
One pole is associated with the input/gate-side node of `M1`, which contains `CGS` and the input-side effect of `CGD`. The other pole is associated with the output/cascode node, which contains `CDB`, `CDB2`, and the output-side effects of the capac... | {
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CGS (net19 VSS) capacitor
M2 (VO VSS VSS VSS) pmos
CDB2 (VSS VO) capacitor
RS (VIN net19) resistor
CGD2 (VSS VO) capacitor
CGD (net19 VO) capacitor
CDB (VO VSS) capacitor |
Analyze the circuit shown in Figure 19. | Figure 19 is two series NMOS devices sharing the same gate signal, with a resistive load at the top. If `M1` and `M2` are identical and biased together, the pair behaves like a single transistor with approximately twice the channel length.
This is not a differential half-circuit, not a gain-boosted cascode, and not a ... | {
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M1 (net12 VIN VSS VSS) nmos
RD (VDD VO) resistor |
Analyze the circuit of Figure 20. | Figure 20 can be viewed as a source follower `M1` driving a common-gate stage `M2`. The input is applied to the gate of `M1`; the source of `M1` drives the source of `M2`; the output is taken at the drain of `M2` through `RD`.
Thus the circuit is not a common-source amplifier with an NMOS cascode. The signal first app... | {
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I1 (net16 VSS) isource
M2 (VO Vb net16 net16) nmos
RD (net12 VO) resistor |
Explain why the output impedance of the circuit shown in Figure 21 can be inductive. | The output impedance can look inductive because the impedance seen at the output changes from one real resistance at low frequency to another at high frequency with a phase lead over the transition.
At very low frequency, `CGS1` is open and the output impedance is approximately `1/gm1`. At very high frequency, `CGS1` ... | {
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M2 (VO Vb VSS VSS) nmos
Rs (VIN net12) resistor |
Analyze the circuit shown in Figure 22. | Figure 22 is a current-input circuit with positive feedback. The input current is injected into node `X`, which drives the gate of `M1`. `M1` is a common-source device with load `RD1`, so an increase in `X` lowers `Vout`. The gate of `M2` is tied to `Vout`, not to its drain at `X`.
This creates positive feedback at th... | {
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M1 (VO net10 VSS VSS) nmos
RD1 (VDD VO) resistor |
Analyze the circuit of Figure 23. | Figure 23 is a feedback transimpedance-style amplifier. `M1` is a common-gate input device: its gate is fixed at `Vb`, the input current enters its source node, and its drain voltage appears at node `X` through `RD1`. Node `X` drives the gate of `M2`, which is a common-source second stage with load `RD2`.
The resistor... | {
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M1 (net11 Vb net14 net14) nmos
M2 (VO net11 VSS VSS) nmos
RD2 (net9 VO) resistor
RF_1 (net14 VO) resistor
RD1 (net9 net11) resistor |
Analyze the circuit shown in Figure 24. | Figure 24 is a current-input feedback circuit using a common-gate NMOS input device and a PMOS feedback device. `M1` is an NMOS biased by `Vb`, with its source connected to the input/summing node and its drain connected to `Vout`. `M2` is the upper PMOS device connected to `VDD`, with its gate driven by `Vout` and its ... | {
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I1 (net17 VSS) isource
I2 (VDD VO) isource
M1 (VO Vb net17 net17) nmos
M2 (net17 VO VDD VDD) pmos |
Does the circuit in Figure 5 fail to oscillate if the three capacitors become arbitrarily large? | No. With identical capacitors added at all three nodes of the ring oscillator, the circuit continues to oscillate, but the oscillation frequency decreases as the node capacitance increases.
The capacitors slow each inverter transition and increase the delay per stage. In a three-stage ring, oscillation is maintained a... | {
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INV1 (net1 net2) inverter
C2 (net3 VSS) capacitor
C3 (net1 VSS) capacitor
INV2 (net2 net3) inverter
C1 (net2 VSS) capacitor
INV3 (net3 net1) inverter
ends ckt_figure-05 |
What happens to the phase noise if the three capacitors in Figure 5 are doubled? | Doubling all three load capacitors lowers the oscillation frequency by about a factor of two. For white-noise-induced phase noise in this ring oscillator, the relevant expression scales with `f0^2` while the other parameters are approximately independent of `CL`.
Therefore, when `CL` is doubled and `f0` is halved, the... | {
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INV1 (net1 net2) inverter
C2 (net3 VSS) capacitor
C3 (net1 VSS) capacitor
INV2 (net2 net3) inverter
C1 (net2 VSS) capacitor
INV3 (net3 net1) inverter
ends ckt_figure-05 |
Does the circuit in Figure 6 fail to oscillate if CL becomes arbitrarily large? | Yes. When a large capacitor is added to only one node, it creates a dominant pole that causes excessive gain roll-off around the loop.
For sufficiently large `CL`, the loop gain falls below unity at the phase-crossover frequency, so the Barkhausen condition is no longer satisfied and oscillation fails. | {
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INV2 (net2 net3) inverter
INV1 (net1 net2) inverter
CL (net2 VSS) capacitor
INV3 (net3 net1) inverter
ends ckt_figure-06 |
If we double the widths of the NMOS and PMOS devices in Figure 7, what happens to the phase noise? | Doubling the widths of all NMOS and PMOS devices reduces the phase noise by about 3 dB.
A linear scaling argument gives this result: doubling device widths doubles the drive strength and capacitances in a way roughly equivalent to placing two identical ring oscillators in parallel. The signal power/current capability ... | {
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MN1 (net13 net12 VSS VSS) nmos
MN2 (net14 net13 VSS VSS) nmos
MN3 (net12 net14 VSS VSS) nmos
MP1 (net13 net12 VDD VDD) pmos
MP2 (net14 net13 VDD VDD) pmos
MP3 (net12 net14 VDD VDD) pmos
ends ckt_figure-07 |
Determine the small-signal resistance seen looking into the supply node of the ring oscillator in Figure 8. | The resistance seen looking into the supply node of the oscillating ring is not simply the static resistance of diode-connected inverter devices. Oscillation matters because the supply current charges and discharges the three load capacitances each cycle.
For a three-stage ring with node capacitance `CL` and oscillati... | {
"bytes": "iVBORw0KGgoAAAANSUhEUgAACBYAAAT8CAYAAAA955GJAAAEDmlDQ1BrQ0dDb2xvclNwYWNlR2VuZXJpY1JHQgAAOI2NVV1oHFUUPpu5syskzoPUpqaSDv41lLRsUtGE2uj+ZbNt3CyTbLRBkMns3Z1pJjPj/KRpKT4UQRDBqOCT4P9bwSchaqvtiy2itFCiBIMo+ND6R6HSFwnruTOzu5O4a73L3PnmnO9+595z7t4LkLgsW5beJQIsGq4t5dPis8fmxMQ6dMF90A190C0rjpUqlSYBG+PCv9rt7yDG3tf2t/f/Z+... | subckt ckt_figure-08 VSS R
INV1 (net2 net3 VSS R) inverter
INV2 (net3 net4 VSS R) inverter
INV3 (net4 net2 VSS R) inverter
ends ckt_figure-08 |
If the circuit oscillates, does your answer change? | Considering the oscillation does not make `RX` much larger. The effective resistance is set by the dynamic charging and discharging of the oscillator nodes, not by a dc path that is mostly off.
Using `f0 = 1/(6 TD)` for a three-stage ring, the equivalent supply resistance can be written approximately as
`RX ~= 2 TD /... | null | null |
In the circuit of Figure 9, what happens to the initial voltage gain as the width of M7 increases? | As the width of tail transistor `M7` increases, the initial voltage gain decreases.
A wider `M7` increases the tail current available during regeneration. In the StrongARM comparator relation cited by Razavi, the initial gain scales roughly like
`Av ~= gm1,2 VTHN / ICM`,
where `ICM` is tied to the current through `M... | {
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M7 (Tail CK VSS VSS) nmos
M1 (P Vin1 Tail VSS) nmos
M2 (Q Vin2 Tail VSS) nmos
M3 (X Y P VSS) nmos
M4 (Y X Q VSS) nmos
M5 (X Y VDD VDD) pmos
M6 (Y X VDD VDD) pmos
S1 (P CK VDD VDD) pmos
S2 (Q CK VDD VDD) pmos
S3 (X CK VDD VDD) pmos
... |
In Figure 9, what happens to the initial voltage gain if we increase the capacitance at nodes P and Q? | The initial voltage gain remains approximately unchanged.
The initial gain expression depends mainly on the transconductance of the input pair and the common-mode/tail current, not directly on the capacitance at nodes `P` and `Q`. Increasing those capacitances slows the transient response, but it does not change the i... | {
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M7 (Tail CK VSS VSS) nmos
M1 (P Vin1 Tail VSS) nmos
M2 (Q Vin2 Tail VSS) nmos
M3 (X Y P VSS) nmos
M4 (Y X Q VSS) nmos
M5 (X Y VDD VDD) pmos
M6 (Y X VDD VDD) pmos
S1 (P CK VDD VDD) pmos
S2 (Q CK VDD VDD) pmos
S3 (X CK VDD VDD) pmos
... |
If we increase the widths of M5 and M6 in Figure 9, does the speed improve or degrade? | Increasing the widths of `M5` and `M6` initially improves speed.
Although their capacitances increase, the dominant capacitances at nodes `X` and `Y` initially come from other devices and nodes. Wider `M5`/`M6` provide stronger regenerative or pull-up action, so the comparator speeds up until the added capacitance fro... | {
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M7 (Tail CK VSS VSS) nmos
M1 (P Vin1 Tail VSS) nmos
M2 (Q Vin2 Tail VSS) nmos
M3 (X Y P VSS) nmos
M4 (Y X Q VSS) nmos
M5 (X Y VDD VDD) pmos
M6 (Y X VDD VDD) pmos
S1 (P CK VDD VDD) pmos
S2 (Q CK VDD VDD) pmos
S3 (X CK VDD VDD) pmos
... |
In the circuit of Figure 10, does the speed improve or degrade if we increase the widths of the clocked transistors? | For the C2MOS divider in Figure 10, increasing the widths of the clocked transistors can improve speed initially.
If the data-driven devices are the bottleneck, stronger clocked devices reduce their on-resistance and help the latch transfer data faster. These wider clocked devices also add capacitance in the data path... | {
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M6 (net13 P4 net10 VDD) pmos
M7 (net13 P1 net17 VSS) nmos
M2 (net8 P2 net9 VDD) pmos
M1 (net9 net1 VDD VDD) pmos
M8 (net17 net8 VSS VSS) nmos
M5 (net10 net8 VDD VDD) pmos
M3 (net8 P3 net16 VSS) nmos
M4 (net16 net1 VSS VSS) nmos
U1 (net13 net1 ... |
Does the structure in Figure 10 provide quadrature outputs? | The structure does not provide ideal quadrature outputs in a robust sense.
The internal nodes can appear phase-shifted, but the delay through `Inv3` skews node `Z`. Also, the two latches do not necessarily see equal load capacitances. For example, the gate-drain capacitances in `Inv3` experience Miller multiplication,... | {
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M6 (net13 P4 net10 VDD) pmos
M7 (net13 P1 net17 VSS) nmos
M2 (net8 P2 net9 VDD) pmos
M1 (net9 net1 VDD VDD) pmos
M8 (net17 net8 VSS VSS) nmos
M5 (net10 net8 VDD VDD) pmos
M3 (net8 P3 net16 VSS) nmos
M4 (net16 net1 VSS VSS) nmos
U1 (net13 net1 ... |
Repeat question 10 for the topology in Figure 11. | For the topology in Figure 11, increasing the widths of the clocked transistors improves speed considerably over an initial useful range.
In this arrangement, the clocked devices do not interfere strongly with the data path, so their lower on-resistance directly helps the transition speed. Charge sharing can occur, bu... | {
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M4 (net15 P3 VSS VSS) nmos
M8 (net14 P1 VSS VSS) nmos
M5 (net11 P4 VDD VDD) pmos
M1 (net10 P2 VDD VDD) pmos
M7 (net13 net12 net14 VSS) nmos
M2 (net12 net1 net10 VDD) pmos
M3 (net12 net1 net15 VSS) nmos
M6 (net13 net12 net11 VDD) pmos
U1 (net13... |
Analyze the arrangement in Figure 12(a). | Figure 12(a) is a divide-by-two circuit built from dynamic latches.
The clocked latches alternately sample and hold, so the output toggles once for every two input clock cycles. The dynamic nature means stored charge and leakage matter, but the intended function is a frequency divider by two. | {
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S1 (net_a_fb net_a_in1) switch
U1 (net_a_in1 net_a_out1) inverter
S2 (net_a_out1 net_a_in2) switch
U2 (net_a_in2 net_a_out2) inverter
U3 (net_a_out2 net_a_fb) inverter
ends ckt_figure-12a
subckt ckt_figure-12b
S3 (net_b_fb net_b_in1) switch
U5 (net_b_i... |
How does the red inverter in Figure 12(b) affect the performance? | The red inverter creates a feedforward path around the first latch. This feedforward path improves divider speed because part of the signal can bypass the main latch path.
It is not simply a keeper or a cross-coupled latch with `Inv1`. At low clock frequencies, the unclocked feedforward branch can dominate the main pa... | {
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S1 (net_a_fb net_a_in1) switch
U1 (net_a_in1 net_a_out1) inverter
S2 (net_a_out1 net_a_in2) switch
U2 (net_a_in2 net_a_out2) inverter
U3 (net_a_out2 net_a_fb) inverter
ends ckt_figure-12a
subckt ckt_figure-12b
S3 (net_b_fb net_b_in1) switch
U5 (net_b_i... |
But the input of the red inverter is not tied to the output of Inv1. | Because the input of the red inverter is not tied to the output of `Inv1`, the red inverter is not cross-coupled with `Inv1` and should not be interpreted as a keeper.
Instead, it is a feedforward branch. It takes an earlier signal and drives a later node, bypassing part of the latch path. This can improve high-speed ... | null | null |
How do we optimize the circuit of Figure 13 for the NF if Rin must remain equal to 50 Ohm? | The circuit should be optimized by using channel-length modulation and feedback together, not by simply making the load resistance as large as possible.
With `Rin` constrained to 50 ohm, the design variables must be chosen so that the input match is maintained while the noise contribution of the active devices and fee... | {
"bytes": "iVBORw0KGgoAAAANSUhEUgAAByIAAARWCAYAAAB3gHWFAAAEDmlDQ1BrQ0dDb2xvclNwYWNlR2VuZXJpY1JHQgAAOI2NVV1oHFUUPpu5syskzoPUpqaSDv41lLRsUtGE2uj+ZbNt3CyTbLRBkMns3Z1pJjPj/KRpKT4UQRDBqOCT4P9bwSchaqvtiy2itFCiBIMo+ND6R6HSFwnruTOzu5O4a73L3PnmnO9+595z7t4LkLgsW5beJQIsGq4t5dPis8fmxMQ6dMF90A190C0rjpUqlSYBG+PCv9rt7yDG3tf2t/f/Z+... | subckt ckt_figure-13 VDD VSS in out
M1 (out net2 VSS VSS) nmos
M2 (out net2 VDD VDD) pmos
C1 (in net2) capacitor
RF (net2 out) resistor
ends ckt_figure-13 |
Compute the input impedance of the circuit in Figure 14(a). | Use the simplified model in Figure 14(b) and apply Miller's theorem to the feedback resistor.
The exact input resistance is
`Rin = (RF + RD2) / (1 + A0)`
where the unloaded gain is
`A0 = (1/2) gm1 gm2,3 RD1 RD2`.
This expression is preferable to a generic shunt-shunt feedback formula because it follows the actual ... | {
"bytes": "iVBORw0KGgoAAAANSUhEUgAAAzsAAAGPCAIAAAD0iVkyAAB6C0lEQVR4nO3dB1iT1xoH8BP23kPZoiAIyHCAOHHirKNO6qpad7VV66it2useVavV1q0VcWPddeGqiiIiAdkgCgKyZxgJuU84+DUGRDZJ+P9un/skJ1++nHxBeHPOe97D4vP5BAAAAADEmExTdwAAAAAAPgMRGwAAAIC4Q8QGAAAAIO4QsQEAAACIO0RsAAAAAOIOERsAAACAuEPEBgAAACDuELEBAAAAiDtEbAAAAADiDhEbAAAAgLhDxAYAAAAg7h... | subckt ckt_figure-14a VDD VSS Vb P Vout
Iin (P VSS) isource
Cin (P VSS) capacitor
M1 (X P VSS VSS) nmos
RD1 (VDD X) resistor
ISS (VDD Tail) isource
M2 (VSS X Tail VDD) pmos
M3 (Vout Vb Tail VDD) pmos
RD2 (Vout VSS) resistor
RF (P Vout) resistor
ends ckt_figure-14a
subckt ck... |
If the LDO regulator in Figure 15 generates thermal noise with spectrum Sth, how do we compute the VCO output phase noise? | The LDO output noise modulates the VCO frequency through the supply-pushing gain. First determine the pushing gain
`Kpush = d fosc / d Vout`
usually by simulation or perturbation analysis. Then convert the LDO noise spectrum `Sth` to phase noise through frequency modulation. In the notation of the article, the single... | {
"bytes": "iVBORw0KGgoAAAANSUhEUgAACKoAAAT0CAYAAABFfnhTAAAEDmlDQ1BrQ0dDb2xvclNwYWNlR2VuZXJpY1JHQgAAOI2NVV1oHFUUPpu5syskzoPUpqaSDv41lLRsUtGE2uj+ZbNt3CyTbLRBkMns3Z1pJjPj/KRpKT4UQRDBqOCT4P9bwSchaqvtiy2itFCiBIMo+ND6R6HSFwnruTOzu5O4a73L3PnmnO9+595z7t4LkLgsW5beJQIsGq4t5dPis8fmxMQ6dMF90A190C0rjpUqlSYBG+PCv9rt7yDG3tf2t/f/Z+... | subckt ckt_figure-15 VDD VSS Vcont X Y
XLDO (VDD Vout VSS) LDO_subcircuit
L1 (Vout X) inductor
L2 (Vout Y) inductor
M1 (X Y net9 VSS) nmos
M2 (Y X net9 VSS) nmos
I (net9 VSS) isource
M_v1 (Vcont X Vcont Vcont) nmos_varactor
M_v2 (Vcont Y Vcont Vcont) nmos_varactor
C1 (X net7) capaci... |
We add CT to the tail node, as in Figure 16. What happens to the phase noise? | Adding `CT` to the tail node has a nonmonotonic effect on phase noise.
For small or moderate `CT`, the tail-node waveform changes and the flicker noise of `M1` and `M2` can be upconverted to phase noise unless the devices follow an ideal square law. For a certain range of `CT`, the cross-coupled devices enter class-C-... | {
"bytes": "iVBORw0KGgoAAAANSUhEUgAAB0YAAAYiCAYAAACooI9xAAAEDmlDQ1BrQ0dDb2xvclNwYWNlR2VuZXJpY1JHQgAAOI2NVV1oHFUUPpu5syskzoPUpqaSDv41lLRsUtGE2uj+ZbNt3CyTbLRBkMns3Z1pJjPj/KRpKT4UQRDBqOCT4P9bwSchaqvtiy2itFCiBIMo+ND6R6HSFwnruTOzu5O4a73L3PnmnO9+595z7t4LkLgsW5beJQIsGq4t5dPis8fmxMQ6dMF90A190C0rjpUqlSYBG+PCv9rt7yDG3tf2t/f/Z+... | subckt ckt_figure-16 VDD VSS X Y
M1 (X Y P VSS) nmos
M2 (Y X P VSS) nmos
L1 (VDD X) inductor
L2 (VDD Y) inductor
ISS (P VSS) isource
CT (P VSS) capacitor
ends ckt_figure-16 |
Estimate the oscillation frequency of the circuit in Figure 17. | Start from the tank resonance
`omega0 = 1 / sqrt(L Cnode)`.
The coupling shifts the oscillation frequency away from resonance. The shift is
`Delta omega = alpha omega0 / (2 Q)`
where `alpha` is the coupling coefficient. In a typical large-signal design with nearly complete switching,
`alpha ~= I1 / ISS`,
so
`Del... | {
"bytes": "iVBORw0KGgoAAAANSUhEUgAABB4AAAWeCAYAAADHYeZfAAAEDmlDQ1BrQ0dDb2xvclNwYWNlR2VuZXJpY1JHQgAAOI2NVV1oHFUUPpu5syskzoPUpqaSDv41lLRsUtGE2uj+ZbNt3CyTbLRBkMns3Z1pJjPj/KRpKT4UQRDBqOCT4P9bwSchaqvtiy2itFCiBIMo+ND6R6HSFwnruTOzu5O4a73L3PnmnO9+595z7t4LkLgsW5beJQIsGq4t5dPis8fmxMQ6dMF90A190C0rjpUqlSYBG+PCv9rt7yDG3tf2t/f/Z+... | subckt ckt_figure-17 VDD VSS X1 Y1 X2 Y2
L1 (VDD X1) inductor
L2 (VDD Y1) inductor
M2 (X1 Y1 tail_in1 VSS) nmos
M3 (Y1 X1 tail_in1 VSS) nmos
I1 (tail_in1 VSS) isource
M1 (X1 Y2 tail_out1 VSS) nmos
M4 (Y1 X2 tail_out1 VSS) nmos
I2 (tail_out1 VSS) isource
L3 (VDD X2) inductor
L4 (V... |
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