| ConceptID,ConceptLabel,Dependencies,TaxonomyID |
| 1,Binary Number System,,NUMSYS |
| 2,Decimal to Binary Conversion,1,NUMSYS |
| 3,Binary to Decimal Conversion,1,NUMSYS |
| 4,Hexadecimal Numbers,1,NUMSYS |
| 5,Hex to Binary Conversion,1|4,NUMSYS |
| 6,Octal Numbers,1,NUMSYS |
| 7,Binary Addition,1,NUMSYS |
| 8,Binary Subtraction,1|7,NUMSYS |
| 9,Two's Complement,1|8,NUMSYS |
| 10,Signed Binary Numbers,1|9,NUMSYS |
| 11,Overflow Detection,7|10,NUMSYS |
| 12,BCD Encoding,1|3,NUMSYS |
| 13,Gray Code,1,NUMSYS |
| 14,Weighted Codes,1|12,NUMSYS |
| 15,Boolean Variable,,BOOL |
| 16,Boolean Constant,15,BOOL |
| 17,Boolean Expression,15|16,BOOL |
| 18,Boolean Function,17,BOOL |
| 19,Truth Table,17|18,BOOL |
| 20,AND Operation,15|16,BOOL |
| 21,OR Operation,15|16,BOOL |
| 22,NOT Operation,15|16,BOOL |
| 23,Boolean Algebra,15|20|21|22,BOOL |
| 24,Identity Law,23,BOOL |
| 25,Null Law,23,BOOL |
| 26,Idempotent Law,23,BOOL |
| 27,Complement Law,23|22,BOOL |
| 28,Commutative Law,23,BOOL |
| 29,Associative Law,23,BOOL |
| 30,Distributive Law,23,BOOL |
| 31,Absorption Law,23|30,BOOL |
| 32,De Morgan's Theorem,23|22|20|21,BOOL |
| 33,Dual Expression,23|32,BOOL |
| 34,Consensus Theorem,23|31,BOOL |
| 35,Boolean Proof Technique,23|24|25|26|27|28|29|30|31|32,BOOL |
| 36,Logic Gate,18|19,GATES |
| 37,AND Gate,36|20,GATES |
| 38,OR Gate,36|21,GATES |
| 39,NOT Gate,36|22,GATES |
| 40,Buffer Gate,36,GATES |
| 41,NAND Gate,36|37|39,GATES |
| 42,NOR Gate,36|38|39,GATES |
| 43,XOR Gate,36|20|21|22,GATES |
| 44,XNOR Gate,43|39,GATES |
| 45,Gate Symbol,36,GATES |
| 46,IEEE Gate Symbols,45,GATES |
| 47,Functional Completeness,36|41|42,GATES |
| 48,Universal Gate,47,GATES |
| 49,NAND-Only Design,41|47|48,GATES |
| 50,NOR-Only Design,42|47|48,GATES |
| 51,Gate Delay,36,GATES |
| 52,Propagation Delay,51,GATES |
| 53,Rise Time,52,GATES |
| 54,Fall Time,52,GATES |
| 55,Fan-In,36,GATES |
| 56,Fan-Out,36,GATES |
| 57,Logic Levels,36,GATES |
| 58,Noise Margin,57,GATES |
| 59,Voltage Threshold,57,GATES |
| 60,Logic Family,57,GATES |
| 61,TTL Logic,60,GATES |
| 62,CMOS Logic,60,GATES |
| 63,Digital Signal,57,GATES |
| 64,Analog vs Digital,63,GATES |
| 65,Signal Integrity,58|63,GATES |
| 66,Combinational Logic,36|18,COMB |
| 67,Sequential Logic,66|135,COMB |
| 68,Gate-Level Design,36|66,COMB |
| 69,Boolean to Gates Mapping,17|36|68,COMB |
| 70,Multi-Level Logic,68|69,COMB |
| 71,Two-Level Logic,68|69,COMB |
| 72,Sum of Products,17|71|74,COMB |
| 73,Product of Sums,17|71|75,COMB |
| 74,Minterm,17|19,COMB |
| 75,Maxterm,17|19,COMB |
| 76,Canonical Form,72|73|74|75,COMB |
| 77,Standard Form,76,COMB |
| 78,Minimal Form,77|79,COMB |
| 79,Logic Minimization,17|23,COMB |
| 80,Algebraic Simplification,79|35,COMB |
| 81,Factoring,80,COMB |
| 82,Common Term Extraction,80|81,COMB |
| 83,Karnaugh Map,19|79,COMB |
| 84,K-Map 2 Variable,83,COMB |
| 85,K-Map 3 Variable,83|84,COMB |
| 86,K-Map 4 Variable,83|85,COMB |
| 87,K-Map Grouping Rules,83|84,COMB |
| 88,Adjacent Cells,87,COMB |
| 89,Don't Care Condition,83|19,COMB |
| 90,Prime Implicant,83|87|88,COMB |
| 91,Essential Prime Implicant,90,COMB |
| 92,Implicant Cover,90|91,COMB |
| 93,Minimal SOP,72|91|92,COMB |
| 94,Minimal POS,73|91|92,COMB |
| 95,Quine-McCluskey Method,90|91|92,COMB |
| 96,Hazard,66|52,COMB |
| 97,Static Hazard,96,COMB |
| 98,Dynamic Hazard,96|97,COMB |
| 99,Hazard-Free Design,97|98|83,COMB |
| 100,Multiplexer,66|37|38,BLOCKS |
| 101,MUX 2-to-1,100,BLOCKS |
| 102,MUX 4-to-1,100|101,BLOCKS |
| 103,MUX 8-to-1,100|102,BLOCKS |
| 104,MUX Tree,102|103,BLOCKS |
| 105,MUX as Logic Function,100|18,BLOCKS |
| 106,Demultiplexer,66|100,BLOCKS |
| 107,DEMUX 1-to-4,106,BLOCKS |
| 108,Encoder,66|1,BLOCKS |
| 109,Decoder,66|1|108,BLOCKS |
| 110,2-to-4 Decoder,109,BLOCKS |
| 111,3-to-8 Decoder,109|110,BLOCKS |
| 112,Decoder Enable,109,BLOCKS |
| 113,Priority Encoder,108,BLOCKS |
| 114,7-Segment Display,,BLOCKS |
| 115,7-Segment Decoder,109|114,BLOCKS |
| 116,Binary Comparator,66|43,BLOCKS |
| 117,Magnitude Comparator,116,BLOCKS |
| 118,Equality Comparator,116|44,BLOCKS |
| 119,Half Adder,66|7|43,BLOCKS |
| 120,Full Adder,119|121,BLOCKS |
| 121,Carry Bit,119,BLOCKS |
| 122,Sum Bit,119,BLOCKS |
| 123,Ripple Carry Adder,120|121,BLOCKS |
| 124,Carry Propagation Delay,123|52,BLOCKS |
| 125,Carry Lookahead Concept,123|124,BLOCKS |
| 126,Adder Subtractor,123|9,BLOCKS |
| 127,Overflow in Addition,126|11,BLOCKS |
| 128,ALU Concept,126|117|66,BLOCKS |
| 129,Parity Bit,43,BLOCKS |
| 130,Parity Generator,129|43,BLOCKS |
| 131,Parity Checker,130,BLOCKS |
| 132,Error Detection,129|131,BLOCKS |
| 133,Tri-State Buffer,40|57,BLOCKS |
| 134,Bus Architecture,133,BLOCKS |
| 135,Memory Element,66,SEQ |
| 136,State Concept,135,SEQ |
| 137,Feedback Loop,36|135,SEQ |
| 138,Bistable Element,137,SEQ |
| 139,SR Latch,138|41|42,SEQ |
| 140,SR Latch Truth Table,139|19,SEQ |
| 141,Invalid State Problem,139|140,SEQ |
| 142,Gated SR Latch,139|148,SEQ |
| 143,D Latch,142,SEQ |
| 144,Level Sensitive,143|148,SEQ |
| 145,Transparent Latch,143|144,SEQ |
| 146,Latch Timing Problem,145,SEQ |
| 147,Race Condition,146|137,SEQ |
| 148,Clock Signal,,SEQ |
| 149,Clock Edge,148,SEQ |
| 150,Rising Edge,149,SEQ |
| 151,Falling Edge,149,SEQ |
| 152,Clock Period,148,SEQ |
| 153,Clock Frequency,152,SEQ |
| 154,Duty Cycle,152,SEQ |
| 155,D Flip-Flop,143|149|156,FLIPFLOP |
| 156,Edge Triggered,149,FLIPFLOP |
| 157,Positive Edge Triggered,156|150,FLIPFLOP |
| 158,Negative Edge Triggered,156|151,FLIPFLOP |
| 159,Master-Slave Flip-Flop,155|143,FLIPFLOP |
| 160,JK Flip-Flop,155|139,FLIPFLOP |
| 161,JK Toggle Mode,160,FLIPFLOP |
| 162,T Flip-Flop,160|161,FLIPFLOP |
| 163,Flip-Flop Symbol,155|160|162,FLIPFLOP |
| 164,Preset Input,155,FLIPFLOP |
| 165,Clear Input,155,FLIPFLOP |
| 166,Asynchronous Reset,165,FLIPFLOP |
| 167,Synchronous Reset,165|149,FLIPFLOP |
| 168,Setup Time,155|156,FLIPFLOP |
| 169,Hold Time,155|156,FLIPFLOP |
| 170,Clock-to-Q Delay,155|52,FLIPFLOP |
| 171,Timing Diagram,148|155,FLIPFLOP |
| 172,Timing Constraint,168|169,FLIPFLOP |
| 173,Timing Violation,172,FLIPFLOP |
| 174,Metastability,155|173,FLIPFLOP |
| 175,MTBF Concept,174,FLIPFLOP |
| 176,Synchronous System,155|148,FLIPFLOP |
| 177,Asynchronous Input,176,FLIPFLOP |
| 178,Synchronizer Circuit,177|174,FLIPFLOP |
| 179,Double Flop Synchronizer,178|155,FLIPFLOP |
| 180,Finite State Machine,67|136|155,FSM |
| 181,FSM State,180,FSM |
| 182,State Transition,180|181,FSM |
| 183,Current State,181,FSM |
| 184,Next State,182|183,FSM |
| 185,Next State Logic,184|66,FSM |
| 186,Output Logic,180|66,FSM |
| 187,Moore Machine,180|186,FSM |
| 188,Moore Output,187,FSM |
| 189,Mealy Machine,180|186,FSM |
| 190,Mealy Output,189,FSM |
| 191,State Diagram,180|182,FSM |
| 192,State Diagram Notation,191,FSM |
| 193,State Table,191|19,FSM |
| 194,State Encoding,180|1,FSM |
| 195,Binary Encoding,194,FSM |
| 196,One-Hot Encoding,194,FSM |
| 197,Gray Code Encoding,194|13,FSM |
| 198,State Assignment,194|195|196,FSM |
| 199,State Minimization,193|198,FSM |
| 200,Next State Equation,185|193,FSM |
| 201,Output Equation,186|193,FSM |
| 202,FSM Design Process,191|193|200|201,FSM |
| 203,FSM Verification,202|171,FSM |
| 204,Sequence Detector,180|202,FSM |
| 205,Pattern Recognition FSM,204,FSM |
| 206,Overlapping Detection,204,FSM |
| 207,Non-Overlapping Detection,204|206,FSM |
| 208,Traffic Light Controller,202,FSM |
| 209,Vending Machine FSM,202|208,FSM |
| 210,Counter,180|155,REG |
| 211,Up Counter,210,REG |
| 212,Down Counter,210|211,REG |
| 213,Up-Down Counter,211|212,REG |
| 214,Mod-N Counter,210,REG |
| 215,Binary Counter,210|1,REG |
| 216,BCD Counter,215|12,REG |
| 217,Decade Counter,216,REG |
| 218,Ring Counter,210|224,REG |
| 219,Johnson Counter,218,REG |
| 220,Counter State Diagram,210|191,REG |
| 221,Counter Overflow,210|11,REG |
| 222,Register,155|176,REG |
| 223,Parallel Load Register,222|231,REG |
| 224,Shift Register,222,REG |
| 225,Serial In Serial Out,224,REG |
| 226,Serial In Parallel Out,224|225,REG |
| 227,Parallel In Serial Out,224,REG |
| 228,Parallel In Parallel Out,224|223,REG |
| 229,Bidirectional Shift,224,REG |
| 230,Universal Shift Register,225|226|227|228|229,REG |
| 231,Enable Signal,222,REG |
| 232,Load Signal,222|223,REG |
| 233,Clear Signal,222|165,REG |
| 234,Register File,222,REG |
| 235,Datapath Concept,222|128|66,REG |
| 236,Control Unit,180|235,REG |
| 237,Register Transfer Level,235|236,REG |
| 238,RTL Notation,237,REG |
| 239,Verilog HDL,,HDL |
| 240,HDL vs Programming,239,HDL |
| 241,Module Definition,239,HDL |
| 242,Port Declaration,241,HDL |
| 243,Input Port,242,HDL |
| 244,Output Port,242,HDL |
| 245,Inout Port,242|133,HDL |
| 246,Wire Data Type,239|66,HDL |
| 247,Reg Data Type,239|67,HDL |
| 248,Parameter,241,HDL |
| 249,Assign Statement,239|246,HDL |
| 250,Continuous Assignment,249,HDL |
| 251,Always Block,239|247,HDL |
| 252,Sensitivity List,251,HDL |
| 253,Blocking Assignment,251,HDL |
| 254,Non-Blocking Assignment,251|253,HDL |
| 255,If-Else in Verilog,251,HDL |
| 256,Case Statement,251|255,HDL |
| 257,Combinational Always,251|252|66,HDL |
| 258,Sequential Always,251|252|67,HDL |
| 259,Posedge Keyword,258|150,HDL |
| 260,Negedge Keyword,258|151,HDL |
| 261,Initial Block,239,HDL |
| 262,Structural Modeling,239|241|266,HDL |
| 263,Behavioral Modeling,239|251,HDL |
| 264,Gate-Level Verilog,262|36,HDL |
| 265,RTL Verilog,263|237,HDL |
| 266,Module Instantiation,241,HDL |
| 267,Hierarchical Design,266|262,HDL |
| 268,Testbench,239|261,VERIFY |
| 269,Stimulus Generation,268,VERIFY |
| 270,Clock Generation,268|148,VERIFY |
| 271,Test Vector,268|269,VERIFY |
| 272,Self-Checking Testbench,268|271,VERIFY |
| 273,Simulation,268|239,VERIFY |
| 274,Simulation Time,273,VERIFY |
| 275,Waveform Viewer,273|171,VERIFY |
| 276,Debugging Waveforms,275,VERIFY |
| 277,Synthesis,239|265,VERIFY |
| 278,Synthesizable Code,277,VERIFY |
| 279,Non-Synthesizable Code,277|278,VERIFY |
| 280,FPGA Architecture,,VERIFY |
| 281,FPGA LUT,280|66,VERIFY |
| 282,FPGA Flip-Flop,280|155,VERIFY |
| 283,FPGA Routing,280,VERIFY |
| 284,FPGA Implementation,280|277,VERIFY |
| 285,Pin Assignment,284,VERIFY |
| 286,Breadboard Prototyping,36,VERIFY |
| 287,Logic Probe,286|57,VERIFY |
| 288,Logic Analyzer,287|171,VERIFY |
| 289,LED Indicator,286,VERIFY |
| 290,Switch Input,286,VERIFY |
| 291,Debouncing,290|155,VERIFY |
| 292,Design Verification,273|203,VERIFY |
| 293,Functional Verification,292,VERIFY |
| 294,Timing Verification,292|172,VERIFY |
| 295,Hardware-Software Boundary,239|240,VERIFY |
| 296,Abstraction Levels,68|237|265,VERIFY |
| 297,Design Hierarchy,267|296,VERIFY |
| 298,Design Reuse,241|297,VERIFY |
| 299,Design Documentation,298,VERIFY |
| 300,Digital System Design,235|236|292|297,VERIFY |
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