Datasets:

danyarm
/

ckg-benchmark

+{"id": "digital-electronics_T1_58", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Noise Margin?", "ground_truth": ["Noise Margin", "GATES"], "concept_id": 58, "hop_depth": 0}
+{"id": "digital-electronics_T1_13", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Gray Code?", "ground_truth": ["Gray Code", "NUMSYS"], "concept_id": 13, "hop_depth": 0}
+{"id": "digital-electronics_T1_141", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Invalid State Problem?", "ground_truth": ["Invalid State Problem", "SEQ"], "concept_id": 141, "hop_depth": 0}
+{"id": "digital-electronics_T1_126", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Adder Subtractor?", "ground_truth": ["Adder Subtractor", "BLOCKS"], "concept_id": 126, "hop_depth": 0}
+{"id": "digital-electronics_T1_115", "domain": "digital-electronics", "type": "T1_entity", "query": "What is 7-Segment Decoder?", "ground_truth": ["7-Segment Decoder", "BLOCKS"], "concept_id": 115, "hop_depth": 0}
+{"id": "digital-electronics_T1_72", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Sum of Products?", "ground_truth": ["Sum of Products", "COMB"], "concept_id": 72, "hop_depth": 0}
+{"id": "digital-electronics_T1_53", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Rise Time?", "ground_truth": ["Rise Time", "GATES"], "concept_id": 53, "hop_depth": 0}
+{"id": "digital-electronics_T1_280", "domain": "digital-electronics", "type": "T1_entity", "query": "What is FPGA Architecture?", "ground_truth": ["FPGA Architecture", "VERIFY"], "concept_id": 280, "hop_depth": 0}
+{"id": "digital-electronics_T1_45", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Gate Symbol?", "ground_truth": ["Gate Symbol", "GATES"], "concept_id": 45, "hop_depth": 0}
+{"id": "digital-electronics_T1_217", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Decade Counter?", "ground_truth": ["Decade Counter", "REG"], "concept_id": 217, "hop_depth": 0}
+{"id": "digital-electronics_T1_17", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Boolean Expression?", "ground_truth": ["Boolean Expression", "BOOL"], "concept_id": 17, "hop_depth": 0}
+{"id": "digital-electronics_T1_16", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Boolean Constant?", "ground_truth": ["Boolean Constant", "BOOL"], "concept_id": 16, "hop_depth": 0}
+{"id": "digital-electronics_T1_48", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Universal Gate?", "ground_truth": ["Universal Gate", "GATES"], "concept_id": 48, "hop_depth": 0}
+{"id": "digital-electronics_T1_112", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Decoder Enable?", "ground_truth": ["Decoder Enable", "BLOCKS"], "concept_id": 112, "hop_depth": 0}
+{"id": "digital-electronics_T1_120", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Full Adder?", "ground_truth": ["Full Adder", "BLOCKS"], "concept_id": 120, "hop_depth": 0}
+{"id": "digital-electronics_T1_259", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Posedge Keyword?", "ground_truth": ["Posedge Keyword", "HDL"], "concept_id": 259, "hop_depth": 0}
+{"id": "digital-electronics_T1_14", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Weighted Codes?", "ground_truth": ["Weighted Codes", "NUMSYS"], "concept_id": 14, "hop_depth": 0}
+{"id": "digital-electronics_T1_288", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Logic Analyzer?", "ground_truth": ["Logic Analyzer", "VERIFY"], "concept_id": 288, "hop_depth": 0}
+{"id": "digital-electronics_T1_102", "domain": "digital-electronics", "type": "T1_entity", "query": "What is MUX 4-to-1?", "ground_truth": ["MUX 4-to-1", "BLOCKS"], "concept_id": 102, "hop_depth": 0}
+{"id": "digital-electronics_T1_215", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Binary Counter?", "ground_truth": ["Binary Counter", "REG"], "concept_id": 215, "hop_depth": 0}
+{"id": "digital-electronics_T1_113", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Priority Encoder?", "ground_truth": ["Priority Encoder", "BLOCKS"], "concept_id": 113, "hop_depth": 0}
+{"id": "digital-electronics_T1_230", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Universal Shift Register?", "ground_truth": ["Universal Shift Register", "REG"], "concept_id": 230, "hop_depth": 0}
+{"id": "digital-electronics_T1_143", "domain": "digital-electronics", "type": "T1_entity", "query": "What is D Latch?", "ground_truth": ["D Latch", "SEQ"], "concept_id": 143, "hop_depth": 0}
+{"id": "digital-electronics_T1_4", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Hexadecimal Numbers?", "ground_truth": ["Hexadecimal Numbers", "NUMSYS"], "concept_id": 4, "hop_depth": 0}
+{"id": "digital-electronics_T1_82", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Common Term Extraction?", "ground_truth": ["Common Term Extraction", "COMB"], "concept_id": 82, "hop_depth": 0}
+{"id": "digital-electronics_T1_175", "domain": "digital-electronics", "type": "T1_entity", "query": "What is MTBF Concept?", "ground_truth": ["MTBF Concept", "FLIPFLOP"], "concept_id": 175, "hop_depth": 0}
+{"id": "digital-electronics_T1_80", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Algebraic Simplification?", "ground_truth": ["Algebraic Simplification", "COMB"], "concept_id": 80, "hop_depth": 0}
+{"id": "digital-electronics_T1_111", "domain": "digital-electronics", "type": "T1_entity", "query": "What is 3-to-8 Decoder?", "ground_truth": ["3-to-8 Decoder", "BLOCKS"], "concept_id": 111, "hop_depth": 0}
+{"id": "digital-electronics_T1_173", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Timing Violation?", "ground_truth": ["Timing Violation", "FLIPFLOP"], "concept_id": 173, "hop_depth": 0}
+{"id": "digital-electronics_T1_195", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Binary Encoding?", "ground_truth": ["Binary Encoding", "FSM"], "concept_id": 195, "hop_depth": 0}
+{"id": "digital-electronics_T1_50", "domain": "digital-electronics", "type": "T1_entity", "query": "What is NOR-Only Design?", "ground_truth": ["NOR-Only Design", "GATES"], "concept_id": 50, "hop_depth": 0}
+{"id": "digital-electronics_T1_184", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Next State?", "ground_truth": ["Next State", "FSM"], "concept_id": 184, "hop_depth": 0}
+{"id": "digital-electronics_T1_177", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Asynchronous Input?", "ground_truth": ["Asynchronous Input", "FLIPFLOP"], "concept_id": 177, "hop_depth": 0}
+{"id": "digital-electronics_T1_136", "domain": "digital-electronics", "type": "T1_entity", "query": "What is State Concept?", "ground_truth": ["State Concept", "SEQ"], "concept_id": 136, "hop_depth": 0}
+{"id": "digital-electronics_T1_23", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Boolean Algebra?", "ground_truth": ["Boolean Algebra", "BOOL"], "concept_id": 23, "hop_depth": 0}
+{"id": "digital-electronics_T1_236", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Control Unit?", "ground_truth": ["Control Unit", "REG"], "concept_id": 236, "hop_depth": 0}
+{"id": "digital-electronics_T1_275", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Waveform Viewer?", "ground_truth": ["Waveform Viewer", "VERIFY"], "concept_id": 275, "hop_depth": 0}
+{"id": "digital-electronics_T1_64", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Analog vs Digital?", "ground_truth": ["Analog vs Digital", "GATES"], "concept_id": 64, "hop_depth": 0}
+{"id": "digital-electronics_T1_194", "domain": "digital-electronics", "type": "T1_entity", "query": "What is State Encoding?", "ground_truth": ["State Encoding", "FSM"], "concept_id": 194, "hop_depth": 0}
+{"id": "digital-electronics_T1_41", "domain": "digital-electronics", "type": "T1_entity", "query": "What is NAND Gate?", "ground_truth": ["NAND Gate", "GATES"], "concept_id": 41, "hop_depth": 0}
+{"id": "digital-electronics_T1_283", "domain": "digital-electronics", "type": "T1_entity", "query": "What is FPGA Routing?", "ground_truth": ["FPGA Routing", "VERIFY"], "concept_id": 283, "hop_depth": 0}
+{"id": "digital-electronics_T1_151", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Falling Edge?", "ground_truth": ["Falling Edge", "SEQ"], "concept_id": 151, "hop_depth": 0}
+{"id": "digital-electronics_T1_186", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Output Logic?", "ground_truth": ["Output Logic", "FSM"], "concept_id": 186, "hop_depth": 0}
+{"id": "digital-electronics_T1_296", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Abstraction Levels?", "ground_truth": ["Abstraction Levels", "VERIFY"], "concept_id": 296, "hop_depth": 0}
+{"id": "digital-electronics_T1_99", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Hazard-Free Design?", "ground_truth": ["Hazard-Free Design", "COMB"], "concept_id": 99, "hop_depth": 0}
+{"id": "digital-electronics_T1_36", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Logic Gate?", "ground_truth": ["Logic Gate", "GATES"], "concept_id": 36, "hop_depth": 0}
+{"id": "digital-electronics_T1_24", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Identity Law?", "ground_truth": ["Identity Law", "BOOL"], "concept_id": 24, "hop_depth": 0}
+{"id": "digital-electronics_T1_117", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Magnitude Comparator?", "ground_truth": ["Magnitude Comparator", "BLOCKS"], "concept_id": 117, "hop_depth": 0}
+{"id": "digital-electronics_T1_149", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Clock Edge?", "ground_truth": ["Clock Edge", "SEQ"], "concept_id": 149, "hop_depth": 0}
+{"id": "digital-electronics_T1_52", "domain": "digital-electronics", "type": "T1_entity", "query": "What is Propagation Delay?", "ground_truth": ["Propagation Delay", "GATES"], "concept_id": 52, "hop_depth": 0}
+{"id": "digital-electronics_T2_199", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for State Minimization?", "ground_truth": ["State Table", "State Assignment"], "concept_id": 199, "hop_depth": 1}
+{"id": "digital-electronics_T2_146", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Latch Timing Problem?", "ground_truth": ["Transparent Latch"], "concept_id": 146, "hop_depth": 1}
+{"id": "digital-electronics_T2_237", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Register Transfer Level?", "ground_truth": ["Datapath Concept", "Control Unit"], "concept_id": 237, "hop_depth": 1}
+{"id": "digital-electronics_T2_191", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for State Diagram?", "ground_truth": ["Finite State Machine", "State Transition"], "concept_id": 191, "hop_depth": 1}
+{"id": "digital-electronics_T2_86", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for K-Map 4 Variable?", "ground_truth": ["Karnaugh Map", "K-Map 3 Variable"], "concept_id": 86, "hop_depth": 1}
+{"id": "digital-electronics_T2_194", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for State Encoding?", "ground_truth": ["Finite State Machine", "Binary Number System"], "concept_id": 194, "hop_depth": 1}
+{"id": "digital-electronics_T2_186", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Output Logic?", "ground_truth": ["Finite State Machine", "Combinational Logic"], "concept_id": 186, "hop_depth": 1}
+{"id": "digital-electronics_T2_110", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for 2-to-4 Decoder?", "ground_truth": ["Decoder"], "concept_id": 110, "hop_depth": 1}
+{"id": "digital-electronics_T2_140", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for SR Latch Truth Table?", "ground_truth": ["SR Latch", "Truth Table"], "concept_id": 140, "hop_depth": 1}
+{"id": "digital-electronics_T2_39", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for NOT Gate?", "ground_truth": ["Logic Gate", "NOT Operation"], "concept_id": 39, "hop_depth": 1}
+{"id": "digital-electronics_T2_90", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Prime Implicant?", "ground_truth": ["Karnaugh Map", "K-Map Grouping Rules", "Adjacent Cells"], "concept_id": 90, "hop_depth": 1}
+{"id": "digital-electronics_T2_279", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Non-Synthesizable Code?", "ground_truth": ["Synthesis", "Synthesizable Code"], "concept_id": 279, "hop_depth": 1}
+{"id": "digital-electronics_T2_129", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Parity Bit?", "ground_truth": ["XOR Gate"], "concept_id": 129, "hop_depth": 1}
+{"id": "digital-electronics_T2_242", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Port Declaration?", "ground_truth": ["Module Definition"], "concept_id": 242, "hop_depth": 1}
+{"id": "digital-electronics_T2_142", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Gated SR Latch?", "ground_truth": ["SR Latch", "Clock Signal"], "concept_id": 142, "hop_depth": 1}
+{"id": "digital-electronics_T2_292", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Design Verification?", "ground_truth": ["Simulation", "FSM Verification"], "concept_id": 292, "hop_depth": 1}
+{"id": "digital-electronics_T2_116", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Binary Comparator?", "ground_truth": ["Combinational Logic", "XOR Gate"], "concept_id": 116, "hop_depth": 1}
+{"id": "digital-electronics_T2_171", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Timing Diagram?", "ground_truth": ["Clock Signal", "D Flip-Flop"], "concept_id": 171, "hop_depth": 1}
+{"id": "digital-electronics_T2_31", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Absorption Law?", "ground_truth": ["Boolean Algebra", "Distributive Law"], "concept_id": 31, "hop_depth": 1}
+{"id": "digital-electronics_T2_121", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Carry Bit?", "ground_truth": ["Half Adder"], "concept_id": 121, "hop_depth": 1}
+{"id": "digital-electronics_T2_19", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Truth Table?", "ground_truth": ["Boolean Expression", "Boolean Function"], "concept_id": 19, "hop_depth": 1}
+{"id": "digital-electronics_T2_166", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Asynchronous Reset?", "ground_truth": ["Clear Input"], "concept_id": 166, "hop_depth": 1}
+{"id": "digital-electronics_T2_210", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Counter?", "ground_truth": ["Finite State Machine", "D Flip-Flop"], "concept_id": 210, "hop_depth": 1}
+{"id": "digital-electronics_T2_141", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Invalid State Problem?", "ground_truth": ["SR Latch", "SR Latch Truth Table"], "concept_id": 141, "hop_depth": 1}
+{"id": "digital-electronics_T2_36", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Logic Gate?", "ground_truth": ["Boolean Function", "Truth Table"], "concept_id": 36, "hop_depth": 1}
+{"id": "digital-electronics_T2_111", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for 3-to-8 Decoder?", "ground_truth": ["Decoder", "2-to-4 Decoder"], "concept_id": 111, "hop_depth": 1}
+{"id": "digital-electronics_T2_297", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Design Hierarchy?", "ground_truth": ["Hierarchical Design", "Abstraction Levels"], "concept_id": 297, "hop_depth": 1}
+{"id": "digital-electronics_T2_261", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Initial Block?", "ground_truth": ["Verilog HDL"], "concept_id": 261, "hop_depth": 1}
+{"id": "digital-electronics_T2_207", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Non-Overlapping Detection?", "ground_truth": ["Sequence Detector", "Overlapping Detection"], "concept_id": 207, "hop_depth": 1}
+{"id": "digital-electronics_T2_240", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for HDL vs Programming?", "ground_truth": ["Verilog HDL"], "concept_id": 240, "hop_depth": 1}
+{"id": "digital-electronics_T2_76", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Canonical Form?", "ground_truth": ["Sum of Products", "Product of Sums", "Minterm", "Maxterm"], "concept_id": 76, "hop_depth": 1}
+{"id": "digital-electronics_T2_139", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for SR Latch?", "ground_truth": ["Bistable Element", "NAND Gate", "NOR Gate"], "concept_id": 139, "hop_depth": 1}
+{"id": "digital-electronics_T2_74", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Minterm?", "ground_truth": ["Boolean Expression", "Truth Table"], "concept_id": 74, "hop_depth": 1}
+{"id": "digital-electronics_T2_130", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Parity Generator?", "ground_truth": ["Parity Bit", "XOR Gate"], "concept_id": 130, "hop_depth": 1}
+{"id": "digital-electronics_T2_294", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Timing Verification?", "ground_truth": ["Design Verification", "Timing Constraint"], "concept_id": 294, "hop_depth": 1}
+{"id": "digital-electronics_T2_282", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for FPGA Flip-Flop?", "ground_truth": ["FPGA Architecture", "D Flip-Flop"], "concept_id": 282, "hop_depth": 1}
+{"id": "digital-electronics_T2_138", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Bistable Element?", "ground_truth": ["Feedback Loop"], "concept_id": 138, "hop_depth": 1}
+{"id": "digital-electronics_T2_224", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Shift Register?", "ground_truth": ["Register"], "concept_id": 224, "hop_depth": 1}
+{"id": "digital-electronics_T2_209", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Vending Machine FSM?", "ground_truth": ["FSM Design Process", "Traffic Light Controller"], "concept_id": 209, "hop_depth": 1}
+{"id": "digital-electronics_T2_190", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Mealy Output?", "ground_truth": ["Mealy Machine"], "concept_id": 190, "hop_depth": 1}
+{"id": "digital-electronics_T2_73", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Product of Sums?", "ground_truth": ["Boolean Expression", "Two-Level Logic", "Maxterm"], "concept_id": 73, "hop_depth": 1}
+{"id": "digital-electronics_T2_266", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Module Instantiation?", "ground_truth": ["Module Definition"], "concept_id": 266, "hop_depth": 1}
+{"id": "digital-electronics_T2_258", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Sequential Always?", "ground_truth": ["Always Block", "Sensitivity List", "Sequential Logic"], "concept_id": 258, "hop_depth": 1}
+{"id": "digital-electronics_T2_49", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for NAND-Only Design?", "ground_truth": ["NAND Gate", "Functional Completeness", "Universal Gate"], "concept_id": 49, "hop_depth": 1}
+{"id": "digital-electronics_T2_27", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Complement Law?", "ground_truth": ["Boolean Algebra", "NOT Operation"], "concept_id": 27, "hop_depth": 1}
+{"id": "digital-electronics_T2_59", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Voltage Threshold?", "ground_truth": ["Logic Levels"], "concept_id": 59, "hop_depth": 1}
+{"id": "digital-electronics_T2_81", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Factoring?", "ground_truth": ["Algebraic Simplification"], "concept_id": 81, "hop_depth": 1}
+{"id": "digital-electronics_T2_84", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for K-Map 2 Variable?", "ground_truth": ["Karnaugh Map"], "concept_id": 84, "hop_depth": 1}
+{"id": "digital-electronics_T2_221", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Counter Overflow?", "ground_truth": ["Counter", "Overflow Detection"], "concept_id": 221, "hop_depth": 1}
+{"id": "digital-electronics_T2_35", "domain": "digital-electronics", "type": "T2_dependency", "query": "What are the prerequisites for Boolean Proof Technique?", "ground_truth": ["Boolean Algebra", "Identity Law", "Null Law", "Idempotent Law", "Complement Law", "Commutative Law", "Associative Law", "Distributive Law", "Absorption Law", "De Morgan's Theorem"], "concept_id": 35, "hop_depth": 1}
+{"id": "digital-electronics_T3_148_164", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Clock Signal to Preset Input?", "ground_truth": ["Preset Input", "D Flip-Flop", "Clock Edge", "Clock Signal"], "concept_id": 164, "hop_depth": 3, "path_ids": [164, 155, 149, 148]}
+{"id": "digital-electronics_T3_280_285", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from FPGA Architecture to Pin Assignment?", "ground_truth": ["Pin Assignment", "FPGA Implementation", "FPGA Architecture"], "concept_id": 285, "hop_depth": 2, "path_ids": [285, 284, 280]}
+{"id": "digital-electronics_T3_239_293", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Verilog HDL to Functional Verification?", "ground_truth": ["Functional Verification", "Design Verification", "Simulation", "Verilog HDL"], "concept_id": 293, "hop_depth": 3, "path_ids": [293, 292, 273, 239]}
+{"id": "digital-electronics_T3_1_127", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Binary Number System to Overflow in Addition?", "ground_truth": ["Overflow in Addition", "Adder Subtractor", "Two's Complement", "Binary Number System"], "concept_id": 127, "hop_depth": 3, "path_ids": [127, 126, 9, 1]}
+{"id": "digital-electronics_T3_280_285", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from FPGA Architecture to Pin Assignment?", "ground_truth": ["Pin Assignment", "FPGA Implementation", "FPGA Architecture"], "concept_id": 285, "hop_depth": 2, "path_ids": [285, 284, 280]}
+{"id": "digital-electronics_T3_239_250", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Verilog HDL to Continuous Assignment?", "ground_truth": ["Continuous Assignment", "Assign Statement", "Verilog HDL"], "concept_id": 250, "hop_depth": 2, "path_ids": [250, 249, 239]}
+{"id": "digital-electronics_T3_15_78", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Boolean Variable to Minimal Form?", "ground_truth": ["Minimal Form", "Logic Minimization", "Boolean Expression", "Boolean Variable"], "concept_id": 78, "hop_depth": 3, "path_ids": [78, 79, 17, 15]}
+{"id": "digital-electronics_T3_1_111", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Binary Number System to 3-to-8 Decoder?", "ground_truth": ["3-to-8 Decoder", "Decoder", "Binary Number System"], "concept_id": 111, "hop_depth": 2, "path_ids": [111, 109, 1]}
+{"id": "digital-electronics_T3_239_295", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Verilog HDL to Hardware-Software Boundary?", "ground_truth": ["Hardware-Software Boundary", "Verilog HDL"], "concept_id": 295, "hop_depth": 1, "path_ids": [295, 239]}
+{"id": "digital-electronics_T3_1_112", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Binary Number System to Decoder Enable?", "ground_truth": ["Decoder Enable", "Decoder", "Binary Number System"], "concept_id": 112, "hop_depth": 2, "path_ids": [112, 109, 1]}
+{"id": "digital-electronics_T3_15_50", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Boolean Variable to NOR-Only Design?", "ground_truth": ["NOR-Only Design", "NOR Gate", "OR Gate", "OR Operation", "Boolean Variable"], "concept_id": 50, "hop_depth": 4, "path_ids": [50, 42, 38, 21, 15]}
+{"id": "digital-electronics_T3_15_50", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Boolean Variable to NOR-Only Design?", "ground_truth": ["NOR-Only Design", "NOR Gate", "OR Gate", "OR Operation", "Boolean Variable"], "concept_id": 50, "hop_depth": 4, "path_ids": [50, 42, 38, 21, 15]}
+{"id": "digital-electronics_T3_15_122", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Boolean Variable to Sum Bit?", "ground_truth": ["Sum Bit", "Half Adder", "XOR Gate", "AND Operation", "Boolean Variable"], "concept_id": 122, "hop_depth": 4, "path_ids": [122, 119, 43, 20, 15]}
+{"id": "digital-electronics_T3_239_243", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Verilog HDL to Input Port?", "ground_truth": ["Input Port", "Port Declaration", "Module Definition", "Verilog HDL"], "concept_id": 243, "hop_depth": 3, "path_ids": [243, 242, 241, 239]}
+{"id": "digital-electronics_T3_148_175", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Clock Signal to MTBF Concept?", "ground_truth": ["MTBF Concept", "Metastability", "D Flip-Flop", "Clock Edge", "Clock Signal"], "concept_id": 175, "hop_depth": 4, "path_ids": [175, 174, 155, 149, 148]}
+{"id": "digital-electronics_T3_15_56", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Boolean Variable to Fan-Out?", "ground_truth": ["Fan-Out", "Logic Gate", "Boolean Function", "Boolean Expression", "Boolean Variable"], "concept_id": 56, "hop_depth": 4, "path_ids": [56, 36, 18, 17, 15]}
+{"id": "digital-electronics_T3_148_158", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Clock Signal to Negative Edge Triggered?", "ground_truth": ["Negative Edge Triggered", "Edge Triggered", "Clock Edge", "Clock Signal"], "concept_id": 158, "hop_depth": 3, "path_ids": [158, 156, 149, 148]}
+{"id": "digital-electronics_T3_148_175", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Clock Signal to MTBF Concept?", "ground_truth": ["MTBF Concept", "Metastability", "D Flip-Flop", "Clock Edge", "Clock Signal"], "concept_id": 175, "hop_depth": 4, "path_ids": [175, 174, 155, 149, 148]}
+{"id": "digital-electronics_T3_148_288", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Clock Signal to Logic Analyzer?", "ground_truth": ["Logic Analyzer", "Timing Diagram", "Clock Signal"], "concept_id": 288, "hop_depth": 2, "path_ids": [288, 171, 148]}
+{"id": "digital-electronics_T3_148_288", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Clock Signal to Logic Analyzer?", "ground_truth": ["Logic Analyzer", "Timing Diagram", "Clock Signal"], "concept_id": 288, "hop_depth": 2, "path_ids": [288, 171, 148]}
+{"id": "digital-electronics_T3_15_94", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Boolean Variable to Minimal POS?", "ground_truth": ["Minimal POS", "Product of Sums", "Boolean Expression", "Boolean Variable"], "concept_id": 94, "hop_depth": 3, "path_ids": [94, 73, 17, 15]}
+{"id": "digital-electronics_T3_148_233", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Clock Signal to Clear Signal?", "ground_truth": ["Clear Signal", "Register", "Synchronous System", "Clock Signal"], "concept_id": 233, "hop_depth": 3, "path_ids": [233, 222, 176, 148]}
+{"id": "digital-electronics_T3_15_86", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Boolean Variable to K-Map 4 Variable?", "ground_truth": ["K-Map 4 Variable", "Karnaugh Map", "Truth Table", "Boolean Expression", "Boolean Variable"], "concept_id": 86, "hop_depth": 4, "path_ids": [86, 83, 19, 17, 15]}
+{"id": "digital-electronics_T3_148_213", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Clock Signal to Up-Down Counter?", "ground_truth": ["Up-Down Counter", "Up Counter", "Counter", "D Flip-Flop", "Clock Edge", "Clock Signal"], "concept_id": 213, "hop_depth": 5, "path_ids": [213, 211, 210, 155, 149, 148]}
+{"id": "digital-electronics_T3_239_270", "domain": "digital-electronics", "type": "T3_path", "query": "What is the prerequisite chain from Verilog HDL to Clock Generation?", "ground_truth": ["Clock Generation", "Testbench", "Verilog HDL"], "concept_id": 270, "hop_depth": 2, "path_ids": [270, 268, 239]}
+{"id": "digital-electronics_T4_NUMSYS", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all NUMSYS concepts in this knowledge graph", "ground_truth": ["Binary Number System", "Decimal to Binary Conversion", "Binary to Decimal Conversion", "Hexadecimal Numbers", "Hex to Binary Conversion", "Octal Numbers", "Binary Addition", "Binary Subtraction", "Two's Complement", "Signed Binary Numbers", "Overflow Detection", "BCD Encoding", "Gray Code", "Weighted Codes"], "taxonomy_id": "NUMSYS", "hop_depth": 0}
+{"id": "digital-electronics_T4_BOOL", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all BOOL concepts in this knowledge graph", "ground_truth": ["Boolean Variable", "Boolean Constant", "Boolean Expression", "Boolean Function", "Truth Table", "AND Operation", "OR Operation", "NOT Operation", "Boolean Algebra", "Identity Law", "Null Law", "Idempotent Law", "Complement Law", "Commutative Law", "Associative Law", "Distributive Law", "Absorption Law", "De Morgan's Theorem", "Dual Expression", "Consensus Theorem", "Boolean Proof Technique"], "taxonomy_id": "BOOL", "hop_depth": 0}
+{"id": "digital-electronics_T4_GATES", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all GATES concepts in this knowledge graph", "ground_truth": ["Logic Gate", "AND Gate", "OR Gate", "NOT Gate", "Buffer Gate", "NAND Gate", "NOR Gate", "XOR Gate", "XNOR Gate", "Gate Symbol", "IEEE Gate Symbols", "Functional Completeness", "Universal Gate", "NAND-Only Design", "NOR-Only Design", "Gate Delay", "Propagation Delay", "Rise Time", "Fall Time", "Fan-In", "Fan-Out", "Logic Levels", "Noise Margin", "Voltage Threshold", "Logic Family", "TTL Logic", "CMOS Logic", "Digital Signal", "Analog vs Digital", "Signal Integrity"], "taxonomy_id": "GATES", "hop_depth": 0}
+{"id": "digital-electronics_T4_COMB", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all COMB concepts in this knowledge graph", "ground_truth": ["Combinational Logic", "Sequential Logic", "Gate-Level Design", "Boolean to Gates Mapping", "Multi-Level Logic", "Two-Level Logic", "Sum of Products", "Product of Sums", "Minterm", "Maxterm", "Canonical Form", "Standard Form", "Minimal Form", "Logic Minimization", "Algebraic Simplification", "Factoring", "Common Term Extraction", "Karnaugh Map", "K-Map 2 Variable", "K-Map 3 Variable", "K-Map 4 Variable", "K-Map Grouping Rules", "Adjacent Cells", "Don't Care Condition", "Prime Implicant", "Essential Prime Implicant", "Implicant Cover", "Minimal SOP", "Minimal POS", "Quine-McCluskey Method", "Hazard", "Static Hazard", "Dynamic Hazard", "Hazard-Free Design"], "taxonomy_id": "COMB", "hop_depth": 0}
+{"id": "digital-electronics_T4_BLOCKS", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all BLOCKS concepts in this knowledge graph", "ground_truth": ["Multiplexer", "MUX 2-to-1", "MUX 4-to-1", "MUX 8-to-1", "MUX Tree", "MUX as Logic Function", "Demultiplexer", "DEMUX 1-to-4", "Encoder", "Decoder", "2-to-4 Decoder", "3-to-8 Decoder", "Decoder Enable", "Priority Encoder", "7-Segment Display", "7-Segment Decoder", "Binary Comparator", "Magnitude Comparator", "Equality Comparator", "Half Adder", "Full Adder", "Carry Bit", "Sum Bit", "Ripple Carry Adder", "Carry Propagation Delay", "Carry Lookahead Concept", "Adder Subtractor", "Overflow in Addition", "ALU Concept", "Parity Bit", "Parity Generator", "Parity Checker", "Error Detection", "Tri-State Buffer", "Bus Architecture"], "taxonomy_id": "BLOCKS", "hop_depth": 0}
+{"id": "digital-electronics_T4_SEQ", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all SEQ concepts in this knowledge graph", "ground_truth": ["Memory Element", "State Concept", "Feedback Loop", "Bistable Element", "SR Latch", "SR Latch Truth Table", "Invalid State Problem", "Gated SR Latch", "D Latch", "Level Sensitive", "Transparent Latch", "Latch Timing Problem", "Race Condition", "Clock Signal", "Clock Edge", "Rising Edge", "Falling Edge", "Clock Period", "Clock Frequency", "Duty Cycle"], "taxonomy_id": "SEQ", "hop_depth": 0}
+{"id": "digital-electronics_T4_FLIPFLOP", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all FLIPFLOP concepts in this knowledge graph", "ground_truth": ["D Flip-Flop", "Edge Triggered", "Positive Edge Triggered", "Negative Edge Triggered", "Master-Slave Flip-Flop", "JK Flip-Flop", "JK Toggle Mode", "T Flip-Flop", "Flip-Flop Symbol", "Preset Input", "Clear Input", "Asynchronous Reset", "Synchronous Reset", "Setup Time", "Hold Time", "Clock-to-Q Delay", "Timing Diagram", "Timing Constraint", "Timing Violation", "Metastability", "MTBF Concept", "Synchronous System", "Asynchronous Input", "Synchronizer Circuit", "Double Flop Synchronizer"], "taxonomy_id": "FLIPFLOP", "hop_depth": 0}
+{"id": "digital-electronics_T4_FSM", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all FSM concepts in this knowledge graph", "ground_truth": ["Finite State Machine", "FSM State", "State Transition", "Current State", "Next State", "Next State Logic", "Output Logic", "Moore Machine", "Moore Output", "Mealy Machine", "Mealy Output", "State Diagram", "State Diagram Notation", "State Table", "State Encoding", "Binary Encoding", "One-Hot Encoding", "Gray Code Encoding", "State Assignment", "State Minimization", "Next State Equation", "Output Equation", "FSM Design Process", "FSM Verification", "Sequence Detector", "Pattern Recognition FSM", "Overlapping Detection", "Non-Overlapping Detection", "Traffic Light Controller", "Vending Machine FSM"], "taxonomy_id": "FSM", "hop_depth": 0}
+{"id": "digital-electronics_T4_REG", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all REG concepts in this knowledge graph", "ground_truth": ["Counter", "Up Counter", "Down Counter", "Up-Down Counter", "Mod-N Counter", "Binary Counter", "BCD Counter", "Decade Counter", "Ring Counter", "Johnson Counter", "Counter State Diagram", "Counter Overflow", "Register", "Parallel Load Register", "Shift Register", "Serial In Serial Out", "Serial In Parallel Out", "Parallel In Serial Out", "Parallel In Parallel Out", "Bidirectional Shift", "Universal Shift Register", "Enable Signal", "Load Signal", "Clear Signal", "Register File", "Datapath Concept", "Control Unit", "Register Transfer Level", "RTL Notation"], "taxonomy_id": "REG", "hop_depth": 0}
+{"id": "digital-electronics_T4_HDL", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all HDL concepts in this knowledge graph", "ground_truth": ["Verilog HDL", "HDL vs Programming", "Module Definition", "Port Declaration", "Input Port", "Output Port", "Inout Port", "Wire Data Type", "Reg Data Type", "Parameter", "Assign Statement", "Continuous Assignment", "Always Block", "Sensitivity List", "Blocking Assignment", "Non-Blocking Assignment", "If-Else in Verilog", "Case Statement", "Combinational Always", "Sequential Always", "Posedge Keyword", "Negedge Keyword", "Initial Block", "Structural Modeling", "Behavioral Modeling", "Gate-Level Verilog", "RTL Verilog", "Module Instantiation", "Hierarchical Design"], "taxonomy_id": "HDL", "hop_depth": 0}
+{"id": "digital-electronics_T4_VERIFY", "domain": "digital-electronics", "type": "T4_aggregate", "query": "List all VERIFY concepts in this knowledge graph", "ground_truth": ["Testbench", "Stimulus Generation", "Clock Generation", "Test Vector", "Self-Checking Testbench", "Simulation", "Simulation Time", "Waveform Viewer", "Debugging Waveforms", "Synthesis", "Synthesizable Code", "Non-Synthesizable Code", "FPGA Architecture", "FPGA LUT", "FPGA Flip-Flop", "FPGA Routing", "FPGA Implementation", "Pin Assignment", "Breadboard Prototyping", "Logic Probe", "Logic Analyzer", "LED Indicator", "Switch Input", "Debouncing", "Design Verification", "Functional Verification", "Timing Verification", "Hardware-Software Boundary", "Abstraction Levels", "Design Hierarchy", "Design Reuse", "Design Documentation", "Digital System Design"], "taxonomy_id": "VERIFY", "hop_depth": 0}
+{"id": "digital-electronics_T5_286_36", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Breadboard Prototyping relate to Logic Gate?", "ground_truth": ["Breadboard Prototyping", "Logic Gate"], "concept_id_a": 286, "concept_id_b": 36, "hop_depth": 1}
+{"id": "digital-electronics_T5_87_84", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does K-Map Grouping Rules relate to K-Map 2 Variable?", "ground_truth": ["K-Map Grouping Rules", "K-Map 2 Variable", "Karnaugh Map"], "concept_id_a": 87, "concept_id_b": 84, "hop_depth": 1}
+{"id": "digital-electronics_T5_104_103", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does MUX Tree relate to MUX 8-to-1?", "ground_truth": ["MUX Tree", "MUX 8-to-1", "MUX 4-to-1"], "concept_id_a": 104, "concept_id_b": 103, "hop_depth": 1}
+{"id": "digital-electronics_T5_171_148", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Timing Diagram relate to Clock Signal?", "ground_truth": ["Timing Diagram", "Clock Signal"], "concept_id_a": 171, "concept_id_b": 148, "hop_depth": 1}
+{"id": "digital-electronics_T5_121_119", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Carry Bit relate to Half Adder?", "ground_truth": ["Carry Bit", "Half Adder"], "concept_id_a": 121, "concept_id_b": 119, "hop_depth": 1}
+{"id": "digital-electronics_T5_35_28", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Boolean Proof Technique relate to Commutative Law?", "ground_truth": ["Boolean Proof Technique", "Commutative Law", "Boolean Algebra"], "concept_id_a": 35, "concept_id_b": 28, "hop_depth": 1}
+{"id": "digital-electronics_T5_35_31", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Boolean Proof Technique relate to Absorption Law?", "ground_truth": ["Boolean Proof Technique", "Absorption Law", "Distributive Law", "Boolean Algebra"], "concept_id_a": 35, "concept_id_b": 31, "hop_depth": 1}
+{"id": "digital-electronics_T5_181_180", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does FSM State relate to Finite State Machine?", "ground_truth": ["FSM State", "Finite State Machine"], "concept_id_a": 181, "concept_id_b": 180, "hop_depth": 1}
+{"id": "digital-electronics_T5_35_27", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Boolean Proof Technique relate to Complement Law?", "ground_truth": ["Boolean Proof Technique", "Complement Law", "Boolean Algebra"], "concept_id_a": 35, "concept_id_b": 27, "hop_depth": 1}
+{"id": "digital-electronics_T5_33_32", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Dual Expression relate to De Morgan's Theorem?", "ground_truth": ["Dual Expression", "De Morgan's Theorem", "Boolean Algebra"], "concept_id_a": 33, "concept_id_b": 32, "hop_depth": 1}
+{"id": "digital-electronics_T5_279_277", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Non-Synthesizable Code relate to Synthesis?", "ground_truth": ["Non-Synthesizable Code", "Synthesis"], "concept_id_a": 279, "concept_id_b": 277, "hop_depth": 1}
+{"id": "digital-electronics_T5_296_68", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Abstraction Levels relate to Gate-Level Design?", "ground_truth": ["Abstraction Levels", "Gate-Level Design"], "concept_id_a": 296, "concept_id_b": 68, "hop_depth": 1}
+{"id": "digital-electronics_T5_89_19", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Don't Care Condition relate to Truth Table?", "ground_truth": ["Don't Care Condition", "Truth Table"], "concept_id_a": 89, "concept_id_b": 19, "hop_depth": 1}
+{"id": "digital-electronics_T5_298_297", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Design Reuse relate to Design Hierarchy?", "ground_truth": ["Design Reuse", "Design Hierarchy"], "concept_id_a": 298, "concept_id_b": 297, "hop_depth": 1}
+{"id": "digital-electronics_T5_43_22", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does XOR Gate relate to NOT Operation?", "ground_truth": ["XOR Gate", "NOT Operation"], "concept_id_a": 43, "concept_id_b": 22, "hop_depth": 1}
+{"id": "digital-electronics_T5_102_101", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does MUX 4-to-1 relate to MUX 2-to-1?", "ground_truth": ["MUX 4-to-1", "MUX 2-to-1", "Multiplexer"], "concept_id_a": 102, "concept_id_b": 101, "hop_depth": 1}
+{"id": "digital-electronics_T5_39_36", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does NOT Gate relate to Logic Gate?", "ground_truth": ["NOT Gate", "Logic Gate"], "concept_id_a": 39, "concept_id_b": 36, "hop_depth": 1}
+{"id": "digital-electronics_T5_38_21", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does OR Gate relate to OR Operation?", "ground_truth": ["OR Gate", "OR Operation"], "concept_id_a": 38, "concept_id_b": 21, "hop_depth": 1}
+{"id": "digital-electronics_T5_131_130", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Parity Checker relate to Parity Generator?", "ground_truth": ["Parity Checker", "Parity Generator"], "concept_id_a": 131, "concept_id_b": 130, "hop_depth": 1}
+{"id": "digital-electronics_T5_233_165", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Clear Signal relate to Clear Input?", "ground_truth": ["Clear Signal", "Clear Input"], "concept_id_a": 233, "concept_id_b": 165, "hop_depth": 1}
+{"id": "digital-electronics_T5_70_68", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Multi-Level Logic relate to Gate-Level Design?", "ground_truth": ["Multi-Level Logic", "Gate-Level Design"], "concept_id_a": 70, "concept_id_b": 68, "hop_depth": 1}
+{"id": "digital-electronics_T5_139_41", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does SR Latch relate to NAND Gate?", "ground_truth": ["SR Latch", "NAND Gate"], "concept_id_a": 139, "concept_id_b": 41, "hop_depth": 1}
+{"id": "digital-electronics_T5_27_22", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Complement Law relate to NOT Operation?", "ground_truth": ["Complement Law", "NOT Operation"], "concept_id_a": 27, "concept_id_b": 22, "hop_depth": 1}
+{"id": "digital-electronics_T5_44_43", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does XNOR Gate relate to XOR Gate?", "ground_truth": ["XNOR Gate", "XOR Gate"], "concept_id_a": 44, "concept_id_b": 43, "hop_depth": 1}
+{"id": "digital-electronics_T5_245_133", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Inout Port relate to Tri-State Buffer?", "ground_truth": ["Inout Port", "Tri-State Buffer"], "concept_id_a": 245, "concept_id_b": 133, "hop_depth": 1}
+{"id": "digital-electronics_T5_182_181", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does State Transition relate to FSM State?", "ground_truth": ["State Transition", "FSM State", "Finite State Machine"], "concept_id_a": 182, "concept_id_b": 181, "hop_depth": 1}
+{"id": "digital-electronics_T5_147_137", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Race Condition relate to Feedback Loop?", "ground_truth": ["Race Condition", "Feedback Loop"], "concept_id_a": 147, "concept_id_b": 137, "hop_depth": 1}
+{"id": "digital-electronics_T5_113_108", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Priority Encoder relate to Encoder?", "ground_truth": ["Priority Encoder", "Encoder"], "concept_id_a": 113, "concept_id_b": 108, "hop_depth": 1}
+{"id": "digital-electronics_T5_133_57", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Tri-State Buffer relate to Logic Levels?", "ground_truth": ["Tri-State Buffer", "Logic Levels"], "concept_id_a": 133, "concept_id_b": 57, "hop_depth": 1}
+{"id": "digital-electronics_T5_152_148", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Clock Period relate to Clock Signal?", "ground_truth": ["Clock Period", "Clock Signal"], "concept_id_a": 152, "concept_id_b": 148, "hop_depth": 1}
+{"id": "digital-electronics_T5_230_226", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Universal Shift Register relate to Serial In Parallel Out?", "ground_truth": ["Universal Shift Register", "Serial In Parallel Out", "Serial In Serial Out"], "concept_id_a": 230, "concept_id_b": 226, "hop_depth": 1}
+{"id": "digital-electronics_T5_75_17", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Maxterm relate to Boolean Expression?", "ground_truth": ["Maxterm", "Boolean Expression"], "concept_id_a": 75, "concept_id_b": 17, "hop_depth": 1}
+{"id": "digital-electronics_T5_173_172", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Timing Violation relate to Timing Constraint?", "ground_truth": ["Timing Violation", "Timing Constraint"], "concept_id_a": 173, "concept_id_b": 172, "hop_depth": 1}
+{"id": "digital-electronics_T5_267_266", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Hierarchical Design relate to Module Instantiation?", "ground_truth": ["Hierarchical Design", "Module Instantiation"], "concept_id_a": 267, "concept_id_b": 266, "hop_depth": 1}
+{"id": "digital-electronics_T5_41_37", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does NAND Gate relate to AND Gate?", "ground_truth": ["NAND Gate", "AND Gate", "Logic Gate"], "concept_id_a": 41, "concept_id_b": 37, "hop_depth": 1}
+{"id": "digital-electronics_T5_9_1", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Two's Complement relate to Binary Number System?", "ground_truth": ["Two's Complement", "Binary Number System"], "concept_id_a": 9, "concept_id_b": 1, "hop_depth": 1}
+{"id": "digital-electronics_T5_267_262", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Hierarchical Design relate to Structural Modeling?", "ground_truth": ["Hierarchical Design", "Structural Modeling", "Module Instantiation"], "concept_id_a": 267, "concept_id_b": 262, "hop_depth": 1}
+{"id": "digital-electronics_T5_56_36", "domain": "digital-electronics", "type": "T5_cross_concept", "query": "How does Fan-Out relate to Logic Gate?", "ground_truth": ["Fan-Out", "Logic Gate"], "concept_id_a": 56, "concept_id_b": 36, "hop_depth": 1}