add files

README.md

@@ -72,7 +72,7 @@ ComBack is sourced from GCC and LLVM backends corresponding  to 178 target platf
 
 ## Organization
 
-- `Existing_Targets/*`: **split data of 178 backends into train/valid/test set in the ratio of 80%:10%:10%**
+- `Code_Generation/*` and `Code_Completion/*`: **split data of 178 backends into train/valid/test set in the ratio of 80%:10%:10%**
   
   | Task | Train | Valid | Test |
   | ---- | ---- | ---- | ---- |
@@ -81,7 +81,7 @@ ComBack is sourced from GCC and LLVM backends corresponding  to 178 target platf
   | Code Generation. | 36,236(5.10M Token) | 4,530(0.64M Token)  | 4,530(0.64M Token) |
 
 
-- `New_Targets/*`: **Take data of RISC-V,ARC,NVPTX both in GCC and LLVM as test set, split train/valid set in the ratio of 85%:15% of other 171(178 - 2*3 - 1) targets excluding RI5CY(RI5CY is custmoized based on RISCV)**
+- `New_Target_Generation/Existing_Types/*` and `New_Target_Completion/Existing_Types/*`: **Take data of RISC-V,ARC,NVPTX both in GCC and LLVM as test set, split train/valid set in the ratio of 85%:15% of other CPU, MPU and GPU targets excluding RI5CY(RI5CY is custmoized based on RISCV)**
 
 
 
@@ -90,3 +90,33 @@ ComBack is sourced from GCC and LLVM backends corresponding  to 178 target platf
   | Statement-Level Comp. | 114,016(10.20M Token) | 20,121(1.81M Token)  | 6,645(0.58M Token) |
   | Next-Statement Sugg. | 152,114(14.10M Token) | 26,844(2.49M Token)   | 9,313(0.83M Token) |
   | Code Generation. | 30,633(4.44M Token) | 5,406(0.79M Token)  | 2,819(0.37M Token) |
+
+
+
+- `New_Target_Generation/New_Types/*` and `New_Target_Completion/New_Types/*`: **Take data of ARC,NVPTX both in GCC and LLVM as test set, split train/valid set in the ratio of 85%:15% of other CPU targets excluding RI5CY(RI5CY is custmoized based on RISCV)**
+
+
+
+  | Task | Train | Valid | Test |
+  | ---- | ---- | ---- | ---- |
+  | Statement-Level Comp. | 87,018(7.78M Token) | 15,357(1.37M Token)  | 2,764(0.26M Token) |
+  | Next-Statement Sugg. | 113,684(10.65M Token) | 20,063(1.87M Token)   | 4,029(0.38M Token) |
+  | Code Generation. | 21,184(3.14M Token) | 3,739(0.55M Token)  | 1,372(0.18M Token) |
+
+
+- `Iterative_Expansion_Generation/*` and `Iterative_Expansion_Completion/*`: **Take data of RI5CY in LLVM as test set, split train/valid set in the ratio of 85%:15% of other CPU targets excluding RISC-V(a) and including RISC-V(b)**
+
+
+  ##### (a)
+    | Task | Train | Valid | Test |
+    | ---- | ---- | ---- | ---- |
+    | Statement-Level Comp. | 87,018(7.78M Token) | 15,357(1.37M Token)  | 721(0.04M Token) |
+    | Next-Statement Sugg. | 113,684(10.65M Token) | 20,063(1.87M Token)   | 1,035(0.06M Token) |
+    | Code Generation. | 21,184(3.14M Token) | 3,739(0.55M Token)  | 219(0.02M Token) |
+
+  ##### (b)
+    | Task | Train | Valid | Test |
+    | ---- | ---- | ---- | ---- |
+    | Statement-Level Comp. | 90,316(8.06M Token) | 15,940(1.42M Token)  | 721(0.04M Token) |
+    | Next-Statement Sugg. | 118,175(11.04M Token) | 20,856(1.94M Token)   | 1,035(0.06M Token) |
+    | Code Generation. | 22,413(3.30M Token) | 3,957(0.58M Token)  | 219(0.02M Token) |