| |
| """Recover the full design source of every corpus record from its upstream repository |
| (repositories downloaded under $CIRCUITQA_ROOT/repos). A file is accepted only if it starts with |
| the design text the question was generated from (its first 3,000 characters) and declares the |
| module; texts shorter than 3,000 characters are complete and are used as they are. |
| python3 corpus_resolve.py candidates.jsonl designs_full.jsonl""" |
| import json, os, re, sys, collections |
| ROOT = os.path.join(os.environ.get("CIRCUITQA_ROOT", os.path.expanduser("~/circuitqa")), "repos") |
| MAP = [("chipyard_verilog/sims/firesim/platforms/f1/aws-fpga/", "firesim_aws-fpga-firesim/"), |
| ("chipyard_verilog/sims/firesim/platforms/xilinx_vcu118/garnet-firesim/", "firesim_garnet-firesim/"), |
| ("chipyard_verilog/sims/firesim/platforms/rhsresearch_nitefury_ii/NiteFury-and-LiteFury-firesim/", "firesim_NiteFury-and-LiteFury-firesim/"), |
| ("chipyard_verilog/sims/firesim/", "firesim_firesim/"), |
| ("chipyard_verilog/generators/nvdla/", "ucb-bar_nvdla-wrapper/")] |
| def local(sf): |
| if sf.startswith("github_repos/"): |
| p = sf.split("/"); return os.path.join(ROOT, p[1], *p[2:]) |
| for a, b in MAP: |
| if sf.startswith(a): return os.path.join(ROOT, b + sf[len(a):]) |
| return None |
| declared = lambda code, m: m and re.search(r"\bmodule\s+" + re.escape(m) + r"\s*(#|\(|;)", code) |
| st = collections.Counter(); out = open(sys.argv[2], "w") |
| for l in open(sys.argv[1]): |
| c = json.loads(l); stored = c["stored"]; code = None; how = None |
| if len(stored) < 3000: |
| code, how = stored, "complete_in_v1" |
| else: |
| p = local(c["source_file"]) |
| if p and os.path.exists(p): |
| t = open(p, encoding="utf-8", errors="ignore").read() |
| if t[:3000] == stored[:3000]: code, how = t, "recovered" |
| else: st[(c["split"], "changed_upstream")] += 1; continue |
| else: st[(c["split"], "missing")] += 1; continue |
| if not declared(code, c["module_name"]): st[(c["split"], "module_not_declared")] += 1; continue |
| st[(c["split"], how)] += 1 |
| out.write(json.dumps({"design_id": c["design_id"], "split": c["split"], "source_file": c["source_file"], |
| "module_name": c["module_name"], "verilog_code": code, "how": how}) + "\n") |
| for k, v in sorted(st.items()): print(k, v) |
|
|
