{"design_id": "003256a861cd", "module_name": "axis_rate_limit", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_rate_limit.v", "sha256": "bdfb4e29768c5224c543098765b8d648f3fe774eb42643c289d85b446414d155"}}
{"design_id": "0036dd6de909", "module_name": "ct_lsu_lm", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_lm.v", "sha256": "983cea5f7ee969d1794e5b59c4eb237f61bb3ad9abf06b63fd26101fb930d8d4"}}
{"design_id": "00400c8da762", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/cn0579/coraz7s/system_top.v", "sha256": "a0589de5035cc348a8366ea68af9e6c09894c682f7bb609204d4b0e6194cffa7"}}
{"design_id": "005c3cf20b91", "module_name": "jesd204_f_tile_adapter_rx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx.v", "sha256": "60afdbe451cb1e674982fd041ecda9fbedce57ea69d526bcc80e7cac4b101eb1"}}
{"design_id": "005dc1828524", "module_name": "axil_cdc", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_cdc.v", "sha256": "fbb8018e34b7173e9a8de97c9e70be092abbb9a581dc83ec037561f401d11edb"}}
{"design_id": "0090fd5a7d07", "module_name": "zipbones", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/zipbones.v", "sha256": "7331c004434ab9ac72d4c089c6429eea421f35a60a4d070757cc0385b31125f2"}}
{"design_id": "009d1387bece", "module_name": "ct_l2c_prefetch", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_l2c_prefetch.v", "sha256": "0ec98d650ff38786393f71f748e9cec0eaeddcef99b90f74241f6f04dd3a28d2"}}
{"design_id": "01156403d141", "module_name": "fec_rot_1", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_1.v", "sha256": "04d729f6f74fafdde4b7e83036d676103e79f8b74efc62ec7f6d041806f82289"}}
{"design_id": "014412191b9b", "module_name": "ct_spsram_128x104", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_128x104.v", "sha256": "9d8cd20446a804a7df726d38bf52ac6110c179a68c905a09f98125bc0d40e37f"}}
{"design_id": "017428f872ba", "module_name": "axi_vfifo_enc", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_vfifo_enc.v", "sha256": "ec401dd8d0f29e6bf816c4709bb2b9e9afc89ec4eb046cbcb23b2db6abdc46fa"}}
{"design_id": "019f0b716455", "module_name": "axis_switch", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_switch.v", "sha256": "ccfe5eb62d5fead748bca36f22a0012599af46d2ec486c1bb091308234510e6f"}}
{"design_id": "01b98bd6ed40", "module_name": "NV_NVDLA_RUBIK_dr2drc", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/rubik/NV_NVDLA_RUBIK_dr2drc.v", "sha256": "27cea2aae721752cdd3aed967c27850adae2986406b7d0f7863796f982606646"}}
{"design_id": "01c31ce8fc61", "module_name": "pcileech_pcie_cfg_a7", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "pciescreamer/src/pcileech_pcie_cfg_a7.sv", "sha256": "f0e619b4a33cec0bccf444ac26792f01636ba7d27c0671e94bcaab8546d099a4"}}
{"design_id": "01c5eafaf490", "module_name": "axil_reg_if", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_reg_if.v", "sha256": "6aac73057466d4c16f79a5575f5fb4136b494d41cd63aaa83fefe90319006a39"}}
{"design_id": "01c6bec2f093", "module_name": "zipdma_s2mm", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/zipdma/zipdma_s2mm.v", "sha256": "3cf1392d68a1a01d1b7ba92609fe062bfd5f397515648d990f8ddfc94c26b8dd"}}
{"design_id": "01d205de60f4", "module_name": "servant_tb", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "bench/servant_tb.v", "sha256": "1d4ca9b0d78990f5c9b6fa161849ff3ea72d9edad9eb3bd99b4bac5f9b41583a"}}
{"design_id": "01fe16ffb83a", "module_name": "sfifo", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/ex/sfifo.v", "sha256": "f97bc8f20fa52b4819f9cfd4a18cfd257370359c065760441da37dba281c0145"}}
{"design_id": "01ff01fee60e", "module_name": "axis_arb_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_arb_mux.v", "sha256": "2e71c10f54a03375e7b9e2f6ae559a0c122715297d6db75a764c0db70701108b"}}
{"design_id": "0208353faf8d", "module_name": "mac_pause_ctrl_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/mac_pause_ctrl_rx.v", "sha256": "4b8d5d985fe5e7d3ec28f0c70a8c212fb7b3df6548cbf4dcaac2473a23b24a57"}}
{"design_id": "022f529315ad", "module_name": "sirv_debug_module", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/debug/sirv_debug_module.v", "sha256": "cb1a2aa61cbc22c1e718844fa6cff4df95dafd2d056a64b3a574db01118258e9"}}
{"design_id": "0234b1c0fe61", "module_name": "uclock", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/uclock.v", "sha256": "2a73beb76a7f2b364f8e18047a7dcf71f3bda1a07dd772ae1dd9ec6acc40b118"}}
{"design_id": "02363a256c98", "module_name": "sirv_gnrl_pipe_stage", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/general/sirv_gnrl_bufs.v", "sha256": "d46f8701f99a79b321cecd2e2b776caa2d7a76925e07b675bbd3952a47fb3ab2"}}
{"design_id": "0244f7d4ed10", "module_name": "nv_ram_rwsp_256x11", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsp_256x11.v", "sha256": "1969a6775530c1cd34acde1fa09e30ae97f54ff9d40759cb52729e9231d14f6a"}}
{"design_id": "0257f6d8dd6c", "module_name": "util_mii_to_rmii", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_mii_to_rmii/util_mii_to_rmii.v", "sha256": "2547c609fc7cd733c59e2eae637d12e339d618550104ca39818c751e4b8dc474"}}
{"design_id": "027a7ac58213", "module_name": "oh_oa32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oa32.v", "sha256": "664eb2c1501a6d5d2581ad071c4cc1b392ac8a96cab88fa828e6b80a00be45e5"}}
{"design_id": "02aafd3f71c9", "module_name": "edma_dp", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "edma/hdl/edma_dp.v", "sha256": "20d40c73ef80e12368567a3fa41682a152fc056e6e5da9320512ad5b0f0a1727"}}
{"design_id": "02b09b9a60ad", "module_name": "ct_f_spsram_256x84", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x84.v", "sha256": "ba5095de2c6444a6d02c3c69959e801f6969e2a17702d042b48a48fe91c9c794"}}
{"design_id": "02b188cc4361", "module_name": "mtx_fifo", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "mio/hdl/mtx_fifo.v", "sha256": "f7e18ac8da531372bfb4c499bb217e70bf548fa46479a3489c1f70a77d398fef"}}
{"design_id": "0311e75ae9b3", "module_name": "aes_256", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/aes/aes_256.v", "sha256": "d583ef9948be20f305335a9475fb62244aa6a1b4bd0416a5ce58fbaed116199d"}}
{"design_id": "03139372ea05", "module_name": "axis_arb_mux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/axis_arb_mux.v", "sha256": "04b4e5a8838c94a7d5752c7d4270330a3241ee4fd160642cba27cfad4c1094a5"}}
{"design_id": "031d79e4f7d3", "module_name": "priority_encoder", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/priority_encoder.v", "sha256": "df28220d95b47df349a72803a9751aad331eb8e1435416e8686d00572a974dd5"}}
{"design_id": "032316cda79f", "module_name": "ct_clk_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_clk_top.v", "sha256": "6778d1644853eebf0f1f176e13b257113c3c726aa2ac2b2a6b09d3f1271b482a"}}
{"design_id": "032974379cfa", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/ATLYS/fpga/rtl/fpga.v", "sha256": "960ca32f8ca762458b3f82768c7e835e12550afcd620b661a689d531ac2c1626"}}
{"design_id": "032cbbcb5a44", "module_name": "axis_broadcast", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_broadcast.v", "sha256": "a644b7542adf7552cb4713ab22856e1b76c58780da970d122351e45bc0bc51bf"}}
{"design_id": "033f3e48d47c", "module_name": "crc24_dat64_only_flat", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc24_dat64_only_flat.v", "sha256": "9a3f0f0ec842fe616d833bd9054130a2de6266e3176ae0a93c922f5fe0263514"}}
{"design_id": "03434622043b", "module_name": "RAMDP_80X15_GL_M2_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_80X15_GL_M2_E2.v", "sha256": "9e69ad95c5eb54ef9c220b336f1f8910c867cca2dfdf57471bf79c311026c978"}}
{"design_id": "034b39c6d6f2", "module_name": "ct_ifu_decd_normal", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_decd_normal.v", "sha256": "17f475965e15af27ab44d9c91412f547bad3734510d7dabcc73cf1f00fbb0684"}}
{"design_id": "036be0a4c9ae", "module_name": "asic_aoi33", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_aoi33.v", "sha256": "3056d83cd2732a2210bba39d5209bbccd92dee5d505ae90b1bfa5449230e7e70"}}
{"design_id": "038933ea5922", "module_name": "sub_module", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/get_ports1.v", "sha256": "274fe8610a8f00ee75eec7a7b00ce1c04c42108f837e7a2cb124896292484212"}}
{"design_id": "03cbd92299f5", "module_name": "usi_i2c_test", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "case/usi_i2c/usi_i2c_test.v", "sha256": "27d58e86787fd79842dcc7e46d747edd9129fc5b63a5c54b63f21c6c8d8d3be6"}}
{"design_id": "03dd2c454a32", "module_name": "udp_ip_tx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_ip_tx_64.v", "sha256": "e3bb0ebd4c7f0c1d9753dcea3940809ac7a747d681e7d3cb9c5744f7aa4088fc"}}
{"design_id": "03e99aadb78f", "module_name": "axis_xgmii_tx_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_xgmii_tx_64.v", "sha256": "e65559d1aad43507629efa1b54e59a9bfa650ee2e06f1ead8451c1b4134fe8e2"}}
{"design_id": "040ae23d3cc4", "module_name": "cpu_mem_icg_check_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/impl/mem_icg_test/cpu_mem_icg_check_top.v", "sha256": "3c2c5dcd224e8a8b6b475ef4d3d11b4749f1b50c77e1fe974d9c71c1f5e0bab5"}}
{"design_id": "04278c6fa62d", "module_name": "ct_had_private_ir", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_private_ir.v", "sha256": "ede3e2e7447ece50fbfbbc92178f7568afdc97404fc2287d1bebe7a529799bd6"}}
{"design_id": "0434fde05100", "module_name": "pcie_tlp_demux_bar", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_tlp_demux_bar.v", "sha256": "4d3e0499692c627875729d08e8c4c60e60500a78e1885e10acd7afb611c46cd3"}}
{"design_id": "043586e54a0e", "module_name": "oh_reg1", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_reg1.v", "sha256": "60e1bd5ace98a71458f37b128ca37dcaa80f332cea9864b032a76e705e48b34f"}}
{"design_id": "046a678ee120", "module_name": "test_axis_cobs_encode_zero_frame", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_cobs_encode_zero_frame.v", "sha256": "3d212d1f84cc4c64c1244b71e0278f0cc579cd73f8912a482847ef9aa5e8f335"}}
{"design_id": "046e3670d11c", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/fmcomms2/zcu102/system_top.v", "sha256": "f3d79c4c723be1ee576b3297b442ef60e73580e6c00d0e40ec84645755e9ef7c"}}
{"design_id": "049a2fa09d6b", "module_name": "io_generic_fifo", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_uart/io_generic_fifo.v", "sha256": "106ee607c8e48cee322a61295b52cc275c0fa540ec6d78547723cca5e9dfd0b1"}}
{"design_id": "04ab15ffca83", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "edma/dv/dut_edma.v", "sha256": "91d73e540c961e1b6185f324f82a3224095c790e058a0a6af03aaf8e96a30c9e"}}
{"design_id": "04e09a045e58", "module_name": "asic_xor2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_xor2.v", "sha256": "2c83a9821cb6fb079d546762400fc4c43a58a7519f7804b1c7a073a27197c92d"}}
{"design_id": "051422024433", "module_name": "ct_lsu_mcic", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_mcic.v", "sha256": "5ca52fc8fad921cbfb55939363d88363e9e599a7f3bd7deb27a4d78bb0830dc9"}}
{"design_id": "052745db4692", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/S10DX_DK/fpga/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "05368e9b28b1", "module_name": "up_tdd_cntrl", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_tdd_cntrl.v", "sha256": "36ba71613190c1c36b23eba3a566f100f9896ffd17af60a4e53f82161a78e8c2"}}
{"design_id": "053d41449bf2", "module_name": "axi_ad9361_cmos_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/intel/axi_ad9361_cmos_if.v", "sha256": "a630b9d6bb1ca389677951635365a610e79b3e3ade6a1925f54a9cde85b929fe"}}
{"design_id": "053f5d437a56", "module_name": "FP17_TO_FP16_mgc_in_wire_wait_v1", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/HLS_fp17_to_fp16.v", "sha256": "938b2df37315aa2f00f7aad58119d0a7ab3e35b748155190356a2e1b6af1fcac"}}
{"design_id": "05442ef43933", "module_name": "pcie_us_axi_master", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_axi_master.v", "sha256": "7f5dff665f88b4b66da5d9de6a96594b06b10468fdded3a4d56492e79f9cdf65"}}
{"design_id": "059bb4fbb91f", "module_name": "axis_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_mux.v", "sha256": "599c47b8889b6f22a325b3bb27a38b13b64a7ba08b0f4aefea1e2f550389e68a"}}
{"design_id": "05af878ae78a", "module_name": "ip_eth_rx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip_eth_rx_64.v", "sha256": "8773830d79d7e339ee40c72cd63287fdf3dd884c80e151e401c1195bd32fd917"}}
{"design_id": "05fdd1dffc1c", "module_name": "ct_biu_lowpower", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_lowpower.v", "sha256": "2434834c91c9337d5a94807f56ba06ea34cc140d173457cf22dcca3f4ccb697a"}}
{"design_id": "0624430a8c2a", "module_name": "ct_vfpu_cbus", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfpu/rtl/ct_vfpu_cbus.v", "sha256": "ceee498a703ffafdd0678980aa673f453ed9b68b1edfa27808890ba900707174"}}
{"design_id": "06603cfc65b8", "module_name": "cordic", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/cordic.v", "sha256": "88ab7a631b9328d628fe71bc772ace15b181c676c99b26f826176f147b5e7711"}}
{"design_id": "06666d1f55af", "module_name": "NV_NVDLA_MCIF_WRITE_IG_spt", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_spt.v", "sha256": "8f8e72bff8c1cdb89d428960a5c966af91a82e0e144d56a649298a01edcc3c5e"}}
{"design_id": "0671eb4c9cbd", "module_name": "axislave_stub", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "axi/dv/axislave_stub.v", "sha256": "02ae9d9b6a1f3d69dcaed2d4dd2e07a6fb08e1d2c07ed0709d9541c11cc68ba6"}}
{"design_id": "06778b88a759", "module_name": "serv_rf_ram_if", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_rf_ram_if.v", "sha256": "abb39b6bdf4d335bd2f90f75ddb1a410500a1a51a3e9f170453cb491d98d8697"}}
{"design_id": "06cb742dc63d", "module_name": "serv_bufreg", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_bufreg.v", "sha256": "76404174ec92c6cf68e0042798dede84d77c5e454c7f428afc7b9f612a3c52d4"}}
{"design_id": "06d7749edf27", "module_name": "oh_aoi22", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_aoi22.v", "sha256": "a3c7b70e3fdc1e7c401ca53a6ee41318837eb3f6a2cf7991b6afeb8632d3ccb1"}}
{"design_id": "06e479e0801d", "module_name": "scrambler", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/scrambler.v", "sha256": "ad358b51e504902043d1c6f0b93e53eeac48e60ab62814e29f73ccffa14ecad9"}}
{"design_id": "06e5b2dc6e78", "module_name": "mac_pause_ctrl_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/mac_pause_ctrl_tx.v", "sha256": "c5de52ceae4cf7c048262132191b1e4c366deca15d931e4703f6a05eff789c5a"}}
{"design_id": "06f3079bba57", "module_name": "uart", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/uart/uart.v", "sha256": "a50efd8ac28041aac3cb49bacd69616fc71c244b5ffa6983984a863a96ade296"}}
{"design_id": "06fa7dd019fe", "module_name": "mac_pause_ctrl_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/mac_pause_ctrl_rx.v", "sha256": "4b8d5d985fe5e7d3ec28f0c70a8c212fb7b3df6548cbf4dcaac2473a23b24a57"}}
{"design_id": "0710d49c17de", "module_name": "ct_spsram_256x7", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_256x7.v", "sha256": "80e2f92e707f3e6474b5d519d452806d031c70f1122ebc54be13416fc4dc0bc6"}}
{"design_id": "07173daae86b", "module_name": "ct_mmu_sysmap_hit", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_sysmap_hit.v", "sha256": "d06c358546d0c5e381b309425d5b90f3e7e344a7d1f21b2ed53ef90c41300491"}}
{"design_id": "0719a05c21b3", "module_name": "mqnic_dram_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_dram_if.v", "sha256": "4105cc699d188192c000d10203a14e979db5a0330a187ccea4c3a4ac4ca2ac3d"}}
{"design_id": "072929cf3629", "module_name": "bmc_spi", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/fb2CG/fpga_25g/rtl/bmc_spi.v", "sha256": "e5f068feec8a6d7c82d6fb977e7caf308811e311ea9e618ee701849e520754c5"}}
{"design_id": "074f8bf249d7", "module_name": "tdma_ber_ch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tdma_ber_ch.v", "sha256": "708fb6736f342c97118ed7ec58eec6b6c22289607ee844db37ba15fcb72d7f43"}}
{"design_id": "07685427c1b9", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/read_verilog6.v", "sha256": "fb521c6d96f759de88449e00a50a2f4e96d89cf4ecc8e838e7b54bbf773d6b17"}}
{"design_id": "0770463192f9", "module_name": "tempsenseInst", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/pdn/test/sky130_power_switch/netlist_regions.v", "sha256": "e35aed9d6f98fdf688fd96793b5eb3b61cb64f5839f8cd3437afe5cc387f924c"}}
{"design_id": "078e3a1579f0", "module_name": "karatsuba_mult", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/karatsuba_mult.v", "sha256": "6de762e2705a27168fbb71ea8f5a713ff37ac1cba987a81cab20a62a7db82857"}}
{"design_id": "0792944d7d81", "module_name": "ct_ifu_sfp_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_sfp_entry.v", "sha256": "99f8bd52c1de314372b1dc72455a13eb63824cf5ac567c2df5a773559175e20c"}}
{"design_id": "07cf9b3a7ab8", "module_name": "sirv_repeater_6", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_repeater_6.v", "sha256": "330a75c050c67454c568890c6e251341972440bf7eb743d73508adfd5321fae0"}}
{"design_id": "07dc4f283159", "module_name": "asic_oai222", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oai222.v", "sha256": "07983af3d8d39f2f4240874e07d6f18191008f97f306da9d3075577fc57614ea"}}
{"design_id": "0801bc4e896f", "module_name": "axi_adxcvr_mstatus", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v", "sha256": "82ff448434dbef831e732bcda6137cd55f0acf4b233fa798be2832a61be84afd"}}
{"design_id": "086f9316c8ad", "module_name": "sirv_gnrl_ram", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/general/sirv_gnrl_ram.v", "sha256": "b3273f66d2922151b177aeaa52e7aa78cef5aa521148880b9017224534f2eca0"}}
{"design_id": "0876c75104f9", "module_name": "cordic_demod", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/cordic_demod/cordic_demod.v", "sha256": "bdf075da1dc6ccd9479b4b261728b1fbbdde6027ceb64668a4d068e185187a24"}}
{"design_id": "0887a60c57a8", "module_name": "axis_eth_fcs_check_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_eth_fcs_check_64.v", "sha256": "5d5d06c813a8b108173db5636266f4511de5fa6cf5478fb48472e72e6a752ad9"}}
{"design_id": "0888d48f2598", "module_name": "pcie_us_if_cc", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_if_cc.v", "sha256": "0349d7a18d87fa1cd47d7a1e89da18c6c53f052cf926daabc4d706678d90a943"}}
{"design_id": "088f5a48f150", "module_name": "ad9434_spi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9434_fmc/common/ad9434_spi.v", "sha256": "d1aeced43e700a080b57eabbca5c61a5ae514429e929a62619520ac50be25ba1"}}
{"design_id": "08ae97ead797", "module_name": "IBUFGDS", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IBUFGDS.v", "sha256": "2f0e9ff0071bcec4a7e251692fb27bf7cc508eabffe765131edeeba7ab2b72dc"}}
{"design_id": "08f1b39698e7", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/fb2CG/fpga_25g/rtl/fpga.v", "sha256": "9a9855f784c6decb46471b776bcfd6f8fe20705dbab8803f655907f4e1c47059"}}
{"design_id": "08fd5c77eb14", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/DE5-Net/fpga/rtl/fpga.v", "sha256": "7fa45b46ed07da14066c8188cc41b59199d92dac83eea20596fc31ceb9c7d0f0"}}
{"design_id": "0939564c6041", "module_name": "cmac_pad", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/cmac_pad.v", "sha256": "db4349a03850733cc4870c94b90b5bc04cfa2d59f5c4d18fcab3493904455d16"}}
{"design_id": "093cd18e11fa", "module_name": "led_sreg_driver", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/fb2CG/fpga_axi/rtl/led_sreg_driver.v", "sha256": "91ef35971991fd2b536d1ccb263e892441e9fa0d631e8a14d3db896238f3cb34"}}
{"design_id": "096b515fe8cf", "module_name": "dec_67_64", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/dec_67_64.v", "sha256": "f55965bc48ca2b2b89ce07f367f55e8289aa5d3104bcb4694412ac76c29bf764"}}
{"design_id": "09bc431b6d97", "module_name": "pll_audio", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/pll_audio.v", "sha256": "82118b01e3c3ba8bed269b9eed7cf06bf6af69e028e40f2c4c184de0d7b9f227"}}
{"design_id": "09c2d87e0cd3", "module_name": "crc16_dat32", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc16_dat32.v", "sha256": "bf5d311669de894ffd607ea608cbfa5eafc979ea404ad79e213d5919e5b10e16"}}
{"design_id": "09de49df29d4", "module_name": "oh_dffsqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_dffsqn.v", "sha256": "e2ebe1bb4a5ce196dfa1fc6f7596eea9c2f9e84c3a5156cee800d5a437eacb5f"}}
{"design_id": "09dfa18e3094", "module_name": "pcileech_mux", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "GBOX/src/pcileech_mux.sv", "sha256": "0c264ebf3ab163fbe122bc90ad03cb874809ac9f3e73048b563a768abbd5e63c"}}
{"design_id": "09eae5b57b14", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_k35.v", "sha256": "71548085064c295c9ff098be3b20af2bff9cc7df663d74e5e1dbb38528b134e2"}}
{"design_id": "09ee6230d861", "module_name": "ct_ifu_icache_data_array1", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_icache_data_array1.v", "sha256": "359cc1fd57943aed281b2095758785c86aacddfcff4da43adaefc602234fa985"}}
{"design_id": "0a177c67cb52", "module_name": "sirv_jtag_dtm", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/debug/sirv_jtag_dtm.v", "sha256": "e5c8afe172ecb8b152fadbf3b3e8913b2aa43af5239ffeb8fd8c4b044fe6fa40"}}
{"design_id": "0a49bdc5606e", "module_name": "oh_standby", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_standby.v", "sha256": "61d424bbcb7f70abf510b2769eae5d826b12ad7411e8e3f6c6085c3edaefbfeb"}}
{"design_id": "0a4c7b2e7243", "module_name": "timer", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/common/timer.v", "sha256": "f3c7d3604409960087dee8c0d24679d83d1e947cd937c7eef18d13a46d93746c"}}
{"design_id": "0a567bfd3c6f", "module_name": "asic_dmux7", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dmux7.v", "sha256": "55cec81f9b2b184927609a960256cefd000d60cc8cb88b95cf643a48c9cf6476"}}
{"design_id": "0a5cdef37ddb", "module_name": "ct_ebiu_lowpower", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ebiu_lowpower.v", "sha256": "08369ffbb8bbf7ce91727a1f3e500b95040cf3074b9189e39612b22fbc5e82a6"}}
{"design_id": "0ac8e76fd8af", "module_name": "test_eth_arb_mux_4", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_eth_arb_mux_4.v", "sha256": "8da564ea9494b417c22166b239625cd2a10d7ab0c76be1f8d3e6ac9f2c9875ff"}}
{"design_id": "0ad43acd1c32", "module_name": "dma_ram_demux_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_ram_demux_wr.v", "sha256": "77dbe7e0f710744b34e11d8a83a41bac3c63c83b858e2c0bce3aa9a160083cc2"}}
{"design_id": "0ad8b1fb26b5", "module_name": "eth_mac_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/eth_mac_wrapper.v", "sha256": "3db555ace2fc858592764d4dd8bf09cc1cfff3f271398c7f2d5f273d3d67419a"}}
{"design_id": "0ae05d9fdfae", "module_name": "mlab_dcfifo", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/mlab_dcfifo.v", "sha256": "d591f4eedddb98f484f23373301f567cb6c2ac797d688424958c6a19325725cc"}}
{"design_id": "0ae1a27340eb", "module_name": "oh_ao21", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_ao21.v", "sha256": "ceb8e68365dd44b63c999c871e6c77b6fa44b3916fee2f9c2a9644bd965d77b3"}}
{"design_id": "0b87fdb48b2d", "module_name": "mqnic_tx_scheduler_block", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v", "sha256": "15a682fbae8367a7d536d646e98954fc41b258de508f524fa6783e18036a4f52"}}
{"design_id": "0b8c27af250c", "module_name": "SDFCNQD1", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/SDFCNQD1.v", "sha256": "4aefb891c8d8baa3f110bec4aa8fccef674fa411de35749390a5d1f9201e72fe"}}
{"design_id": "0bea69883cef", "module_name": "aximaster_stub", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "axi/dv/aximaster_stub.v", "sha256": "c462c7884e2a64acd2f8942280c08f75d09921b68c5c3e383ad210093d155914"}}
{"design_id": "0bfe5ccab79a", "module_name": "test_axi_adapter_32_32", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "tb/test_axi_adapter_32_32.v", "sha256": "7e41cc0a1b76baca34eb58eec0d9f6381fb2209fda284d0b4856ddd80c29cd5f"}}
{"design_id": "0c0e797467e4", "module_name": "axi_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_register.v", "sha256": "76eea19cf4967cfeb40cb4c0f10de3e20b70e841a79271134de685df7e91e3a2"}}
{"design_id": "0c506d2b8b18", "module_name": "emmu", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emmu/hdl/emmu.v", "sha256": "4e86356d401c2287267a06980b8b8d1029da2e7028f45ec89266c73ef6d85f87"}}
{"design_id": "0c5851e3885f", "module_name": "axis_tap", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_tap.v", "sha256": "9b659c8c99dcef1feba2f859369c8c127a1b5539c35245446e35591de9fa8106"}}
{"design_id": "0c6aefbd3a03", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/max96724/kv260/system_top.v", "sha256": "59079a06e1b7aa8213ba4ce850d09d82610a7a2c51e63a131b7a71e0f4008904"}}
{"design_id": "0c803d44d185", "module_name": "axil_cdc_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_cdc_rd.v", "sha256": "49b0e680b3f69918f6cc0628bdda3fdaf0fb80914b43a0ae9638554b6dc905ec"}}
{"design_id": "0c85dcd6337c", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/testbench/dut_template.v", "sha256": "196f6ebf58b22950ada6f56397f73806e0090837a585c568bc64a50197dcc563"}}
{"design_id": "0c929c2b9f3c", "module_name": "axi_adc_decimate_reg", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adc_decimate/axi_adc_decimate_reg.v", "sha256": "f38c8be9ce6d5286ed36427db32ae715ff1136ff1aa1a4d886566d807f37a183"}}
{"design_id": "0cae8d4dc9ab", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9783_ebz/zcu102/system_top.v", "sha256": "2e4ecb70a2cfc39592e9b6f31e37a63e66545edefdc088175883356feb5318ff"}}
{"design_id": "0d0213535826", "module_name": "axis_srl_register", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_srl_register.v", "sha256": "5c0a8b0810977520e78fdee88254a824e6e86e526b0e1b04b89734217a66e6a6"}}
{"design_id": "0d4e5fd3f6f5", "module_name": "ct_idu_is_aiq_lch_rdy_3", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_is_aiq_lch_rdy_3.v", "sha256": "906c355c6009a5450a9e2ce1dfa13b9dd21f3bda95471bdf87c81deae6be7cd5"}}
{"design_id": "0d71a500f3ef", "module_name": "axi_ad9361_cmos_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v", "sha256": "a0aea713bfbbd3e7c57a10a329714f498ef20995ce6036b8e41f561748d8e8f8"}}
{"design_id": "0d817c1e8173", "module_name": "NV_NVDLA_SDP_wdma", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_wdma.v", "sha256": "1ba4e02a64f206f59b9d5379befea25fc3b34f868273f91717aae0ae23dff50c"}}
{"design_id": "0d8730c7ff03", "module_name": "bmc_spi", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/fb2CG/fpga_100g/rtl/bmc_spi.v", "sha256": "e5f068feec8a6d7c82d6fb977e7caf308811e311ea9e618ee701849e520754c5"}}
{"design_id": "0d97e55fbd04", "module_name": "ptp_perout", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ptp_perout.v", "sha256": "78dc33fda3b18a4027dab0d444e88e2cd6eb5cde7de3b72dd8bea50a48256123"}}
{"design_id": "0dba66f51009", "module_name": "ct_ifu_btb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_btb.v", "sha256": "41061c6771ad4d9d6c73425c2ff9d47c96a2e59f087505206993c376ca361e2f"}}
{"design_id": "0dc728f8a082", "module_name": "xcvr_ctrl", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v", "sha256": "c119978a2fb8e94b3547b893b045ed2e0eff835de41e0e41c0faa4bb1800472c"}}
{"design_id": "0dd6f814c0be", "module_name": "test_eth_mac_10g_fifo_ptp_32", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_eth_mac_10g_fifo_ptp_32.v", "sha256": "0229c8b073b782bbf0f84c8041836503af8122a7b6249920c22fe5104795f622"}}
{"design_id": "0ddf34a930f0", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "0de9c8a00e38", "module_name": "gcd", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/par/test/gcd.v", "sha256": "38269e4715fdc2c034efe29d7d9895da1fe76ee1fe30b4176e784cc6d8403f11"}}
{"design_id": "0e099769f970", "module_name": "NV_NVDLA_RUBIK_wr_req", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/rubik/NV_NVDLA_RUBIK_wr_req.v", "sha256": "812f37aab0f93a64f691e36ececfc8b2d494efd01aa21a5dbc7ad834922f02a8"}}
{"design_id": "0e1a3348b097", "module_name": "gearbox_40_66", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_40_66.v", "sha256": "a624dc7e4c6e3c8535d2f24c451decb759d335c2f6919428cbcd8a14b85d7f9e"}}
{"design_id": "0e1a5d42f5eb", "module_name": "ad_data_in", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/common/ad_data_in.v", "sha256": "2c41a1bdce5ba97c6741d347f8574f5d6bf336a0327003739d8b1e615a3c345d"}}
{"design_id": "0e3f11020fb8", "module_name": "axi_vfifo_enc", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_vfifo_enc.v", "sha256": "ec401dd8d0f29e6bf816c4709bb2b9e9afc89ec4eb046cbcb23b2db6abdc46fa"}}
{"design_id": "0e9ec139f2b8", "module_name": "jtag_to_c_probe", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/jtag_to_c_probe.v", "sha256": "b4a502e87e9e89b27a541ad51c91f5965a385e6a5c134daeed457d042c2deb4c"}}
{"design_id": "0eaa7497cd4f", "module_name": "axi_ad9361_lvds_if_10", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v", "sha256": "a55d153d7287ed596ed7eaa86783ab2ae3e6f56ec86827094ce0c871f3f97d6d"}}
{"design_id": "0ef2da63568b", "module_name": "ram_delay_reg", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/ram_delay_reg.v", "sha256": "c2c78fd5533e7bc82a68dc77bd127ccee338b3be2fde601ab942e5a82a3512df"}}
{"design_id": "0efca1a4c2d4", "module_name": "NV_NVDLA_PDP_slcg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/NV_NVDLA_PDP_slcg.v", "sha256": "3a6fb238205bf7360fa335e9e848d96d4247373dafe130805c2ce035c63938cd"}}
{"design_id": "0f2de6b3a4f0", "module_name": "phy", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/DE5-Net/fpga/cores/phy.v", "sha256": "7725db673c8ec470a2ed994343745a969aea39dc7859dc06245a768c602016d9"}}
{"design_id": "0f521444fc80", "module_name": "altera_avalon_sc_fifo", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/altera_avalon_sc_fifo.v", "sha256": "b71ebd28aab28bd9393df54e92fada1d4b02d0c8817afca0d6d497871dcf8850"}}
{"design_id": "0f5f87509da7", "module_name": "i2c_master", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/NetFPGA_SUME/fpga/rtl/i2c_master.v", "sha256": "ff46775d79e00853c9008f668ae9dfb71ad2cb93d6fec783aa08e527f207efb4"}}
{"design_id": "0f61631b423e", "module_name": "fec_rot_20", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_20.v", "sha256": "9b83b31d5bc5daeaf3f5616d680ffd48cd668946687a20662cb693659cc2782a"}}
{"design_id": "0fa25b06f5d1", "module_name": "addrdecode", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/addrdecode.v", "sha256": "fe13ae1935f682b46a73529b70127f3a71ca08f4223f63a58433e50d09886734"}}
{"design_id": "0fa7617a0042", "module_name": "oh_ser2par", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_ser2par.v", "sha256": "af81f59eb67b56dd7caea6fc775e2665ac95007912517a28296b81b1ff771f06"}}
{"design_id": "103dd8eb451a", "module_name": "ct_ifu_bht_pre_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_bht_pre_array.v", "sha256": "174cbe8a939eee4f79125102925bde322ef5ab4fe7d3d170d26cc99804c9fc78"}}
{"design_id": "10531f204b85", "module_name": "test_axi_fifo", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "tb/test_axi_fifo.v", "sha256": "fa1d6c2b73678fdb01353bc8671d8034142dd97c97217bc26e9bbb8a1f2cece4"}}
{"design_id": "1053b12c3dd6", "module_name": "crc32_dat48", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat48.v", "sha256": "e87d8df0ca41a3050eaf416f96ecf56f98f2375a5d77c8962dd815171d2ce520"}}
{"design_id": "1078167d2ae5", "module_name": "test_dma_if_pcie_us_rd_256", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.v", "sha256": "3528b9a38e80a1733db3179ff9f3e7b6450b05cfe654cbe20504621554074a7f"}}
{"design_id": "1078962b4928", "module_name": "CKLNQD12", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/CKLNQD12.v", "sha256": "80bf2ace4582b6d834281c18cb9b18ce7e591c423268a968dcd42aaadda0ddb3"}}
{"design_id": "108415de0864", "module_name": "ODELAYE2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/ODELAYE2.v", "sha256": "c5933ecc499471174e0573d83261db3cfc0cd1514d05dd6493d6cf85b719e23c"}}
{"design_id": "108b6c737f69", "module_name": "ct_had_pcfifo", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_pcfifo.v", "sha256": "f2efc8eda5f885157cc305652ac2d362bc79339fe28fbfc294991ea94e00f59a"}}
{"design_id": "1090455a236d", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/cn0506/zed/system_top_mii.v", "sha256": "d226103719469ca13be5b753bde724ed4027993640132856fc34a2e8e933cdfc"}}
{"design_id": "10926a17e1ea", "module_name": "oh_lfsr", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_lfsr.v", "sha256": "1ed2704e38427ed01d86f1e9faf54a035b45b2a0fe92ded1c93ea89c84d902fd"}}
{"design_id": "109bd7db9848", "module_name": "memdev", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "bench/rtl/memdev.v", "sha256": "033732fa6c613dcad2c6d48f4eaa841c187a1272b0faf7e66f225fbd1e5690c9"}}
{"design_id": "109cb93ab022", "module_name": "axi_ad7606x_18b_pif", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad7606x/axi_ad7606x_18b_pif.v", "sha256": "65b6b3a3a82270e84f676191a06d06ae75cd6650dbe808644a7733a97d0bd52e"}}
{"design_id": "10d19988e10d", "module_name": "adc_ctrl_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/adc_ctrl_rom.v", "sha256": "e17d325d130aea050bd89d181a6c3d5502775922913b1842622cfb8964962516"}}
{"design_id": "10e1fd8898da", "module_name": "apb_spi_master", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_spi_master/apb_spi_master.v", "sha256": "ff7fe26e7f54bbea8961d9edf94c1d0ca78e62eb12f63ab961d7322cfdade4ed"}}
{"design_id": "10ee2bc12d64", "module_name": "parallax_gps", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/parallax_gps.v", "sha256": "d08dde532b0707acf296926184f74af3e7d3589ca8acdb3d716ec55012c69e0d"}}
{"design_id": "10fb217cbeb1", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v", "sha256": "a4c9c65250507cf5fda79689130865404998ec4373958a6091d83516931a6ebf"}}
{"design_id": "110216c0335d", "module_name": "sirv_ResetCatchAndSync", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_ResetCatchAndSync.v", "sha256": "b6d9378451815c6ba48c86ad32d6ee5d67b337ea01e0dd61fb956800c8516e4c"}}
{"design_id": "110474fcc4ee", "module_name": "div", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/div.v", "sha256": "ca220c1db020a4b3365d8c29fe9cdb24dfbc93a5db82827cb818b888d834abf5"}}
{"design_id": "11089d60ef5f", "module_name": "eth_gth_phy_quad", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/HTG640/fpga/rtl/eth_gth_phy_quad.v", "sha256": "a9c86e87b929bcc3fc4048415a3a05d8c504b15b8224bfed62f2bb95a72b9261"}}
{"design_id": "1164b4b1a905", "module_name": "fec_rot_24", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_24.v", "sha256": "57548468968affdfb721f1b4166f00eb2da567c65df6071941d0f965f2b5a9b2"}}
{"design_id": "117655996e3f", "module_name": "eth_phy_10g", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_phy_10g.v", "sha256": "89d13d9dec752dcfebba26b11bf8070467a0304e4c771020b5009e220ab3ae59"}}
{"design_id": "118b3a0fd82a", "module_name": "NV_NVDLA_CDP_DP_cvtout", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtout.v", "sha256": "66d049b6a344b07b369d6c40283bb6cc98892e14cda22b951e28566d44cdd5f9"}}
{"design_id": "11b12137b75f", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adaq8092_fmc/zed/system_top.v", "sha256": "e14224f058629f8a3887b46f8a534e5dbf4649a42569d701d31f0aeb396e2eef"}}
{"design_id": "11b968f32346", "module_name": "pcie_us_axil_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_axil_master.v", "sha256": "8c38c63c02c2fae91b80b00e7a0d5c7d5133fdb06d25c8b60ed98c708d749ab4"}}
{"design_id": "11da7f61ed07", "module_name": "NV_NVDLA_CDP_RDMA_REG_single", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v", "sha256": "f6cd0b9475c684da045bdf15713c3481b535d4db6b4340ab47a0c28bd0d73347"}}
{"design_id": "11ef00a56115", "module_name": "oh_aoi222", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_aoi222.v", "sha256": "5514629e33bb7a90a9c3286e84b2986aaa081866f1a316e3766acc0bc1015c0a"}}
{"design_id": "120c66c54946", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/read_verilog8.v", "sha256": "bbbb737feb03b0b8f82a70e2e679a09e19a18b3d0d10851ddc9157bdbfbdd664"}}
{"design_id": "1224630dcbdd", "module_name": "axi_dacfifo_address_buffer", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v", "sha256": "f977e78b1dee2e5282be84c5dd1a163c1c4722bb310499ce05e9f43bb5027f3b"}}
{"design_id": "1224e51890d5", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU118/fpga_axi/rtl/fpga.v", "sha256": "d2a8c8707bf4de4e8e1bee435e887621109c2a164af321de5f29f9d263f7b3a3"}}
{"design_id": "126e5594138e", "module_name": "up_xfer_cntrl", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_xfer_cntrl.v", "sha256": "9ebf24d576075d0c4bf5122ef2cb66301257d642de2822505694e11a6d7766f5"}}
{"design_id": "127b22da5ce1", "module_name": "IDELAYE2_FINEDELAY", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IDELAYE2_FINEDELAY.v", "sha256": "9038678b64cbae5923cf1616ccf84a8be0abaa9ff3405600bdac21708c8e3edf"}}
{"design_id": "128a46ccbea7", "module_name": "pcie_us_axis_rc_demux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_axis_rc_demux.v", "sha256": "fbb616656003efb1602ce7948d67cd8a688fdc7bc7d20ec1c19198231188d10a"}}
{"design_id": "1290d1b9f418", "module_name": "clk_mux2", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/common.v", "sha256": "f5b756f1df083aec2a48e1e59ce0f8e9e1ce53ec500bce7133948294df741857"}}
{"design_id": "12c5bdb59cdd", "module_name": "ssio_ddr_out_diff", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ssio_ddr_out_diff.v", "sha256": "53d0476c7446111feb4e3ad637feb7e20dd61785d924262b2c4284c101ec5f4f"}}
{"design_id": "12cd2d0298bf", "module_name": "fec_rot_13", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_13.v", "sha256": "0d263ef175fc5b706a44a48d7764458c0830f19d13b5fce9780183632e1a3021"}}
{"design_id": "1308e9248e57", "module_name": "axi_dmac_response_manager", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/axi_dmac_response_manager.v", "sha256": "905c017bda0811dfa6ce07a97cd5f442ed1d22c6548c926d8f48d16fff4b2c76"}}
{"design_id": "13387ef99e69", "module_name": "ct_f_spsram_512x7", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_512x7.v", "sha256": "a217460a72fbe1e105fa49977dfdddccff4b2d4b492e5e3c058d727891dbe527"}}
{"design_id": "134e532001e2", "module_name": "axis_mux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_mux.v", "sha256": "599c47b8889b6f22a325b3bb27a38b13b64a7ba08b0f4aefea1e2f550389e68a"}}
{"design_id": "1377996dfa95", "module_name": "cpu_imem_test_tb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/impl/mem_icg_test/cpu_imem_test_tb.v", "sha256": "a18df4c2c4ceb4fe4ed879346ce013b3f035b4bff2f493da7c0f46530761b111"}}
{"design_id": "139d488499e7", "module_name": "test_eth_mac_10g_32", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_eth_mac_10g_32.v", "sha256": "03215ba6299d1f6b182cc315f93f5bd45834d3fd85d6f9e7f37d02f7980a5b7f"}}
{"design_id": "13a6eba745be", "module_name": "ad_dds_2", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_dds_2.v", "sha256": "5a03f04d6c1db8d319ebab4e7b843d9c9f17b5224287d76353723450f17cb136"}}
{"design_id": "13b364adc26a", "module_name": "true_dual_port_ram_single_clock", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "dual_port_single_port_ram_templates/Verilog/true_dual_port_ram_single_clock.v", "sha256": "bac05be80ab9cb83ec51ce4dbb49d8bb3e33313346fa67956c0dce9fec5c56f3"}}
{"design_id": "14037e5207ed", "module_name": "dma_ram_demux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_ram_demux.v", "sha256": "32950ea2cdbfdfab35bbd6a741754150505fc8aaf84086144c6fd1c2c0923f7b"}}
{"design_id": "140bb36a2188", "module_name": "ct_rtu_expand_32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_expand_32.v", "sha256": "4467b90f7b447790649fa18b44b6f9425a0f6eca990e2220e2482a7dd636c27e"}}
{"design_id": "141527aff076", "module_name": "up_clock_mon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_clock_mon.v", "sha256": "58f4715e1f35009c4b60bc39e8969d8444614d33613682a534a87eba0a259fe2"}}
{"design_id": "1417029371dd", "module_name": "compressor_42", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/common/rtl/compressor_42.v", "sha256": "ca352a7bae4e31134c17846410ea000c61e86ab9ea246f2cf8f11205c4829c7d"}}
{"design_id": "149a5d77bdec", "module_name": "lis3dh_stub", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "rtl/lib/spi/lis3dh_stub.v", "sha256": "ef26f9f38c0d254a8c444acdcbf60d404f43f1f9670c012b4788cd48467b03fd"}}
{"design_id": "14ae43e82779", "module_name": "mtx", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "mio/hdl/mtx.v", "sha256": "9534b9ae269682cc48f5c1041ddbd4c2a8a243d10c417ec62af411e62984dcc5"}}
{"design_id": "14b9ee7c3f2f", "module_name": "RAMPDP_64X116_GL_M1_D2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMPDP_64X116_GL_M1_D2.v", "sha256": "43316937ffdf8f4480f306ce6a4e46b3a9ef0f13a87ddbb82820d86907f0e00e"}}
{"design_id": "14c6b34b0df2", "module_name": "ternary_add", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/video/ternary_add.v", "sha256": "e287c6de9a38c3a43151a81b69cd8361d25381aea9a8c61fa9a94ceafe98f2a8"}}
{"design_id": "14fb611c73f1", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/AU200/fpga/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "1506ddfd80f6", "module_name": "axi_cdma", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_cdma.v", "sha256": "5fef148a3d21ede1f6e43eb7eac8b5a1a7cbb68a8ab76a2bd569a35d6e56c8e2"}}
{"design_id": "15212b1b7c04", "module_name": "oh_buf", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_buf.v", "sha256": "d2a7e5125e0a11c0efb7eca395053642848a45431381fed8b3fafbf76a49c155"}}
{"design_id": "15332cde9b53", "module_name": "xor6", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/xor6.v", "sha256": "54cb668183e4519ab50993195977fafcb6302554e2b8b41c2e2ff5294a41aad6"}}
{"design_id": "158d4c2c2def", "module_name": "test_axis_fifo_adapter_8_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_fifo_adapter_8_64.v", "sha256": "c71008046228cc2e1227665df6f0e031696cf22a177398c7772585a57c1dc68e"}}
{"design_id": "15c451b55681", "module_name": "ad_addsub", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_addsub.v", "sha256": "fb6c8a3c7122bd5e9c784f7a4b79f942dbb619ccd4c1335b20fd2c6a083aea4f"}}
{"design_id": "15d96b1ea9be", "module_name": "PGAOPV_AN2D2PO4", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/PGAOPV_AN2D2PO4.v", "sha256": "045102f4179fb57d8ffa3e95d0c08acffc9126ee4976f2b3cb7a1777343cfe87"}}
{"design_id": "15e6bfb4fff3", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9001_dual/zcu102/system_top.v", "sha256": "ea424896abfa899e5cfe9ac7ed232ba5633140cc015d904613d170f55040ae36"}}
{"design_id": "1657553f5cd2", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/pulsar_lvds_adc/zed/system_top_ad7960.v", "sha256": "16d6d78df8f4849e715d8b427cb783868133aed9421144cd2481b5a9baaa3ea8"}}
{"design_id": "1678add7a98b", "module_name": "desc_op_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/desc_op_mux.v", "sha256": "54409b42fdb36c075d0570307febcfbccf7e0126501434f0c0fdb0b12806677a"}}
{"design_id": "167f3b23f918", "module_name": "ahb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/ahb/ahb.v", "sha256": "08cbe30f6bc92cf2e13f6bb7d72955b82b2580a5cf3401e212b8af2a721d8e23"}}
{"design_id": "169fb11d5768", "module_name": "eth_phy_10g_tx_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_phy_10g_tx_if.v", "sha256": "eb7b22ac57abbc4ee887ac945ac66507aeda06417c7dd188cd8e7a5e713f3ac4"}}
{"design_id": "16b51fd2a225", "module_name": "bus_mux", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/muxing/bus_mux.v", "sha256": "b6487cc1733b7afa5f4ff95524ed683786d2b93448636f25e41cda158512bda0"}}
{"design_id": "1736d946a12c", "module_name": "si5341_i2c_init", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG9200/fpga_25g/pll/si5341_i2c_init.v", "sha256": "b786d5d6f5fa051ce15a46b3dbea5ca1a2cf4745a2ba154718518fcd9069df1b"}}
{"design_id": "17502091e6e5", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/cn0540/de10nano/system_top.v", "sha256": "f89317d77e89dcbc05b2ee125ffb6d0e83ce01cb0d08f242a646bf9b4ece154f"}}
{"design_id": "17859d9f279b", "module_name": "test_axi_dma_rd_32_32", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "tb/test_axi_dma_rd_32_32.v", "sha256": "be7ffe3e6fae4bb3fd17bd8c16f417fe02e4c5966056580cbafdfc05d6d14740"}}
{"design_id": "17a5b4f77930", "module_name": "pcie_ptile_if", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_ptile_if.v", "sha256": "8cec3e6e9188f3b849447ff9d4af703f9af9bd0d74ec0454951ea0187aaf41f6"}}
{"design_id": "17c44abd61c9", "module_name": "lane_tx_crc", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/lane_tx_crc.v", "sha256": "402fd8e5ec7379eedc339c57e0f65cecc9dbaf838d2a4c9105d7a3cb3e7068fe"}}
{"design_id": "17ccf1cf6422", "module_name": "oh_pll", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_pll.v", "sha256": "e3e98632ced52cef0e329e55a1dcf917b6653fff05978d3d29a3a5c53d0294b3"}}
{"design_id": "17d193c3a326", "module_name": "IOBUF", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IOBUF.v", "sha256": "61362079f172ea377d703d788b574c5ec1994208458c9b1a730fc56449ddea7e"}}
{"design_id": "17d8b39c2d72", "module_name": "test_fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.v", "sha256": "d42e878a1a61264bc9a6609003d24f702111b367aa57fe4198fda464b1c3ef92"}}
{"design_id": "17fbc6c18664", "module_name": "ct_ifu_ind_btb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_ind_btb.v", "sha256": "e5c3a74232500bb0ea8ad0594d265bfe2858b6875ac4075325f38159e8e65ca6"}}
{"design_id": "1831630bb6b5", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "etrace/dv/dut_etrace.v", "sha256": "514b1f5b7a6345893dd5724a5b06ab712afa0438d7e8560f1dc46d4e490e35f6"}}
{"design_id": "18362df34176", "module_name": "pipeline_add", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/pipeline_add.v", "sha256": "2fae134e809bcbb160c0ecaf120844fcb18e3c39f5652f4e3c07f45c0e0d885e"}}
{"design_id": "1886870c9b0b", "module_name": "mlab_fifo_cells", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/mlab_fifo_cells.v", "sha256": "9dbe69aa3a79db18f2ac779e937d2fd5903a10bf44f955700c5cc0a5ac8ef28a"}}
{"design_id": "18ae2f080c52", "module_name": "stats_dma_if_axi", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/stats_dma_if_axi.v", "sha256": "9eae46a8a18d24082d3767b5edcef420aeca8cb8f6e350b2c40f6ed48625fb81"}}
{"design_id": "18b2d4c315c6", "module_name": "ad_mux", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_mux.v", "sha256": "3b43fce9683ed30b08091a405a80d4cfa937f758298c03ae1f8e9d105c7e4e10"}}
{"design_id": "18c2e17996b5", "module_name": "pcie_ptile_if_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_ptile_if_rx.v", "sha256": "f303f9cd079acf0dc9e8039b704d41e0d7648c2bfd928f3af3f4bcffc16647dd"}}
{"design_id": "18daea2df37b", "module_name": "axis_xgmii_tx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_xgmii_tx_64.v", "sha256": "097750af9f48497c3c5743c37e743eef22a314de139c2088756346c167915f7b"}}
{"design_id": "1947f4b74892", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ZCU102/fpga/rtl/eth_xcvr_phy_wrapper.v", "sha256": "33014523748633b9139714f5b08dd3f3547a95968d734af9fed5b47dd1778f15"}}
{"design_id": "194c71b8fc94", "module_name": "axi_ad9739a", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9739a/axi_ad9739a.v", "sha256": "fb2313f61671a2eefb6884d226460fafe0ae1d8d53c6c862bab1809769429c2d"}}
{"design_id": "197f42d715f3", "module_name": "ct_spsram_512x54", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_512x54.v", "sha256": "fd5e92b68e567ea1bea5e48e97b6f1c4994504f06fc24d6d2e24485ac2b5fa4b"}}
{"design_id": "19af72a7f473", "module_name": "axis_frame_len", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_frame_len.v", "sha256": "6862690f1f4f0ca8b5416caba90f4fe7523d8616c7405ba581df1e63e96ac9c9"}}
{"design_id": "19b8ce8b5477", "module_name": "axis_pipeline_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_pipeline_fifo.v", "sha256": "a7cdccbf905c3f95d4a626fe77d84879a09c3f472dffc5ea2eb7acc9ba113c02"}}
{"design_id": "19bf48040916", "module_name": "oh_pads_gpio", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "padring/rtl/oh_pads_gpio.v", "sha256": "53f5082db7be9f1517901c9afee105a04893d9f74f9f6d236d732fa740563232"}}
{"design_id": "19c954a35548", "module_name": "axi_laser_driver", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_laser_driver/axi_laser_driver.v", "sha256": "5bda7ffa4fdbbb334dd4fdf6b44579a47178407ee827b6fafdaf9d42752bfde1"}}
{"design_id": "19f2bf2f6b4f", "module_name": "mdio_master", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/VCU118/fpga_25g/rtl/mdio_master.v", "sha256": "63308070f3c1f13bb298f0e971ee5ff9fd161fe4070b5eddd85278f6dd043da3"}}
{"design_id": "1a08e836c99d", "module_name": "axi_ad9963_rx_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9963/axi_ad9963_rx_pnmon.v", "sha256": "6b272f38bb2563db4eae4dd891c8ceda5c1aacae9a5cfcda32490f07e1bd4467"}}
{"design_id": "1a24981f7506", "module_name": "udp_demux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_demux.v", "sha256": "c734f329ed67f289d98832855eb5182f7d863653a8aac13b56a76eee59e5e0d8"}}
{"design_id": "1a3a3f114325", "module_name": "uart_hw_test", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/uart_hw_test.v", "sha256": "139ff2fcfddc751fc4330a27744c05fb35b45eb7c8e3f911bb8e1ffb407a666e"}}
{"design_id": "1a5634cba419", "module_name": "led_sreg_driver", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/fb2CG/fpga_25g/rtl/led_sreg_driver.v", "sha256": "91ef35971991fd2b536d1ccb263e892441e9fa0d631e8a14d3db896238f3cb34"}}
{"design_id": "1a5bb8d0ee31", "module_name": "pcie_ptile_fc_counter", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_ptile_fc_counter.v", "sha256": "83c705df7fcfd78bae79258829e05a49ed2e0362434fc544541e673ed66e0ec4"}}
{"design_id": "1a647783066d", "module_name": "test_eth_mac_1g_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_eth_mac_1g_fifo.v", "sha256": "30e973561cb800ede505b4d228534248c53c8abcb7d4a7d0e54693767a513426"}}
{"design_id": "1a98ac48031f", "module_name": "mask_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/translation/mask_tb.v", "sha256": "e72c83168056841a6421855b202aa55687b2688d3521d51e2944bc6ff3d46056"}}
{"design_id": "1aa574ade9d0", "module_name": "uart6_ml605", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "KCPSM6_Release9_30Sept14/UART_and_PicoTerm/ML605_design/uart6_ml605.v", "sha256": "7f88c5be571ecb070ead8cc91939ac98b044620e6300d886e0b71282ecf11897"}}
{"design_id": "1b01805dc63a", "module_name": "sirv_pwm8", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_pwm8.v", "sha256": "4908a7dc4484a739264a456a9d431cd6a9ade2382aeedad935972850d2596a68"}}
{"design_id": "1b16f25f6029", "module_name": "NV_CLK_gate_power", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/NV_CLK_gate_power.v", "sha256": "a70ff151f1b40c75816b3aff24447140988453a48fc8f751c1c06a72a915c66c"}}
{"design_id": "1b26e108b416", "module_name": "ct_iu_div_srt_radix16", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_div_srt_radix16.v", "sha256": "9bd2402ba7738d29b8728d7bcd1681523ae005017da7eb476863ad2d3d79f56c"}}
{"design_id": "1b5b5178ac13", "module_name": "si5324_i2c_init", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v", "sha256": "fbac639a0bef00982bd199470edb63b398123302aa66923a2b9049eff1680875"}}
{"design_id": "1b6023ba3112", "module_name": "mqnic_ptp", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_ptp.v", "sha256": "121d751e9bd0ddb882b73b008fb785f1bc514847fbaeb7c5fc7a889561a041ed"}}
{"design_id": "1b9045e4485c", "module_name": "e203_irq_sync", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/core/e203_irq_sync.v", "sha256": "ddaa59031209a12134c4254f389872a23446258f23282356ae0d97f387ecc2f9"}}
{"design_id": "1b9fce2edc71", "module_name": "oh_clockdiv", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_clockdiv.v", "sha256": "808eb5e6fb37037be76b78c58c8e08cb0c41b7aee23dec9aab4d3abf7393c69f"}}
{"design_id": "1bc1308a2359", "module_name": "pcie_us_axil_master", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_axil_master.v", "sha256": "8c38c63c02c2fae91b80b00e7a0d5c7d5133fdb06d25c8b60ed98c708d749ab4"}}
{"design_id": "1bc76dd20246", "module_name": "oh_bitreverse", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_bitreverse.v", "sha256": "879fda36f0bcec07eb61ae51f92845a95cefef7fe836ffcb394c7c7e62ee51cf"}}
{"design_id": "1c1362bc04c0", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG9200/fpga_25g/rtl/eth_xcvr_phy_wrapper.v", "sha256": "a4c9c65250507cf5fda79689130865404998ec4373958a6091d83516931a6ebf"}}
{"design_id": "1c29cf1c3d84", "module_name": "dma_ram_demux_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_ram_demux_rd.v", "sha256": "41ffae6d95c4781848cb9f392ce419770de78446ac506b6fcaf1ce7fc1627fc7"}}
{"design_id": "1c2fb1863904", "module_name": "udp_checksum_gen_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_checksum_gen_64.v", "sha256": "c28f8aeebfe34c74ef753f45478d64dfbaf615d0d854d61f75d0d112ca8995f0"}}
{"design_id": "1c48d550cadb", "module_name": "place_sort", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dft/test/place_sort_sky130.v", "sha256": "e761e77c979d3a3c2672ddaf4da67ff5a9d4fc536d5778d603895903152c8bff"}}
{"design_id": "1c4e4ab13567", "module_name": "oh_oai22", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oai22.v", "sha256": "015ae43aef00813dd3de25e3ba36c8b1665d2ccd843a07abb27142a3415d0a76"}}
{"design_id": "1c6b0241566e", "module_name": "fec_rot_22", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_22.v", "sha256": "bcafa2b5f7bc9b9b5c4cace3a2369353ec69fba1c8d63bd96fa61defa3e11b93"}}
{"design_id": "1c82e53b03a7", "module_name": "dma_client_axis_source", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_client_axis_source.v", "sha256": "e2dc4b2ab3ed88e2d6256e3ebcb7470fe0b11249a1616bbd1746460399ba5044"}}
{"design_id": "1c880cd46be5", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_wrapper.v", "sha256": "a4c9c65250507cf5fda79689130865404998ec4373958a6091d83516931a6ebf"}}
{"design_id": "1c980eab02f3", "module_name": "axi_ltc235x", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ltc235x/axi_ltc235x.v", "sha256": "f90140bf6a4516ab93b8cb3bcdceb9873c6e98fc248f5425543d62806e96f9ee"}}
{"design_id": "1cbfa1c86fe0", "module_name": "test_pcie_us_axi_master_256", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axi_master_256.v", "sha256": "b0487837e8a67071ecfe6856dd8f0d142afab35d3280368a54ec2339081d1d62"}}
{"design_id": "1cc7c27c4ebe", "module_name": "fixed_to_float", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/fixed_to_float.v", "sha256": "a23b02714b5915f3af8db8abf56aada2afcbae024473c626073b8a1461546e2d"}}
{"design_id": "1cc8ea46101e", "module_name": "oh_ao211", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_ao211.v", "sha256": "8411e7e5e401a89cacb2f8567b84bea356ca57598415018aa5a4e7c781739360"}}
{"design_id": "1cd6d03ede0e", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "1cf8b142bce9", "module_name": "mac_ctrl_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/mac_ctrl_rx.v", "sha256": "b5c0eda334c078518adb5fb7db324ae966ebddba0031bc91cedd32b831137fb1"}}
{"design_id": "1d0eb6f0a995", "module_name": "ct_spsram_512x7", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_512x7.v", "sha256": "29cfc1289a9e8af6f26389cc59ea9d7531741f632039af33ee501b0e4209ca23"}}
{"design_id": "1d1913634169", "module_name": "queue_manager", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/queue_manager.v", "sha256": "c940b75bcb3f811fa0bbf6b5831b75881c3d2ad80417920ac8073e242e4d5e3e"}}
{"design_id": "1d381277d3d8", "module_name": "flag_array", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/flag_array.v", "sha256": "2067367231c1ea20ba42858d6a6256cd61bd22db91b2f6e9761d325dc3e09591"}}
{"design_id": "1d3dc0e3a8ba", "module_name": "oh_fall2pulse", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_fall2pulse.v", "sha256": "0ac8d12b6de82810ddf886678d0245717fc371e1c8f9ad652a18e7ff30160b53"}}
{"design_id": "1d4314962506", "module_name": "axi_ltc235x_lvds", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ltc235x/axi_ltc235x_lvds.v", "sha256": "a7343a3eb0bb5ddb88056968e38177064c2976b218634b59749baf219270e126"}}
{"design_id": "1dfa6f14c5bc", "module_name": "UINT16_TO_FP17_mgc_in_wire_wait_v1", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/HLS_uint16_to_fp17.v", "sha256": "063de8c0b936a9058307d5de6cb9e41da5b5c050bab6f1feee44d94388b7c9cf"}}
{"design_id": "1e08adf0cfe0", "module_name": "ct_vfalu_top_pipe6", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_vfalu_top_pipe6.v", "sha256": "9531fe6d819a98bd31b792fcf8fef42f0fd19fd49225937ebadd7c2b2c070590"}}
{"design_id": "1e0cdc1e929a", "module_name": "nv_ram_rws_256x3", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rws_256x3.v", "sha256": "4bec2b85bd72335a62239f5227cb99a112b86bf5d4938a879058206fb4429e94"}}
{"design_id": "1e26503ff576", "module_name": "sync", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/pmu/sync.v", "sha256": "cf525125485591f64da85b5f754373906eaef908fe4d87355b3ed2188b1f37e4"}}
{"design_id": "1e2c0f79df5c", "module_name": "avl_adxcvr_octet_swap", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v", "sha256": "98cc0604cce9d06dc45c2a3994549fa7b2d932390d47f99b0acaa9adf1936fd1"}}
{"design_id": "1e312d1fcfee", "module_name": "OBUFT", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/OBUFT.v", "sha256": "e569da97e6d2b8d7ffe3923d88033251bfc297d41da0ae457b908783a6a9f00f"}}
{"design_id": "1e39f9528b98", "module_name": "test_axis_xgmii_rx_32", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_axis_xgmii_rx_32.v", "sha256": "356b4e87f1cd17613d7211ba88b957a39b3a5aada863240d50bfa103b62144e2"}}
{"design_id": "1e3e016b2ef8", "module_name": "ct_rtu_pst_ereg_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_pst_ereg_entry.v", "sha256": "63a003f801b5d2e9ef09f89d8078c74c847218ce9debe4f56c394244ebaafcfc"}}
{"design_id": "1e4083e72377", "module_name": "test_pcie_us_axil_master_128", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axil_master_128.v", "sha256": "112a1e856af0fd2cf48e6592539851d1d6a751e0f30c7684f457294d74c83e4d"}}
{"design_id": "1e4bd9944660", "module_name": "oh_padring", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "padring/rtl/oh_padring.v", "sha256": "4d028f5598589953484535f0ae2dca239d6b413116d4f6af007e6f43a31377c5"}}
{"design_id": "1e4d2ca5d194", "module_name": "crc16_dat8", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc16_dat8.v", "sha256": "37248791e4c931cd2d3d4285e446bf06f3211fd5e3a2b991d3003beedec54995"}}
{"design_id": "1e5090cf2adc", "module_name": "simple_dual_port_ram_single_clock", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "dual_port_single_port_ram_templates/Verilog/simple_dual_port_ram_single_clock.v", "sha256": "106adf1624a1a0b0a4cac6944d078910ab6b8d5088dd7ba7d48ec266cc3f716d"}}
{"design_id": "1e6897f9781a", "module_name": "addsub", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/addsub.v", "sha256": "1cf7cc2c422863dccffd1db6ffdd1fade96565c76d970e08531623ece5233551"}}
{"design_id": "1e9b60541929", "module_name": "ssio_sdr_out_diff", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ssio_sdr_out_diff.v", "sha256": "40ffaeee4189b900d59186b6d88ea7ecf49db7cfebb962a8ae1d6538154c44ee"}}
{"design_id": "1eb0e9f1e289", "module_name": "esaxi", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "axi/hdl/esaxi.v", "sha256": "2958f91c2e4644851b7051f9b94def939a08bab8c5499cf91f4b1bb88763d51f"}}
{"design_id": "1eb844ccf823", "module_name": "axis_crosspoint", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_crosspoint.v", "sha256": "4d34473a887a571e860c226fac3afc9252728f92c383df6b73e9a3e3e067ef39"}}
{"design_id": "1ecb47d9dee5", "module_name": "axi_adapter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_adapter.v", "sha256": "38f7a2ca6396fc95bcc74050b0298c8682dbd4b0a7b0b095b90d980ca73f7e9e"}}
{"design_id": "1ef091131aac", "module_name": "memops", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/memops.v", "sha256": "b2d0f99a20263acc860d91c835f05df6ad0b2713a4a03ac1acb96da47946ed61"}}
{"design_id": "1f29cd237b12", "module_name": "servant_pf_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_pf_clock_gen.v", "sha256": "7964acf1d07122c85bdf7ff495a654f1a03b67410a5f528ffed20ca0a928e6f6"}}
{"design_id": "1f459c4f2a1d", "module_name": "axi_adcfifo_dma", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_adcfifo/axi_adcfifo_dma.v", "sha256": "221e72d641949f32ea968a832eb0ed3729845acf28e4df89797c8b0b263c01c5"}}
{"design_id": "1f6313fcfff9", "module_name": "eight_input_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/aes/sub_bytes.v", "sha256": "14b2d7a8efe74b7b4fcaec8eb8b165f41d24fac2988500f3b0c27ffb08be0a19"}}
{"design_id": "1f750bb00178", "module_name": "ct_spsram_256x59", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_256x59.v", "sha256": "1768f384b9508f2e5aa22aa6485f6f9dc642131bc121ea45bbc14f13b61497ae"}}
{"design_id": "2039613d8f2b", "module_name": "pcie_tlp_fifo_mux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_tlp_fifo_mux.v", "sha256": "509ae597705cf3ee22447edd7176b1ad6c34a3d49d95a4994ad37dae50161ee9"}}
{"design_id": "204459408b5f", "module_name": "axis_gmii_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_gmii_rx.v", "sha256": "70d8e8c8ebfd22b8b1ffed7c077864c1944217a3e844f79cd3807cc41cf449d7"}}
{"design_id": "20473fb9110d", "module_name": "wbdblpriarb", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/ex/wbdblpriarb.v", "sha256": "c712a16ba8b9e4725bb9ffb9c9642359b0dda4b2c5bc2d1fa727c2ab0ef90561"}}
{"design_id": "206722600b68", "module_name": "ct_idu_id_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_id_ctrl.v", "sha256": "6c3960de956f05fab4cb2fd11203efa7e53a934bd8d579d87d1fce1d08ebb691"}}
{"design_id": "207241a566c0", "module_name": "test_axi_cdma_32_unaligned", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/tb/test_axi_cdma_32_unaligned.v", "sha256": "90908b0cde824c7b70970645e96bb17b61376bcb773b3a9d1ae964e935a92c2f"}}
{"design_id": "2088a9fd36b1", "module_name": "simple_quad", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/simple_quad.v", "sha256": "9e9b61b2ffd24c13dd525bc059718c91fc1be429f42cf3094345273a7bdf9c38"}}
{"design_id": "20a81facc728", "module_name": "led_sreg_driver", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/fb2CG/fpga/rtl/led_sreg_driver.v", "sha256": "91ef35971991fd2b536d1ccb263e892441e9fa0d631e8a14d3db896238f3cb34"}}
{"design_id": "20ac38b08f22", "module_name": "dual_spm", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/gpl/test/region01-dual_spm.v", "sha256": "b01849cd5361cce48a5f9fd0d63b99c9b472b652013fe546fe2e4fa239990985"}}
{"design_id": "20d439eb0549", "module_name": "asic_mux3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_mux3.v", "sha256": "01a8151e2f93353ce7bf09f286d5bfe6c79ef7d9fa0483751a424ecad916fc92"}}
{"design_id": "20eadc0566e5", "module_name": "test_axis_xgmii_tx_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_axis_xgmii_tx_64.v", "sha256": "ceb0b23534c3417a986588d12ff0966418d35264fd51c5ac3bbe408e3b965416"}}
{"design_id": "213ae14866fe", "module_name": "oh_isobuflo", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_isobuflo.v", "sha256": "fc4d10e8f14a8799a93da7ce1e24f78c1a46df2ab047cb83d8c6fbe607e6d0f9"}}
{"design_id": "21a059653fc8", "module_name": "eth_phy_10g_rx_ber_mon", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v", "sha256": "46587623ecfec35434b21cf97b98d5c619ee3d292ef16aa9b8c226c143b1fddd"}}
{"design_id": "22073fbddbb8", "module_name": "ct_fcnvt_stod_sh", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fcnvt_stod_sh.v", "sha256": "62397d9cc8d7c3431866537867d5f8ba769fb04f9047e1c409bfefa47763d345"}}
{"design_id": "220dd9ebfc3a", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/DE10_Agilex/fpga/rtl/fpga_core.v", "sha256": "d0822b05cf8a988f6d5f8ed300c3dc00f5d2161a603f1b6698c7ccadcbc6fc30"}}
{"design_id": "2231f7c1cc63", "module_name": "axis_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/AU280/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "223f9ac736d3", "module_name": "riscv_divider", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "core/riscv/riscv_divider.v", "sha256": "41e1a02fdfe635a8dd9c17c4c7dbf303e4c9c0d2f624e74aa8df06789b97d402"}}
{"design_id": "2250c98c4120", "module_name": "i3c_controller_unpack", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/i3c_controller/i3c_controller_host_interface/i3c_controller_unpack.v", "sha256": "2ac040e2654575491946eb9961e0f8c52bb99befb3984e849e55471a02a23d6f"}}
{"design_id": "225ab93d0763", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9081_fmca_ebz/s10soc/system_top.v", "sha256": "634dc2d98aac08e9b1a13d09d1566e63c70d64da083d2c545e48e0eb26688f1b"}}
{"design_id": "226fc91d0282", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/eliminate_dead_logic1.v", "sha256": "ccb5cfe59a03b369762612b1b2bb35cee2ac3dd65fb935666b5a0579b9d27096"}}
{"design_id": "22753c4e5784", "module_name": "util_adcfifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_adcfifo/util_adcfifo.v", "sha256": "5d0e5435bb0e26903c26de6835067cb8c596cd9bfb8ccb581ab7fabca2a8c3d9"}}
{"design_id": "22780a53fb0c", "module_name": "asc_to_7seg", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/translation/asc_to_7seg.v", "sha256": "71e2fb8eb551d159d4db42ecf638b81c49bbde5925c7d9dffcfaa92013d9283a"}}
{"design_id": "229f4a1d2e44", "module_name": "serv_alu", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_alu.v", "sha256": "2e0c31b5b992618e514083aacf10cb38c2229b68b3b1e93d6663104f32143332"}}
{"design_id": "22bc60f03a67", "module_name": "RAMDP_80X14_GL_M2_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_80X14_GL_M2_E2.v", "sha256": "fc085d0ea5c398f371fbb16c99982b85a7c2a9f9d9db1d4d20dc098390801b36"}}
{"design_id": "22dd3e15c0e8", "module_name": "fec_rot_28", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_28.v", "sha256": "59c41a4b3ccc0a06280a8fd40cb7166b9c9f3626190cc3d53a7a96c83de594f4"}}
{"design_id": "22f9f03baaa9", "module_name": "servant_upduino2", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_upduino2.v", "sha256": "f399f2a106c2caa0fe7e0b88973848a10656401f098f811514c35f7e27dc2c4c"}}
{"design_id": "23285dacc0eb", "module_name": "erx", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/erx.v", "sha256": "bb02570b31cf953a597c8dda78f0054561a1e26fe650a8cd0034b661c92f1f73"}}
{"design_id": "234983d5ccae", "module_name": "ct_ifu_addrgen", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_addrgen.v", "sha256": "4b61709654abd56494e65169ac93e81a10f8f1bca5a2662324ad50a91111c286"}}
{"design_id": "234fe0b36add", "module_name": "ct_idu_dep_reg_src2_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_dep_reg_src2_entry.v", "sha256": "c7cb5b8ef0f828b2f32162ebef44104b57ea6fca7f648524a9a7c88a3074acb7"}}
{"design_id": "235ca0959437", "module_name": "pcileech_com", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "CaptainDMA/100t484-1/src/pcileech_com.sv", "sha256": "bfd0f367d1192418df47301b7d71a8aae5a996821e12fe8b94a6638b44ef9630"}}
{"design_id": "235d2e26019d", "module_name": "sm", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/remove_buffers_hier1.v", "sha256": "465c69c5e2aeeaabf54585ae970e97ff54eaca482fa7f9e704bbe5d36af6d9fa"}}
{"design_id": "23800332b743", "module_name": "NV_DW_minmax", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/NV_DW_minmax.v", "sha256": "421c24e9f8d4f7052df2eef8183c936614ddc5665fce40d48a073bbd24305bf1"}}
{"design_id": "2399e5f95858", "module_name": "ct_spsram_512x96", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_512x96.v", "sha256": "f7e24af3f50ba4769de22e1e5af26d4fe2cf98a6d3fe48d4e468cc53c213df4a"}}
{"design_id": "23b91e48c178", "module_name": "NV_NVDLA_core_reset", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/car/NV_NVDLA_core_reset.v", "sha256": "c08c3a1612e9e82de0674a4be7f1542f46e208d62e2c9d6eff78dbc30c7ce1e3"}}
{"design_id": "240dcef0d22e", "module_name": "gray_to_bin", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/gray_to_bin.v", "sha256": "68182875093c56f762dec0730b98e98bc4f7c0f3c7d7de58c3b1727bbc5283d2"}}
{"design_id": "240effab4c74", "module_name": "eth_mux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mux.v", "sha256": "120ad9170c8847e989df626ead412261f4e637c717b3163a7478971cae7d323d"}}
{"design_id": "2422f1bc3f2e", "module_name": "axi_ad9434", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9434/axi_ad9434.v", "sha256": "88601bbbf5b5c272193065c9f579977e0746390244b398fe847c4f00484bb8b1"}}
{"design_id": "246d1efe08da", "module_name": "nv_ram_rwsp_80x14", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsp_80x14.v", "sha256": "6f9c25434af9576f1a1fc8d41082c2d5f0338c2a55d3ccaf6a0680fa3a3ef276"}}
{"design_id": "24a803de9a60", "module_name": "ct_spsram_256x52", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_256x52.v", "sha256": "c8d1a970b1982f3a7174de60d47fb68cc76ce346e6d9c440b5b4ed6f458b9e11"}}
{"design_id": "24ac2d29b8fa", "module_name": "oh_and2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_and2.v", "sha256": "dbffb963593a07acb1054f8dcb3e1b555f78128bab6ebedde0edfdf5957e9f45"}}
{"design_id": "2501f803c142", "module_name": "temp_sense_s5", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/temp_sense_s5.v", "sha256": "f5815de38f93ee913986788e80708069538e32f7f839deb7a8fb1206a4214a6f"}}
{"design_id": "250a9f4ed63f", "module_name": "spi_master_bb", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "rtl/lib/spi/spi_master_bb.v", "sha256": "499844e7410282b3445012319c0b26addb9e3085047be9355bea54926cd7dff8"}}
{"design_id": "25140d014e2c", "module_name": "NV_NVDLA_SDP_mrdma", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v", "sha256": "8307c6b45c4bf946d40483b9dbe2019c7a8413ac25ae1f233318020119d8f40d"}}
{"design_id": "2540348979b0", "module_name": "ls_sub_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/ls_sub_top.v", "sha256": "f697fd48cc388d8f154b2d821bd309025acf47bdaa3b8fd8e5196ce26adec2f7"}}
{"design_id": "254ecbfcc5bd", "module_name": "e203_soc_top", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/soc/e203_soc_top.v", "sha256": "a03744c1ba036948031c30939fa791226928bceb1981b02910aa71861f0b3001"}}
{"design_id": "25bf00e050c6", "module_name": "NV_NVDLA_CACC_assembly_buffer", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v", "sha256": "4797c877f63ae99f696b7c59daea7753964efcbc5dc7a9ded0bbed0a141f1448"}}
{"design_id": "25d605ed2080", "module_name": "sirv_clint", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_clint.v", "sha256": "1ab8186374487dd2fb91047f1b925fa54170f0f67dc2956ed2158cae864df606"}}
{"design_id": "25dd7d0d91a6", "module_name": "pcie_us_cfg", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_cfg.v", "sha256": "f5426615494cf74680ca744b589fdfd44847e4342b809f92298df9d5714e95bb"}}
{"design_id": "26206a9f32bd", "module_name": "pcileech_mux", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "ac701_ft601/src/pcileech_mux.sv", "sha256": "0c264ebf3ab163fbe122bc90ad03cb874809ac9f3e73048b563a768abbd5e63c"}}
{"design_id": "268e8cabeb1a", "module_name": "apb0_leaf_mux", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/apb0.v", "sha256": "b5ee495858be9989183ce2a5047e10c15267dc690bfd9820b58c96f3712cc145"}}
{"design_id": "26905a68f66c", "module_name": "ct_vfmau_lza_42", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfmau/rtl/ct_vfmau_lza_42.v", "sha256": "bd4bfc04c7e7e628615cd04b11784d455e8815a38390c8e6eb7906bd8c310107"}}
{"design_id": "2690982c1b24", "module_name": "i2c_master", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v", "sha256": "ec735fe59297c73dc165ca127cfd487ca19fe051f3dbecebd98e13589f77cd86"}}
{"design_id": "2692aca9d0f2", "module_name": "ad_g2b", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_g2b.v", "sha256": "4ce0833408423911b091131901ca6ae8e0800faaa8159089f92756fe27124a04"}}
{"design_id": "26b7909b936a", "module_name": "asic_rsync", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_rsync.v", "sha256": "514efb3d8d5add556ab877ef64cb67341a2350bfe4af733837fb05c80bf46adc"}}
{"design_id": "26b855f4d557", "module_name": "e203_subsys_gfcm", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/subsys/e203_subsys_gfcm.v", "sha256": "4ab432eabba1f038cdb52c6b42f2d62f5e17e0f17e4f7f3d8fb60c85f209c865"}}
{"design_id": "26c224c1ab91", "module_name": "NV_NVDLA_PDP_RDMA_REG_single", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v", "sha256": "a6abe11446881b956e1e0679a925e5bdd4625d4accb6a099590d16e753af5b7e"}}
{"design_id": "26d9c693d4a5", "module_name": "ct_f_spsram_256x54", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x54.v", "sha256": "589532c7d2141a41728c52d8501a7f91de6e65cae038a004343dbdee506e7138"}}
{"design_id": "26e0da182cb4", "module_name": "crc32c_dat64", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/crc32c_dat64.v", "sha256": "797355e6f804f0f6dedb393d8b9eb71aa5934da32a2ed479d2e22e30420c3c78"}}
{"design_id": "26e6823ca7c2", "module_name": "axi_dma_desc_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_dma_desc_mux.v", "sha256": "5ab36d7829d1b3ee3c56944b6299cc10eae6c3ed4394d027ce4f22baedee0537"}}
{"design_id": "26e75f978643", "module_name": "lfsr", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/random/lfsr.v", "sha256": "dceea48b2995afe0029fddb8f5d64377099067cb4e4b58a7a7f9a8113260309c"}}
{"design_id": "26f7215fe216", "module_name": "cntr_modulus", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/counter/cntr_modulus.v", "sha256": "bb4b41077980dae51026756a7ce12159e5656f8bf617ab99aa17595bd04a1fcb"}}
{"design_id": "272cee75ffd4", "module_name": "IOBUFDSE3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IOBUFDSE3.v", "sha256": "ed1f7f3d31d1ffe5fe4f81ba467e20b5f58633f70e892b69c5f7d67f2f5f00ad"}}
{"design_id": "27546da3b171", "module_name": "pcie_ptile_if_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_ptile_if_tx.v", "sha256": "49c4f3424ab1bd4c429e38e42eead52c9232d8375731aa816cfae84c79d3c360"}}
{"design_id": "278af3cb3ad4", "module_name": "arbiter", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/arbiter.v", "sha256": "a001507c82843e36e133dea75491fc044f56660fac0aff0127cf3afec7f927e0"}}
{"design_id": "2794495a5332", "module_name": "IOBUF_INTERMDISABLE", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IOBUF_INTERMDISABLE.v", "sha256": "1fbfe71cf8aaf7af2eb90debcfe4b21c3533c6c2bdbfb84e41b21d9c87f9178c"}}
{"design_id": "27d0c64ec0a1", "module_name": "axis_baser_rx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_baser_rx_64.v", "sha256": "38b4d6ec695420176906c71584dd40d741f4289121a970497f69e26945cafe5b"}}
{"design_id": "27d18834b5b6", "module_name": "asic_tielo", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_tielo.v", "sha256": "feae3ec3a4218b7b45cecf9fd22419b43c5f45b53688e6bfd54b920bf3cabbbe"}}
{"design_id": "27dee490b7de", "module_name": "serv_mem_if", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_mem_if.v", "sha256": "a4fbd74579447710ed43e81dd80b4ea9415da0a3425a447f29446f9bd7a9aa6f"}}
{"design_id": "27fe6c6a8890", "module_name": "ssio_sdr_out", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ssio_sdr_out.v", "sha256": "3eb5251c2cc1bdbf8d380e1954d5d8cdf107c3977541afe219e4a1034cc7eb80"}}
{"design_id": "2805ffa6801f", "module_name": "NV_NVDLA_SDP_ERDMA_gate", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_gate.v", "sha256": "76dfbf12df4df19944c9773fac89071fc591d5ae005684570edc72178a4428fa"}}
{"design_id": "281b00cb832a", "module_name": "fec_rot_n2112", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_n2112.v", "sha256": "1a49c6621efbb616d4c7111f713d7b9cf2aebe89e4eab932828029f656607a4d"}}
{"design_id": "2849128e3072", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9213_dual_ebz/s10soc/system_top.v", "sha256": "9a20736e6f518a23c312f037cf5721fefeed7fcf96b190ee20e9b3ecde1ab443"}}
{"design_id": "286552208b7d", "module_name": "axi_vfifo_raw_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_vfifo_raw_rd.v", "sha256": "3173828129ebb045f8127d5658469f7aef1bae58c065f8b3b3fffb86684901a5"}}
{"design_id": "28655ae2ef43", "module_name": "ct_hpcp_cnt", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_cnt.v", "sha256": "0d102d69ec82644ab801c1ae42a781e96d3989a8a631a951e038761efa2823d8"}}
{"design_id": "28794c78c00b", "module_name": "axil_reg_if_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_reg_if_wr.v", "sha256": "ec2f3d3d97b694dd4ff046d791fc7a0f95856c41049a107eac1aa3b3daab7412"}}
{"design_id": "2898b3b1535c", "module_name": "oh_aoi221", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_aoi221.v", "sha256": "b632b36bbf15ff44f4bc5569f1f427c2221850c38361d5aab06806dc85da7768"}}
{"design_id": "28aa749cba15", "module_name": "ct_lsu_st_wb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_st_wb.v", "sha256": "e25adf86323519e777af1b2e0e7fd1582c3d385b3e5b344f4d910ed13b9dc7fa"}}
{"design_id": "28fc57ea0cff", "module_name": "NV_DW02_tree", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/NV_DW02_tree.v", "sha256": "9c82f73fa7d7cfaed742a23b280b281bf2e1e965fa95600a0e9aa07f0f85a33e"}}
{"design_id": "2916737bcbba", "module_name": "sync2d_c_pp", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/sync2d_c_pp.v", "sha256": "b5bf6ac5ab888c9f48cbc57af066d818814553b6525c96648f4e19187fa55928"}}
{"design_id": "2938cfa9edbb", "module_name": "test_axis_eth_fcs_insert_64_pad", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_axis_eth_fcs_insert_64_pad.v", "sha256": "067c3c788ea6b3257686eeb2cef3af485bacfe3dc0c888ed245b1f92e8c08c57"}}
{"design_id": "2952d03ea886", "module_name": "stats_counter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/stats_counter.v", "sha256": "63f77dea123d1414482cd2ddb3942f6f55550824034f42b81d4875acd7a4b7bf"}}
{"design_id": "29663085172c", "module_name": "sigma_delta_dac", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/sigma_delta_dac.v", "sha256": "352d31dd185bce14d9d1e8a4999fbb5f2b5b2e42b048bdc9f4b828119cc5127a"}}
{"design_id": "297441510d5e", "module_name": "reset_control_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/synchronization/reset_control_tb.v", "sha256": "b3bcb26881d1a6c0d08a416e12b087f447285111f215e6d9589a202dfe4ac399"}}
{"design_id": "298b861eae39", "module_name": "gearbox_67_40", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_67_40.v", "sha256": "3286325e313bd903918c1c7c7b3b0a3ca9fa2a945a95fcb8535aa8f3c1afb3d6"}}
{"design_id": "29ee6db5caec", "module_name": "test_axi_fifo_delay", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "tb/test_axi_fifo_delay.v", "sha256": "095a2e5356040c63eeae5106bbbfbe806334a99097527d04865754e383cd023e"}}
{"design_id": "2a5c045ffc33", "module_name": "oh_sdffsq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_sdffsq.v", "sha256": "c591557b13fe2c05794744caa576d3df253647cf0e34394686d2ee61bf56ebd5"}}
{"design_id": "2a732e5992d8", "module_name": "ct_f_spsram_512x96", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_512x96.v", "sha256": "9e429716e8a4d830d988fd758954e2944233e827859e15a6340cb6964005aa9a"}}
{"design_id": "2ab6b65e53c3", "module_name": "example_core_pcie_s10", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/common/rtl/example_core_pcie_s10.v", "sha256": "33b88c3944c80cd49694e693f96552a2d7c48cba2f1033163944acb19d9c7c85"}}
{"design_id": "2abaef0de339", "module_name": "carry_and", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/compare/carry_and.v", "sha256": "bf344d6a40acc11309085ab7dee9c729a2b5895746ce94a1b66ff9310701c2f0"}}
{"design_id": "2ad23a96448d", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/cn0506/zcu102/system_top_rgmii.v", "sha256": "f60c3fdea9cf648512b4439d1dbb46a9dcc9071e281a05e2525edde31273d00f"}}
{"design_id": "2b35645881c3", "module_name": "axi_clkgen", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_clkgen/axi_clkgen.v", "sha256": "6b3b2a5c6cdeb993390be9b7367e8a20e53c51d88b4c391d68985392e94f0b5f"}}
{"design_id": "2b4d44c0689a", "module_name": "ptp_td_leaf", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ptp_td_leaf.v", "sha256": "aef2c2e2a1d6eedf49e81618025974f288e08d7f9dfe7bc8dbb4d9c1e6283d95"}}
{"design_id": "2b4dcc525f26", "module_name": "apb_gpio", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_gpio/apb_gpio.v", "sha256": "c2515b9d72d8f5c8c29a2c3e7b35dd880a81751f4c333871371ac95f881f2294"}}
{"design_id": "2b5e63036029", "module_name": "darksimv", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "sim/darksimv.v", "sha256": "031b1a8de4029ea09baa3229e77af9772abe3136d7d68fd5c2e7cf52a03f54ba"}}
{"design_id": "2b654dbd589a", "module_name": "asic_delay", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_delay.v", "sha256": "86b0709b875308d66c5411a6b1d194e8c5e4476c947e681ad8c76e78790ac121"}}
{"design_id": "2b714d1f4be1", "module_name": "sirv_spigpioport_1", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_spigpioport_1.v", "sha256": "d8f0f1d7db45e44cabaac4f61c15ecdb4f2cc12458867f7858ed24f33d7473eb"}}
{"design_id": "2bbbac85ef0d", "module_name": "arbiter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/arbiter.v", "sha256": "a001507c82843e36e133dea75491fc044f56660fac0aff0127cf3afec7f927e0"}}
{"design_id": "2bcc65535087", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9009/s10soc/system_top.v", "sha256": "e53ac612ea50f80df8f63347d315da2c211db6d6bbc493c419a418e8cc235ac2"}}
{"design_id": "2c0f184603ba", "module_name": "asic_dffq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dffq.v", "sha256": "8670bc47aa570c818b1f4cf54d52cf27f96ac6ac9dd8265262b0b1f0f3449a1d"}}
{"design_id": "2c1055d88e88", "module_name": "NV_NVDLA_CVIF_READ_IG_cvt", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_CVIF_READ_IG_cvt.v", "sha256": "1e3b83d55140d44a0aeca2b27c2cc29d71c93b50bdb3e0872ea0859c141afe12"}}
{"design_id": "2c42f036b5d6", "module_name": "axi_dmac_reset_manager", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/axi_dmac_reset_manager.v", "sha256": "0531706c60e6754a6460366dc4506b63292fea61dcff5ddbb038ff44938d6916"}}
{"design_id": "2c7142641e96", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/Arty/fpga/rtl/fpga_core.v", "sha256": "42dcbad35bff012fe1aa97d66234ccfb19f5e8afeb4bb12bbbcfc5296375fea0"}}
{"design_id": "2c73096f1f97", "module_name": "oh_nor3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_nor3.v", "sha256": "c24a91ed460ee15b9fd36a3f71452185e1962ddc42c5c28812298a35a18c77f2"}}
{"design_id": "2cbd4acf0c2a", "module_name": "ct_rtu_encode_32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_encode_32.v", "sha256": "b50d7c9faf452630f6eec0cd0f7a51f27bacbaadb6da001f82c368bc92d89bbe"}}
{"design_id": "2cdce96d9bad", "module_name": "ct_biu_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_top.v", "sha256": "aa986b784f17514dc08e4c8c131d701e58026b5019646dfcbec0b748ebdfe29c"}}
{"design_id": "2ce82be80f39", "module_name": "udp_ip_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_ip_rx.v", "sha256": "bed1fb03cabe705b9757bfa17e262dfc739ccf48700e04c234ebc276a5f527c1"}}
{"design_id": "2d23a98befb5", "module_name": "ad_edge_detect", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_edge_detect.v", "sha256": "7b7d2cca032f82a9e62c49da166a71925e0580963713d9921f65550dc6b5dcce"}}
{"design_id": "2d30a7473338", "module_name": "gcd", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "test/gcd_nangate45.v", "sha256": "a7ac54960562b5bcc012efe899a059b4cc22fda89f64c36da7f14305e1d945f3"}}
{"design_id": "2d43e7d79fb7", "module_name": "asic_or3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_or3.v", "sha256": "d7ba95f6cb139fb548ad2d31a0d957f9b54f0824696d103702fff5aa160c2f30"}}
{"design_id": "2d56b739e903", "module_name": "emesh_decode", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emesh/hdl/emesh_decode.v", "sha256": "fca480503a165cbe155bb9207bef37e41c85507a20c461436079d4348faff614"}}
{"design_id": "2da7af0c0d86", "module_name": "ct_had_sm", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_sm.v", "sha256": "8e04c38b3727dd16acd6a55c20b688adc6dd16f408352fb9bc3e125f6a45a2ab"}}
{"design_id": "2da938e5142d", "module_name": "parallella_gpio", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "gpio/hdl/parallella_gpio.v", "sha256": "eb829c72da71605a580a0f9840240864ee90815e43325e0f6d0134bd0705211c"}}
{"design_id": "2de89f76fa89", "module_name": "adrv9009zu11eg_spi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9009zu11eg/common/adrv9009zu11eg_spi.v", "sha256": "c60d19662bd91ed774c5ca44beb5a6863137997a648f41ff7d86fe689a5970fe"}}
{"design_id": "2e0a9c8f1413", "module_name": "ct_fadd_scalar_dp", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fadd_scalar_dp.v", "sha256": "fd5aca22878a5a483e6d6826e1f0766d40c78a4a4512b22b5fbbd9d510882d04"}}
{"design_id": "2e1de44b22cf", "module_name": "ram_based_cam", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/ram_based_cam.v", "sha256": "43a677371d2e8235aac8fa3bb68da5078c851dba81cd66d3544264faffea4524"}}
{"design_id": "2e56963c9063", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/AU280/fpga_axi/rtl/fpga_core.v", "sha256": "ccee19624525052abd6679bc1645c1257285a12d6a1bc9b43dcfc4fd7dfd2d0e"}}
{"design_id": "2e9c233efa13", "module_name": "ct_had_io", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_io.v", "sha256": "6ec00c67a2ac0111b319484f97bb70a1b7ada62589271e4d1670bf27c133fc4c"}}
{"design_id": "2eadd2aa2b4a", "module_name": "pcie_tlp_fifo", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_tlp_fifo.v", "sha256": "7f08e45fac4ad71449164c1dffefba7cc4bb64d9cac67752970a076489e5256e"}}
{"design_id": "2ec5484f4630", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga/rtl/fpga.v", "sha256": "6a1f3f3c727e9c586868bd1e1f311726c8cfc07653ef691daedd5e60eb17c222"}}
{"design_id": "2eccdfe10a94", "module_name": "eth_mac_mii", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_mii.v", "sha256": "0de7c247c1d13b0069d969f4b0bbbf6377c5db380feff9eb87c99a0bd715daf7"}}
{"design_id": "2f077ff4fb94", "module_name": "udp", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp.v", "sha256": "750d3cf657463e28cab742eaf2309022840f3d00b45e3b668153b7fd63254cd7"}}
{"design_id": "2f2400857de2", "module_name": "testcase", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/make_port.v", "sha256": "c33efdcf9e95f00256e542f2e77e3b97e05201a9a40f5bd92fc790c387dd1f3a"}}
{"design_id": "2f27706bbe50", "module_name": "oh_oa221", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oa221.v", "sha256": "04202bb49a3890696f7d108958aacedfe869ed1b44d08ecc647e95f0e9683c3e"}}
{"design_id": "2f3094fcc47a", "module_name": "ct_idu_rf_pipe2_decd", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_rf_pipe2_decd.v", "sha256": "3816b89282e1050d4f99f8377a85357fdeaf4e504a979d10edf623982c7527da"}}
{"design_id": "2f44c08a6e22", "module_name": "axil_cdc", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_cdc.v", "sha256": "fbb8018e34b7173e9a8de97c9e70be092abbb9a581dc83ec037561f401d11edb"}}
{"design_id": "2f7cd78dcd0c", "module_name": "ct_fcnvt_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fcnvt_top.v", "sha256": "1931debe60a706ed0d3f8f8bcf137fc9e556bd8be8ec9ddd7859092652aef865"}}
{"design_id": "2f81ba658896", "module_name": "jtag_io", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/jtag_io.v", "sha256": "00e762dec8c293dfaed93bdd874207e658b14971e7c5bf4abf94bbe764393f5b"}}
{"design_id": "2f8f50061532", "module_name": "xilinx_true_dual_port_read_first_2_clock_ram", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "dual_port_single_port_ram_templates/xilinx_true_dual_port_read_first_2_clock_ram.v", "sha256": "28c5a6fcd6caea99d3316ceca3f812e94ccca64cf4c8507f77b1d7ffe34354fc"}}
{"design_id": "2fcea52f0ec4", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "30083fddeb5d", "module_name": "IBUF_IBUFDISABLE", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IBUF_IBUFDISABLE.v", "sha256": "b84f6f5f0d2f7d4881dbcb8dc9539552e7978a1e82c3a36bf1111434212446fe"}}
{"design_id": "303533c0dd82", "module_name": "dma_ram_demux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_ram_demux.v", "sha256": "32950ea2cdbfdfab35bbd6a741754150505fc8aaf84086144c6fd1c2c0923f7b"}}
{"design_id": "3043a8d41254", "module_name": "axi_adc_trigger", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adc_trigger/axi_adc_trigger.v", "sha256": "5a05e0031f622888e52c50585f069ceb77c068f56df66b7596dc02aa66860462"}}
{"design_id": "305aa8898e32", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/cut/test/simple_and_gate_extract.v", "sha256": "c8051223f3a3a19d2d3a51863ec76941c386da83fb0c22f6403b955b12ff383c"}}
{"design_id": "308186eb7732", "module_name": "ad_dds_1", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_dds_1.v", "sha256": "79998d370aba911f2f3c5aa797772b1219c256ddc512ddd8d8ffe3c18857d497"}}
{"design_id": "30937bba98a4", "module_name": "axis_gmii_tx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_gmii_tx.v", "sha256": "6803d245a1482269f234f84d00739a23ecdeb4ca06340570454ad78f98550229"}}
{"design_id": "30cd597c9d7b", "module_name": "axi_crossbar", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_crossbar.v", "sha256": "f2e5177a8c8bbe4ed844554eece7abd207365a8a7a20796e0654e08362b51b3d"}}
{"design_id": "30d536bddab9", "module_name": "oh_mux9", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mux9.v", "sha256": "8ae2daf72b43979629878b193f0ea6b6a8e405a37d36bb1048de79436fa2e026"}}
{"design_id": "30ecb4e79629", "module_name": "ct_fadd_close_s1_d", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fadd_close_s1_d.v", "sha256": "c1e951d7cff0021ae2aafc9ff12ac34521704de0c20b08cb893ba45171afa110"}}
{"design_id": "30ee38bffe8f", "module_name": "chain_delay_rand", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/random/chain_delay_rand.v", "sha256": "b6591a2103aa020c9f0da2e895ba320fc5936e221a761b87bde95b17348a73ff"}}
{"design_id": "30f04f473f48", "module_name": "gmii_phy_if", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/gmii_phy_if.v", "sha256": "9da180f3c5e7036c8cdc81a157315789c409cbf7c63f672ad3fec37ac966afc3"}}
{"design_id": "310f723aebce", "module_name": "ct_spsram_8192x32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_8192x32.v", "sha256": "69afea0afe6258350d603c7c5f9a3445ebc1877c6c25d2ea2c62f148e0ab0c4d"}}
{"design_id": "311237dde33f", "module_name": "asic_dmux3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dmux3.v", "sha256": "03c56cb0ed95677f7c0a6029b57cfffd7584179417d7c34dfea8dc3bc0135ff3"}}
{"design_id": "3126eb9d02db", "module_name": "riscv_exec", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "core/riscv/riscv_exec.v", "sha256": "bf8ef962bcfbdc250b53562e842d0c42aad53a14b4ea33830fbf5490b0a85536"}}
{"design_id": "312df4c8056b", "module_name": "dcache_core_tag_ram", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_cache_axi/src_v/dcache_core_tag_ram.v", "sha256": "a0bbfaba8f336eb9c46181b530c3f3826c17c0df73a438ef7db15092d23257a4"}}
{"design_id": "312f9c585153", "module_name": "icache_tag_ram", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_cache_axi/src_v/icache_tag_ram.v", "sha256": "bd0d5fbdbd2e30bd637074bb0a4747294bf03652427b2c95ed8f1d0507f5aa85"}}
{"design_id": "312ffb97aee0", "module_name": "clk_divider", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "verif/synth_tb/clk_divider.v", "sha256": "ba6b88c6f10485da2542323aae44df0bac0879ca28dcda7f3bcd7a7eb50d6da9"}}
{"design_id": "31422015a566", "module_name": "int_test", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/int_test.v", "sha256": "9b47efdd19057b42d68b747a173420026a2344ca84f39b10190a1b22a956aa6b"}}
{"design_id": "3161f170f52b", "module_name": "ct_hpcp_adder_sel", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_adder_sel.v", "sha256": "b87fae62644e1e98ed00a286121d09e75c37211a9830e7bc707a61fcbb939c42"}}
{"design_id": "3179a7699e7b", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/DE10_Agilex/fpga/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "31a640bab4d5", "module_name": "test_pcie_us_axi_master_128", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axi_master_128.v", "sha256": "36d8c2869bcd3b0651945d4834adf1965319c001219acaf923f52303057d4b96"}}
{"design_id": "31aa250b1685", "module_name": "ct_f_spsram_1024x59", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_1024x59.v", "sha256": "fb343486eb94b7c1c05c748eb0c2236498741273db94e007821ed2070f9a672c"}}
{"design_id": "31b6d5ba0adf", "module_name": "axis_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "31d560688780", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/RV901T/fpga/rtl/fpga.v", "sha256": "fc71a44c191c0dca25fdec1547ef0598e30ec54f458b71c51d218259a4f4b258"}}
{"design_id": "322fb4579020", "module_name": "asic_clkbuf", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clkbuf.v", "sha256": "d20ccf86e53578f3b654ff595732b8f3059ff6e78e1b4d510a64fc5d68f4451e"}}
{"design_id": "3237582c5ee9", "module_name": "ct_spsram_2048x32_split", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_2048x32_split.v", "sha256": "3597ff3058e8bde9afa0bb6044c1a0822994ed0841f58c441151a5a230ac389c"}}
{"design_id": "323b9709488f", "module_name": "NV_NVDLA_CDP_DP_mul", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v", "sha256": "ebc4377439d876979e0dabdb4195c4fd62a537c77dc5582e2f476a4d75118a0d"}}
{"design_id": "325df844c0c3", "module_name": "oh_mux8", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mux8.v", "sha256": "a2e0761119cd6598670c835617ab61e12752bec80c377b13bf6bb663c69591d1"}}
{"design_id": "327634abce30", "module_name": "i2c_master", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/HTG9200/fpga_25g/rtl/i2c_master.v", "sha256": "ec735fe59297c73dc165ca127cfd487ca19fe051f3dbecebd98e13589f77cd86"}}
{"design_id": "328e1745b429", "module_name": "dma_client_axis_sink", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_client_axis_sink.v", "sha256": "a1e03efa7a8810a967b1e4a6b68fc75b0cbfc6f6a2ac137b9aa7321001029dd5"}}
{"design_id": "32a2b5f92d2e", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/HTG640/fpga/rtl/fpga.v", "sha256": "7c95f5b3c52f4ce0be5c5e40817ec56fe74af785e696199175a68f6a52e50c14"}}
{"design_id": "32b43003b090", "module_name": "dcache_core_data_ram", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_cache_axi/src_v/dcache_core_data_ram.v", "sha256": "421b5cf828adb66e355ffda8e6223a5421d296f4ad206efd0ed0c611680d7a79"}}
{"design_id": "330610e8f022", "module_name": "dblfetch", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/dblfetch.v", "sha256": "442309a5d22405c396dad26e5b1b1d74d038b3f009d6c2a81abd1bae7f5fa153"}}
{"design_id": "3359888ef8fc", "module_name": "oh_and4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_and4.v", "sha256": "222b5438b2d945d0484d1723fdacc480e0b931c10759466960037b75c4fe1dc5"}}
{"design_id": "335e43475c94", "module_name": "axi_ad9361_lvds_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/intel/axi_ad9361_lvds_if.v", "sha256": "a03ebba8458e8a8f367d1f2060f628738c9bc3f43ceab977398251246e455b63"}}
{"design_id": "336e091264e8", "module_name": "test_axis_tap", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_tap.v", "sha256": "0bc80288f20464db30145cfc1b709912d1bdb11a904624eca3cb598c5fd5520d"}}
{"design_id": "33d5e2e13ec0", "module_name": "ct_f_spsram_4096x32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_4096x32.v", "sha256": "89b1da8d8420dfe5593a4f55bc84887d41eff090a473ab642e39f6721f277d9b"}}
{"design_id": "345f596fa4a9", "module_name": "asic_oa211", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oa211.v", "sha256": "15d363555bb8d9bc871e9ac04510b3eca6117b2f31300e8bd1f23be5479c88d1"}}
{"design_id": "34658c5c776c", "module_name": "servile_mux", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servile/servile_mux.v", "sha256": "38ca38dade5805eb5f4ea9d20c9d2003ddb44926a4e17b2708067c152385fa17"}}
{"design_id": "3486db9f78c0", "module_name": "nv_ram_rws_16x256", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rws_16x256.v", "sha256": "eecb43caa7d5daf725054087ce331c18116d958d56583bbce89a4a34befafebe"}}
{"design_id": "34c7854d0890", "module_name": "axis_arb_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/axis_arb_mux.v", "sha256": "04b4e5a8838c94a7d5752c7d4270330a3241ee4fd160642cba27cfad4c1094a5"}}
{"design_id": "34d6750ee978", "module_name": "XORCY", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/XORCY.v", "sha256": "6b9d23c770c5303173e302332857b33ae0c880368d08bc4d0067a0dcbe57343e"}}
{"design_id": "34de09e03cd7", "module_name": "eth_mac_phy_10g_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_phy_10g_rx.v", "sha256": "1abe51cf3937c7dd7edfd3dc03d3500e25973458bcb00028518fd3ebb47a1d53"}}
{"design_id": "34f8551f1208", "module_name": "ptp_ts_extract", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ptp_ts_extract.v", "sha256": "6373a8982dae454eb6b3275a007901ac6d658c10c1976848f751348008c8abaa"}}
{"design_id": "3508dfe0b1b6", "module_name": "ct_lsu_vb_sdb_data_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_vb_sdb_data_entry.v", "sha256": "8b8be3a663c23ff022bdcb9b2f609a9309847fdcd847f4a1d67200b7f0f311da"}}
{"design_id": "350c0bc70769", "module_name": "i2s", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/i2s.v", "sha256": "927d2aea6797fb837f383e5e8a3259609e132ed24883127240ab21601f467efa"}}
{"design_id": "35229439ce1f", "module_name": "oh_dffrqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_dffrqn.v", "sha256": "783b829af476bad8ed4949cff108d5fe7aaa8675137e5114ebae959e1c6eaccc"}}
{"design_id": "356589f9e67f", "module_name": "csky_apb_1tox_matrix", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/plic/rtl/csky_apb_1tox_matrix.v", "sha256": "6dbf8b4f07214f179e4e1d92d5d6239e6a6a582378de6f9a515254fd92145229"}}
{"design_id": "356d4eb9b918", "module_name": "ecc_16bit_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ecc/ecc_16bit_tb.v", "sha256": "11843ebd4711ddccbd069206813a70da532fb641d25a1bafa6d00a80ac54fae5"}}
{"design_id": "356fafd22ca2", "module_name": "FP16_TO_FP17_mgc_in_wire_wait_v1", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/HLS_fp16_to_fp17.v", "sha256": "8754276ed4e4afeff4fba22291c0bfd1d81c58bf01979d5b8a39bc80024637d7"}}
{"design_id": "35b44013cd11", "module_name": "pcie_tlp_demux_bar", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_tlp_demux_bar.v", "sha256": "4d3e0499692c627875729d08e8c4c60e60500a78e1885e10acd7afb611c46cd3"}}
{"design_id": "35bb990a3127", "module_name": "ct_rst_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rst/rtl/ct_rst_top.v", "sha256": "ba3bfae1f22f7a639890ecc81aa36a075fc00a9eb93cc28fdd698e2381286ad4"}}
{"design_id": "35bd3ec8a770", "module_name": "hex_display", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/DE2-115/fpga/rtl/hex_display.v", "sha256": "ea22655727a677b17d5fa73929ef535aca235915a18d69e9091dd31b98efec1c"}}
{"design_id": "35c7d9ba5834", "module_name": "NV_NVDLA_SDP_BRDMA_gate", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_gate.v", "sha256": "b66b89bd127f0c8c36abb52cc97ee23dfe1b88446fbe87c56bfb3d09be752275"}}
{"design_id": "3607471805ab", "module_name": "NV_NVDLA_RUBIK_rf_ctrl", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_ctrl.v", "sha256": "b8f920e9c04e4cb520ca4cfeac54c946c4a64fd8cda9f709125e46789ddf8803"}}
{"design_id": "360d94359a06", "module_name": "asic_or4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_or4.v", "sha256": "ff39f4bb1e1c35a239431a5cd6dece6fddfdbd41437ad5e4e1201be1bdf89cc8"}}
{"design_id": "3610bc313647", "module_name": "ct_spsram_1024x59", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_1024x59.v", "sha256": "af06ff33f915e8ab4e3d4284bee5fe9fc99ffeb8b584c9beeb0800151c4f9770"}}
{"design_id": "3628bba1e2be", "module_name": "oh_mxi4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mxi4.v", "sha256": "0909f6632a9934b1fc112e28ccf380e78ad42bfce132fa724c9273fdfd0ee656"}}
{"design_id": "3667e5fd08a4", "module_name": "axi_ad9265", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9265/axi_ad9265.v", "sha256": "cb8c6d666b9fc34cd5b63f4408d2762dd740fb04fa38499e98e3223da794c1f0"}}
{"design_id": "366bdaf53b2d", "module_name": "sync_event", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_cdc/sync_event.v", "sha256": "da21cc018ba5b8caae72a36490ec06813d131d3f725d59a08b6a4fd2ae0c99dd"}}
{"design_id": "3672e3e536a9", "module_name": "ct_idu_id_decd_special", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_id_decd_special.v", "sha256": "27f371a2fa49d25c1a69355ba58e9b4059ad37d560b9fddf7ebb00c85c575cb8"}}
{"design_id": "3686dbb8f6da", "module_name": "axi_ad9671", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9671/axi_ad9671.v", "sha256": "754cb470f9be16835c7b753eb88dc6c37face9ffad3a7acfe7b719b7d1c74d75"}}
{"design_id": "36947280d64b", "module_name": "SDFQD1", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/SDFQD1.v", "sha256": "516bfb250faabc5496fd015278836e4eab7c93a798b180f8083aea76ccd6fb60"}}
{"design_id": "36b8180b5e67", "module_name": "ct_mmu_arb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_arb.v", "sha256": "20df29580c68baa1086605e6397997f3c3e556062dcb06e0f22c852c19d4471b"}}
{"design_id": "36ca94b8c37f", "module_name": "arbiter", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arbitration/arbiter.v", "sha256": "2ea1fd375cbc0ff56014e0cf41a2b81a644d4293c5bf0499bb44d394af9980a8"}}
{"design_id": "36d5a5c7f909", "module_name": "emesh_pack", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emesh/hdl/emesh_pack.v", "sha256": "0d19d394f6d3920a0f84c906788cf800109ffe271e18dc2819c7d3e48b6a1fbd"}}
{"design_id": "371797df2c55", "module_name": "ct_fadd_onehot_sel_h", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fadd_onehot_sel_h.v", "sha256": "26520dea3730a66417df754393c895f5f5781dec87f260c3e6d4021dbad592e4"}}
{"design_id": "3754fb81cf6d", "module_name": "i2c_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/DE5-Net/fpga/rtl/i2c_master.v", "sha256": "ff46775d79e00853c9008f668ae9dfb71ad2cb93d6fec783aa08e527f207efb4"}}
{"design_id": "375665b9158a", "module_name": "fpga_tb_top", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "fpga/fpga_tb_top/fpga_tb_top.v", "sha256": "d6f0bbd2bfa1de8d08f4d9c9f845a5ac2b633e2c3ea8594f0bd10843404e23a9"}}
{"design_id": "379e45693b42", "module_name": "ct_biu_snoop_channel", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_snoop_channel.v", "sha256": "7b6710fcb797477de6bc9f0883b4d59290696f762d84765611ade3bf6dbc124b"}}
{"design_id": "37aaec7ab6eb", "module_name": "fp_format_cvt", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/fp_format_cvt.v", "sha256": "9e4a9d30e5bd25c7c7da1a20aa83856178c7f6f301adb406b1dd0120175e1911"}}
{"design_id": "37ac71f31737", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9081_fmca_ebz_x_band/zcu102/system_top.v", "sha256": "8fff2a6bcfd717b5721aaeddac0eff2da0863e13ccd845c6fb055cbc50a78ae8"}}
{"design_id": "37b17d3f0a0a", "module_name": "gcd", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/gpl/test/design/nangate45/gcd/gcd.v", "sha256": "8c258dc444b20b8a4e6ae86dbe488bc741d957691a03cd7ac9c4a86297f17116"}}
{"design_id": "37bece1754ac", "module_name": "memory_nangate45", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rmp/test/memory_nangate45.v", "sha256": "3be1aac70b9752c93fac84693cac6cb01f90989ecd7c57b4ea8f769e21154969"}}
{"design_id": "37d6755ff153", "module_name": "axi_vfifo_raw_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_vfifo_raw_rd.v", "sha256": "3173828129ebb045f8127d5658469f7aef1bae58c065f8b3b3fffb86684901a5"}}
{"design_id": "37db0125a04e", "module_name": "NV_NVDLA_MCIF_write", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_MCIF_write.v", "sha256": "d74d865529a2a1fed47c8f62299694db3dcad42c60860ba8de5c01e5193f0a9a"}}
{"design_id": "37f7cfc2e443", "module_name": "ct_l2c_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_l2c_top.v", "sha256": "ea5d6c834c1c686740755fbbe1348885e5a376730c7088c83c9d485adf83f7b9"}}
{"design_id": "3830c4875b92", "module_name": "double_addsub", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/video/double_addsub.v", "sha256": "b422ac05d9d2be6604b2b2319e7c6f9fa6d2380e49c10fdc1e252dedd292e95f"}}
{"design_id": "385d26abefad", "module_name": "ct_rtu_rob_expt", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_rob_expt.v", "sha256": "9ff6c0f9387d15a8bd95a830c1b624e890f2da8c6b97c1ebacf0b6c03838122d"}}
{"design_id": "38710c688c8e", "module_name": "axilops", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/axilops.v", "sha256": "283dfb0ff7599e8a4087ab2853d1baae8b4cbd79af4fd2fbfe3dedb4108010a0"}}
{"design_id": "3893557105c5", "module_name": "BUFR", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/BUFR.v", "sha256": "868efda87889722c239b4fb4fb0a72cc2a7944bddf0900e48934a8d94fa2d8c1"}}
{"design_id": "38c3c53066b5", "module_name": "sum_of_64", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/sum_of_64.v", "sha256": "ee591b00dd1f9ac25753b1f5797fc12abf9ee4b8e55d733b6f778957c04689a6"}}
{"design_id": "38d1b10a5623", "module_name": "ct_rtu_encode_96", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_encode_96.v", "sha256": "93b710e31372d1d51d2dd50092eab6baf5ac281fd88c9db585aca73ce40520d7"}}
{"design_id": "38e3b96494a5", "module_name": "ct_f_spsram_256x7", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x7.v", "sha256": "3f0c24b5f57508e50ed5351aa57ba5de4003fad9c50d78e75b2a37c4b3845797"}}
{"design_id": "39142e196c92", "module_name": "pcileech_top", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "sp605_ft601/pcileech_top.v", "sha256": "9f9f3b2b683ed966d54dabbf624c62a4402b46ddc196a8040cb2ce9326ad4d33"}}
{"design_id": "391958776d2f", "module_name": "bin_to_asc_hex", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/bin_to_asc_hex.v", "sha256": "cca22eefdd72fd1c43ec48dc8759b0ad4bfcbeca2b40fcda45058b4f97019886"}}
{"design_id": "39208bf35fd6", "module_name": "enc_64_67", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/enc_64_67.v", "sha256": "a7f3f982c0bfdc89142bf76909e28d52c47da8a49f190dca35b1d023c2dc4ad7"}}
{"design_id": "396913f69746", "module_name": "axi_logic_analyzer", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_logic_analyzer/axi_logic_analyzer.v", "sha256": "e3db2ba6b7d8e37184365cbdcea627c46b5af970e06aefcd6e26d86a2f02d7aa"}}
{"design_id": "399b733284e7", "module_name": "mac_pause_ctrl_tx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/mac_pause_ctrl_tx.v", "sha256": "c5de52ceae4cf7c048262132191b1e4c366deca15d931e4703f6a05eff789c5a"}}
{"design_id": "39aaf0d85ef4", "module_name": "ct_rtu_expand_8", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_expand_8.v", "sha256": "4ce9e12bcb4658ab96e101a1357918caff0a652f4090e952625cee2029d1c8d0"}}
{"design_id": "39aeb8ce05da", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "gpio/dv/dut_gpio.v", "sha256": "dd65fdc4a44627d8928bf0564f8882a085e40978b58f84eb9cd75ea46f88ea55"}}
{"design_id": "3a2d37d8b664", "module_name": "NV_NVDLA_GLB_fc", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/glb/NV_NVDLA_GLB_fc.v", "sha256": "700551c47b6638e5c65a1cf917d978ad58726e5b7a03c88c033736f83211603a"}}
{"design_id": "3a61ef14e2e3", "module_name": "ct_pmp_regs", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/pmp/rtl/ct_pmp_regs.v", "sha256": "949b11e9b02e216ddbd7212a5072cee5e4996886829931258a2330947d6e943e"}}
{"design_id": "3a78cd06f85f", "module_name": "xgmii_deinterleave", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/xgmii_deinterleave.v", "sha256": "5ab0de601da6ac2917a980b4ad30dbcda86a1cfc62dfd52bd891e9b654c44cea"}}
{"design_id": "3a7ca81701e3", "module_name": "pcileech_pcie", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "sp605_ft601/pcileech_pcie.v", "sha256": "d0455218ab15dffa574fa3b8c39bef602b316bbc88a0e68fa1b6bd213401859e"}}
{"design_id": "3ad2e4269853", "module_name": "axi_vfifo", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_vfifo.v", "sha256": "1fed2250a36b21275d22bd05eeb3ce6185c38bdfbb367c5fa862e374698bbee6"}}
{"design_id": "3b0d42c09d36", "module_name": "NV_NVDLA_RUBIK_single_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/rubik/NV_NVDLA_RUBIK_single_reg.v", "sha256": "773fe8ed893920ee79e366fb5ff5fe387fa2d641a88d4cbb80ff2094283d3075"}}
{"design_id": "3b175734b994", "module_name": "axilscope", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/axilscope.v", "sha256": "5bd5cb04bcfaef413b7b577f9098ba7bf8cd9bc8f011ff79b078cd455f83a04e"}}
{"design_id": "3b265ac5067a", "module_name": "asic_mux2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_mux2.v", "sha256": "7303a7344808038daa8dabc68ae8402ae937ff8d13d08447d54a7d59084bbb39"}}
{"design_id": "3b2fe0052b6e", "module_name": "tim7_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/tim7.v", "sha256": "c05aba5a2a659e207f9e92842c30c4db92075b1cb992a0be3da81e111a5681bb"}}
{"design_id": "3b31e7cc86bf", "module_name": "axi_ad9671_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9671/axi_ad9671_channel.v", "sha256": "986a26b00197903704938c790a3b94502f205adfc9d8b824a9b546ebe580c215"}}
{"design_id": "3b6efb28c917", "module_name": "ct_pmp_acc", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/pmp/rtl/ct_pmp_acc.v", "sha256": "fb11f016e1a1a982f842776ed8fd57cd16d8cb4fb1154cc50b3e1b454560737d"}}
{"design_id": "3b7f483af027", "module_name": "tcm_mem", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_tcm_axi/src_v/tcm_mem.v", "sha256": "960e745a4c9ff4c48b7114070d90c54cd415e6a4cc8ab12dffb6100ae4b15504"}}
{"design_id": "3ba8277332ac", "module_name": "uart_interrupt", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_uart/uart_interrupt.v", "sha256": "75298c2bfb4921cee757641927d55500a54f8604d808f59717834e8507045e60"}}
{"design_id": "3bcd608af25c", "module_name": "ct_idu_is_sdiq_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_is_sdiq_entry.v", "sha256": "e4a2b72c78058eef64b89d83cf18ebbf9927a2451753a0783a68f854df589fa8"}}
{"design_id": "3bd6dbb5020a", "module_name": "axil_adapter_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_adapter_rd.v", "sha256": "8d79906e62200be851fb4eead9f094b6598a728ad729c1fddfcdce8402506dfa"}}
{"design_id": "3bfb32f10371", "module_name": "ct_fspu_single", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fspu_single.v", "sha256": "41d3914ba097fc93358ef94f854ebe3af1cfc7d2d10e634d7aceecd84926d7ab"}}
{"design_id": "3c19c9f72930", "module_name": "fec_rot_8", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_8.v", "sha256": "bd6bee4b47a79a3a6d04ab42e5d4a86c1e63457db0bb9e26fa2b7b22484487d5"}}
{"design_id": "3c28370ac950", "module_name": "pcie_axi_dma_desc_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_axi_dma_desc_mux.v", "sha256": "5989b73aeb196e36cfa5f461d4a7be2a3772a487f30a26919ad6c7c681d41f6c"}}
{"design_id": "3c2b7f2b98f0", "module_name": "oh_dffqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_dffqn.v", "sha256": "af3e425cb52fee8e8d627cb50a466dc80eaba8e1ec1aa50a286629ee17206872"}}
{"design_id": "3c6549ef9d68", "module_name": "asic_clkinv", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clkinv.v", "sha256": "14c54cffc85a4043b125deb12aaeb88967c88d0f7053376acf3f0de2c9f685e0"}}
{"design_id": "3c78b58b65ac", "module_name": "cntr_updn", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/counter/cntr_updn.v", "sha256": "359be27c2a1f057a75d1f3715e5dfc1f6c2a826c67818dfb2d40330d86e753a9"}}
{"design_id": "3c87e1a14e05", "module_name": "eth_mac_1g_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_1g_fifo.v", "sha256": "a5cf2d9e28a4dc0193634c4530f33bf5c5e8536741c3a0e5b78e3f74219ad868"}}
{"design_id": "3c99226c56c1", "module_name": "pcileech_mux", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "EnigmaX1/src/pcileech_mux.sv", "sha256": "0c264ebf3ab163fbe122bc90ad03cb874809ac9f3e73048b563a768abbd5e63c"}}
{"design_id": "3ca0442733df", "module_name": "sirv_queue", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_queue.v", "sha256": "e2fef7b7e979d657d2d05edacc63570ddd1ce8e2a92b2ac7c4a2af173a298ac2"}}
{"design_id": "3cc0ede94f13", "module_name": "eth_mac_dual_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/eth_mac_dual_wrapper.v", "sha256": "d4b9d772cf254c0721701b8a9fc19850575f148fe4840c5a405bae136938057c"}}
{"design_id": "3cce8d788d58", "module_name": "ct_idu_ir_vrt", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_ir_vrt.v", "sha256": "f01c5dc796e3bbab0598aa98f987ea3e6356cb37d5b872a8503aee868eeb3aa3"}}
{"design_id": "3ce325d3a8d3", "module_name": "asic_aoi222", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_aoi222.v", "sha256": "6346decc4f2c6955a0d0446c0596d2946f036e589745f03f7433f5b172ff3909"}}
{"design_id": "3ce97c6d9424", "module_name": "testsub_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/testsub_rom.v", "sha256": "b773d30ebb888960cc078ddfeedb0dc2e235fc16600f8ae14ff2ee2bc4ae86c6"}}
{"design_id": "3cf9929d6cb8", "module_name": "ct_iu_special", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_special.v", "sha256": "95b34fd4cf45e6867f81a0516fa6d90dc58dad09150b6985bb3ebd17c6ef734e"}}
{"design_id": "3cffba97e995", "module_name": "test_pcie_us_axi_dma_wr_128", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.v", "sha256": "53d64da33b61a57e47602592a9c818285a97149024130fd5885a28ef51f00677"}}
{"design_id": "3d090c251291", "module_name": "ct_mmu_dutlb_huge_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_dutlb_huge_entry.v", "sha256": "580a6181487bf4a9e8222c324d8e9574924c45601f1ea64639e59593b504026e"}}
{"design_id": "3d34f0cdbe97", "module_name": "gearbox_20_22", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_20_22.v", "sha256": "509a8b3d894cb8d4b6071116bcac4c8955f5e9d6b9484b420b33120ada80df25"}}
{"design_id": "3d49323a2f83", "module_name": "remove_parity", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/remove_parity.v", "sha256": "04ed5d5f4b71d7f06a8e5b826844242a035b9ceee73ffd5ada3903f7a1fbc31e"}}
{"design_id": "3d532992a878", "module_name": "gearbox_20_67", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_20_67.v", "sha256": "9d04b93fb04d1a03125751ed800b988c0b406d512a8721b2d7ef4aa476248ae2"}}
{"design_id": "3d554c0eea75", "module_name": "NV_NVDLA_PDP_nan", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/NV_NVDLA_PDP_nan.v", "sha256": "23e4013fddd4ffdd4acae040f5c277874386205c7a9dcc3df9712ab656a1e289"}}
{"design_id": "3d75ae33883a", "module_name": "axi_adapter_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_adapter_wr.v", "sha256": "915b13883a1f13fd7b2c279186e5857778812802c52aea1580aacd804b82abe1"}}
{"design_id": "3d938a42d879", "module_name": "ct_had_ddc_dp", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_ddc_dp.v", "sha256": "9c8ed405be293087a0f2207a726cc0dc9a5a2d47d7e94f192214c1ed65e58478"}}
{"design_id": "3d9ad9f0b6c0", "module_name": "oh_aoi211", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_aoi211.v", "sha256": "5ad192134169db337c7b52d5619dd9393033cb93d822630d5ebb5546031fa67c"}}
{"design_id": "3db6fc83a56a", "module_name": "dma_if_pcie", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_if_pcie.v", "sha256": "5255c2291f3d431df000d88995c9ea29490634b194437d0ecf71e39bf124d8f3"}}
{"design_id": "3de5ad53e310", "module_name": "mqnic_tx_scheduler_block", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_tx_scheduler_block_rr.v", "sha256": "69a3eaaccd3cd228a5f56b864087f3600eddabfa289e7141565be1c7c077ef0c"}}
{"design_id": "3e2a2921d253", "module_name": "oh_ao221", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_ao221.v", "sha256": "d9305596f7a242ffaac819ec7b515db1ac1824a5223c63b68189e7cac3c2516e"}}
{"design_id": "3e2bae440c6c", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/AU250/fpga/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "3e744fef709c", "module_name": "axi_adxcvr", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/axi_adxcvr/axi_adxcvr.v", "sha256": "9b85ee43f4e48c4ac82ce659a8df3a50c696d745b808cda38645b258c2a1009a"}}
{"design_id": "3e811059f605", "module_name": "fpga", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/VCU108/fpga/rtl/fpga.v", "sha256": "95b6a8036ed89fc67a67b5236a02040cd020c54ee9bb95a4e26315db01a1a473"}}
{"design_id": "3e8e0477d117", "module_name": "p_SSYNC3DO", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/p_SSYNC3DO.v", "sha256": "557f76cadc8a1683d58a60648551783ff5ab58d8210adb8d62fe2db57370a881"}}
{"design_id": "3e94bab37661", "module_name": "ct_f_spsram_32768x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_32768x128.v", "sha256": "1ddbdb066a6feffe2221c814f971b3173844f5421e0dc25954eb4063c500407c"}}
{"design_id": "3ea0a85b2f3f", "module_name": "dma_if_desc_mux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_if_desc_mux.v", "sha256": "338312e054d42f66e36f28946e05b94646ed1d63a41e4e740f4d55cbe278e64b"}}
{"design_id": "3eab18faad5f", "module_name": "pcileech_ft601", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "pciescreamer/src/pcileech_ft601.sv", "sha256": "fc12a47719c98bf657072aae65710ba3fca3d3a2e276e0e611e861b6d165593d"}}
{"design_id": "3ef646c97514", "module_name": "system_timer_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/counter/system_timer_tb.v", "sha256": "ff9ad8b3b963eb27beb2b2367cd6414f19e7ca7fad663678fda5cbfdca38a3da"}}
{"design_id": "3ef705a966a4", "module_name": "axi_adrv9001", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/axi_adrv9001.v", "sha256": "a2c5001bf41ee5a3b3963519e863d88d5d7fb039eadc896690a9e9bfb37c9939"}}
{"design_id": "3f24d2663a12", "module_name": "ad_axis_inf_rx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_axis_inf_rx.v", "sha256": "c3e57c58cc22fcc314d48d98a3456de8e3a6d46acf6e2d4c37dda74202f02184"}}
{"design_id": "3f76ebfedef3", "module_name": "BUFIO", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/BUFIO.v", "sha256": "1d686682baa19a8d6ebfef420c3c2433043756bb61df92a9125dcca1c77017ba"}}
{"design_id": "3fba9b4b45f6", "module_name": "test_axi_interconnect_4x4", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/tb/test_axi_interconnect_4x4.v", "sha256": "c863c5bc9f9a1ce97ec54a5d339e9c5862e5bed16962d39a22e59ed8cd4ed2dc"}}
{"design_id": "3fdc84e1a063", "module_name": "oh_7seg_decode", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_7seg_decode.v", "sha256": "034f5d73879feeebd9a7cbd9e20a9b918aa8063129d13c756a4222a8a1701c49"}}
{"design_id": "4019b2166ca0", "module_name": "ct_had_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_ctrl.v", "sha256": "acb2d3bfd7e052a4eeca6f4f8a4b07638cc4ccb9bec31d4550e016250185c1b0"}}
{"design_id": "4020de2bf4df", "module_name": "test_axis_cobs_encode_zero_frame", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_cobs_encode_zero_frame.v", "sha256": "3d212d1f84cc4c64c1244b71e0278f0cc579cd73f8912a482847ef9aa5e8f335"}}
{"design_id": "4030f7a8f5fd", "module_name": "oh_xor2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_xor2.v", "sha256": "d3434982f64a255173f15ddb5f967fbb0f263996d0533c68458f925d64cf9098"}}
{"design_id": "406bb289c2ac", "module_name": "pcie_tlp_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_tlp_mux.v", "sha256": "73fb3855161b9c81801ee612152046791b9fee5a75b36f1919d5268c5138c340"}}
{"design_id": "407f20613008", "module_name": "encoder_8b10b", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/encoder_8b10b.v", "sha256": "6c2a7eaad56489ecbafe384cfd1e235a363f5a3a8001cee0d6f177e3fc24887b"}}
{"design_id": "40849d28674f", "module_name": "crc32_dat40", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat40.v", "sha256": "5f89f770abd2a84115f2e786abf72d830a934623d8d6af45f864cebe9ad84d0b"}}
{"design_id": "408697e99e0e", "module_name": "simple_dual_port_ram_dual_clock", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "dual_port_single_port_ram_templates/Verilog/simple_dual_port_ram_dual_clock.v", "sha256": "695f2ac9b5cfce0a61b82366701c34f62f5b5df4df92ce99042a44892e5c1338"}}
{"design_id": "40b618ec4e5c", "module_name": "erx_remap", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/erx_remap.v", "sha256": "157a85f5a314a6709cb7f58d3c202f4e0b3de18a7fb695a82cf3684b490d7594"}}
{"design_id": "40d08e0da0d5", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad_quadmxfe1_ebz/vcu118/system_top.v", "sha256": "c582175c550bbb849ad2dc29f68b04856805fbb4be92446ae15d9d9a902783fe"}}
{"design_id": "40db5f2f9c68", "module_name": "axi_axil_adapter_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_axil_adapter_rd.v", "sha256": "838caa3b52268f2c9c2778a30b899ebfa374ea5e11975681d613e37904d61cbe"}}
{"design_id": "40e911238939", "module_name": "axi_ad9467_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9467/axi_ad9467_channel.v", "sha256": "2e26bcfb5ee359610a34e93898d394800e38f3eb5f18bb5eca0f1a6d9300002c"}}
{"design_id": "41386311b2ee", "module_name": "test_axis_crosspoint_4x4", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_crosspoint_4x4.v", "sha256": "d230eb5d84341c62ddca9ff18df1c0c9bd84c30650559c920ff976682eec2340"}}
{"design_id": "413f2d24a0b9", "module_name": "oh_clockmux2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_clockmux2.v", "sha256": "ebf31aaf53953f19271f9ddbc83f40cc011f741ecf4800fb2c415c2297e57dc1"}}
{"design_id": "4146656e538d", "module_name": "service", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/service.v", "sha256": "e09203c0ea5646df41b86df8b3e5ea9291c8ffde661f5dd960394dbb14b2fccf"}}
{"design_id": "41491b129059", "module_name": "twelve_four_comp", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/twelve_four_comp.v", "sha256": "fcfd9aa201974676d7d287f8e6ad5ffa4cf963922bc01754fa3b201ac7d1982f"}}
{"design_id": "4182704597bf", "module_name": "ct_prio", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_prio.v", "sha256": "2cd7d0e3350c6e4e3df90953570ed95915d6b38e3398ede956df0be321eb6865"}}
{"design_id": "41865c7b2c88", "module_name": "axi_dp_ram", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_dp_ram.v", "sha256": "e7c5e853a1cac5a79e057ccbb8ea25f5335bfc5c061c95edf378d7f52ce4da43"}}
{"design_id": "41c2357e8209", "module_name": "ct_idu_dep_vreg_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_dep_vreg_entry.v", "sha256": "b21884fe841727b0250922300fdb56da7326d8813b44c86121f746100d22616c"}}
{"design_id": "41fd32722032", "module_name": "upack_tb", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_pack/tb/upack_tb.v", "sha256": "1f88feb59a6a0d9d78afed03be65f48550829adb3540462ae5c2775d498a0bbb"}}
{"design_id": "41fd645e13ef", "module_name": "less_than_const", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/compare/less_than_const.v", "sha256": "8f5bd486cfa775090ca3319ef385605aabfb714c7afd5ac28a522be22d26910e"}}
{"design_id": "420d91dcfdfa", "module_name": "ecc_encode_16bit", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ecc/ecc_matrix_16bit.v", "sha256": "33a114ec3759b79265c9fcdf947de3dbbcacbc562ee6c618be3b1c4d5602b297"}}
{"design_id": "42cf8b11ce8d", "module_name": "test_axi_crossbar_4x4", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "tb/test_axi_crossbar_4x4.v", "sha256": "49024fbb7a20a9f151288e112430145dc80bfc11ef26743fc4e2982dd1761609"}}
{"design_id": "42d5d446e046", "module_name": "oh_lat1", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_lat1.v", "sha256": "8fbbd594bd587fc3489a8888f4fcc40a8cfb6d0ff209a83a65e7dd0f0a9dfa49"}}
{"design_id": "42d818bf6dba", "module_name": "example_core_pcie", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/common/rtl/example_core_pcie.v", "sha256": "34e62561df75230ed56e05a3ce40b1c70f48f7d666967062cdf7f923c646c77b"}}
{"design_id": "42d9bc315311", "module_name": "bmc_spi", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/fb4CGg3/fpga_100g/rtl/bmc_spi.v", "sha256": "e5f068feec8a6d7c82d6fb977e7caf308811e311ea9e618ee701849e520754c5"}}
{"design_id": "430b20a23dcd", "module_name": "axi_adrv9001_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/axi_adrv9001_if.v", "sha256": "8936e4f643887f1622424e17c2c33cf804c9122916f5b02415d1a6165bb495a3"}}
{"design_id": "433c8158086e", "module_name": "pb3_int_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/pb3_int_rom.v", "sha256": "f52fdb30e0a5df97b3e6aadad2b8c6def818e18914a59320b89481d8f2b75a4f"}}
{"design_id": "433e982b3065", "module_name": "test_axi_dma_wr_32_32_unaligned", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "tb/test_axi_dma_wr_32_32_unaligned.v", "sha256": "dc7db7c005ab11cc6f80f6e7df1e05c1d932277ed9f04e94caabb3456374dffd"}}
{"design_id": "434637c8e9e1", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ZCU102/fpga/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "4369dc7c4645", "module_name": "skidbuffer", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/ex/skidbuffer.v", "sha256": "ae8b294b58c139f15aece4e4270b868aa21f690727c15a05e15bba2e83169635"}}
{"design_id": "437868e3cf23", "module_name": "eth_mac_phy_10g", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_phy_10g.v", "sha256": "e204853d1e23643e608f08d3084a5ae6064b617872119ec40a88949e00b4a1f8"}}
{"design_id": "43b37a15b11b", "module_name": "axi_vfifo_raw_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_vfifo_raw_wr.v", "sha256": "3d9161cd40ae9697bedf1af27de74d18b97b0321efd9da0a3e4ef7f2ce851ca3"}}
{"design_id": "43dd7b49ee2e", "module_name": "ad_data_out", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/common/ad_data_out.v", "sha256": "1ff65adb8fecb3e11a2b916fad69007571dff0d13e74a5a8a46c53a805738042"}}
{"design_id": "4404e03e676a", "module_name": "test_axis_rate_limit", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_rate_limit.v", "sha256": "3f8918ce45ac37ed047f4d94b334e378b61f5f697c7d2579ef99162b8bda5aa2"}}
{"design_id": "442a7202ef37", "module_name": "axis_xgmii_rx_32", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_xgmii_rx_32.v", "sha256": "4e8dca908de53671958b3c88ce2362ab844d0e3f34681c905ad192307e36c8ab"}}
{"design_id": "4437322f62c1", "module_name": "asic_sdffq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_sdffq.v", "sha256": "41e18f423c06be0e90565baf5bdf2ddcc98473a6b5478145ac3a864ca5299850"}}
{"design_id": "443f4c411c98", "module_name": "aou_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/aou_top.v", "sha256": "d74f9efde7e119ac6460946d273f13e88cf20b3135aba9ada6027748f0574ee0"}}
{"design_id": "4449d8c9f537", "module_name": "tim4_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/tim4.v", "sha256": "f4043175a345c7723c32e52b0896c8dc1d738879487cf6fb2a60be06ca34e7ef"}}
{"design_id": "4473384ce4ab", "module_name": "udp_checksum_gen", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_checksum_gen.v", "sha256": "95ad19792cb143b4250d8e65ad8dea9ac1be8a8d1fa61ca631c80b24d16719fa"}}
{"design_id": "4492e0513da1", "module_name": "ssio_sdr_in", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ssio_sdr_in.v", "sha256": "b71edd7c90d19ebe30850f20ef8e781d74e1233ab4b01bc613d652d853d88d2b"}}
{"design_id": "44980aceccd3", "module_name": "mqnic_interface_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_interface_rx.v", "sha256": "4d02c654c072cd06c39c1e03ebdb99ce3af88f779d0dc244f349a1581a7563e0"}}
{"design_id": "44cb39d9b26c", "module_name": "crc32_dat32", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat32.v", "sha256": "7ffa2a2d2b79754c6f6f07d9114f5be5543e838bacdb97873e392f2fe9ff2871"}}
{"design_id": "44fa80f75f6c", "module_name": "eth_mac_phy_10g_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_phy_10g_rx.v", "sha256": "be594605bdb2ecc67de0eaa1fabb38f8f81125e66cfff56626085d33acf0ad39"}}
{"design_id": "451063bcb183", "module_name": "bin_to_dec", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/translation/bin_to_dec.v", "sha256": "671070a340478cf6f069f65b3dffb180ab45caddf5b3b2f66c7b668a8bfdae30"}}
{"design_id": "45261ea5992b", "module_name": "apb_dummy_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/dummy.v", "sha256": "1ee877ade5ddcd4cbe211987135671483dd81ed39dbf89d235c5147c9966bc0f"}}
{"design_id": "4549aaf9b199", "module_name": "test_axi_adapter_32_16", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/tb/test_axi_adapter_32_16.v", "sha256": "beaa194d385d7d4c03d24d8a799f74b549afa86d20894d66a2657463fb2147dc"}}
{"design_id": "454bd7e0d21f", "module_name": "MUX2D4", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/MUX2D4.v", "sha256": "9b3dd689031fe84747d5a4845b2b202766928ba6fe0be1f829f1feb5718c4934"}}
{"design_id": "454dcd3f5397", "module_name": "ad_iobuf", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_iobuf.v", "sha256": "ab5899d451dd8f1690e6efa4a3161eb3f5b62cafa31fc685d6ead1b4cc254cea"}}
{"design_id": "458ecaa8ebdd", "module_name": "ct_fifo", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_fifo.v", "sha256": "59f387c64e92b25fa90abd549d7cae7fa1440d4927be080ea698e5e9aece3301"}}
{"design_id": "45a6c10cd97d", "module_name": "dv_top", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/testbench/dv_stimulus.v", "sha256": "e85b7a1eaa9edffbcf4620eb6f90dbe227c689ef16bd9aa293f9f9a5ec8b82ae"}}
{"design_id": "45b1a1328fa5", "module_name": "sirv_qspi_fifo", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_qspi_fifo.v", "sha256": "6f61e7ee3c1a86ffc6a43cae8b3e28ffdf5d4273981c265012f9469025246fc7"}}
{"design_id": "45b6924180e2", "module_name": "axi_adrv9001_rx_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/axi_adrv9001_rx_channel.v", "sha256": "3de17b149e08f44b9fea6bcf452e800d548e7f2d270fd298c497529276205355"}}
{"design_id": "45e48355f507", "module_name": "NV_NVDLA_CMAC_CORE_MAC_mul", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_MAC_mul.v", "sha256": "e3863ee66376dab62f7a07ec4cb86dc32084bc00999748cd65083342654394f6"}}
{"design_id": "45e4864a1c87", "module_name": "rtc0_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/rtc.v", "sha256": "f633b5f9e9781ea7d70139f5d37acdbea2d310054703d58a0e78376e35355340"}}
{"design_id": "45f3eade5ca1", "module_name": "mt48lc16m16a2_ctrl", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "rtl/lib/sdram/mt48lc16m16a2_ctrl.v", "sha256": "843b470e4b03c7d8e05f2084bf2aefea4d5f73af06d6f6089e8b3a2cf86b64fb"}}
{"design_id": "4634ecec2578", "module_name": "axis_cobs_decode", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_cobs_decode.v", "sha256": "5964e1b3a0820c2ab348e0f87793b4a18c08b55586a5c65d6a1c86d9602babf6"}}
{"design_id": "463e5bff0125", "module_name": "scale_up", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/scale_up.v", "sha256": "131f12b13e3f56898845c39bef54b0b2ca8f0c357040b58ba315eecca8b01689"}}
{"design_id": "465727a87cd1", "module_name": "gpio_apbif", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/gpio/gpio_apbif.v", "sha256": "30b196dec4f3f321c431cde60324f5fa43f5a020029962251263287169c03955"}}
{"design_id": "465edd309dbb", "module_name": "test_dma_if_pcie_us_rd_128", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_dma_if_pcie_us_rd_128.v", "sha256": "cae9c34a05f8446b613c49e863acd23bdc484498e8282956baf37a90e960bf70"}}
{"design_id": "4665220fe85d", "module_name": "RAMPDP_80X72_GL_M1_D2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMPDP_80X72_GL_M1_D2.v", "sha256": "2cce2daf31920ceba14f76788db306c8389d8a04ecf990548644d74dc90d62a4"}}
{"design_id": "46959f6fd427", "module_name": "rgmii_phy_if", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/rgmii_phy_if.v", "sha256": "3ca6c38f17934a1a305345db93536739e5a482f3283a9fa7498c1fa747e8539a"}}
{"design_id": "46c8706613c1", "module_name": "MUXCY", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/MUXCY.v", "sha256": "dc222df376b1eac4d187dc6fc8ea3ad7b7e8943c95a41ca6e19907946885998b"}}
{"design_id": "46cb263fa815", "module_name": "axi_write_slave", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/tb/axi_write_slave.v", "sha256": "af4cb3ecedc8430e7373e998b6294adb691721ab52235da6da637734366c765a"}}
{"design_id": "46f78c49f2ef", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/daq2/zcu102/system_top.v", "sha256": "665758d98d5780003504859607c1bc7e2c0833584ed88468445a7c4d8036e9fb"}}
{"design_id": "472daae875c7", "module_name": "servix_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servix_clock_gen.v", "sha256": "b326b1ee26f5534913a9ef5f9e501ff7b1546e1a8dec518f8a70753b76f0c9b7"}}
{"design_id": "473d1111d409", "module_name": "ct_ciu_snb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_snb.v", "sha256": "423b9d052056363ee0362716f9e07906d2fc563620402e4c1352c784ce7af88c"}}
{"design_id": "47587a88e5ae", "module_name": "clockgen", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/hierclock_gate.v", "sha256": "658d9b12358e78b28f15258adc2533747119d320e2431bc356f79aa9e62d8735"}}
{"design_id": "47903981b32c", "module_name": "pb3_ret_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/pb3_ret_rom.v", "sha256": "82ce5483a619d82c7ddb810d893c547abe36f865c1cd953ccf6f48b5d5fae215"}}
{"design_id": "47af43b7c461", "module_name": "gray_to_bin", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/translation/gray_to_bin.v", "sha256": "839c4e319796a335e236b3dcc0214865d03d6e12c41d55f92938bb3d12a5f798"}}
{"design_id": "47b426a7ab87", "module_name": "sirv_uarttx", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_uarttx.v", "sha256": "8fe7b4717f6852917c0718b91dd7a6b8dba2225ad43e8e749440953591c1ac49"}}
{"design_id": "47be882f509f", "module_name": "util_fir_dec", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_fir_dec/util_fir_dec.v", "sha256": "cd02c78d755a9d7875f9bf8d3f6747799de51e35425346aa7708def9676751e2"}}
{"design_id": "47e197d8e396", "module_name": "fc_ctrl_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/fc_ctrl_rom.v", "sha256": "6f8624c23012820486fdd663808a729de89171156d3c846509f57d7ee69d0333"}}
{"design_id": "47fdb6e867a5", "module_name": "mdc_mdio", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_gmii_to_rgmii/mdc_mdio.v", "sha256": "166cc349e1bf299302a428db6848de35f2d66b967b309470b463a5b5a47d9020"}}
{"design_id": "4821cb936918", "module_name": "axi_axil_adapter_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_axil_adapter_rd.v", "sha256": "838caa3b52268f2c9c2778a30b899ebfa374ea5e11975681d613e37904d61cbe"}}
{"design_id": "483d726aa6b8", "module_name": "crc24_zer64x2_flat", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc24_zer64x2_flat.v", "sha256": "e3251f6b7789a0f4ebae1cf8bf568621a302901bcc47f3e1e4725e9be5188fe4"}}
{"design_id": "484841872459", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/testbench/dut_clockdiv.v", "sha256": "a0902a62ca38b4a207a2c576baa488a8231bba53939ba20c49580129753c9e32"}}
{"design_id": "486f5d09966d", "module_name": "sys_top", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/sys_top.v", "sha256": "4b62e96295a5611eaf891b03928f17ed6859314b6f0acfc8563633e1d73f388d"}}
{"design_id": "48765c87cefb", "module_name": "eth_mac_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/eth_mac_quad_wrapper.v", "sha256": "68601a77f500d7b042fa40585dfab6d42fcf2fbd1b5f415b39196f4f0400c857"}}
{"design_id": "48b655988ca3", "module_name": "jtag_io", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io_bb.v", "sha256": "dc671cdd53e5baee60309fbd1fd204c57a6efe69d48becdada23899895647e78"}}
{"design_id": "48d0b7092c8d", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU118/fpga_1g/rtl/fpga.v", "sha256": "950465f32b8f9d0ba240013ed22615c4197334c7902145f10e296e3b3c9064ab"}}
{"design_id": "48d54aee8f0b", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU108/fpga_10g/rtl/fpga.v", "sha256": "bd0b91b235dd1c2b088478078f24493b5bede872a7f02680274ae1226e96a917"}}
{"design_id": "490542fc1ce0", "module_name": "oh_pads_domain", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "padring/rtl/oh_pads_domain.v", "sha256": "a9c6d6ba5a99c2d562e3f3e65363a2d67fe53892c1850630886f0ca56fc97390"}}
{"design_id": "490bb949c568", "module_name": "LUT3", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/LUT3.v", "sha256": "96ec43f94993e5a358e672ed114ab03ee40393cf2ba9de3a0f309c5ca58ad982"}}
{"design_id": "4917c7df4205", "module_name": "ct_vfmau_lza", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfmau/rtl/ct_vfmau_lza.v", "sha256": "4700a656a86349041a135184afb271c22b33839608d51c5087b4cdb579c2b17f"}}
{"design_id": "495e558eeb52", "module_name": "axil_adapter_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_adapter_rd.v", "sha256": "8d79906e62200be851fb4eead9f094b6598a728ad729c1fddfcdce8402506dfa"}}
{"design_id": "4982149c471f", "module_name": "ll_axis_bridge", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/ll_axis_bridge.v", "sha256": "cfdef6d0c0f8958f37dc3f5a50b517f16c76eac98233c18ea00c33b745f291f9"}}
{"design_id": "49889d378dc1", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/S10MX_DK/fpga/rtl/fpga.v", "sha256": "68934c6caa3376e4988fd498c418cbcf45d37c6080015c4158f8b8b051b76a06"}}
{"design_id": "49ac6ecaee30", "module_name": "asic_oai33", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oai33.v", "sha256": "80b8d69af67fa5403c08ee0c064bbaac40b1408efa15b905a3c57721de7e256d"}}
{"design_id": "49b3c74747ee", "module_name": "NV_NVDLA_PDP_REG_dual", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/NV_NVDLA_PDP_REG_dual.v", "sha256": "c12210a5ff18be8a2e11361be2df5bb012eea4658aa3431b214a339e2eac46d9"}}
{"design_id": "49b91b6eed04", "module_name": "uart6_kc705", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "KCPSM6_Release9_30Sept14/UART_and_PicoTerm/KC705_design/uart6_kc705.v", "sha256": "3816349fce940167ff7395374e4d8daeb32d11fb880ff9925c351e9748630938"}}
{"design_id": "49baeb0dbefd", "module_name": "pipemem", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/pipemem.v", "sha256": "8474d0d2eab6757bc45a9d5d27f78e955b0a8e491aba67fd64a48a26d2adfbf2"}}
{"design_id": "49be59a70abd", "module_name": "stream_grabber", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/stream_grabber.v", "sha256": "e6df68867d447d4da63dcd5a0c046fddbd1559410579c80fbdad855f400253f8"}}
{"design_id": "49c73d39090c", "module_name": "ptp_tag_insert", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ptp_tag_insert.v", "sha256": "b74bfd1750bd4f62a980828d29ed0976c0128bf27b880b1fe76936280da4d5b4"}}
{"design_id": "49fcb148ffe7", "module_name": "dma_if_mux_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_if_mux_wr.v", "sha256": "fdb5ea18a19f17ac76e22e215ab01eea572c5145096259eb62af735afc4cef21"}}
{"design_id": "49fea695c863", "module_name": "axi_adc_decimate", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adc_decimate/axi_adc_decimate.v", "sha256": "8607b1e3d69146bfe2b10ff154ae845fb87f463683f1b8f2fba3993c2b03b591"}}
{"design_id": "4a09cd231139", "module_name": "sirv_jtag_dtm", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/debug/sirv_jtag_dtm.v", "sha256": "e458dabf62b8f70bf02d3fba96ca8be58b5e294db47b3423136af315e794bd03"}}
{"design_id": "4a15c28524ab", "module_name": "ct_f_spsram_4096x84", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_4096x84.v", "sha256": "0be41d2d6d1c8e0b9015161ccd969af7100da71486902d140b665097a8ef0929"}}
{"design_id": "4a1d1c1f0d7f", "module_name": "darkcache", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "rtl/darkcache.v", "sha256": "5117331dfecba90192cc50719c08286ae95633005d81a0b7b72cbd4233a5f549"}}
{"design_id": "4a3d56df945d", "module_name": "ip_arb_mux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ip_arb_mux.v", "sha256": "ceec7cb7e1d9304c6550cdae183c31cd03a611fdc29641d93e0e650aa7a6b70b"}}
{"design_id": "4a414ae524be", "module_name": "int_mnt", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/tb/int_mnt.v", "sha256": "0a0b1f326b30aa5afc768c04f37f8b08fe4633ee009daf644c99f0fb71974357"}}
{"design_id": "4a4ae45fe750", "module_name": "wid_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/common/wid_entry.v", "sha256": "22d056a96fbc6487921061a0e69cfda630c2d8cf2b781f80de053a14152be84a"}}
{"design_id": "4a568ea1b886", "module_name": "ad_tdd_control", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_tdd_control.v", "sha256": "4ecc949db52d289ff577778ed906e9dcbef102972cf5803dfa2542854bded4c4"}}
{"design_id": "4a658bba54b4", "module_name": "ct_vfdsu_srt", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v", "sha256": "ad871494ea3042962e78e11ce669a6b05e06c20f3503ece0d21147fe495707bb"}}
{"design_id": "4a9493cd392c", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "4aaa89d5c51f", "module_name": "ptp_td_leaf", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ptp_td_leaf.v", "sha256": "3218f57ab5f8942f0bc15735144e2aa6f60fc08f7f4a3b3ef874b1730a3818ef"}}
{"design_id": "4aad02a869b7", "module_name": "ct_f_spsram_512x54", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_512x54.v", "sha256": "e340f3fee5293afcefc141d152e8567151a287a2a3c13dbe8b55f028a880dc6c"}}
{"design_id": "4ab77b825085", "module_name": "crc32_dat72", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat72.v", "sha256": "6ea5f50b85034186b247687c2ee7876ab103e08920e36dd1236b2a5f80209536"}}
{"design_id": "4b0e145446eb", "module_name": "uart_tx", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_uart/uart_tx.v", "sha256": "d21960c4faffb9bbd0687db02d119ac1e95b6f495b5b49f5efcaed18667dbe83"}}
{"design_id": "4b197d1e2b57", "module_name": "ct_mmu_jtlb_data_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_jtlb_data_array.v", "sha256": "7d2b84fefcc0cb71b19ed95542ff81707adff9bb37bbcff43b3a6b3a912d7353"}}
{"design_id": "4b333d730042", "module_name": "rand_test", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/random/rand_test.v", "sha256": "e143095862cd2d6c8b8782a996743dab08f51708a3a213057bb5ebf0e45b5b29"}}
{"design_id": "4b3de34e8f6d", "module_name": "sirv_tlwidthwidget_qspi", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_tlwidthwidget_qspi.v", "sha256": "1ee34f620ba12cc47fdd6f9dfd04788545cdc986d280f7286544e99dce447db2"}}
{"design_id": "4b4cc86d0a13", "module_name": "axis_eth_fcs_check", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_eth_fcs_check.v", "sha256": "af5c29694f070a5fe550e46557ac07d1f4e276767a275bdcfbb379072cd48a9b"}}
{"design_id": "4b67cf057d70", "module_name": "oddr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/oddr.v", "sha256": "402394a215bd8b748f880e31cb17f525a313ecb758234fd5b01d447cc4581402"}}
{"design_id": "4b77fce3ddf0", "module_name": "eth_mac_phy_10g", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_phy_10g.v", "sha256": "aec69dea924f19f0279dfed1070ca0bd092d424e5a7d6983a60c41ce9d5f638e"}}
{"design_id": "4b7b815f8884", "module_name": "arp_eth_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/arp_eth_tx.v", "sha256": "88be298ea8f236900416ebd3295aa2fa86a8785acc2b8edca87278afc2338f86"}}
{"design_id": "4ba01b8c5d92", "module_name": "ct_f_spsram_4096x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_4096x128.v", "sha256": "c0d05bd6a598f589f56b96875ded716f852bd77c7c66543d06c34c1d53fb0734"}}
{"design_id": "4bbbf842afdc", "module_name": "tx_scheduler_ctrl_tdma", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tx_scheduler_ctrl_tdma.v", "sha256": "93aab479ae0e9a61bf9ca218cdd6c0849be8413b23da963ab094f7c79cd32160"}}
{"design_id": "4bcbb99f7f81", "module_name": "blockram", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/pacoblaze/blockram.v", "sha256": "f1d2819cbc441387455cd08f8660dac722c6c438db49cc3de2f8eface4d6cc39"}}
{"design_id": "4bcc109b8bc4", "module_name": "asic_clkxor2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clkxor2.v", "sha256": "524d6126c73d244042c8a794974637182fee0094159e658da28a5713ee13c096"}}
{"design_id": "4bd73ffcd8f3", "module_name": "fec_rot_23", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_23.v", "sha256": "a7c6486a63426681def4a29fad88ceb982c1a67fe23fa629a114fcfe7d9b71b9"}}
{"design_id": "4be3cc290595", "module_name": "axil_reg_if_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_reg_if_rd.v", "sha256": "57f196a4e073bfe1b483c19127088006e1d5fdd33f514d4c6672ab08fd7d8359"}}
{"design_id": "4c108dfac78a", "module_name": "asic_ao33", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao33.v", "sha256": "0c31101ebcdc54aaeeb586014d753bf64f94f8cf2f848bf08b0bfa6e8cfe2c2b"}}
{"design_id": "4c26f8755e4d", "module_name": "i2c_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v", "sha256": "ec735fe59297c73dc165ca127cfd487ca19fe051f3dbecebd98e13589f77cd86"}}
{"design_id": "4c3d90d4f356", "module_name": "oh_oa33", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oa33.v", "sha256": "c2dc3a8343ba0cfa10391d662e8f060cb791a974db7a9cb7deb2f13b875885d4"}}
{"design_id": "4ce468f35f60", "module_name": "xcvr_ctrl", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/xcvr_ctrl.v", "sha256": "c119978a2fb8e94b3547b893b045ed2e0eff835de41e0e41c0faa4bb1800472c"}}
{"design_id": "4cf1e4f02ee1", "module_name": "e203_clkgate", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/core/e203_clkgate.v", "sha256": "246adffd3af4cc8ffbd1a87f7aafbece1221c538a9f8c66137e388068991c742"}}
{"design_id": "4d1304b75d85", "module_name": "f_spsram_large", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/mem/f_spsram_large.v", "sha256": "69eb2f54a87ccdcd6fdf19e95d62157cb81bd92edf62a93eca776e8de92d2947"}}
{"design_id": "4d1a964a58cd", "module_name": "axi_fifo", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_fifo.v", "sha256": "bae5ea55dcd8c145a56d75931c555697d284a5c7972c0914ac12df4a452cc71d"}}
{"design_id": "4d321a072d24", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ZCU106/fpga/rtl/fpga_core.v", "sha256": "6a8ca5782d6d78f24a7687e701b48993557d8b127ded76afd56511df12ec081a"}}
{"design_id": "4db4753dfaa1", "module_name": "pacoblaze3m_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/pacoblaze/pacoblaze3m_tb.v", "sha256": "21cd32fd33ddd82dafff8c399f99f04a0d4aa06aa30dfe826f480501d1dfcb3b"}}
{"design_id": "4ddeaac11c27", "module_name": "zipcounter", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/peripherals/zipcounter.v", "sha256": "bef1d1e536ab22e8846e80b9faaf46fb573b1c8871f5c57f316cfe205ab43685"}}
{"design_id": "4de5e2e45806", "module_name": "tcm_mem_pmem", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_tcm_wrapper/tcm_mem_pmem.v", "sha256": "171b6a903df5b76b98893acdbfd6c75e029a21ffce6f916789129bac08de51aa"}}
{"design_id": "4df8528fb854", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X25/fpga/rtl/fpga.v", "sha256": "ecf6202adfe2b41d8609969f3fbe93e5f26b09b0a61e6297eb827c4c952396d4"}}
{"design_id": "4e0665cf1a41", "module_name": "ct_f_spsram_256x59", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x59.v", "sha256": "bd3ece5df665bde740d12212b780ac3604fdfb49065a10a937742703f2860845"}}
{"design_id": "4e18d650e352", "module_name": "axis_baser_tx_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_baser_tx_64.v", "sha256": "b3b8267f9a2c5af1d45836e73051407f919b0f1cee226eb27c233cc6e958f240"}}
{"design_id": "4e1c2c76cc7c", "module_name": "NV_NVDLA_GLB_ic", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/glb/NV_NVDLA_GLB_ic.v", "sha256": "723c009dbfb0f50ea383c674e1c73e14bb5dfb093ded2c1ca6092b38011024ec"}}
{"design_id": "4e26534e1651", "module_name": "cam_ram_block", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/cam_ram_block.v", "sha256": "d5cc4eb13e73c076bcff13d51bcc6a86cf9ce0fb2bdb8a5c25c2c09ed7d37722"}}
{"design_id": "4e3a96152893", "module_name": "ssio_sdr_out", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ssio_sdr_out.v", "sha256": "3eb5251c2cc1bdbf8d380e1954d5d8cdf107c3977541afe219e4a1034cc7eb80"}}
{"design_id": "4e72182e4871", "module_name": "eightbyeight_sad_test", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/video/eightbyeight_sad_test.v", "sha256": "dbd49bcd8647288821f1edfd7232746cd18dddbb043e4626f803a7d7c0948168"}}
{"design_id": "4e7266d9a2e8", "module_name": "sirv_aon_wrapper", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_aon_wrapper.v", "sha256": "c0e3b5d0d3971c999421d5c4e27f52d926f17f74c7c19cec1f62d4e6fbbab9d9"}}
{"design_id": "4ef0a339e67a", "module_name": "asic_buf", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_buf.v", "sha256": "8a97da814d1964c3429d0bd8f3f50e291c81e86626def1c78145c15412616961"}}
{"design_id": "4ef5d9498c73", "module_name": "test_pcie_us_axi_master_rd_128", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axi_master_rd_128.v", "sha256": "9975722e0050c8bf152ac85b518264bcca4474718caec04ab6b31d719d154296"}}
{"design_id": "4f051314796c", "module_name": "test_fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/IA_420F/fpga_100g/tb/fpga_core/test_fpga_core.v", "sha256": "883870bd2453f548affe91569518c943ea0ed54223f6dd4b1fddcd059c6b1d89"}}
{"design_id": "4f0a4c19eb47", "module_name": "asic_xnor3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_xnor3.v", "sha256": "70538b0b25283face933f1d95bf1ec89034760bdab029690682c58579f01c227"}}
{"design_id": "4f1107cf9c82", "module_name": "uart_trans", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/uart/uart_trans.v", "sha256": "2de40f010a8b0cb4824c763bdb1ad67f254886d32c32fc1250cf2a74cbd228ed"}}
{"design_id": "4f2070aa96eb", "module_name": "axis_tap", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_tap.v", "sha256": "9b659c8c99dcef1feba2f859369c8c127a1b5539c35245446e35591de9fa8106"}}
{"design_id": "4f563ad0619f", "module_name": "asic_oa222", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oa222.v", "sha256": "56d8916361548590bfbfa2f28aee4dffc749ed95bd47d4a47d7fcf70eda99217"}}
{"design_id": "4f573838ef25", "module_name": "fourbyfour_sad", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/video/fourbyfour_sad.v", "sha256": "555393fed3915902e0a453f3023561b1fec0a43256654ed98370a373f1f84e0b"}}
{"design_id": "4f668dd7f407", "module_name": "x4_encoder_8b10b", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/x4_encoder_8b10b.v", "sha256": "6eee4b8cfc81b029463c7c6b0cccb44b45191f7bef5cf7754c2bc057afc37dde"}}
{"design_id": "4f6b1a2fd9a3", "module_name": "NV_NVDLA_SDP_WDMA_dat", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_dat.v", "sha256": "484cedac281737c1ccb3c3f5d28c541230c508b8e755463b17ebd97a42a7fd82"}}
{"design_id": "4f738335f9fd", "module_name": "NV_NVDLA_RUBIK_wrdma_cmd", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v", "sha256": "14b786912da91e083155b1f4872d28456c45ada5ffc984e371a4eda7eedde71a"}}
{"design_id": "4f766b5e9f76", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "4f8c45c6e213", "module_name": "udp_complete", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_complete.v", "sha256": "c801c805a1e42ec4f2309ad58c1a0d533ad369993236224b2214c2ee5b8844a7"}}
{"design_id": "4f95bcc18291", "module_name": "ct_idu_ir_decd", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_ir_decd.v", "sha256": "6bcde9ed62df393e9d95218642cfa50ecefb5518bbb338204db606facfe29a6e"}}
{"design_id": "4fa810280258", "module_name": "bitscan", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arbitration/bitscan.v", "sha256": "b491413c29a2448c4a892c22118b800fbc06cf915f6162731980376fcd9f0302"}}
{"design_id": "4faa274fb326", "module_name": "eth_mac_1g_rgmii_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v", "sha256": "5abd4448f31c0234efab84f53ef8c1b14642a1a07d2804f0a0a4dbb60306f22d"}}
{"design_id": "4fc56aeadef8", "module_name": "axis_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "4fcc33885bad", "module_name": "err_gen", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/common/err_gen.v", "sha256": "b0eea928920ab5a1f36778fd33aba533f2cd226df69f400464c3eceda069c0c4"}}
{"design_id": "4fd08ed92a4a", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ZCU106/fpga/rtl/fpga.v", "sha256": "c405ce98e6845585c9322255e70dffdc66de9e04231b5196ff11ef0b3c984e6d"}}
{"design_id": "4fd939ebfdb0", "module_name": "sirv_sim_ram", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/general/sirv_sim_ram.v", "sha256": "f25074ac97a3511c393c1b17a8081ef650d1f53ab12b4f4334c222342e31e63b"}}
{"design_id": "4fd97ca009cf", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/S10DX_DK/fpga/rtl/fpga.v", "sha256": "a37e6a369c53755959c52a0bed0122884de75bdc32e32c580b6529e0040b9482"}}
{"design_id": "4fda52404aff", "module_name": "test_pcie_us_axi_master_wr_512", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/tb/test_pcie_us_axi_master_wr_512.v", "sha256": "e81b51440421f4b77786b8f3eb6eedc53d58f6d39cdb326976249d6a417f9271"}}
{"design_id": "4feb34c5251b", "module_name": "ct_ifu_l1_refill", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_l1_refill.v", "sha256": "a1918526e04cb5f2d2fb478aa8d6ad61293560e1966de0c0b320d81ec00aee62"}}
{"design_id": "4ff9a5f3d02d", "module_name": "sirv_spigpioport_2", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_spigpioport_2.v", "sha256": "a56901d2fe546eeaabdb122f7950253a788e736d01b0d40a62ef00894168ae50"}}
{"design_id": "50081c576c14", "module_name": "ct_lsu_pfu_pmb_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_pmb_entry.v", "sha256": "e9d67e1b5cec4a7b504b4b905f53974020dd3537405d525fa4e496e344ffa677"}}
{"design_id": "500e27ec475f", "module_name": "serving", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "serving/serving.v", "sha256": "190502b9f455bc5f19e68130d94066b77f4b049704f95a18781f96c8cf1f446d"}}
{"design_id": "50570d785b2e", "module_name": "axi_ltc2387", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ltc2387/axi_ltc2387.v", "sha256": "5766f1fc23f70e3c84eb4ef0cb042102b38aa167d547b86e6d00d65c3fbe6d01"}}
{"design_id": "5069ee26c049", "module_name": "NV_NVDLA_sync3d_c", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/car/NV_NVDLA_sync3d_c.v", "sha256": "8f5fc1fba9635d725b6226424dd85aaf50d23be82089f81005f0cfeb19894faf"}}
{"design_id": "508719be36b4", "module_name": "emesh_unpack", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emesh/hdl/emesh_unpack.v", "sha256": "783da3c9969a8367b17db81174bccfb7597ab01f0defd9736ef2daf3cfd70766"}}
{"design_id": "5093b206a381", "module_name": "axi_ada4355_regmap", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ada4355/axi_ada4355_regmap.v", "sha256": "20121009f22fc5462ef2c2b89a6ab194d763da42cd421474b561af4bf4fcf7e2"}}
{"design_id": "509f9715b594", "module_name": "ls_test_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/ls_test_rom.v", "sha256": "661b231546c516bd0d3acf2df155173fb9b8a9a7a3f410dee9c32e9c1cbd2018"}}
{"design_id": "509ff3d90e8d", "module_name": "mqnic_interface_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_interface_tx.v", "sha256": "6b84b887560489ccff032e072ad998cfd353211463a66efcdc7a46c82553cca4"}}
{"design_id": "50ba7cd0b216", "module_name": "splitter", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/splitter.v", "sha256": "513bdf56459edc81cd68c997b0395856fd8aa197cf88beb03ce6d505effe8680"}}
{"design_id": "50c4a79ec5f1", "module_name": "asic_mux4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_mux4.v", "sha256": "37ca49fbf1124c6fde2991b39e6854906c197b1489814de9b36e104f4e7d57a7"}}
{"design_id": "50ce880f6451", "module_name": "oh_sdffqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_sdffqn.v", "sha256": "83cf23c575db0ddfbc1a52a1eb61ef28bf576af3ab93fc3f56dc2412b2ae52f2"}}
{"design_id": "50d37e53449d", "module_name": "udp_ip_rx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_ip_rx_64.v", "sha256": "d91fae456b9687f4b9a5ee5720091b315b2bc9922eb7c7b1a682e37a6a92c51f"}}
{"design_id": "50eaee0d2fe9", "module_name": "axis_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DE10_Agilex/fpga_100g/rtl/axis_fifo.v", "sha256": "b49606665dcef7805fd2cc42ee8514402898a0dee1af2df61dd0a2d332d19a28"}}
{"design_id": "5114c4996a8e", "module_name": "asic_clkmux2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clkmux2.v", "sha256": "815189c8e19d1d1476683730470c7b68f07e15b25540f98c3143f9a6485a6199"}}
{"design_id": "51636f15c397", "module_name": "axi_adapter_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_adapter_rd.v", "sha256": "e9031d79a7699c1b7fa55400fa41106645d141f56615eacd0f5973cdc4459036"}}
{"design_id": "516c072b48b6", "module_name": "dma_if_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_if_mux.v", "sha256": "b98f11ef6c7e0acf4433d1bf9e5383b3792c8fde3ef4c8c3e4938e225f19ae52"}}
{"design_id": "5178c7052402", "module_name": "arbiter", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/arbiter.v", "sha256": "d54d337db4812f927b2e9b5788dfa39f9bd578ad01b7846c5fa7f2610b0923fa"}}
{"design_id": "5181f117c704", "module_name": "test_fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v", "sha256": "6c4e49f1e42bd703d2368a2f8502de26708ea26daf07b9916469bf5dde91f71e"}}
{"design_id": "5199f080d808", "module_name": "fifo_async_104x32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/fifo_async_104x32.v", "sha256": "832f5512032e555d08b9383436a3b87b2752a6d15e1de8ebfe201fa6ba248e67"}}
{"design_id": "51ad71b2aff9", "module_name": "ad_dcfilter", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/common/ad_dcfilter.v", "sha256": "13ef58388f593dc5e254d09a2a16ac0e2188b1ede33593b32aa6f9af2fd56f71"}}
{"design_id": "521b984e9c13", "module_name": "asic_aoi221", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_aoi221.v", "sha256": "cfda747f7f5f027efa938afa449608aafb111ccbf7c122188f7b1534ec090996"}}
{"design_id": "527266fe032c", "module_name": "eight_to_twenty", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/muxing/eight_to_twenty.v", "sha256": "8aed72fe014d72cc5a26ca50a51e795db005bcb2a3e1ebc9ffbceb82ed5b162b"}}
{"design_id": "52aa735ba230", "module_name": "mqnic_port_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_port_rx.v", "sha256": "8338b791a5da9f2359a4bed5de8ebf5fb59753a3fbcd1ba2ad6de4a9991019d9"}}
{"design_id": "52acab9dff3a", "module_name": "ct_spsram_16384x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_16384x128.v", "sha256": "4e1b8d911d5d50707e83dd42cfcf524de863564f484dd640dc77acf4d0f3a06f"}}
{"design_id": "52aeb39099f8", "module_name": "ad_rst", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_rst.v", "sha256": "721cf03b9b6146a487aa4687482b3781230b0d5ea523741c946d4eb1c8dfd95f"}}
{"design_id": "52c27495c53c", "module_name": "ad_mul", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/common/ad_mul.v", "sha256": "e4086e20202c283e7dfea3beefb0a96155ebf634cfa6a9a6d278072611817948"}}
{"design_id": "52d6d507b449", "module_name": "sbox0", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/des/sboxes.v", "sha256": "cdc83df74900c2f6041ac1e21fae5d541dbda16e3178c76a3efa2dd830498f44"}}
{"design_id": "52d764be2c25", "module_name": "util_var_fifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_var_fifo/util_var_fifo.v", "sha256": "68892522e5b59e9cd0c610b23cd25aaa5c3b88de5c3878f850f7c2ba7e150ce2"}}
{"design_id": "52ddeb734661", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/520N_MX/fpga/rtl/sync_reset.v", "sha256": "a6701ef1a7412be2615592c2db70a7cebc07baa208ffba79e34ecaedf0289a91"}}
{"design_id": "52dfe0ab0b27", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU108/fpga_10g/rtl/fpga_core.v", "sha256": "de591ed4d5b20f9350515b9e5f12672017aeebf3c1e66a39045a773a4fbb5818"}}
{"design_id": "52e1b04513c4", "module_name": "test_eth_mac_10g_fifo_ptp_32", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_eth_mac_10g_fifo_ptp_32.v", "sha256": "0229c8b073b782bbf0f84c8041836503af8122a7b6249920c22fe5104795f622"}}
{"design_id": "52ed8c00a645", "module_name": "random_delay", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/random_delay.v", "sha256": "ece32e48ca28b271e2b83449405edba27a34bfeb1c45a28f97d2ce6116f1324f"}}
{"design_id": "5323cd569023", "module_name": "pcie_ptile_fc_counter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_ptile_fc_counter.v", "sha256": "83c705df7fcfd78bae79258829e05a49ed2e0362434fc544541e673ed66e0ec4"}}
{"design_id": "532c62f4143d", "module_name": "test_pcie_us_axil_master_256", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axil_master_256.v", "sha256": "5c11868672b1a088491d382cfe068b4ba1d96d9c4cbff5e4737488a5d70d5ba5"}}
{"design_id": "532d31f6527d", "module_name": "axi_cdma_desc_mux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_cdma_desc_mux.v", "sha256": "9ea015e93946c6415f9ce87b4119e56dbb30db2ecb189dc8b8849dcb3fa3c5f7"}}
{"design_id": "533e1cb0bc97", "module_name": "mlab_sr_cells", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/mlab_sr_cells.v", "sha256": "ade137cb6196052739e0dc73324de3dd4f0e3f45c1d2d3cbf99d8b28b42e3010"}}
{"design_id": "53460beb4256", "module_name": "asic_dffsq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dffsq.v", "sha256": "196f7d8870e92f7842cc4cdd1e427c6e1d1add4aa1dc8978b92955334fd9dad0"}}
{"design_id": "5386f2a9cf49", "module_name": "arp_cache", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/arp_cache.v", "sha256": "d8b573a7582c08f67f90aba9316d98e5b0e0c5bbcbcd7a6935d6537e3f4aa2f8"}}
{"design_id": "539f3cf3e7a3", "module_name": "asic_csa32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_csa32.v", "sha256": "53e00be5a8e5924c3eadff958154a786e8208f86be5030fdc8f5fc36d7881cc8"}}
{"design_id": "53bfe16ce81b", "module_name": "oh_simchecker", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/testbench/oh_simchecker.v", "sha256": "21b8dc3a140828d9d514df741a70380de40bd73f5f5d1e347c283403487a2fb3"}}
{"design_id": "53cc82ebca6b", "module_name": "test_dma_if_pcie_us_256", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_dma_if_pcie_us_256.v", "sha256": "1dabfbce01f6cc22b0b6815c3d86dc48ea8d041b250cf8980cb5b3941f6be71c"}}
{"design_id": "53e3cd49d574", "module_name": "ad_upack", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_upack.v", "sha256": "99f4670d619b0281494cd54bc1f944337b822f325ff0af4bfbfb3b1ebd21dc9c"}}
{"design_id": "53e7ce2a9dfd", "module_name": "ct_f_spsram_16384x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_16384x128.v", "sha256": "980a3e9d1ad67165387ea1fbfa484fbcffab9794eff674274ef77130313121c9"}}
{"design_id": "53f27a8ccb0e", "module_name": "util_wfifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_wfifo/util_wfifo.v", "sha256": "b5fa20b867651d45a600df19675ac6a904ece8759acd82cf82c048477d2f8a85"}}
{"design_id": "53fffbfb677d", "module_name": "test_dma_if_pcie_us_rd_512", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_dma_if_pcie_us_rd_512.v", "sha256": "84f49802ccbc8ff07c056ba6c3160877309bbb6f297e27e13b3312f6c2b619e8"}}
{"design_id": "54032d033040", "module_name": "erx_clocks", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/erx_clocks.v", "sha256": "c70fe5fd4680eef4cf61f7aa5d9c2f7168a9abc6338e2ab045f81bf37af70b56"}}
{"design_id": "5416e7a23b76", "module_name": "NV_NVDLA_CVIF_write", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_CVIF_write.v", "sha256": "09c071f7f7bb3a6e29f2a58ce378903f134301c9b4fe5009a70c62bec0877b13"}}
{"design_id": "5433155f96e2", "module_name": "axi_adrv9001_sync_ctrl", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/axi_adrv9001_sync_ctrl.v", "sha256": "49a6d2386ae7070070ce933ddd842f692fcf7527fa7cc2845ec1499386dde40a"}}
{"design_id": "5434ff1b80bf", "module_name": "axis_frame_length_adjust_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_frame_length_adjust_fifo.v", "sha256": "26f1636f5d4f219ca1dcf336b45b636e74a0977826ee51cdcab4e5c2d136b7ce"}}
{"design_id": "5447cc113198", "module_name": "test_eth_mac_phy_10g_fifo_ptp", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_eth_mac_phy_10g_fifo_ptp.v", "sha256": "f0c14373f7769d4cc9b7e101919a9ee608505efe08aae47a089c3b920a753408"}}
{"design_id": "544d37ccd07a", "module_name": "ecp5_evn_pll", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/ecp5_evn_pll.v", "sha256": "342964ee6098eaaeb552cb8fb26a65cd405bc58553bbadec8f9510d8a22dac31"}}
{"design_id": "5454d5cc8d08", "module_name": "test_dma_client_axis_sink_512_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/tb/test_dma_client_axis_sink_512_64.v", "sha256": "8d2028d70cad563656a49b91fcd5b80d7f8ff1d2e7702655996b2796ecfa33b8"}}
{"design_id": "54644150d22f", "module_name": "cn0363_phase_data_sync", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v", "sha256": "59f1055f66aa6ac74d8fd173d70178552fe78469dc6141cebdd2c98cc5eba39f"}}
{"design_id": "54763c7efb23", "module_name": "ct_spsram_512x144", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_512x144.v", "sha256": "8cda8511827c4371354fa0a96834ecfb6de5f7a4e22bd9dff278903a5fd97473"}}
{"design_id": "54b140898065", "module_name": "security_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/security_rom.v", "sha256": "6b4f6977deeb2d3689d82ff129cdc4e87d4c1f095bf400ae33d6a2809e170e22"}}
{"design_id": "54da21d98187", "module_name": "NV_NVDLA_CDP_dp", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_dp.v", "sha256": "43a5db8393420ed6271a5157266912b8658b81dd1b36a274e7d9e4422480a11a"}}
{"design_id": "54fea0a6530f", "module_name": "ct_vfalu_top_pipe7", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_vfalu_top_pipe7.v", "sha256": "06bb188a0e3c2171565df20b704d97706d803b42659f32eefba465575ba89251"}}
{"design_id": "552c2f937cb3", "module_name": "ct_fcnvt_dtos_sh", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fcnvt_dtos_sh.v", "sha256": "aa6cba26b00bb7373278340ffe662038148729e16f883c206e34a2caa9a4dedf"}}
{"design_id": "552d30762c18", "module_name": "ct_fcnvt_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fcnvt_ctrl.v", "sha256": "e56fa83f6d1e371b49e8d92451a042ee1faf48a4bea18df1198b407a4f503773"}}
{"design_id": "553590744837", "module_name": "pcie_axil_master_minimal", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_axil_master_minimal.v", "sha256": "2ab3e1318504cd50e96c03d79a651e5b23556e7a97d2ba4b4df7e7fa0cf7107f"}}
{"design_id": "556081d0a791", "module_name": "asic_isohi", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_isohi.v", "sha256": "c945b1463f04d122a22a2b1696195aff3280b0ae11788ebb8e7f07aeb68b3302"}}
{"design_id": "556fdfaa19e3", "module_name": "pcileech_pcie_tlp_a7", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "EnigmaX1/src/pcileech_pcie_tlp_a7.sv", "sha256": "671aaedc84b15b508c59e344ad59f52ab5d1f78daa2c0beaab6030df7758488e"}}
{"design_id": "55715b0c79f8", "module_name": "axi_hdmi_rx_es", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hdmi_rx/axi_hdmi_rx_es.v", "sha256": "ed69bec9622f03e617072bb61dd97023b702a7fbbe595b9ddf673f64b068e43a"}}
{"design_id": "558615f53e8a", "module_name": "test_arp_eth_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_arp_eth_tx.v", "sha256": "cf8bd695fc0f87e4856d3e35be87dcc046dd4981bef9f2e91151df2d587fd627"}}
{"design_id": "55897ebbee3d", "module_name": "CKLNQD12PO4", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/CKLNQD12PO4.v", "sha256": "b7a425e4fb0915b9eeeb0089a4029ae85f4f0d5b6ebdff120d73a2100981c51d"}}
{"design_id": "559722bea751", "module_name": "ct_f_spsram_1024x144", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_1024x144.v", "sha256": "95e1a8e4604e1958b5cb101cca5de00bd5bb5bb820869af9594a6626181269b9"}}
{"design_id": "55c11a68cfdd", "module_name": "axi_ad9361", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/axi_ad9361.v", "sha256": "5e801ae8da03739ea72157295d25bbdc361675e2237c641f7d929fac491a7bbf"}}
{"design_id": "55ccc1840fe9", "module_name": "ip_arb_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip_arb_mux.v", "sha256": "ceec7cb7e1d9304c6550cdae183c31cd03a611fdc29641d93e0e650aa7a6b70b"}}
{"design_id": "560c55075314", "module_name": "thirtysix_six_comp", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/thirtysix_six_comp.v", "sha256": "a8f85ff937d806e1a24756931d219935604089083b877eed4afe4599221904b9"}}
{"design_id": "561c58b71420", "module_name": "altera_reset_synchronizer", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/altera_reset_synchronizer.v", "sha256": "6a94193d77172e0a268e780f1edd45aace45c7c36f0dd96d41fceb82ad311264"}}
{"design_id": "562a0292e4fb", "module_name": "apb_adv_timer", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_adv_timer/apb_adv_timer.v", "sha256": "e7ca6e01e532ef4219fe4231c75f9da93f6451bb30637a5b4371698ffb758096"}}
{"design_id": "5635d475c932", "module_name": "RAMPDP_160X82_GL_M2_D2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMPDP_160X82_GL_M2_D2.v", "sha256": "3d9b945b70f56f4d303b8f7586b87fdec035fde1188c41a2eb6074c4d4c6460e"}}
{"design_id": "56489f334180", "module_name": "ad_data_clk", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/common/ad_data_clk.v", "sha256": "06fe7983b84c38fd2aca82ade7a69778013e4c8d566c3b1d75dda6811ba35ac9"}}
{"design_id": "566347225b13", "module_name": "ct_fspu_half", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fspu_half.v", "sha256": "6edd919dc892e29282f75d0e7bebc1949644001562f41cc882cb485147c2b682"}}
{"design_id": "56a301cab497", "module_name": "ip_demux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ip_demux.v", "sha256": "cbebf69d304360e1619ab14609c26fc3e4af718ccc35a3395e14f4e4d0f7887b"}}
{"design_id": "56bb49a34d1c", "module_name": "serv_aligner", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_aligner.v", "sha256": "adeff8f442db6c93f48e551721146b40c398ab14dcb5b22339746329e7a24f3b"}}
{"design_id": "56fe84bdbc5b", "module_name": "pcie_us_msi", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_msi.v", "sha256": "dfc267f8bebf21226263959f2525ad04fd0b3660a0765f2508505e30e75bfd53"}}
{"design_id": "57160a29d004", "module_name": "axis_demux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_demux.v", "sha256": "b3ec5e59baa6b29f9d2bd077c262b8f3e57ea1de1162e19614f93dc866d5ba38"}}
{"design_id": "57356a55ff63", "module_name": "axil_register_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_register_wr.v", "sha256": "af7fd3bc697c3e2d8e921105bf33fab62199a211e4aca031ba28bf08054b6563"}}
{"design_id": "57869d25ea0b", "module_name": "RAM32X1S", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/RAM32X1S.v", "sha256": "2392114f66f58579dc62af354d8398975d5611f3239840d298933223d80ba9c8"}}
{"design_id": "57a2ac438686", "module_name": "i2c", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/i2c.v", "sha256": "c119d827783a40ba36a8cac53f0663d26fda4a5b081fac5a45ebfb89d072b06b"}}
{"design_id": "57bc4e098891", "module_name": "test_eth_mac_10g_32", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_eth_mac_10g_32.v", "sha256": "03215ba6299d1f6b182cc315f93f5bd45834d3fd85d6f9e7f37d02f7980a5b7f"}}
{"design_id": "5815e485128e", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9009/zcu102/system_top.v", "sha256": "1c715c887c17fbc474f8bfc03f3d425f57ebce26d5a1243b10d4f3e63c3b8ff2"}}
{"design_id": "5816dc1673c9", "module_name": "ct_ifu_btb_tag_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_btb_tag_array.v", "sha256": "6831cd49b22208c38ba535b4b8e4490824648413dbaee3f5c686ca632ba46ffb"}}
{"design_id": "5816f832e42f", "module_name": "p_STRICTSYNC3DOTM_C_PPP", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/p_STRICTSYNC3DOTM_C_PPP.v", "sha256": "c8f138e831768effe3b42730746c67d37ffe7f3fb465dd04b207b395b9a30828"}}
{"design_id": "581ac332327d", "module_name": "NV_NVDLA_CVIF_CSB_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_CVIF_CSB_reg.v", "sha256": "b00e35bf52465e8f3082e99decdb087f664cd7d78aaca7ed3f437361b299fe5a"}}
{"design_id": "583b15ae4238", "module_name": "MUXF5", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/MUXF5.v", "sha256": "bc812f7fdd9ca9f8ef340d7df1babef6fe16aea6aab40343ffb084673981ba92"}}
{"design_id": "58797db20c1f", "module_name": "tx_engine", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tx_engine.v", "sha256": "cc5f1f5b22d0b65f9e3454f521ec99f7a13f72b4d9339cffe60d2538291772da"}}
{"design_id": "58b3b42ec847", "module_name": "word_adder_plain", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/basic_adder.v", "sha256": "109fd88760da9defe88a49489a39f0e9f8f06095088488992ea52d298bc3b3b3"}}
{"design_id": "58e243abda1e", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9009/kcu105/system_top.v", "sha256": "72bac0da81f93eaf7ee380dc456251f75eae7bf2c2254edb2733dbf7dfe039c0"}}
{"design_id": "58ebc53fef10", "module_name": "sirv_qspi_fifo", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_qspi_fifo.v", "sha256": "51d04bf4cd09182b7d5e2ebf4070af69a90354d128850e793ca90a6c3576b871"}}
{"design_id": "59048496b92e", "module_name": "zipmmu_tb", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "bench/rtl/zipmmu_tb.v", "sha256": "9902c59054d5c83763b3bb3e0d6315c32fc8f5cc93c678775c1e8c84ddca6aba"}}
{"design_id": "59312613abde", "module_name": "scan_architect", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dft/test/scan_architect_sky130.v", "sha256": "8f974a55a662a87bf8035e37d62543a9abe824616b8bc25263a7e8ac1200ec88"}}
{"design_id": "594c26f40284", "module_name": "ct_spsram_256x196", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_spsram_256x196.v", "sha256": "aea21ae4ea39d924b6841bfe36842b44a226f495f414853a7b97a7a914109d9c"}}
{"design_id": "595c4771d380", "module_name": "udp_complete", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_complete.v", "sha256": "c801c805a1e42ec4f2309ad58c1a0d533ad369993236224b2214c2ee5b8844a7"}}
{"design_id": "59606c43cec5", "module_name": "axi_adapter_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_adapter_rd.v", "sha256": "e9031d79a7699c1b7fa55400fa41106645d141f56615eacd0f5973cdc4459036"}}
{"design_id": "59769e292b75", "module_name": "ct_ciu_ncq_gm", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_ncq_gm.v", "sha256": "feeda792c196be1cc8bd0e814ecd5228e57d347881c3f157d381bee0b85b5afc"}}
{"design_id": "597a877755d1", "module_name": "nv_ram_rws_64x10", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rws_64x10.v", "sha256": "e37b56893141457f59211e810768ecea15b6f4a0bb7f037590ac53f7195773cb"}}
{"design_id": "59ad63dca01e", "module_name": "eth_mac_1g_gmii_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_1g_gmii_fifo.v", "sha256": "738e2619795fe52202498dfdad940ef32d009132a42477fe6bc59493c5fb430e"}}
{"design_id": "59b2e2dd672f", "module_name": "mtx_io", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "mio/hdl/mtx_io.v", "sha256": "2293df02dd89e56b538ccc60e6e29b3286c49b079d72f6761cdfd1d9914e3012"}}
{"design_id": "59c20b83efcc", "module_name": "axi_ad9361_tx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/axi_ad9361_tx.v", "sha256": "2f596f29effc284273c3d2f498e32d7725155f63d1e249211873ea224b39cc88"}}
{"design_id": "59d6c2ec932b", "module_name": "i3c_controller_cmd_parser", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v", "sha256": "be398bbc0943b07b72dc39feb8b80842f679bf2db099ae7307f0692b4b18eff7"}}
{"design_id": "59e0e50af705", "module_name": "ct_hpcp_event", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_event.v", "sha256": "8b4ccfda26ab1c1e31f5c19300fd923d6e76bc50da663365b24d1df52595a9cb"}}
{"design_id": "59e8d197993a", "module_name": "test_axis_srl_register_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_srl_register_64.v", "sha256": "a8752a131a4a9dda7ba244036e25a2587c88be3349c940aebb5a5df23af329bc"}}
{"design_id": "59f5c6e0e732", "module_name": "e203_subsys_pllclkdiv", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/subsys/e203_subsys_pllclkdiv.v", "sha256": "652153dcf7c940083dbf3f4094473d35207ba3c20f3cf2bf7a16277b750c000a"}}
{"design_id": "5a1601643c5e", "module_name": "oh_delay", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_delay.v", "sha256": "d2f72a6406952667fcdc2726519a3685a4764a1523910e84545cdea4e7ccb846"}}
{"design_id": "5a410bea5811", "module_name": "asic_oa311", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oa311.v", "sha256": "e72847c6fb1fb98509746ecd98ef17285b89d1e5b37aaa8c9844810b6676aa9c"}}
{"design_id": "5a4c4b69a3b4", "module_name": "sirv_tl_repeater_5", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_tl_repeater_5.v", "sha256": "01fd0d2bc946f92374d7c0b3c69a1553bdfc87e4709a0b22db56d6df09fbe9f4"}}
{"design_id": "5a7bc2525f67", "module_name": "ct_ciu_regs", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_regs.v", "sha256": "9fbe7a2f44b60c2f8924024eec7a7f3310fcf19459437c4d9ff5b01d1c125de5"}}
{"design_id": "5a80933cb439", "module_name": "axiempty", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/axiempty.v", "sha256": "500976667c7bd106fe8891e3b3aa76ac868a84dcf76a377ed0a91ff5e07c0cda"}}
{"design_id": "5a8e6bc8dd5e", "module_name": "oh_fifo_cdc", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_fifo_cdc.v", "sha256": "94c98b627818a54eef4b7dd1e617000e3f6a3dcc98f49d767859310d97623507"}}
{"design_id": "5a98f7f9b191", "module_name": "ct_ifu_ipb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_ipb.v", "sha256": "babc84b31293576b7f4c7bf6b143db1888f3bfb1702076b0cfe8df71be17f0de"}}
{"design_id": "5aaa431e4763", "module_name": "oh_dpram", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_dpram.v", "sha256": "18fc7e4aaa1143c7f4eadf3dbcc56738aad23794c8e4dc45c31b004ce87d95c6"}}
{"design_id": "5ab902fb6a37", "module_name": "approx_fp_div_lut", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/approx_fp_div_lut.v", "sha256": "de548ae4d6d9fd87d944f9f98d4b52988f35a094dd48b9cfd1400be36240b4bb"}}
{"design_id": "5ad1a3ba34c9", "module_name": "ad_serdes_out", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/common/ad_serdes_out.v", "sha256": "f4327f478a12566fa6f07a9c4a6fdf632f7700b84b5cb1b1c922b0d485824562"}}
{"design_id": "5adb2aa0fbf1", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/cut/test/empty_cut_set.v", "sha256": "363acdaa1e2d5ca66c9ec1507ca4af4a433c1bbcc0c85afb49d0a33121119f4a"}}
{"design_id": "5b14692a91d9", "module_name": "sirv_aon_lclkgen_regs", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_aon_lclkgen_regs.v", "sha256": "9ac3530dd1935a6cb73504ba034aa62240091fc6abefa2f3cedfc48c23a08059"}}
{"design_id": "5b15070c483c", "module_name": "axi_adcfifo_rd", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_adcfifo/axi_adcfifo_rd.v", "sha256": "96c0ac578f0b340bbdfc0eef01fa5d37b474f84d3705b1c3799d20dad2815ae6"}}
{"design_id": "5b1fd0e3b0ae", "module_name": "spi_prog_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/spi_prog_rom.v", "sha256": "65132711365fef86bfa89c82a3b5fee62ee47d0c29e9b7ad32236e19a1b80723"}}
{"design_id": "5b2bb09a7e35", "module_name": "ct_f_spsram_512x144", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_512x144.v", "sha256": "31f8cc7ea3e5411725861e52fa90fdd9aab7ff2fb990ada0138f7419a7c77720"}}
{"design_id": "5b53e84e06a1", "module_name": "mac_ctrl_tx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/mac_ctrl_tx.v", "sha256": "48202a9a8f4b4e9688a4a0eac9dfe7492825be9f1f54a77590008db851b391c1"}}
{"design_id": "5b5d68c1f2d7", "module_name": "sirv_DeglitchShiftRegister", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_DeglitchShiftRegister.v", "sha256": "eff8f32016e601d2a3b879fe20bea09aa6cee5e3a23c24e027bb7e040b1f5504"}}
{"design_id": "5b7330f97fb6", "module_name": "lane_rx", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/lane_rx.v", "sha256": "4612fa6fe4edb4dbd2115527a580ad251793b1ed1a49778f353b935935882104"}}
{"design_id": "5b9091b846d0", "module_name": "servant_timer", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_timer.v", "sha256": "9590ad30f4e51c481db792a350ce31f030a242413c356b645fed96e22cc18c7f"}}
{"design_id": "5b94f6c9e366", "module_name": "osd", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/osd.v", "sha256": "0e9ca65720edb4494bc9c33f714f813785048957f58fa56b3ab2364017c31b70"}}
{"design_id": "5bb3f7d4aa46", "module_name": "eth_mac_1g_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_1g_fifo.v", "sha256": "a5cf2d9e28a4dc0193634c4530f33bf5c5e8536741c3a0e5b78e3f74219ad868"}}
{"design_id": "5bbc7448f434", "module_name": "eth_mac_1g_rgmii_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_1g_rgmii_fifo.v", "sha256": "5abd4448f31c0234efab84f53ef8c1b14642a1a07d2804f0a0a4dbb60306f22d"}}
{"design_id": "5bcb53cdd702", "module_name": "pcie_msix", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_msix.v", "sha256": "85da9abfe32cc3ca92934ac9ae2c1228da606496e8762a9015766791410d9570"}}
{"design_id": "5bcbad0c4c6a", "module_name": "wbarbiter", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/ex/wbarbiter.v", "sha256": "85040b4f69fc4627707e9fb3125c696ea4bf1b6256074f19702a91f532c3ff14"}}
{"design_id": "5bd46a85ba76", "module_name": "eth_phy_10g_rx_watchdog", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v", "sha256": "d7ca2d1ee86841094b291764ccf2d0c832b36ff61a188935c3a9b0723ae93d5e"}}
{"design_id": "5c0ca1ed6cc5", "module_name": "ct_iu_bju_pcfifo_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_bju_pcfifo_entry.v", "sha256": "e609da4d098c66c61b614830bda3caba946990db5b47f7b30cea6e89d21f2ffc"}}
{"design_id": "5c15fc0e8837", "module_name": "oh_csa32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_csa32.v", "sha256": "2f6dcc5a3364b9140c2ec4e983818f0e1aeb38b06bc19771a6f6a5aab243c5ef"}}
{"design_id": "5c1a93e7c9ee", "module_name": "servant_cmod_a7_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_cmod_a7_clock_gen.v", "sha256": "d85802a08b6d0f8f6223c81268b9f9d220707f781347dc0206ce653f13ab5c49"}}
{"design_id": "5c2bb86ed61f", "module_name": "example_core_pcie_s10", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/common/rtl/example_core_pcie_s10.v", "sha256": "33b88c3944c80cd49694e693f96552a2d7c48cba2f1033163944acb19d9c7c85"}}
{"design_id": "5c8e2f769809", "module_name": "adi_jesd204_glue", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/adi_jesd204/adi_jesd204_glue.v", "sha256": "7fac7110834901ffdd6baeb8ea63c76400e0e40e41e18e862b13cd790fa7c1ee"}}
{"design_id": "5c98ff8c32c0", "module_name": "xgmii_baser_dec_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/xgmii_baser_dec_64.v", "sha256": "0b57e2106bc74851a452fd99a394ee1b8bf9f8aac11083f7ec5f4884bfab4b17"}}
{"design_id": "5ca32bed9660", "module_name": "sirv_AsyncResetRegVec_129", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_AsyncResetRegVec_129.v", "sha256": "59f7b19022abe58b21db8f5b9880bacc71c14c4d7f0320c37fb91605c93b4e64"}}
{"design_id": "5cd15e178bbd", "module_name": "xgmii_baser_enc_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/xgmii_baser_enc_64.v", "sha256": "588a0871d72fe7350636e404fb3345c8659d94ee79b97abbd9feb81e447b7696"}}
{"design_id": "5cd8f652dc75", "module_name": "gearbox_67_20", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/gearbox_67_20.v", "sha256": "8ae994ff86c8c8b8b3ad89d7a8add15b129fba64b785557caf319838a42a70d0"}}
{"design_id": "5cf63a9af41c", "module_name": "gpio_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/gpio/gpio_ctrl.v", "sha256": "a78666dc4b3fe1cf4e244e2f25ef9b7a41f4fec6b3bc00a453b6cf9dc5ee0550"}}
{"design_id": "5d1ccfa038d2", "module_name": "axil_cdc_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_cdc_wr.v", "sha256": "a997547ca0b34c281be57184805ea5f91d74e29882017e36e718d8e9bb84a9ed"}}
{"design_id": "5d285fbe3d44", "module_name": "ct_fspu_double", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fspu_double.v", "sha256": "ab73074e4c017f0437bad2a7d32b963e6d59975be83c5b9f2bf0e125b0f668c1"}}
{"design_id": "5d2f29dc2cf9", "module_name": "axi_ad9739a_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9739a/axi_ad9739a_if.v", "sha256": "84e7e0b28fac2a0b085d2350f86dec8d88fe8704a8b10f0837c87e474fc8befc"}}
{"design_id": "5d4260ad8cde", "module_name": "gcd", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rmp/test/gcd_asap7.v", "sha256": "372a06ae26760da19d04f20b6600375d2ecbe88c1046c7bec8b6b872ca8bc030"}}
{"design_id": "5d46bd780012", "module_name": "util_axis_fifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_axis_fifo/util_axis_fifo.v", "sha256": "e388e8734a21e8bc344fed812c6d9862eb1c522a90ca30ad0944921c7fe0e6d1"}}
{"design_id": "5d4b64372861", "module_name": "comparator", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_adv_timer/comparator.v", "sha256": "a9ed41b6147c432a9283fdb6ac5482be48af9451fa41ff47bf4ed699dead191f"}}
{"design_id": "5d50c801d7f9", "module_name": "servus_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servus_clock_gen.v", "sha256": "ec897c6e4c008304ca6900c16ef1f2af29e11f8f7e0aebc08904818ee5ac4d2e"}}
{"design_id": "5d629602adea", "module_name": "asic_dffqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dffqn.v", "sha256": "aa6a727411b9c9b36df660f1005835f16fbd205f10e3e747d23d9ac8221f250a"}}
{"design_id": "5d6f8eca9579", "module_name": "priority_encoder", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/priority_encoder.v", "sha256": "df28220d95b47df349a72803a9751aad331eb8e1435416e8686d00572a974dd5"}}
{"design_id": "5d94e1197388", "module_name": "ad_xcvr_rx_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_xcvr_rx_if.v", "sha256": "805e4cc98790b9dcba817a251f9e3ef4c62f340aac93e0df8bec3feb79074ac8"}}
{"design_id": "5d99d0fc190c", "module_name": "asic_iddr", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_iddr.v", "sha256": "b943c516f6f70cb8be66489d4230bab6c0fbd576b58dac5876fed5f854451a86"}}
{"design_id": "5db32ef3ffeb", "module_name": "spi_master_fifo", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_spi_master/spi_master_fifo.v", "sha256": "8758acb343d6378459006445288b95dfd24c93e5ccc88c6b53b0d0d067d7a66a"}}
{"design_id": "5e1718c3f2ee", "module_name": "ct_lsu_vb_sdb_data", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_vb_sdb_data.v", "sha256": "b146e1a1a0c80fad0f3a145f738c21e1ec5dc3b7760de56932ccd95538e73d17"}}
{"design_id": "5e430448dbaf", "module_name": "i3c_controller_host_interface", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v", "sha256": "6ef444bbcabd3c7301127180ea6484107caa2d7d618f2096a03b5ce501ad957d"}}
{"design_id": "5e4fc4da06ef", "module_name": "asic_xnor2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_xnor2.v", "sha256": "57d0c2974a23a1ad8e0084e100d982afb04a76466c25ff4af2b9c9b7bf46e364"}}
{"design_id": "5e908d9f52db", "module_name": "ll_axis_bridge", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/ll_axis_bridge.v", "sha256": "cfdef6d0c0f8958f37dc3f5a50b517f16c76eac98233c18ea00c33b745f291f9"}}
{"design_id": "5eb7fc526149", "module_name": "eth_mac_1g_rgmii", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_1g_rgmii.v", "sha256": "1b2169d54706005ef54ed5cdb1c994e65bd5b329dca8fc917f6badd212f36b5b"}}
{"design_id": "5f05eb621ebd", "module_name": "RAMDP_256X4_GL_M2_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_256X4_GL_M2_E2.v", "sha256": "62743978c95f1897918d18ee8cab0704e13e97ca52f9c56c8581e65b26a2ae93"}}
{"design_id": "5f26e587ac7a", "module_name": "ct_spsram_4096x32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_4096x32.v", "sha256": "704ccc9711bb1553afb7b0b96ffcdfbe793ed82bce8768241c6119764ccab854"}}
{"design_id": "5f39989b7f75", "module_name": "S00_axi", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "axi_master_slave_templates/S00_axi.v", "sha256": "fd52edfd835ecdf8e59a0fc4b23713100a9a1554a558d3f0cc74e1279ee5eed5"}}
{"design_id": "5f3faafa6657", "module_name": "pll_audio_0002", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/pll_audio/pll_audio_0002.v", "sha256": "8625d01bb2581a56358afe4380e539524a1c8bc7661b97a8b1c94216ac19984d"}}
{"design_id": "5f4dfaf9f1e4", "module_name": "axis_frame_length_adjust", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_frame_length_adjust.v", "sha256": "4b11a92dbdcd0b7b4999d94a62f57b0fc9e0476c543cffcfc817b0b7405f148b"}}
{"design_id": "5f68aab3fe44", "module_name": "LNQD1PO4", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/LNQD1PO4.v", "sha256": "c89821ba1f3fdbb7b207847a90c2fbab81ce2df36519bba9b561bf9f04265bc7"}}
{"design_id": "5f792379342d", "module_name": "ct_spsram_256x100", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_256x100.v", "sha256": "da7e220b2f1e567a4b1f5fc16640bd4759b69b613ed5525b87db87da291a70b0"}}
{"design_id": "5faf5c262665", "module_name": "dport_axi", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_tcm_wrapper/dport_axi.v", "sha256": "11b8b0ec656b9bc05db594e09b610f00c4d9245a73a9bd9c1c910fc15deea43f"}}
{"design_id": "600544b50efc", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad5766_sdz/zed/system_top.v", "sha256": "514803b39fac1afade804acd696e83cb36573ed6d2492d8394d77643401de743"}}
{"design_id": "6025a939c28b", "module_name": "ssio_ddr_out_diff", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ssio_ddr_out_diff.v", "sha256": "53d0476c7446111feb4e3ad637feb7e20dd61785d924262b2c4284c101ec5f4f"}}
{"design_id": "604856115259", "module_name": "si5324_i2c_init", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v", "sha256": "fbac639a0bef00982bd199470edb63b398123302aa66923a2b9049eff1680875"}}
{"design_id": "6062b44ca7d6", "module_name": "tap2_sm", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/pmu/tap2_sm.v", "sha256": "7176641b3323fdcdebd901feea7695264c51ebffe8ff1d4eea88a5d65f74e48b"}}
{"design_id": "6077f14a19f1", "module_name": "eth_demux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_demux.v", "sha256": "5ec09074734c9fcb0d1cd91f7ad752d4f20fe5279dcf44ceb2cdacedb7939aa6"}}
{"design_id": "609a158ae823", "module_name": "ISERDESE2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/ISERDESE2.v", "sha256": "20f5fc721f628344860dcc817b0b3f7a2892ec2bf60d78535f4aa17c11d2b92e"}}
{"design_id": "60cfe4779ef3", "module_name": "sirv_pwm16", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_pwm16.v", "sha256": "98be3fcda1884f8f332e77702a0b820fba77f53dc6cb8a9cd5026dae8089b2bb"}}
{"design_id": "60dc8b9be32a", "module_name": "test_axis_eth_fcs_insert_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_axis_eth_fcs_insert_64.v", "sha256": "0de5cf1cf214ad2a16f809f01cc550f8569508eaa0efd6a05cc04b0e803af749"}}
{"design_id": "60e8d2fdf0be", "module_name": "axi_hdmi_tx_es", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hdmi_tx/axi_hdmi_tx_es.v", "sha256": "3c8b71ce4af8886899c4f0fa5816fddac2d1ab5b0283065425c02aa3f3287fe0"}}
{"design_id": "6116395b5f21", "module_name": "asic_xnor4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_xnor4.v", "sha256": "28f126dad7a7bbe582aeee97734cecff3e925190b6a17cae67669df09c59369f"}}
{"design_id": "61217063ec25", "module_name": "sirv_tlfragmenter_qspi_1", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_tlfragmenter_qspi_1.v", "sha256": "85666e7815fe92713a5ee8f96cbc2158afbec9c9cc58091a88e96c1af104b717"}}
{"design_id": "6129ff64e469", "module_name": "NV_NVDLA_CDP_DP_cvtin", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtin.v", "sha256": "75eb3929c3e71329b8bc2639327d6b2c35dcd27de018edc6b84128efd1cff08a"}}
{"design_id": "612ba7504be1", "module_name": "plic_granu_arb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_granu_arb.v", "sha256": "e314cff5ce6e05698d73c362d4ec5f7444032b5387d31ea8a5e768cf2a20563d"}}
{"design_id": "61616108996d", "module_name": "jesd204_phy_glue", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/jesd204_phy/jesd204_phy_glue.v", "sha256": "100cbeced4b1da2dd157578366ee739d0e3c2a6ba068b1e3ba503b4a88f91c03"}}
{"design_id": "61654ccbb5a6", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/common/lfcpnx/system_top.v", "sha256": "e78b3e68b0f630bfd9c58097e30365c315bed113ed34e3838fa75adea4d44424"}}
{"design_id": "6167c691a09d", "module_name": "RAMPDP_80X16_GL_M2_D2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMPDP_80X16_GL_M2_D2.v", "sha256": "42f299d20feee710eec8f4306b4dada46afcb3b96acd7744ba50aa068b0714e0"}}
{"design_id": "616d688ddfd4", "module_name": "si5341_i2c_init", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v", "sha256": "4a15c9fa10ac5ba44fa21690dc7481c780c9845396bef9045103cc177432bb5e"}}
{"design_id": "61aa133c26b4", "module_name": "ct_ciu_regs_kid", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_regs_kid.v", "sha256": "def5ad2ad21fd99d7c22973369d89c32bfdbad9c61b8de85069289aeeed94fcc"}}
{"design_id": "61ceb177b436", "module_name": "axi_slave128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/axi/axi_slave128.v", "sha256": "0688cde81d7aba61b73a26f55ac49edc01cd612b451d12db2c0ee097c623a00f"}}
{"design_id": "61cfb45d72de", "module_name": "oh_abs", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_abs.v", "sha256": "7309b7bfa5830fc3c4fd63d5eadc1cbd9adff7ded76b1d0a44302470b50dbd50"}}
{"design_id": "61f2f19f5419", "module_name": "axi_fifo_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_fifo_rd.v", "sha256": "ecdb21c322732e8e185c6a1408438565d6990f852a8f271b5442e878174a20aa"}}
{"design_id": "6237efca342c", "module_name": "ct_l2cache_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_l2cache_top.v", "sha256": "f4b2e3e78737a27fb1aaf098be8d59d21248d4b6513e3fbfc40e04a297a37067"}}
{"design_id": "62aabbac0aea", "module_name": "oh_edge2pulse", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_edge2pulse.v", "sha256": "c3545161e57fa578cdc5c5fece1b35933b79f8c5c799a8581db8014e7613f8f0"}}
{"design_id": "62b0964d331d", "module_name": "map_test", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "case/addr_map/map_test.v", "sha256": "e989b0289b8fc58fc385444846e5d8fddf11e8a0d93750233632fe948c19ab1a"}}
{"design_id": "62bfb0b36d50", "module_name": "edma_regs", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "edma/hdl/edma_regs.v", "sha256": "8c363382b115353adff5ade35fd6ce7d7533c1e36eaa34d7d8d7511e4ff4e602"}}
{"design_id": "62c4567ac7d1", "module_name": "debounce_v1", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "debounce_v1.v", "sha256": "914e0ce5a9146673e6f8fbd4967e87553a07d16d79a2977228efded9ec467d3d"}}
{"design_id": "62c5c6f1296b", "module_name": "NV_NVDLA_CMAC_CORE_MAC_nan", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_MAC_nan.v", "sha256": "8ee0f92572e842fbea9e39c77d2b88f80c3ed3744c66b665a4c7366293ea6d42"}}
{"design_id": "62d91ac40246", "module_name": "arp", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/arp.v", "sha256": "41e2301695fdfc1cc93252041107574a0ed040ba92c99d57dce73317804f4698"}}
{"design_id": "62fedb172280", "module_name": "apb_uart_sv", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_uart/apb_uart.v", "sha256": "bd31f4a19b8e81ba2c8ce02b3244ada38cf211445d8ec96151d55f7e946ecadc"}}
{"design_id": "630f90c427a8", "module_name": "clk_gen", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/common/clk_gen.v", "sha256": "bfbde864aa5c688422f862615580e39c6c0f7cf40e13c7e13f7c48808b235cc3"}}
{"design_id": "6331a801085e", "module_name": "oh_nand3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_nand3.v", "sha256": "dd7ad7d74a5607c01669159afaa655de032b9fa1b490454861c494afe08999b4"}}
{"design_id": "635d050134df", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga/rtl/sync_reset.v", "sha256": "67ea2e751ee7cdf5c7528902eab32a63f11bd090e1380934fd7334b361c7d874"}}
{"design_id": "63c944268c3b", "module_name": "ct_spsram_512x44", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_512x44.v", "sha256": "217a3b146879c318a467fa6621b45eab3f35149cb47cafe2c33dc6a754befc93"}}
{"design_id": "63daa8925baf", "module_name": "servix", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servix.v", "sha256": "85b5070eb59a87e57e363210af83d1a9b9bd615aec6795454012818d85c34bc1"}}
{"design_id": "64346e8f3407", "module_name": "ct_vfdsu_srt_radix16_bound_table", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_bound_table.v", "sha256": "dd3fe6708001b89cf78d52db5d81085e05bc4bd0e1b60ea3f269c60094193fdb"}}
{"design_id": "645d0309235e", "module_name": "ssio_sdr_out_diff", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ssio_sdr_out_diff.v", "sha256": "40ffaeee4189b900d59186b6d88ea7ecf49db7cfebb962a8ae1d6538154c44ee"}}
{"design_id": "6460fc9b56d7", "module_name": "pll_cfg", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/pll_cfg.v", "sha256": "89750669762947128e105736d82384587f1cf8ac2f9965090e483c20f7624d59"}}
{"design_id": "6480de8cbf81", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/report_overdriven_nets4.v", "sha256": "b8c3706ee3c49a5af65658087a42e12052d2fe84d8960b9b9f2a7846d1580eb2"}}
{"design_id": "64982ed4655d", "module_name": "PLLE2_BASE", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/PLLE2_BASE.v", "sha256": "2e6f6fa9596022a90cb83400e96313c000cc4ca09258c251c9195fd653f13126"}}
{"design_id": "64bacaf6b67c", "module_name": "servus", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servus.v", "sha256": "133375d3748673d272a80d3e123ad2c044debcc4f05f3c2aa0d3e477c6222f04"}}
{"design_id": "64eca8e3f68b", "module_name": "double_addsub", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/double_addsub.v", "sha256": "b422ac05d9d2be6604b2b2319e7c6f9fa6d2380e49c10fdc1e252dedd292e95f"}}
{"design_id": "64ef640f451b", "module_name": "udp_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_64.v", "sha256": "910e0dfdc12652d520cb49237e35d2dffcb006ac0029e7f46c0c1e66e34ca2a6"}}
{"design_id": "6503908318d7", "module_name": "si5341_i2c_init", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/HTG9200/fpga_25g/pll/si5341_i2c_init.v", "sha256": "b786d5d6f5fa051ce15a46b3dbea5ca1a2cf4745a2ba154718518fcd9069df1b"}}
{"design_id": "65045ff806fe", "module_name": "cpu_l2_mem_test_tb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/impl/mem_icg_test/cpu_l2_mem_test_tb.v", "sha256": "ee0a578a5e8af24d09847ad10d807497ea79781dbd2220a5ec743466fb79be55"}}
{"design_id": "651a96e757b4", "module_name": "ct_clint_func", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/clint/rtl/ct_clint_func.v", "sha256": "935399a3fbff047ad4a41dfe150feca0c34128040fbaabea03113e3013557a18"}}
{"design_id": "65602ed37a9d", "module_name": "axi_ram_wr_rd_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_ram_wr_rd_if.v", "sha256": "36997f5e6de6accab4211704b25c97a5a53319004d2046fe93b1b7d44edb68a2"}}
{"design_id": "657e874d009a", "module_name": "axis_crosspoint", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_crosspoint.v", "sha256": "4d34473a887a571e860c226fac3afc9252728f92c383df6b73e9a3e3e067ef39"}}
{"design_id": "65816404c3f9", "module_name": "mask_16", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/translation/mask_16.v", "sha256": "0aa439dee6643255e4b011b19f7fe2aa052da3fb052f8ddf10773f31414a5c8a"}}
{"design_id": "65950da60ea2", "module_name": "cn0363_dma_sequencer", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v", "sha256": "5a769a1c0d350c64120b9c259414bcdbdd2659a18e1961832b8ad8fa608f7c5f"}}
{"design_id": "65a1a84ae9c9", "module_name": "eth_mac_phy_10g_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_phy_10g_fifo.v", "sha256": "8e6019a5be425aed3b53079a7bba3a5479cb8a46fcb48de8c4cda9f60b0e6bc1"}}
{"design_id": "65ad8e4b4e83", "module_name": "ODDR", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/ODDR.v", "sha256": "c0993a410106a9e77c44a832daab85bfd3f83886005bdbef5dabcd5dfda434e5"}}
{"design_id": "65b8812e36e8", "module_name": "oh_mxi2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mxi2.v", "sha256": "bf9c6df63c433d467dea21fbb63692449e579527703521708d008a7af5c1bd24"}}
{"design_id": "65baafb18fc1", "module_name": "asic_ao22", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao22.v", "sha256": "60e30ff8bae0b7e71845ffdea9f87d7625f5ac8647db6872176295e9b97005d5"}}
{"design_id": "65e4f5e1a2b1", "module_name": "four_lane_jtag_probe", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/four_lane_jtag_probe.v", "sha256": "4fc5012a0e9421be5767f812bca93d2d6af02c8823907515414186c98c1e6811"}}
{"design_id": "65e78b503c1b", "module_name": "ip_mux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ip_mux.v", "sha256": "1d5232ab50868b1a2c386e88af330f7027774d90485cf7ec2f75ec2296de890a"}}
{"design_id": "65e9e6c947e0", "module_name": "axis_eth_fcs_insert", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_eth_fcs_insert.v", "sha256": "864c9d4d5cc3607b38ba5ca3f6c75c930d2dee690663b504f1952bb9e717d981"}}
{"design_id": "65fda8d89972", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/fb2CG/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "6602b7fd034d", "module_name": "axi_ad9434_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9434/axi_ad9434_if.v", "sha256": "84c942ac665430d83e7a1ba90938ba13e75a0f0fc4bbf2d6b32a62cda66508d9"}}
{"design_id": "66199e19a1d6", "module_name": "ct_spsram_64x108", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_64x108.v", "sha256": "431c0d412510fe067d776b3c9b1f9b220b859cf3b61aa09591d48079e751615b"}}
{"design_id": "662684a3428a", "module_name": "fpga_core", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/VCU108/fpga_axi/rtl/fpga_core.v", "sha256": "651f688a0d351f451bc4da04511e73c03c6e3a47e25ce5cf1e0c433c8bb2565f"}}
{"design_id": "662f96b8d1c2", "module_name": "pacoblaze_dregister_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/pacoblaze_dregister_tb.v", "sha256": "b52f0ea3307a55df5aa9652204bfc174f04cfe84271cedeb95267a71ea9213ac"}}
{"design_id": "66447903a38c", "module_name": "tim2_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/tim2.v", "sha256": "1aa65ef7560aa725933c6517de4dffcd30632094ee8f658f150e5899e8e85329"}}
{"design_id": "66465bd44189", "module_name": "axis_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "665ec29d5cd9", "module_name": "servant_ax309_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_ax309_clock_gen.v", "sha256": "e20ac1e2b00181f206cfa92b6f8d26a91b923f5be29bf68dbcfef48be9c97d2f"}}
{"design_id": "669c4d52d059", "module_name": "etx_fifo", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/etx_fifo.v", "sha256": "b6b25c6eb5f81dd029a1a5a788dbd1c051ee69bb14fab2f0455d4a1ded212beb"}}
{"design_id": "66b50b6ceda2", "module_name": "axi_fifo", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/axi/axi_fifo.v", "sha256": "130d86f32feec37ae4fc4cde99cf9d571b267b835ea0b407ab4ef01b519640d8"}}
{"design_id": "66cc239b17d8", "module_name": "booth_code", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/common/rtl/booth_code.v", "sha256": "6b29b6e8090bec94889dc4083fdd2f54b7e667ce2bd41238dd51bd429fca656a"}}
{"design_id": "66edea1bd7e6", "module_name": "asic_nand3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_nand3.v", "sha256": "f39c3b6d17f3056013295ecb2966dc04b838ced656c759b21bb35f6d5578336e"}}
{"design_id": "66f1833c2e84", "module_name": "xgmii_deinterleave", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/xgmii_deinterleave.v", "sha256": "5ab0de601da6ac2917a980b4ad30dbcda86a1cfc62dfd52bd891e9b654c44cea"}}
{"design_id": "6704c1d3f4b3", "module_name": "nv_ram_rwst_256x8", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwst_256x8.v", "sha256": "ce02dd75c3ed6f04c6e0c377c770a72bbcae35108db5f7169786cc0535a1771e"}}
{"design_id": "67317af9d327", "module_name": "system_top_corundum", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9081_fmca_ebz/vcu118/system_top_corundum.v", "sha256": "d0fed84c9cb4f0d08c8a287413bb4fe47f5f75ec8e57efe7ce24dc0f50f39013"}}
{"design_id": "67724c1ef87b", "module_name": "pll", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/ecppll.v", "sha256": "9a5d1328eec013398fd69d835a11cc413378d935dc94ac4b0adff68626dc230f"}}
{"design_id": "678b3a06aab4", "module_name": "test_eth_mac_1g_rgmii_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_eth_mac_1g_rgmii_fifo.v", "sha256": "faf1a5eed6f63da84cc819d35c6366cf45c5bc3820c92ac85f78442467131ed0"}}
{"design_id": "679540f63d54", "module_name": "pcie_s10_if_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_s10_if_tx.v", "sha256": "617347b6e8d5f5941f69dce07d005804db88369be5ea73858f8285390d69e9e5"}}
{"design_id": "679b35003fbe", "module_name": "slave_mem", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "verif/synth_tb/memory.v", "sha256": "00d5a61e959f26d5a26d0b4a9ce68f054af750c8a4f0ae4084863b7228274d52"}}
{"design_id": "679f5140bd14", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga/rtl/fpga.v", "sha256": "92a7d60c464947f4dea1f9c7e6d129513ac5ee884eea7f0330cc537f214f143a"}}
{"design_id": "67b25df8cfe4", "module_name": "aes_round_128", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/aes/aes_round_128.v", "sha256": "cce06c6eb9196947d6c4bcfd5b0724eba317ef5819abcc7d3f28b6de139fc4fe"}}
{"design_id": "67c24cebd909", "module_name": "expand", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/des/round.v", "sha256": "a5a73a01d0ae3c7596e2332424a140ac3650e3f251323266322849e2ec86c052"}}
{"design_id": "67db939bd77c", "module_name": "sirv_qspi_arbiter", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_qspi_arbiter.v", "sha256": "fbe04b6e1969c2297009d5797b4ab83c412311d75d7dc599aa2e97396daff370"}}
{"design_id": "6805de780dab", "module_name": "clock_follow", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/synchronization/clock_follow.v", "sha256": "7542c5ce3b98c1943ea7235ca53987feb6931ca571f143933094fb0018805766"}}
{"design_id": "682679c1b969", "module_name": "ct_vfmau_lza_simd_half", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfmau/rtl/ct_vfmau_lza_simd_half.v", "sha256": "3b09716aa2ba7f14324d3c8325c5ddeedb5dd9939d0860292d4a25d58a2c5c9a"}}
{"design_id": "6841758b0f6f", "module_name": "i3c_controller_write_ibi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/i3c_controller/i3c_controller_host_interface/i3c_controller_write_ibi.v", "sha256": "575e498a7c494e005823f6462d2af89502fb04ad35c750b7b805ea3c40df7a9c"}}
{"design_id": "68785f116366", "module_name": "compress_32", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/wide_compress.v", "sha256": "0fa3666699f958349392c8065ef9476c69af8be16c54ac61b6e56548e564b9c7"}}
{"design_id": "68acf2006820", "module_name": "axilperiphs", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/peripherals/axilperiphs.v", "sha256": "4a9b89d9aec34b1defa73385603e381ab1f6b050bec2c9a2ceb32b082f3ddca0"}}
{"design_id": "690152f76c49", "module_name": "axi_adrv9001_tdd", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/axi_adrv9001_tdd.v", "sha256": "3ecbaaaeed0972bca73df64c10d7a80ef2d54b62016a07d12662054dc843dedb"}}
{"design_id": "69207bc87a21", "module_name": "oh_nor2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_nor2.v", "sha256": "186e239c6d5697513ae4964bd9217f21a46de712401bff51e99adce330add22c"}}
{"design_id": "69227eb54223", "module_name": "oh_inv", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_inv.v", "sha256": "bb00b59da3eb7b5a00ec20894c33df7fa84184c9f375814ec41d91ad74dee0d9"}}
{"design_id": "692cb3c738ab", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga_axi/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "6961a6c89fe0", "module_name": "ct_had_common_dbg_info", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_common_dbg_info.v", "sha256": "f9469dfe4338299e6da44b08d503a2953b408da55b0fa6365883676f5e6c9d3d"}}
{"design_id": "6984793cffd8", "module_name": "ct_biu_csr_req_arbiter", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_csr_req_arbiter.v", "sha256": "6551489df70568c43a52b0e8c674cc080772819bb2675ff54ea233a20bc686e7"}}
{"design_id": "69b7a9dc9815", "module_name": "sirv_AsyncResetReg", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_AsyncResetReg.v", "sha256": "2ca876742ad8590abe6544097ab30054b91e6adae7a6d3976b5941714efe25d9"}}
{"design_id": "69e12cad5b37", "module_name": "NV_NVDLA_MCIF_WRITE_eg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_eg.v", "sha256": "2fc21ee5f41bf8307a01af06544bfe03fcedac3248ba0ed8fa68eb90cddffa66"}}
{"design_id": "6a07dde72cdf", "module_name": "axi_ad9963_tx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9963/axi_ad9963_tx.v", "sha256": "f5f267321c4aa9714e8cd99c24d46734646e34656ce334b6a13f2f5e394f2ae8"}}
{"design_id": "6a0edcb27cde", "module_name": "NV_NVDLA_SDP_rdma", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v", "sha256": "5dddab9062e85c9f4eec2997f433aec29c6c4da8e9cc97982877d512efd98065"}}
{"design_id": "6a19bf941e85", "module_name": "gearbox_66_40", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_66_40.v", "sha256": "60c2c2dbdc3134534e7f79826862e65e7099d3f17c9b0787e8f227fabc3526fc"}}
{"design_id": "6a3f5e8eca98", "module_name": "ct_rtu_rob_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_rob_entry.v", "sha256": "c54df56201f1b89a245e81e79e1f575920ee2a75a150bfc2bd42514a3c17fdec"}}
{"design_id": "6a54a6097764", "module_name": "ct_ifu_bht_sel_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_bht_sel_array.v", "sha256": "078f7406b1cdeee4d0e5efd438973830cc6d6ef841aa48e9e141b3f4332b223b"}}
{"design_id": "6a6214ebdac1", "module_name": "axil_interconnect", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_interconnect.v", "sha256": "f685b0861d4d7a93a8ce4a938589d57e5fdd186204dea32436828496e1426efe"}}
{"design_id": "6a6284036be1", "module_name": "fpga_spram", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/sim_lib/fpga_spram.v", "sha256": "7df2cb008061a03f7728d81869ae3b14d731edcfd02ac93cc6f04f68f6d1d6f4"}}
{"design_id": "6a6944e7f3d6", "module_name": "led_sreg_driver", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/led_sreg_driver.v", "sha256": "58196162c88456016e9219b3e3e20fc59660e92af1889278e0d142b9b3f85f2a"}}
{"design_id": "6a880164ad32", "module_name": "servant_ecp5_evn", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_ecp5_evn.v", "sha256": "f88e25cd3bd4d74623adee7d8124ca7fc74aecc50bc61ce0262c062d4c4c89ca"}}
{"design_id": "6aaa9d4b8cbb", "module_name": "ct_f_spsram_1024x92", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_1024x92.v", "sha256": "9842e1061a1bf989c63455e743ce0ac018112225812d68c6f830cd4b58371db9"}}
{"design_id": "6abe53f3d9ee", "module_name": "asic_tiehi", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_tiehi.v", "sha256": "0de95a6238e2a9bf7aa06db595ea9790bbcbf250cc5108a3cb58899872933107"}}
{"design_id": "6ac2c06c73e9", "module_name": "NV_NVDLA_PDP_CORE_preproc", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v", "sha256": "6806e5b5e96dadd921f3d66fc614923cc39b50436598bdd27edf9fbde1105b7d"}}
{"design_id": "6ac71de0bb8b", "module_name": "axi_ad35xxr_core", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad35xxr/axi_ad35xxr_core.v", "sha256": "0d639275838f3cd5973b1f84fd362381f76bbd9d047dd9200a0203af0cbb526b"}}
{"design_id": "6acb5ff099a0", "module_name": "NV_NVDLA_CDP_slcg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_slcg.v", "sha256": "833cbef85adfe83081120f202ba7fb6d1a00edba4cdc3fe10d40a586b06433cb"}}
{"design_id": "6adc2d3fb22c", "module_name": "asic_aoi311", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_aoi311.v", "sha256": "f42efbd6f1b9f6ab15f0e8854279bdfdf7091ac247cf0a0a4dfee7611bc04d61"}}
{"design_id": "6ae3b5591b07", "module_name": "axil_ram", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_ram.v", "sha256": "5a5ae8c10ab01d8ab3ed18418f4dadfa9c7cadb584ab14838a8d18ac4c3b5644"}}
{"design_id": "6af2ab8d1210", "module_name": "etx_remap", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/etx_remap.v", "sha256": "dd319997bf70da11a206700236834aff501dd96cb0c3de0cafabdb44a2e20339"}}
{"design_id": "6b0568153b6a", "module_name": "avl_dacfifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/avl_dacfifo/avl_dacfifo.v", "sha256": "d2471bd8432e6f654935e7609c1832a9bc48525b1ad14ac3ac33e470cb5c930d"}}
{"design_id": "6b3e47212d3a", "module_name": "arp_eth_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/arp_eth_rx.v", "sha256": "4113e03df063b91d64be4da8e455ba45d8251cecc8e66ec75cec93c518443bee"}}
{"design_id": "6b4971735109", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/VCU118/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "6b8986e52c85", "module_name": "crc32_dat64_any_byte", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat64_any_byte.v", "sha256": "feb86486c0584970690543f3dd14e77e4b5395afc736645336b2f4dfecd785ec"}}
{"design_id": "6b9a8fd86f33", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/daq2/zc706/system_top.v", "sha256": "5a240318897c2136bff92db2fcdf25ad6113295c3334c9ba1c108e8d21886818"}}
{"design_id": "6bba890372f7", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/example1.v", "sha256": "d2ae247ed121c7dfcff41e5f100cfd01fff4b9e3fdf7a95d54ea2f4c6d73acec"}}
{"design_id": "6bd34c4335c6", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad4062_ardz/de10nano/system_top.v", "sha256": "2291b6aa09523f11476992dab33f599826dab064afd9cf491da58b413a31eb38"}}
{"design_id": "6bd5e5de0d54", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/520N_MX/fpga/rtl/fpga_core.v", "sha256": "d51f82a3b22cc1797ba32909d8da2f3ab8144bfdc4e0bd641198339b989219ac"}}
{"design_id": "6be3e4b54b6a", "module_name": "asic_muxi3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_muxi3.v", "sha256": "d39d4c5dd78d665aa18d949cff7149e8f1184a827bd980c9631dc9bed2a70ea1"}}
{"design_id": "6bebe5628a7e", "module_name": "servant_gmm7550", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_gmm7550.v", "sha256": "1b89bff30f0aeb767ac311436039eaf95f6fee98e20f3cd72757bfc1fe61819b"}}
{"design_id": "6bf77d695099", "module_name": "IDELAYE2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IDELAYE2.v", "sha256": "df9fa142e3f56f440f52b1e0aed8045b3c380a552ebb0257a5d255b797509acd"}}
{"design_id": "6c188fb66787", "module_name": "mlab_delay", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/mlab_delay.v", "sha256": "8095b8b5012df57a7e8b2ee7c8d9045b3f257ab27a63af24bee18e873b12c7c2"}}
{"design_id": "6c297e97122b", "module_name": "axil_cdc_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_cdc_rd.v", "sha256": "49b0e680b3f69918f6cc0628bdda3fdaf0fb80914b43a0ae9638554b6dc905ec"}}
{"design_id": "6c606b2a371b", "module_name": "gray_plus_one", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/counter/gray_cntr.v", "sha256": "2dc3f790b89dbfd95a33571d39b2c6d59594103f6ea8fc27891d4e12de6b30b1"}}
{"design_id": "6c7ca180614b", "module_name": "test_pcie_us_axi_dma_wr_64", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axi_dma_wr_64.v", "sha256": "744332a0611f4c29a0deb9d1f3a34c8f3fe623d03b2f930441fd4aecaa38bd7d"}}
{"design_id": "6c9b7aa8279d", "module_name": "oh_or4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_or4.v", "sha256": "4e4c67196f01bfb1c8468c2281d95a2f866f1f7b8aaac0de1f5fa40c045c72d1"}}
{"design_id": "6cd3b9a02cf7", "module_name": "BUFGCE", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/common/BUFGCE.v", "sha256": "7c31df09bdbeac61a35c17889a78762f48172f2b85b06a5238041b3f924a064d"}}
{"design_id": "6cd7d3392326", "module_name": "NV_NVDLA_RT_cmac_a2cacc", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v", "sha256": "a49b0569d31890f17529e0fa8bf1a03a58ee16c6be0315b9e84dedcad778f4d9"}}
{"design_id": "6cda6b91fb24", "module_name": "ad_mul", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/common/ad_mul.v", "sha256": "e9749da9d213ef68af97745f6583918321b451755c51d330e8ccfb5a5a7afce2"}}
{"design_id": "6cec3b69983f", "module_name": "axis_register", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/ExaNIC_X10/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "6d1baba47980", "module_name": "LUT4", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/LUT4.v", "sha256": "f8500cf72d6eaed9e9e520a1d1173b455ace9ed2f2d17beb10decfec13393b08"}}
{"design_id": "6d2d78c3c18c", "module_name": "decoder_8b10b", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/decoder_8b10b.v", "sha256": "66aa675a375ad50ccb45b87366aee419c92e4b8b8e35ee147fecfb73f9c2bb54"}}
{"design_id": "6d3b04700964", "module_name": "eth_mac_10g_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_10g_fifo.v", "sha256": "7a28b8b406789b00d1c23d40f0e6570239d62a8e5bee9b9e04fb17b5dee1e7a3"}}
{"design_id": "6d443c1e1eaa", "module_name": "pwm_ctrl_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/pwm_ctrl_rom.v", "sha256": "af5b32b66622b9c116e923e6670a863fb7104d2c729fc9165076d4eee46c57fc"}}
{"design_id": "6d63e7bada6d", "module_name": "f_spsram_32768x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/mem/f_spsram_32768x128.v", "sha256": "c6e994079845dfee1ab788b4c51a4080b84fcc29910e78c7e7f4e3f977f7e338"}}
{"design_id": "6d6626dc852c", "module_name": "td1", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/pinswap_flat.v", "sha256": "a1e1a2f96a597c8b0eda17ae89c9f908ae920b582468dcf8ea46876e6a203a6d"}}
{"design_id": "6d6b7f5e6a6d", "module_name": "ct_mmu_tlboper", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_tlboper.v", "sha256": "528c7277007f6310713734e64e1c36cc12c1f5ae2404e328824d16e4470b0f05"}}
{"design_id": "6d8e61a98d8e", "module_name": "IBUF", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IBUF.v", "sha256": "e39c1d959a152c26c514c273fe8a7f8de1e9538c9dc295234aca50f3c91fcabc"}}
{"design_id": "6d9980827f80", "module_name": "axi_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_fifo.v", "sha256": "bae5ea55dcd8c145a56d75931c555697d284a5c7972c0914ac12df4a452cc71d"}}
{"design_id": "6d99feb515ae", "module_name": "Standard_Cell_CLK_GATE", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/sim_lib/STD_CELL.v", "sha256": "4fcce27c84d197d4bd4c2b774fd58663fa98ad380328291a96116b3be7ca2bfd"}}
{"design_id": "6dbf2e7b48cb", "module_name": "crc24_dat64", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc24_dat64.v", "sha256": "4ab95b475c2772e606afdd9c6e51ff7ac523af9ced5fe3ee0cb50d03d213443d"}}
{"design_id": "6dcc41295266", "module_name": "axi_crossbar_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_crossbar_wr.v", "sha256": "0892781788371df9d3449608d342542269eb05efd0b6827fdea575d538368816"}}
{"design_id": "6ddcbe1a0ca1", "module_name": "ohr_reg0", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_reg0.v", "sha256": "ab41ea1ca38d8854909a5094361916417e6ebd17d77757b986bde9a07388aa25"}}
{"design_id": "6df3767dbcfe", "module_name": "oh_mux12", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mux12.v", "sha256": "09304994ad097830db94e2958aed7af61cffd98b779345447d1953c29151d4dd"}}
{"design_id": "6dfcc2d161b6", "module_name": "util_pad", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_pad/util_pad.v", "sha256": "8d0c0e854bc8b8487ae6f9cf4b94ed13eeb1e0b74da044ad03743d720ecf2973"}}
{"design_id": "6e00c26b6cb3", "module_name": "pcie_tlp_demux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_tlp_demux.v", "sha256": "6b3c76538e54e7b71ece96ea5ad17bbc720b8b98d1fe18033a58aaea4b142511"}}
{"design_id": "6e0152485a8c", "module_name": "servant_lx9_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_lx9_clock_gen.v", "sha256": "a29d5e5fa334c6a04cf7fa201faf99a9704bcb97fb6e77dea4879c8660ca33a7"}}
{"design_id": "6e01731285bd", "module_name": "f_idecode", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "bench/formal/f_idecode.v", "sha256": "6fc94fd166b5fdf31bb3af92b19e9340696ff4f97347eb7974a216e435cbf7db"}}
{"design_id": "6e092613c0ea", "module_name": "oh_dffsq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_dffsq.v", "sha256": "c342cc258b140f10cd5dee2cd3cb4efc0142a540010d8bff961ca83258703540"}}
{"design_id": "6e2a21e48d2d", "module_name": "axis_async_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_async_fifo.v", "sha256": "339734a7984d7d540451c92f0831495837c451d170ba60dfbd59f851b28f4250"}}
{"design_id": "6e3e2b9cd4d2", "module_name": "pipeline_add_msb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/pipeline_add_msb.v", "sha256": "e23caaeb71faf3cab7423642a60c5040a67eb065aca3d637c47c425438c1b2e0"}}
{"design_id": "6e443c2742ea", "module_name": "ct_spsram_2048x144", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_2048x144.v", "sha256": "136d814a8b9081523c4204903babd5bd858d652087e41d4513372514071e2f19"}}
{"design_id": "6e6a8e75d8c5", "module_name": "pll_0002", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/rtl/pll/pll_0002.v", "sha256": "fd85219355b4dddeeb3dc3f6b8513fbf05d402053b276f8bdaed35d35d29321c"}}
{"design_id": "6e8190c23132", "module_name": "udp_ip_tx_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_ip_tx_64.v", "sha256": "e3bb0ebd4c7f0c1d9753dcea3940809ac7a747d681e7d3cb9c5744f7aa4088fc"}}
{"design_id": "6e85498e8def", "module_name": "approx_fp_div", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/approx_fp_div.v", "sha256": "1d7c4ac05fe1d781ef146ac28ea8cc3a6679d3fb7df82a58cb99240d863ffb18"}}
{"design_id": "6e86d95dfc49", "module_name": "ct_spsram_4096x84", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_4096x84.v", "sha256": "f2acc8cedecf64ed77971a683ba71fc426c32c5032c6bc7232c97f8bb643b002"}}
{"design_id": "6edcf4761b6e", "module_name": "axi_xcvrlb_1", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v", "sha256": "359bcbee615718c5ecd8507287292a304483100fc55f9612b192ff49d251f386"}}
{"design_id": "6f0cb154332a", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga_axi/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "6f1ea97a3d39", "module_name": "asic_oa33", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oa33.v", "sha256": "905ac7286c5f606898b910779da911cf410a951c668023f5a9ade28ac50e5fa9"}}
{"design_id": "6f27561caaeb", "module_name": "addsub1", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/addsub.v", "sha256": "c8f529ddbcf3c4406bbea18d2fe490d0a96a61ebf46a108ac6f63f2d85b48826"}}
{"design_id": "6f376f553829", "module_name": "axi_adcfifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_adcfifo/axi_adcfifo.v", "sha256": "e219c01e281892c883b797e9563bd9d2fa1afc0cf73312d15cc9063652dababd"}}
{"design_id": "6f76f08ee7eb", "module_name": "led_sreg_driver", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/fb2CG/fpga_axi/rtl/led_sreg_driver.v", "sha256": "91ef35971991fd2b536d1ccb263e892441e9fa0d631e8a14d3db896238f3cb34"}}
{"design_id": "6f842ffc92be", "module_name": "dma_if_axi", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_if_axi.v", "sha256": "3c59447dd7ff7b55fc42c53720e5c904edfc380ef2552b0b82975b1eb8348dfa"}}
{"design_id": "6f94a23374a2", "module_name": "fec_rot_19", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_19.v", "sha256": "27a23055df2e0994a3e4b8740a3dffab49fc3a999ae414bc866c0b33f1879ead"}}
{"design_id": "6f9caf6428cb", "module_name": "asic_clkor2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clkor2.v", "sha256": "dd5fb823dc290e6037a1b652bb37db50e7433f8aeb114ff32cc712ebbd31963c"}}
{"design_id": "6f9e0daa795e", "module_name": "pcileech_pcie_cfgspace_shadow", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "pciescreamer/src/pcileech_pcie_cfgspace_shadow.sv", "sha256": "e40fe291906457b3ba855e45b1db56cbc0f092215bc25040e217d4eb1421c5ae"}}
{"design_id": "6fa45123369b", "module_name": "serv_rf_if", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_rf_if.v", "sha256": "63fd0d2ec2f89201b20690c467ebbcae964a85b4570254a95154f832cf0dcb2e"}}
{"design_id": "6fc41f099b0a", "module_name": "jtag_io_mm_interconnect_0_avalon_st_adapter", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/jtag_io_mm_interconnect_0_avalon_st_adapter.v", "sha256": "8ab7256acd66a40c0a172b2338200d84814be9a220326e685b1aea92e1a1a836"}}
{"design_id": "6fd96d431f86", "module_name": "ct_mmu_iplru", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_iplru.v", "sha256": "5509b917eee646b4ed4ab057ee0b7dc960175d254ba2a570a4f84b0a9f312f32"}}
{"design_id": "700de021b80b", "module_name": "asic_xor4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_xor4.v", "sha256": "0e9655279207735678000f14db4a90ed78d50fb708fa6a1ac0a9526fc1de4f30"}}
{"design_id": "700f31800e4a", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga_axi/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "701d8e6cc1ca", "module_name": "asic_oa32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oa32.v", "sha256": "e5ac01729d6de32a362dd21edd9b0ea0d05a4e0113beff1b3c6a4abb86ba917a"}}
{"design_id": "7057fad02292", "module_name": "NV_NVDLA_MCIF_read", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_MCIF_read.v", "sha256": "b6bd6e8db5bff7e930bb27e9dcbc1f9a471cf18982dfe1789d86352611c74fa8"}}
{"design_id": "705ec5370575", "module_name": "mrx_fifo", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "mio/hdl/mrx_fifo.v", "sha256": "fa1ba4aa318bad49ff9ce7f32560262e0c7732d61908708cc7eee830fe8487ba"}}
{"design_id": "70890164bd3a", "module_name": "ct_l2cache_data_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_l2cache_data_array.v", "sha256": "d0956001949aa17a1ae968a162559c42325e0ba0f8e009a0d9942dcd0593b022"}}
{"design_id": "70d04db5666a", "module_name": "spimemio", "split": "train", "source": {"repository": "https://github.com/YosysHQ/picorv32", "commit": "ef203c2b0a3fb793280f5114941416c425c5b461", "path": "picosoc/spimemio.v", "sha256": "3bbd69ef9d49ba82d0fb952a8ca68d0360f6ad4b0bb2aa55e5f1ce1744a7188e"}}
{"design_id": "711b2913dac7", "module_name": "NV_NVDLA_CSC_dual_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/csc/NV_NVDLA_CSC_dual_reg.v", "sha256": "8ea24728f75e4d2ca6679c6a1e7a9850667d3984db776e75a85e39070c79c5da"}}
{"design_id": "711ea88f1c0e", "module_name": "crc16_dat16", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc16_dat16.v", "sha256": "a298ced61c69c2cec5cd16c9eeaeeadbeecf10527c341266e2a87f166c9d4243"}}
{"design_id": "715d08fb6771", "module_name": "erx_fifo", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/erx_fifo.v", "sha256": "27384a7ec58d534f785c87927d2d0fccf19f238e3b1030b021f95ff262b2a19e"}}
{"design_id": "716583cee6c8", "module_name": "NV_NVDLA_SDP_ERDMA_cq", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_cq.v", "sha256": "cc921b840e6d41881fc0b217621a7b4c8f35dfaef4bf6d1ec500cf9d6942593a"}}
{"design_id": "71724d95cf6a", "module_name": "servant_mux", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_mux.v", "sha256": "f4dba03c4f518258b108f90379cfd3b94c295898a342a67ab82c88e877d0082a"}}
{"design_id": "717297473c19", "module_name": "oh_csa42", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_csa42.v", "sha256": "472a36945fcaca576045da2c17ef771f6427882245aa0877d53fff557713ac93"}}
{"design_id": "71732cec8f66", "module_name": "ad_ip_jesd204_tpl_dac_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v", "sha256": "7367057ec029ff14635befbccb72769f218bb51ab5f18c6e18a50cf3eb6ad9c8"}}
{"design_id": "71926ab66312", "module_name": "NV_NVDLA_RT_csb2cmac", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/retiming/NV_NVDLA_RT_csb2cmac.v", "sha256": "3598d091873675a33f170e48158b544ffcf88e5b63c4ef339270772cc1d141d3"}}
{"design_id": "71bcb87fc601", "module_name": "ct_rtu_expand_64", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_expand_64.v", "sha256": "2af0b2fb30d7d8742e09db11291b12abb8f27fe06b9ceb669250ff0d2f0c0942"}}
{"design_id": "71c4989688eb", "module_name": "sync_data", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_cdc/sync_data.v", "sha256": "15a0d6233b5722c15b07dd0bf5c483c7cb7b8bc93aca0d82d89baf17177a331d"}}
{"design_id": "71c8c9bee028", "module_name": "NV_NVDLA_partition_a", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/top/NV_NVDLA_partition_a.v", "sha256": "e0bc77f00501126bbe93b5a0258b5e552a4d777233e911141bb5aba55db13524"}}
{"design_id": "71d6bcf68260", "module_name": "axi_ad7768", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad7768/axi_ad7768.v", "sha256": "1e0a35332c592a0b9bb72dfae595086c2bde2eb64da9869413d55ec11b44b8cc"}}
{"design_id": "7204feed74d0", "module_name": "RAMDP_64X10_GL_M2_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_64X10_GL_M2_E2.v", "sha256": "c62139668ac68785f2305829e25cdd28fa70aac7798f81dbae259cbbc6aa04e9"}}
{"design_id": "720ae7aca0d9", "module_name": "servive", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servive.v", "sha256": "de6e1500b0fbef50c52a647fe400b30bb178666ec25da6cf687350228d4bde35"}}
{"design_id": "7228bea208b9", "module_name": "axi_ad9783", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9783/axi_ad9783.v", "sha256": "893ce8c7ae6080172ff2f1206f50439b0a3e1a056618c854d3404f2e4d0a0e44"}}
{"design_id": "722b5910a24b", "module_name": "NV_NVDLA_rubik", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/rubik/NV_NVDLA_rubik.v", "sha256": "0308fae799e1747ec30f0f06701d84bcbeef1cd7bf2205df4e19470b2704e5ad"}}
{"design_id": "72360df10402", "module_name": "axilpipe", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/axilpipe.v", "sha256": "259cefb93d00ab1b6cc9457b86a0c55dea7cdb9396c8bce7ec05ce2da552e7c2"}}
{"design_id": "723fd0fd9bec", "module_name": "sirv_AsyncResetRegVec_129", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_AsyncResetRegVec_129.v", "sha256": "a45077bf3e1fd8e792a15da2bdefb47a16df2652d71996def48ded9fbe895282"}}
{"design_id": "72430b3543e8", "module_name": "tern_node", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/ternary_sum_nine.v", "sha256": "2931ecca305839f2199ca1700423c2a62240c5c00045a4985510376ebfcd5da9"}}
{"design_id": "7267bc8c90e4", "module_name": "util_bsplit", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_bsplit/util_bsplit.v", "sha256": "42f05ab7448334f32b5c9b4bd3f85da2033e59f618b091da73b81a8561b9c61b"}}
{"design_id": "7277d71f4e99", "module_name": "compress_32", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/compress_32.v", "sha256": "ae4a803ad00df1bedde691403fd7ba4df9dc0f1c1c4cec80aca5b4120ea08770"}}
{"design_id": "72cd7c92db9d", "module_name": "axi_ad9625_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9625/axi_ad9625_if.v", "sha256": "4b9a93a63dd9eef07f4051370e84ecc51319d4177d5585b7d6d93be3906315d7"}}
{"design_id": "72d23cfc4526", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga_axi/rtl/fpga.v", "sha256": "5a53d3ecfe6981738c0c6cf497ff54f59411c9317fcbbdcb293f7f0e5d826076"}}
{"design_id": "72fa64e26a57", "module_name": "ct_f_spsram_512x22", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_512x22.v", "sha256": "ca1e011d6fe1f6c5e0de2f9fb56bd84a1e96c1f243d503a99fbbc207575d5834"}}
{"design_id": "7302285ed66a", "module_name": "axi_dacfifo_rd", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_dacfifo/axi_dacfifo_rd.v", "sha256": "1092106bbf7d67880dc01b268a72cf9557e1c610cf3be3100cfa9a541bcefc23"}}
{"design_id": "7325d5eb19a3", "module_name": "oh_oddr", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oddr.v", "sha256": "1f9f2a7ad82c4d1c2a6a0706b140c414db3bef423518c209cb6a4c3954fa9b58"}}
{"design_id": "73406d6f75d3", "module_name": "ad_pack", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_pack.v", "sha256": "239b88c27d6dfda05aa1eb8a7d6befa2f97510437b62ce8a79ba95f09b21a059"}}
{"design_id": "7354996cd8e4", "module_name": "up_clkgen", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_clkgen.v", "sha256": "9d829119716982962de359d172ab118ae0195f40b32a2f0fbd035aa1f97fd715"}}
{"design_id": "736a78a8e6e0", "module_name": "eth_mac_1g_rgmii", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_1g_rgmii.v", "sha256": "1b2169d54706005ef54ed5cdb1c994e65bd5b329dca8fc917f6badd212f36b5b"}}
{"design_id": "73c0ee3ec3f0", "module_name": "OR2D1", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/OR2D1.v", "sha256": "9c9a70fb594f65d2d54c019ae4afb5135487073b97347103cd000a7f61921037"}}
{"design_id": "73da2215af17", "module_name": "stats_pcie_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/stats_pcie_if.v", "sha256": "2b14d9e488be96f093abba637ddc26d008100fd743c9041d73b9d2a9fb771a2f"}}
{"design_id": "73dbde925855", "module_name": "twenty_to_eight", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/muxing/twenty_to_eight.v", "sha256": "55fdaa57b7edeeb155e470dcaae2edd98e86e0fd84ef7447b05d5cad803dae99"}}
{"design_id": "740ad0604874", "module_name": "ct_spsram_65536x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_65536x128.v", "sha256": "34caea81911444ebf41a42383c8f4178a0b3cc43f443c206f33bb88dd88d276f"}}
{"design_id": "742b3f2445f5", "module_name": "altera_avalon_st_pipeline_base", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/altera_avalon_st_pipeline_base.v", "sha256": "e2e5bc9b27c2d25a0e37343cef349dc82c44f4f6ff8aaf332303e8f4b2760dd5"}}
{"design_id": "743992f525e1", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X25/fpga/rtl/fpga_core.v", "sha256": "67752a9898638dd8803c21948b1296ef2f8e1a7383fd7ace296df4f078c611ae"}}
{"design_id": "74419e80bbea", "module_name": "axil_reg_if_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_reg_if_rd.v", "sha256": "57f196a4e073bfe1b483c19127088006e1d5fdd33f514d4c6672ab08fd7d8359"}}
{"design_id": "7472e6629cd7", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "747515609c2a", "module_name": "equal_const", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/compare/equal_const.v", "sha256": "274fad122f7cc6b9f2147e7cdb009e6f57cc893f0ff3f74e40d3b558d494823b"}}
{"design_id": "747c0030d35a", "module_name": "core_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/core_top.v", "sha256": "52d6e3b95e3fa7f7e6912e90139911bf3ba288628864beb467339c36114563f0"}}
{"design_id": "74824ca16c82", "module_name": "ad_sysref_gen", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_sysref_gen.v", "sha256": "3c2f0140d313f4c8709d57abd26a6de83c6e100d5e352ce9bf153a0b07ee1443"}}
{"design_id": "7483a734155f", "module_name": "axi_dma_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_dma_rd.v", "sha256": "853ff3aedc44ec0c12ef3ae8b84d7559800d372f76832c7c133ed5eecac61dd8"}}
{"design_id": "748884dc6be8", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad719x_asdz/de10nano/system_top.v", "sha256": "7e34788b1dcb67e88dda786458776e60a85bb62f19c0a42435a10df605db7501"}}
{"design_id": "7494f10e1ca4", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ExaNIC_X25/fpga_25g/rtl/eth_xcvr_phy_wrapper.v", "sha256": "8dd5f7389723ae404ac04e7a5e8feca9c444800d56e4a8b3edef03d0f0439a43"}}
{"design_id": "74c4317fe59f", "module_name": "eth_axis_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_axis_rx.v", "sha256": "4fb3ab7e0ccafdc85a46f37e533b7fb6e74a7101cfc18757126175ed01354d59"}}
{"design_id": "74c4e0cfccf4", "module_name": "sirv_DeglitchShiftRegister", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_DeglitchShiftRegister.v", "sha256": "332ad5b31f2e002d14f4a278e1057aede1ba05d0ff16d494cb2b49b981ea53be"}}
{"design_id": "74c572ba9a21", "module_name": "axi_ltc2387_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ltc2387/axi_ltc2387_channel.v", "sha256": "b427f8a38474c77453def63dd639ff3363b2c77163bd49f14040ebee2bafd6ca"}}
{"design_id": "74d722402394", "module_name": "eight_to_one", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/muxing/eight_to_one.v", "sha256": "6908075503edc14a1bface07253dfa92bef4b7a283c75c02bff338cde70724f8"}}
{"design_id": "74e1a1f9bc75", "module_name": "ad_bus_mux", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_bus_mux.v", "sha256": "5d8d9baccdbbc8ec9d9c2d2144d5d05d68f948d7ead595146b5dabe51e445261"}}
{"design_id": "74e95facef90", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X25/fpga/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "74f3a11b80bb", "module_name": "booth_code_v1", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/common/rtl/booth_code_v1.v", "sha256": "64abfc68384cffa1e44f9290f5f798334311e2e2df3ca41a419f1b1db7c1d708"}}
{"design_id": "751fc7aea126", "module_name": "fec_rot_15", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_15.v", "sha256": "6f493f65548df3e17f57dab35aadc0009ccd5825145e850410888f99b397d146"}}
{"design_id": "754262100752", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU118/fpga_axi/rtl/sync_reset.v", "sha256": "67ea2e751ee7cdf5c7528902eab32a63f11bd090e1380934fd7334b361c7d874"}}
{"design_id": "7552d05c6e07", "module_name": "counter", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/odb/test/data/floorplan_initialize.v", "sha256": "742cb0b042178987844e8e6043bd842e22f17240cd7719c57f9588e10c28c2ef"}}
{"design_id": "755987a324fa", "module_name": "pcie_us_if_cq", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_if_cq.v", "sha256": "b5e50b2b8f3df3c237b4ddf5ab383482fc3458aa8f2c80e237a4b80dbf37bd50"}}
{"design_id": "75786886e004", "module_name": "axi_hdmi_tx_core", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hdmi_tx/axi_hdmi_tx_core.v", "sha256": "3dcdf3b9d6830a9679da2fe732117d96859242931f37101c72873babd9ee4092"}}
{"design_id": "7596db9edfd7", "module_name": "IBUFDS_INTERMDISABLE_INT", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IBUFDS_INTERMDISABLE_INT.v", "sha256": "b2cf78d5aee553df4e51eb9420341b8f9cc73ee916fb244ab83bbbd0415c79bf"}}
{"design_id": "759c806c9892", "module_name": "cntr_modulus_la", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/counter/cntr_modulus_la.v", "sha256": "7f6ddbfdf65eb793be720ef6c9bdb208b4889ec3c37d7a815c51d6a84a9aec9b"}}
{"design_id": "75cb8535fecc", "module_name": "axis_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/axis_fifo.v", "sha256": "b49606665dcef7805fd2cc42ee8514402898a0dee1af2df61dd0a2d332d19a28"}}
{"design_id": "75d80a789dd8", "module_name": "ct_f_spsram_2048x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_2048x128.v", "sha256": "ab26200b3677e35f8c9ff6ea1eb48cc6a43a8ad9392b90950a8bb8e25130622d"}}
{"design_id": "75f08ba00723", "module_name": "oh_oa22", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oa22.v", "sha256": "4406af06691660d8904ba2b8e08501647f5d93ce8482ea6b612d6b9afbdeef2f"}}
{"design_id": "75f8aa517a4d", "module_name": "eth_phy_10g", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_phy_10g.v", "sha256": "89d13d9dec752dcfebba26b11bf8070467a0304e4c771020b5009e220ab3ae59"}}
{"design_id": "7624675be79d", "module_name": "uart_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/uart/uart_ctrl.v", "sha256": "295e53be4914324b0d01f232aa268d1ff089d8e28c4ee1aa1d8791690045f17c"}}
{"design_id": "766b4e272d58", "module_name": "asic_oddr", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oddr.v", "sha256": "b6e8d9b59985d2b9329356adea6ce9fa4ea5946529766bb88efe30f3ea54a8c4"}}
{"design_id": "768598e8e861", "module_name": "IDDR", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IDDR.v", "sha256": "44d8e9446fa9f41b31a175ab038ece6e5cf0903f36bd2fe85d3b0e46174e45aa"}}
{"design_id": "773151b26a15", "module_name": "axis_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_switch.v", "sha256": "ccfe5eb62d5fead748bca36f22a0012599af46d2ec486c1bb091308234510e6f"}}
{"design_id": "7756823e4eb4", "module_name": "stream_mux", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/stream_mux.v", "sha256": "d752dd163cb4e4d943464edf3e2e7e28f49ebea19bb45521b214b111784fe24d"}}
{"design_id": "778ae1abbb3a", "module_name": "test_axis_frame_length_adjust_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_frame_length_adjust_fifo.v", "sha256": "7b76f453e9805a4b595917cbdb73899480c3d6517d8f6184353b7a7fbac97d3c"}}
{"design_id": "77950bf6df3d", "module_name": "sirv_tl_repeater_5", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_tl_repeater_5.v", "sha256": "155959f1b8ed74c808339a03d1a30f253f328685650ba7cde07def693abb258f"}}
{"design_id": "779bf3a9debf", "module_name": "pcie_axi_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_axi_master.v", "sha256": "7003ff8fe3dc795f90bf9f7517a093d38ac3fa5cd8a8843fb2104bae410c3897"}}
{"design_id": "77e23591d8af", "module_name": "axis_ram_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_ram_switch.v", "sha256": "bd73b8a982759528b4dd9a6e33396ce5c443ebac0f74ffd23d69ee4bc4b2de42"}}
{"design_id": "77ef9e2d4358", "module_name": "riscv_xilinx_2r1w", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "core/riscv/riscv_xilinx_2r1w.v", "sha256": "4687449f57fcd33deef04bff381a6f4af27b31699d9baa3173eab9283837abab"}}
{"design_id": "77f0a90d93f8", "module_name": "reset_control", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/synchronization/reset_control.v", "sha256": "c0df22f5e60cb3abcefcef7984ad7a96121b3415a5b87c9ee4514348a49a2c17"}}
{"design_id": "77f4bb0b3e97", "module_name": "axi_ad7768_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad7768/axi_ad7768_if.v", "sha256": "7a7de4105968dc316353920c19557af1c0c75e83ddbd6d92d6881c5ffc9c6f4c"}}
{"design_id": "783107a541e8", "module_name": "gearbox_20_67", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/gearbox_20_67.v", "sha256": "276dc17d87a3054e4e528c4be6cb509d84b06bdae4feb8096f933b580ed7de82"}}
{"design_id": "7841f58c652d", "module_name": "sirv_repeater_6", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_repeater_6.v", "sha256": "e34e5052dbc923128707dcef456439d264d23787a2036c8b69081dbe3c7ae1b4"}}
{"design_id": "7853aac494ed", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ExaNIC_X10/fpga/rtl/fpga.v", "sha256": "ffe96e3b6ef2f0370c7403b3c91480f3dd2724ab74345f14a9e28f860a1a85e1"}}
{"design_id": "78565cb860a5", "module_name": "pcie_us_if_rq", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_if_rq.v", "sha256": "2435f567585bad3583e5e985b42e49d3613921ea6e921bd45fb216ca9310a4b1"}}
{"design_id": "7863aa5f3d7c", "module_name": "lfsr15_8", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hsci/lfsr15_8.v", "sha256": "b7564b68dada30d8e400ed94bb07f0a296f22e5f8ea2b10550125e512ee3a754"}}
{"design_id": "7869e8593380", "module_name": "pcie_axil_master_minimal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_axil_master_minimal.v", "sha256": "2ab3e1318504cd50e96c03d79a651e5b23556e7a97d2ba4b4df7e7fa0cf7107f"}}
{"design_id": "78b077671cf2", "module_name": "axis_eth_fcs_insert_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_eth_fcs_insert_64.v", "sha256": "5b9b835fff3a497eecb0f0a406f6b98c351776c64af99bd98ccec82623aadd59"}}
{"design_id": "78b3dafaa23b", "module_name": "sirv_uartgpioport", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_uartgpioport.v", "sha256": "75b0b10aafd67cbc2d703f398f9c96df85f51c5397aefeb4c436ab8d7a43e181"}}
{"design_id": "78e7180b1e43", "module_name": "sirv_AsyncResetReg", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_AsyncResetReg.v", "sha256": "3a1ba85313b901a458725072abbeae820f9e9de84e3675dd636c0524a9c51eba"}}
{"design_id": "78fbfc145700", "module_name": "e203_soc_top", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/soc/e203_soc_top.v", "sha256": "97bfe3fd1119b4682589a48f57a60e108d496e2c1c1a53d7c0255b50fe79c02b"}}
{"design_id": "79107ce94be9", "module_name": "oh_aoi33", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_aoi33.v", "sha256": "c0abb7a213041e4a866c478b7f4261d97a9b0ff854c9786ef967b237562ba44c"}}
{"design_id": "79380736a7a0", "module_name": "zipdma_ctrl", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/zipdma/zipdma_ctrl.v", "sha256": "2bd6dd81d58a695fc348e7e800a8a1a028d6680e99da0b52a65f9b4dad799be1"}}
{"design_id": "79864b45c6bf", "module_name": "ct_ciu_ctcq_respq_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_ctcq_respq_entry.v", "sha256": "52ffe9d9703b4fd067a50eb3360d4c21134b51b9c8f500df3f5d6b97f3d84c4f"}}
{"design_id": "798b737409aa", "module_name": "axi_fmcadc5_sync_calcor", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v", "sha256": "4aeceb7cf19f209a1ed82856c94b7bcea8f7206bccf93ecf196c4d58ae0b3ca5"}}
{"design_id": "79c5db293074", "module_name": "nv_ram_rwsp_80x16", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsp_80x16.v", "sha256": "124d3c023c63286aa3199d11d2105e6d204b14bd64e4cf3e2504394c9cbc1152"}}
{"design_id": "79cdadd6f8c4", "module_name": "test_udp_ip_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_udp_ip_tx.v", "sha256": "5e3e8084795908cb66ef0da27f80ad05215b59867d8fc5859bd759e842fd578f"}}
{"design_id": "79dda40e296c", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9009/zc706/system_top.v", "sha256": "999ec1ecce2ade5dc336c6fae001744bc243c4a35b5d74d59aee6fe04292cac0"}}
{"design_id": "79e9b9f93a77", "module_name": "plic_hreg_busif", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_hreg_busif.v", "sha256": "a81cccc22349e124615b95203d94a89a9e67124aa70ce3706e1f4199289bb9cc"}}
{"design_id": "79f5e8321aab", "module_name": "pcie_tlp_fc_count", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_tlp_fc_count.v", "sha256": "05c471cf6dbb21948be867340aed09507e369dff69aeb4cd7c13f7845ff191be"}}
{"design_id": "7a214fd5d879", "module_name": "eth_mac_10g", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_10g.v", "sha256": "bcc21bf95ef53be1f5c363d1e03368c1b99bfe520273a5c576f7024cd13ac310"}}
{"design_id": "7a766e6b0040", "module_name": "sirv_AsyncResetRegVec_1", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_AsyncResetRegVec_1.v", "sha256": "d492c602befa1dc7ef6bca079324ff75a1f7adcba5240b61cab83db76164528b"}}
{"design_id": "7aa294bb4fbb", "module_name": "clkdivider", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "fpga/hbirdkit/src/clkdivider.v", "sha256": "bb8cf1603b147d801604ff9c5e49c3a43f6e5712e3ea6f3026cc9813d860073f"}}
{"design_id": "7abc49ec0e57", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "mio/dv/dut_mio.v", "sha256": "765cdc2bc7e2f286ab6872ae78053d4636ebd5808a5cbad5e239179ad459b8fe"}}
{"design_id": "7ac5fc10c497", "module_name": "ptp_clock_cdc", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ptp_clock_cdc.v", "sha256": "0c8c81cff4871a4b27998a12403902bbff9c6fc22e66d70eea3150b4e79b9dc6"}}
{"design_id": "7af9f9f92d16", "module_name": "test_udp_ip_rx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_udp_ip_rx_64.v", "sha256": "d8c2502ed30b43be04c02744ee28b6263df8e950df59f00c2fa88ac5bad5ef06"}}
{"design_id": "7b0570d1cae8", "module_name": "pcie_ptile_cfg", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_ptile_cfg.v", "sha256": "56017776de17ea7a42e739a9a663d5b596874b539931dc26e2d6bbede8c3a909"}}
{"design_id": "7b2446d226de", "module_name": "axil_crossbar_addr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_crossbar_addr.v", "sha256": "a687cef2780b571b1a1b85746e4e093d0d7131d77bf9d6c610f333b0e27480c0"}}
{"design_id": "7b362fe57b6b", "module_name": "NV_NVDLA_SDP_brdma", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_brdma.v", "sha256": "e89ed8f4da3a3be97f17b62eec208eac66cc1732ce058855c995d2e5bb9fd724"}}
{"design_id": "7b3aa7578610", "module_name": "etx_arbiter", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/etx_arbiter.v", "sha256": "f529960e92c70e79a6629368fece7d4385104a6cdc1af27080ea3d9d175e4ffc"}}
{"design_id": "7b65c90717ea", "module_name": "dma_if_pcie_us", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_if_pcie_us.v", "sha256": "702429a9b90920cf7b688cccacb408083d8914084612f74c427439ffbe722060"}}
{"design_id": "7b66a174a003", "module_name": "elink", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/elink.v", "sha256": "6b714a031198c3f6dd338554846266f1b5291c6918f6c7cebf1b86c601b1d614"}}
{"design_id": "7bc1c86e954d", "module_name": "udp_ip_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_ip_tx.v", "sha256": "c5e3cd5a4e4b418b7315e7c39f6e0124bd0fcec3f4e073d949ae1235a606846c"}}
{"design_id": "7bc96a8d7b85", "module_name": "ct_had_ddc_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_ddc_ctrl.v", "sha256": "e2d9e79ccf952983538e8a26dbb64e71676b8d739cd629c9168019e0bf2e192e"}}
{"design_id": "7c0fd732cc2e", "module_name": "spi_master_tx", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_spi_master/spi_master_tx.v", "sha256": "b8063cd98a9d1e4709adfb266d59e2e0d1a8a56ac64cfcb64e9ebcf04cea33f0"}}
{"design_id": "7c60ef7220f3", "module_name": "ssio_ddr_in", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ssio_ddr_in.v", "sha256": "ba78fec337d5889fa87acf31079c44e19b2592da714347a5c1b915284707bf1b"}}
{"design_id": "7c8de8d576ed", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9083_evb/zcu102/system_top.v", "sha256": "812a0091e17e7f1e025d1fe99e20bd9cbd6065b5013da60738c68f3399d8b524"}}
{"design_id": "7cacbc834dfe", "module_name": "test_axis_async_fifo_adapter_8_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_async_fifo_adapter_8_64.v", "sha256": "ba54fff33b6656529a24fb13a19a728197c31eab7fef7c97e16889e7dd062b27"}}
{"design_id": "7cb5c488f61e", "module_name": "ct_fadd_onehot_sel_d", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fadd_onehot_sel_d.v", "sha256": "762f1603f65ead1bcb6fc6102399a73b93684fbf3d3ffde6380c1c61b23350f7"}}
{"design_id": "7cc3a1fbb75a", "module_name": "test_udp_demux_64_4", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_udp_demux_64_4.v", "sha256": "c84e0c0e8a8d6b0b71058f48c185de53747bc643f0647b52f1bff1d9a6ecc8c9"}}
{"design_id": "7ce428a7d968", "module_name": "dma_psdpram", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_psdpram.v", "sha256": "5d06400fe8c45ff27a0eaabb33206b684b2f2c5adf59353fcabe891e9ac29513"}}
{"design_id": "7cf302bca021", "module_name": "asic_ao21", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao21.v", "sha256": "3f5544dbe50436869263de756914e67da218ac7c3abe7c047259f44459160ad6"}}
{"design_id": "7d12a91880f1", "module_name": "axi_adxcvr_up", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_adxcvr/axi_adxcvr_up.v", "sha256": "9ede3d6e6c09159c97109a03ce4cf542d90cfe3930582b04f2e367d52c2f9e54"}}
{"design_id": "7d12cca2915f", "module_name": "oh_bin2gray", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_bin2gray.v", "sha256": "26fc4516ad541ed68d43772a9a0d08981a569d6424603adca50f7fbb434a8a36"}}
{"design_id": "7d24c6d98858", "module_name": "altera_avalon_st_clock_crosser", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/altera_avalon_st_clock_crosser.v", "sha256": "8aacb793aa81947b6c7ea29693aba6d44f7a739aacea450f561db95cd9c3c436"}}
{"design_id": "7d3b066b8b57", "module_name": "axi_fan_control", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_fan_control/axi_fan_control.v", "sha256": "d7e54f725517c2d5e64436ef62277a32c254dc4fbee1b1113d0d72d6f3cd48a7"}}
{"design_id": "7d63de1b773f", "module_name": "axi_ad9625_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9625/axi_ad9625_channel.v", "sha256": "8a7f0e241408f209b5db1546825f49713f713eb83c7bf4de8194a4cf2c7ed0e5"}}
{"design_id": "7d77008fa46f", "module_name": "test_axis_cobs_decode", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_cobs_decode.v", "sha256": "d881dd11679bc5d73b6dd1001450372800a32c3690c53901595e392a98dea534"}}
{"design_id": "7d92c4fa2c10", "module_name": "ad_mux_core", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_mux_core.v", "sha256": "3bca634dc2cb009ff8072409b3b6f990baecf560af433612d8ca000cb5cf1d51"}}
{"design_id": "7da1287e1c99", "module_name": "ct_f_spsram_2048x88", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_2048x88.v", "sha256": "68d1eb5754394a8ff066f3a22535f64e31dee17ff96979f95ad88aa36911c439"}}
{"design_id": "7dbb93200cd3", "module_name": "ct_fspu_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fspu_ctrl.v", "sha256": "fe5fc0f74a873c9de0ba76b1eacca92d980c11808b2b3d8bfd1d7ef56b6bb2b5"}}
{"design_id": "7dd2897fee33", "module_name": "axil_reg_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_reg_if.v", "sha256": "6aac73057466d4c16f79a5575f5fb4136b494d41cd63aaa83fefe90319006a39"}}
{"design_id": "7deb4ddc0a97", "module_name": "mask_32", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/translation/mask_32.v", "sha256": "3850683a93401f75328cd37392a7a4ad8052b47d9dab45bf56e9f71468b6f747"}}
{"design_id": "7e0bb690efff", "module_name": "pcie_tlp_mux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_tlp_mux.v", "sha256": "73fb3855161b9c81801ee612152046791b9fee5a75b36f1919d5268c5138c340"}}
{"design_id": "7e32e273e444", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X25/fpga/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "7e6f418dbed3", "module_name": "axi_ad9684_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9684/axi_ad9684_channel.v", "sha256": "da8e088ccc3271aa978c578dbc6ed3d279a424a99a246a673bb768076c2fe458"}}
{"design_id": "7eccd544ecb1", "module_name": "plic_32to1_arb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_32to1_arb.v", "sha256": "23f640a6f9ee83202c9532667f991aa72f087d812cd6185d56882536e2f02b81"}}
{"design_id": "7f12e007c601", "module_name": "oh_oai21", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oai21.v", "sha256": "5bf54d2aec1fc15395ce257170e860fce8bab2870ec42d73d5d9a059b8b51a9f"}}
{"design_id": "7f34fc4ed630", "module_name": "PGAOPV_INVD2PO4", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/PGAOPV_INVD2PO4.v", "sha256": "62c1e551ed5120b369784d9f009e41a73c473108377fb2e4cd505f4f84e3edb8"}}
{"design_id": "7f424919f842", "module_name": "NV_NVDLA_CACC_CALC_int8", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_int8.v", "sha256": "2f7102971bc0bd83ef7146bdf33baff76e055bc09490ed6c4f55d405f0006c00"}}
{"design_id": "7f42ef28d470", "module_name": "ct_ciu_vb_aw_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_vb_aw_entry.v", "sha256": "2e41d64a433dc733d16da5e9cb1d85da6ca3aae77e87b9c2f1ba38f635ac28f7"}}
{"design_id": "7f48f92f80b7", "module_name": "axil_register_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_register_rd.v", "sha256": "ae1a35af8be25b3fa0f2245ce0ca33287f566279ea5bcf04d822d417ffa5f463"}}
{"design_id": "7f7f6e8e2ede", "module_name": "ram_block", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/ram_block.v", "sha256": "3be24b32024d84c9742209ab951d119f4b5e3e43d16d3517c9ebdb1123656ab4"}}
{"design_id": "7f8f2b35ff20", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v", "sha256": "6cc7034eff8cbaa2b940cf7dbb076a0542e72ab9ff665813875d2b14a8ea51c7"}}
{"design_id": "7fa767267a64", "module_name": "ct_piu_other_io_sync", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_piu_other_io_sync.v", "sha256": "076c83e5e26943f54fb8e5af0cb1aee54ad9275dfc89a3a00a75de3514436bee"}}
{"design_id": "7fbe14f16557", "module_name": "axi_fifo_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_fifo_rd.v", "sha256": "ecdb21c322732e8e185c6a1408438565d6990f852a8f271b5442e878174a20aa"}}
{"design_id": "7fc995b2071a", "module_name": "phy", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/DE5-Net/fpga/cores/phy.v", "sha256": "7725db673c8ec470a2ed994343745a969aea39dc7859dc06245a768c602016d9"}}
{"design_id": "7fe28f158b3e", "module_name": "axi_ad9122", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9122/axi_ad9122.v", "sha256": "6a545b131706f064b8c2c7b7411cba46ae50a2b332451d2728e03b836a10f973"}}
{"design_id": "7fec23be12bf", "module_name": "NV_NVDLA_partition_p", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/top/NV_NVDLA_partition_p.v", "sha256": "c4f90c34ea6d25557c90c8ccfbeb069ff400904265cbaa996f0b0468bb45e24a"}}
{"design_id": "803c0cf3dcf9", "module_name": "NV_BLKBOX_SRC0", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/NV_BLKBOX_SRC0.v", "sha256": "fe3978819dcf6fb174fded0a74f0330175d4aa2781af5e1ae0c42310490aed30"}}
{"design_id": "803f75f0dd47", "module_name": "servde1_soc_revF_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servde1_soc_revF_clock_gen.v", "sha256": "0f3358efb4652ec165171ee2e56d2931f7467c793189d2644f801594dabcee4b"}}
{"design_id": "8061933bb718", "module_name": "oh_xnor3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_xnor3.v", "sha256": "c97e3e0bc432c9d33b3ea8f718842e566fffc5941b3ec6c9edb6b8dca95093da"}}
{"design_id": "807c72a31ecc", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "8098c44c1399", "module_name": "lc_mult_signed", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/lc_mult_signed.v", "sha256": "e0e4f73d2c409575afde8ea80527844b6f9253072698b6909fa6d9b9ca4f3ebf"}}
{"design_id": "80efd0112e6c", "module_name": "axi_hdmi_rx_tpm", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hdmi_rx/axi_hdmi_rx_tpm.v", "sha256": "2257b482c5c8a84ed19bb03104ee67b67f784263502e89423a9466839d6ccaf4"}}
{"design_id": "80f07f222d8e", "module_name": "oh_oa211", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oa211.v", "sha256": "bede766d658b803f6d0604d150c58573642493488cbf62923ee3452be6c4d722"}}
{"design_id": "811d09c97c5b", "module_name": "oh_dsync", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_dsync.v", "sha256": "f226086230f687d8a403518c1780cd7c6a1e6d15522bb8da91635a0efd95a49d"}}
{"design_id": "811db17ba2b2", "module_name": "gth_i2c_init", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/HTG640/fpga_cxpt16/rtl/gth_i2c_init.v", "sha256": "62b87caa1275f7c2867bba1e42dfeba4a0071d3c8e8acc7882c996c04b228c8f"}}
{"design_id": "812aab5dad36", "module_name": "ct_spsram_2048x32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_2048x32.v", "sha256": "d365d90fd1e44f45bfa6e19d02b9068fd4e085394b1eb0311fabe1fe345b532f"}}
{"design_id": "812c3d7e907c", "module_name": "NV_NVDLA_SDP_RDMA_REG_single", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v", "sha256": "47923cc47149e7a7d6f67699d6ec2ab0b99d6e5469dcad1f97be4f01585a399c"}}
{"design_id": "813b71dccacc", "module_name": "axis_xgmii_rx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_xgmii_rx_64.v", "sha256": "0c5e88eed6941360134d4fb5e456cfa205327191592f4d03f5e6fe9af914b7d5"}}
{"design_id": "8145baeb211e", "module_name": "sirv_ResetCatchAndSync", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_ResetCatchAndSync.v", "sha256": "e0a7274d248d4a5b080c66c0471a3e3b1b421751d12aedd8938172c3ae9d0147"}}
{"design_id": "81ba406bbaa4", "module_name": "oh_sdffsqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_sdffsqn.v", "sha256": "60261bfe64b833fb015642a94d264b790c40a0b5fc4257f3ae18cfa56d789309"}}
{"design_id": "81cec866f359", "module_name": "mdio_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/mdio_master.v", "sha256": "63308070f3c1f13bb298f0e971ee5ff9fd161fe4070b5eddd85278f6dd043da3"}}
{"design_id": "81d3ec491b89", "module_name": "ecc_encode_32bit", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ecc/ecc_matrix_32bit.v", "sha256": "50569c550db7eaf09c2e76cd85ade1fdc647d4d48a231aaef63b9a6a1a9d732b"}}
{"design_id": "81eaccb15663", "module_name": "ct_lsu_rot_data", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_rot_data.v", "sha256": "224fcd2abecb91c43c0d84a609e0d5560f48aff4a210ccfa17c31c76729c661f"}}
{"design_id": "81ec59384e47", "module_name": "ct_spsram_512x52", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_512x52.v", "sha256": "138cba4bf8288129c2a8b5c629db8b3b9bc96d77c04d63546bd877ec320d3de4"}}
{"design_id": "81ed17839bdf", "module_name": "sirv_qspi_flashmap", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_spi_flashmap.v", "sha256": "75169e7054b1b42e626528a728c668d105eef0a510d23c7d70e454572efa1f3b"}}
{"design_id": "82009e4d1cc2", "module_name": "ad_dcfilter", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/common/ad_dcfilter.v", "sha256": "31548e95c6a70cd874787c19c0a293e91db9d7bb4cde177a65d695033586ef0f"}}
{"design_id": "820d8ef08627", "module_name": "plic_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_ctrl.v", "sha256": "173c0e1e02bc81310b762666c38ef9a227513e57fbb1e1f2f6fa5c31ea3c2730"}}
{"design_id": "821cb1102867", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "821ed50b621e", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga_axi/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "8221a8b65411", "module_name": "pcie_s10_msi", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_s10_msi.v", "sha256": "ebe335e19b1fffcedad2f108284ab0c943da91e7563ba6444e8d2a54a4ffb195"}}
{"design_id": "825c195ed620", "module_name": "asic_aoi211", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_aoi211.v", "sha256": "02a9cbe3dfd29366db7a344cd0c6331e860c47e99d997ae5fff2e5e224adff11"}}
{"design_id": "829d5bcb67a2", "module_name": "ct_ciu_snb_dp_sel_16", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_snb_dp_sel_16.v", "sha256": "434d37c7d1b7727cf4c113f209aa0866e180d084ff7b8c3505667eb7cc162315"}}
{"design_id": "82d076c4a055", "module_name": "ct_rtu_pst_vreg_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_pst_vreg_entry.v", "sha256": "ac976ab610cbaa7416d628807722a40bf0fb964fcee3dbcb11613bef0d45a98b"}}
{"design_id": "82ff9c6f7a97", "module_name": "avl_dacfifo_wr", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/avl_dacfifo/avl_dacfifo_wr.v", "sha256": "6e3ff517cc1d0354312ee584c3f03809c07037068e85b4212a80b3a3ec2a483a"}}
{"design_id": "8306c599ade4", "module_name": "ct_iu_rbus", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_rbus.v", "sha256": "fb7cdc7abfed4f8a9b7502286de450d00f5afe42d4d20c8ef2d7162b485803e6"}}
{"design_id": "833ecf36a67f", "module_name": "ip_eth_tx_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ip_eth_tx_64.v", "sha256": "ec717dc691fc9ede23ec9e593aad84683c68efd245fe088c1ecab18eb74b1e8e"}}
{"design_id": "83762f527e1a", "module_name": "pcie_us_msi", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_msi.v", "sha256": "dfc267f8bebf21226263959f2525ad04fd0b3660a0765f2508505e30e75bfd53"}}
{"design_id": "838bada613a6", "module_name": "test_axis_baser_tx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_axis_baser_tx_64.v", "sha256": "13d8f2aa418c36ef5d69072d608b79f4e45f8ce1b330ea866f06aafa69420b8a"}}
{"design_id": "83b2b63148c4", "module_name": "axi_ltc235x_cmos", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ltc235x/axi_ltc235x_cmos.v", "sha256": "1d5f8344e9d2a7a9cc2185ae8aecc352d53beb01c3231d653cacb651804b25c7"}}
{"design_id": "83ca75b1f1a9", "module_name": "gcd", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/pdn/test/sky130_power_switch/netlist.v", "sha256": "79cb392ed43bf1d94f0074876f4c0671bc1be94c719c7d4717a63e5d02b5e746"}}
{"design_id": "83ff7b8dfbf1", "module_name": "pair_sad", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/video/pair_sad.v", "sha256": "1ff3d550e078bf797a506e72c87bd3a71548bbca6ad9b95e4b0f597500d3feb8"}}
{"design_id": "8411d4bcadb4", "module_name": "spi_master_rx", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_spi_master/spi_master_rx.v", "sha256": "c3b0c7a3cece7606ad5a464c0cdb6b084adbccc5424b7720d768b3812464c124"}}
{"design_id": "84328baf8045", "module_name": "ip_complete", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ip_complete.v", "sha256": "4c0aac8dc73adac3f867f0f15e6bb1abda45f4d7417878e149fea79500791f63"}}
{"design_id": "8442ee5bb3a9", "module_name": "axi2ahb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/axi/axi2ahb.v", "sha256": "75734fa187130f8c816a536397cf50c573dd002e6769cc4261cd0e128495e8a8"}}
{"design_id": "844f3950a0b4", "module_name": "desc_fetch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/desc_fetch.v", "sha256": "737b061f564b476037aa3050a4aba05721baa20720927f688b4d46e83f072285"}}
{"design_id": "8452521e6c16", "module_name": "approx_fp_invsqrt", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/approx_fp_invsqrt.v", "sha256": "2ef9d93fa433a7d1b67def99340bd3c2f3db9eae809212a6c759eeb72f5db844"}}
{"design_id": "8454f7b72b2e", "module_name": "xcvr_ctrl", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/IA_420F/fpga_100g/rtl/xcvr_ctrl.v", "sha256": "c119978a2fb8e94b3547b893b045ed2e0eff835de41e0e41c0faa4bb1800472c"}}
{"design_id": "846b1a91aee1", "module_name": "oh_mux2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mux2.v", "sha256": "e3109c1c98dd88fa3d28c9dd8143d40bf8ca8876f269dfedacecab98b45d3574"}}
{"design_id": "84b5e6ee854f", "module_name": "service_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/service_clock_gen.v", "sha256": "ae338b7c1cc8bf4b6cedf6d057ab4ab38964546385b03a28d8e0a56db4cdfb8f"}}
{"design_id": "855951907040", "module_name": "axi_ad9361_rx_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/axi_ad9361_rx_pnmon.v", "sha256": "f366c19ff2687bc745df0b4306874f71e9e338aa61c13260d504043dc439db8f"}}
{"design_id": "855bd9122be2", "module_name": "ct_sysio_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/cpu/rtl/ct_sysio_top.v", "sha256": "ce012f74b22a5897a22ac9e912f78ed4a71032fd6d8d144e8165166669c528b3"}}
{"design_id": "85e95f3d25b2", "module_name": "test_udp_ip_tx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_udp_ip_tx.v", "sha256": "5e3e8084795908cb66ef0da27f80ad05215b59867d8fc5859bd759e842fd578f"}}
{"design_id": "85f21802d672", "module_name": "asic_sdffsq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_sdffsq.v", "sha256": "a497178e11df98b630d28d5bdca8abf8a1a03ec17bacb7e322ab649f968b248c"}}
{"design_id": "860c5c1e15e8", "module_name": "ct_spsram_8192x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_8192x128.v", "sha256": "98944d44c57cc9f76d420d2a7b4b384a6b0a2b759cb4bca1358af2c4b2fea3f8"}}
{"design_id": "8629c8b38c0d", "module_name": "sum_of_3bit_pair", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/sum_of_3bit_pair.v", "sha256": "b3231bcec73a22ff8e6fcc14ec89dbb4f7665abd06df34ce51c458713d0fb8ba"}}
{"design_id": "862d1ad5cb2b", "module_name": "true_dual_port_ram_dual_clock", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "dual_port_single_port_ram_templates/Verilog/true_dual_port_ram_dual_clock.v", "sha256": "e971b06e56168622c36b9dcbdda01b9a93b27cd4a22ff64535db8db5eba1e3d8"}}
{"design_id": "8646e6a1e5cd", "module_name": "test_ip_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_ip_64.v", "sha256": "32b4dd902d60e1a5699f3ad2f0e612bd1c3331334bc2d1fce80c29db6464805b"}}
{"design_id": "867619884ae5", "module_name": "NV_NVDLA_CDP_rdma", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v", "sha256": "ff79b39358244b5e543adcdcecfb6922a9293b630f05711336db8cf9d431bda3"}}
{"design_id": "868b72b5a227", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ada4355_fmc/zed/system_top_bufmrce_en.v", "sha256": "c20d7ab9f57a5ce3ea1fc6e9ce4336a37aecc5a100a6a7a6195f9a6d89c4d49e"}}
{"design_id": "86e8267b7ad5", "module_name": "ip", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip.v", "sha256": "ec609c681edf22a1bcf803255dceeffe4b668b541bce00105e7c0cdaec710c42"}}
{"design_id": "86e893693876", "module_name": "sirv_pmu_core", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_pmu_core.v", "sha256": "3ed3bb469b56a27dc5de9645017a23b19b280dcd2b384c801ca336a58be11b37"}}
{"design_id": "8703ef9b632c", "module_name": "axis_frame_join", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_frame_join.v", "sha256": "32cfa21be9b9bd7c8d23abab54586cd3665a59dce042a3147b695dc663ef0388"}}
{"design_id": "8729783c0671", "module_name": "axis_cobs_encode", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_cobs_encode.v", "sha256": "2aa1b67891e6bf61941678ebbccd0f24ffa1fa0ef899206f06f1f435830ac9b9"}}
{"design_id": "873605b32f45", "module_name": "pcie_ptile_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_ptile_if.v", "sha256": "8cec3e6e9188f3b849447ff9d4af703f9af9bd0d74ec0454951ea0187aaf41f6"}}
{"design_id": "878f67a11742", "module_name": "pcie_tlp_fifo_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_tlp_fifo_mux.v", "sha256": "509ae597705cf3ee22447edd7176b1ad6c34a3d49d95a4994ad37dae50161ee9"}}
{"design_id": "879230a4de26", "module_name": "axi_ad9434_core", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9434/axi_ad9434_core.v", "sha256": "f92d0f6b8d6cfec641568f5a4fb81e697a953e26d7555e86c1075289e6fcfd4b"}}
{"design_id": "879a076f9aa7", "module_name": "ssio_ddr_in", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ssio_ddr_in.v", "sha256": "ba78fec337d5889fa87acf31079c44e19b2592da714347a5c1b915284707bf1b"}}
{"design_id": "87a1fe51d93b", "module_name": "ct_spsram_512x22", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_512x22.v", "sha256": "111138792955a884678ff2cfcc892cb4b28144c2ce63c3af06e5c7cb6a2858bf"}}
{"design_id": "87a24e2b1f62", "module_name": "avst2axis", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/S10DX_DK/fpga_10g/rtl/avst2axis.v", "sha256": "19a432301f81764397d6c6328d26864502ec95f3f2173465bc88f3d418ce1468"}}
{"design_id": "87b166181a6c", "module_name": "sirv_queue_1", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_queue_1.v", "sha256": "18c323d0b78c5fe6bc3d8e40a4faa8afa107a57d5f1e7a19f7c821442d1bd95b"}}
{"design_id": "87b71935c0b8", "module_name": "pcie_axil_master", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_axil_master.v", "sha256": "4b66bd5dc9c5ed0c2616773a310e0deb6b3e0ecd7958f176a33b850feeaf7767"}}
{"design_id": "87e77b8c7905", "module_name": "system_top_cmos", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/dc2677a/c5soc/system_top_cmos.v", "sha256": "ae01d96ead443a340aa2ff4818c0df5b24a750746f89362d937c3e96425505e9"}}
{"design_id": "87ef97397f62", "module_name": "NV_NVDLA_partition_m", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/top/NV_NVDLA_partition_m.v", "sha256": "9c4895c84cbda661ae5813cdced21427d3fd2f8287a91559e09c3524734a92ee"}}
{"design_id": "880251b25f28", "module_name": "fec_rot_7", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_7.v", "sha256": "d53c1c8222224d6aaeeb90ef97e703298a91109b2a8f8b826b4f1d3359f6e3b8"}}
{"design_id": "8826d6f21b31", "module_name": "NV_NVDLA_RUBIK_dual_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/rubik/NV_NVDLA_RUBIK_dual_reg.v", "sha256": "5b567b031cb1731e0401096b1e3fc5875b13d661375544e49d7812bfacb3b469"}}
{"design_id": "882ca105e7af", "module_name": "NV_NVDLA_CACC_single_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cacc/NV_NVDLA_CACC_single_reg.v", "sha256": "e9c1412a6ebc6d3072b530c34a316ba0c3f01821ca4f4db5b1ce69202a259cc0"}}
{"design_id": "886cbecf0405", "module_name": "soft_ecc_ram_64bit", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ecc/soft_ecc_ram_64bit.v", "sha256": "ece5b3b463db7f8680d71fb6c1f10e28788edf68e45bc337bac208b1e9ca5906"}}
{"design_id": "88924380a26e", "module_name": "sys_pll", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.v", "sha256": "8383756703fb6a5a291283642a109b2c995416afd38e0826b4da1a4c8769773c"}}
{"design_id": "88937e430e6a", "module_name": "axis2avst", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/S10DX_DK/fpga_10g/rtl/axis2avst.v", "sha256": "3822c5400411975ac818f40c72e985e7eaae4d5fe4a089b9874a19ef3143bfd0"}}
{"design_id": "88a3b4ec4862", "module_name": "BUF", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/BUF.v", "sha256": "07c12512e55e8c33bad7745f32b55b911fabb15b35624f29ee3f6292d375757b"}}
{"design_id": "88b3a5a3d6a7", "module_name": "asic_oai21", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oai21.v", "sha256": "19e44afce1c76a3a60086ceba032d78b7be6cb12c3aa496e13cb5cd4ac56edf7"}}
{"design_id": "88c35b358c34", "module_name": "p_SSYNC2DO_C_PP", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/p_SSYNC2DO_C_PP.v", "sha256": "a51723a62dc27ede57300c54a4b4f45b4352cbdec550b488dac62504251180f1"}}
{"design_id": "88cc6db3404b", "module_name": "eth_phy_10g_rx_frame_sync", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v", "sha256": "6bdf55011c55cd96c10aa462e8dbb6c77a1aa8ddef602cb8bc551e2f2b9491e5"}}
{"design_id": "892895f1decc", "module_name": "axi_ad9467_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9467/axi_ad9467_if.v", "sha256": "9d46b2181197006c3e6d7a46a297237598646d285988592d7415be8a691245ef"}}
{"design_id": "893834bf97b5", "module_name": "util_sigma_delta_spi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_sigma_delta_spi/util_sigma_delta_spi.v", "sha256": "2ebc7dc9ea9588f1cfa1f4e16499fce03264268450aec996587c3f5da7630f88"}}
{"design_id": "894b3bb4f521", "module_name": "sirv_jtaggpioport", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_jtaggpioport.v", "sha256": "a9e64f06152c28426c04a7064651439b5bcce827ee7cb43ccd226b8673679d64"}}
{"design_id": "89663390db17", "module_name": "hsci_mcore", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hsci/hsci_mcore.v", "sha256": "8dd001da0bfead13841be67f253c166e1969699a596167984438fa1ecd3cad59"}}
{"design_id": "897cb47a363a", "module_name": "pcie_us_if_rc", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_if_rc.v", "sha256": "538cf0c6caaa535c7d4f28f96dd9ac3e385a8c26ccf3e5ec4c30d7a8954b4eed"}}
{"design_id": "899495b1dff9", "module_name": "asic_xor3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_xor3.v", "sha256": "369fa161e4373094f239b642d34af6d6ca710bdd00842c52fc70e8f8208d598f"}}
{"design_id": "89a18f7c347f", "module_name": "axi_adrv9001_sync", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/axi_adrv9001_sync.v", "sha256": "650ad4dd88179e99cfd95a65dcafae5aa4ed9dd496e167364bb825863568f106"}}
{"design_id": "89af76450787", "module_name": "eth_phy_10g_tx_if", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_phy_10g_tx_if.v", "sha256": "eb7b22ac57abbc4ee887ac945ac66507aeda06417c7dd188cd8e7a5e713f3ac4"}}
{"design_id": "89fcbbeef589", "module_name": "fifo_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/fifo_tb.v", "sha256": "4d1a6373e7c4c549f803452d0888c856ea3c5d93dd7c558a15fc48e1bf83981b"}}
{"design_id": "8a09e47705da", "module_name": "mqnic_l2_egress", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_l2_egress.v", "sha256": "4ccb720835b9e9fca9ec0b1b131375bc84ee7b74d65688f2626985e629f2db90"}}
{"design_id": "8a34e26dcee4", "module_name": "oh_clockgate", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_clockgate.v", "sha256": "92a4275f1541485b8298b222147d0c356470609ff77f83e7047ebbb0f57c316e"}}
{"design_id": "8a56f74ea4d9", "module_name": "axis_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/IA_420F/fpga_100g/rtl/axis_fifo.v", "sha256": "b49606665dcef7805fd2cc42ee8514402898a0dee1af2df61dd0a2d332d19a28"}}
{"design_id": "8a5d08948a94", "module_name": "retu_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/retu_top.v", "sha256": "ee9fdebcd22742c23f7f66b617272fa62c845b9a2a2186720ef9c7ad68609e90"}}
{"design_id": "8a8e7cca9bf4", "module_name": "bilbo_lfsr", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/random/bilbo_lfsr.v", "sha256": "cd34fdc670b64bdfd95684f1ee263ebc49844310292ec3411fa393b09e452e85"}}
{"design_id": "8acfb10b6fd4", "module_name": "eth_mac_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/S10DX_DK/fpga_10g/rtl/eth_mac_quad_wrapper.v", "sha256": "8f791e0327b0b071b54096258ad651b3cf9a0e56f0d2e6041511068c9a31ba5e"}}
{"design_id": "8ae6e3e4907f", "module_name": "RAMPDP_160X16_GL_M2_D2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMPDP_160X16_GL_M2_D2.v", "sha256": "2ba7e1072266ce672eaa54711ae027666794e5f14d906a635bae8ba7584f3f9e"}}
{"design_id": "8b0982fdbdcd", "module_name": "RAMPDP_32X192_GL_M1_D2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMPDP_32X192_GL_M1_D2.v", "sha256": "acd2600b2137015e7ce0bc9d8afee5da07946fa6e655bbf2ed32b8492c1e55ac"}}
{"design_id": "8b0d28703506", "module_name": "axi2axilite", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/axi2axilite.v", "sha256": "580d92d48d0cdce0e9b83041b5f288d6d7ee8be7e9ab4425d450d975bd70cde0"}}
{"design_id": "8b1ce56386f6", "module_name": "ad_datafmt", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_datafmt.v", "sha256": "de24bdd0e3a27f2888c408339c4d6ab94cb75bcdb2dbab9dc9bfcf70072ec470"}}
{"design_id": "8b2d47bd4ebf", "module_name": "mii_phy_if", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/mii_phy_if.v", "sha256": "6e752ba3e981758f1a4d01b54e3b6855111ca5bad5ceab77f972fba935095c00"}}
{"design_id": "8b318fc476d7", "module_name": "cal1d_fp16_pool_sum", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/cal1d_fp16_pool_sum.v", "sha256": "7c5b25ac061590d62d0fcec93367cc2f9d336714c63f702f5dc0486b08cf7647"}}
{"design_id": "8b3baeeb51bc", "module_name": "axi_ad9361_tdd", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/axi_ad9361_tdd.v", "sha256": "6ec902636a9cf0573fb3a3ea9e8aa08679b09df7045b95f330a694169d34ba03"}}
{"design_id": "8b557102635c", "module_name": "NV_NVDLA_CDMA_WT_wrr_arb", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wrr_arb.v", "sha256": "9acdcad2331a06813bf4f332ab270aee0ac608bfc06b7408d55a53c623950b82"}}
{"design_id": "8b590cb9a5d8", "module_name": "float_to_fixed", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/float_to_fixed.v", "sha256": "1554376b1b4e72abd08fc8bfe67446dcd38e2142d17c5b3abce11da179e49d24"}}
{"design_id": "8b7d0bac2c17", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "12f9316c4c4e2563251588e10f6c64b2f4a2690951837caebeb46b602f496901"}}
{"design_id": "8b8ae47b9cc5", "module_name": "pcie_us_axi_dma", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_axi_dma.v", "sha256": "7594904ccb5af430a891ccc93dde2b1e1bc6b996a635a614bfb3648837f6bae1"}}
{"design_id": "8bc3312db0b0", "module_name": "test_dma_client_axis_sink_512_64", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_dma_client_axis_sink_512_64.v", "sha256": "8d2028d70cad563656a49b91fcd5b80d7f8ff1d2e7702655996b2796ecfa33b8"}}
{"design_id": "8bebe6c5b2b3", "module_name": "test_axis_crosspoint_4x4_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_crosspoint_4x4_64.v", "sha256": "43d74b3c219a749e86eec246d8b95bb06e3f85c1edacfe3967217d35b5005fe3"}}
{"design_id": "8bfa3d171638", "module_name": "axi_ad7616_pif", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad7616/axi_ad7616_pif.v", "sha256": "6ef72d54dd501b2849b33468b03fbb16082e5b4090df2256958b59fdfa22c642"}}
{"design_id": "8c17a8ce218b", "module_name": "FP17_TO_FP32_mgc_in_wire_wait_v1", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/HLS_fp17_to_fp32.v", "sha256": "3abde28315619c2124f21b6073dfd03f5432cd9b66181832c341de29ea1bcd52"}}
{"design_id": "8c246e531487", "module_name": "compressor_32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/common/rtl/compressor_32.v", "sha256": "cb552cdf693f16f34f62c4ba52565ec43cb08c990893d62460abdc772812f5a2"}}
{"design_id": "8c41defd0b75", "module_name": "vga", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/rtl/vga.v", "sha256": "dbcc0fc4c6495fd541dde63808a8609d20e82f2e2213aaedf3290794b464067d"}}
{"design_id": "8c4c865ea6cc", "module_name": "emesh_rdalign", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emesh/hdl/emesh_rdalign.v", "sha256": "3ee52f7cf91188d009ca7441ea2bd0594cb1fbaa3cb76b30a9cc2997028544aa"}}
{"design_id": "8c557c80a119", "module_name": "eth_phy_10g_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_phy_10g_tx.v", "sha256": "3ccc7a6dd0c23bd94ca9ab8f603408e823cc000f4429013deeb9b9714c0f7769"}}
{"design_id": "8c57fb2e43d6", "module_name": "NV_NVDLA_MCIF_WRITE_IG_cvt", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v", "sha256": "200b955ce75f2d89faf936e138bc5b83bfb2cbefbfa1cec4bffdb56165e83698"}}
{"design_id": "8cb6eeffa5f8", "module_name": "irq_rate_limit", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/irq_rate_limit.v", "sha256": "fd9a6bc5366f61e8739a7844a6628a1a7cc08e0aa72871d12babd924ce08a65d"}}
{"design_id": "8cc44b38d417", "module_name": "asic_and2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_and2.v", "sha256": "8a671cfcf6070837fa5165f6f42c5e34845853bbf05552354e0c292dbf294889"}}
{"design_id": "8ceb74bcfd1b", "module_name": "tcm_mem", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_tcm_wrapper/tcm_mem.v", "sha256": "960e745a4c9ff4c48b7114070d90c54cd415e6a4cc8ab12dffb6100ae4b15504"}}
{"design_id": "8ceda44ec6ae", "module_name": "RAM64X1S", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/RAM64X1S.v", "sha256": "f04f67ce243e60841426e744b4dea88b5dd2da530def24989daf83823fc734f6"}}
{"design_id": "8d0a450aa18e", "module_name": "asic_nand2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_nand2.v", "sha256": "175a7f52ebfb3bb21b8c555a347e2ea3bfac8bed0309311b4dce8e0806fc132d"}}
{"design_id": "8d65a675c316", "module_name": "axi_ad9122_core", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9122/axi_ad9122_core.v", "sha256": "91c0de73288bc48a769479f8d1395f7a90c9c8006ef946d17278f5192533b3d5"}}
{"design_id": "8d6b0409d753", "module_name": "NV_NVDLA_SDP_nrdma", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_nrdma.v", "sha256": "b3b00d4e863e962615ae7c6388196d4681a99dad06e87805db762d0faa8d46f5"}}
{"design_id": "8d6b14171e73", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/Alveo/fpga_25g/rtl/fpga_au50.v", "sha256": "525d1db702b0c47b6d949bee025f9595beef98342b152edb3d48d7a931532aea"}}
{"design_id": "8d77fdc9ad22", "module_name": "axis_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/fb2CG/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "8d81a4e8e940", "module_name": "ad_mem_asym", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_mem_asym.v", "sha256": "9e186cd5218bf64fd09e10bc5b2713438b4598a1041e28c637733d3aac466ed4"}}
{"design_id": "8d8ba53b6148", "module_name": "servant_ecp5_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_ecp5_clock_gen.v", "sha256": "67e510653a8f4f5e9e31388e4c11fcd84d31746a206d307712235e8d5ba69f59"}}
{"design_id": "8e0b30c7a3e8", "module_name": "axi_ram_rd_if", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_ram_rd_if.v", "sha256": "a7e81cb85d1c922b29c01ac9c3570f8cebc16e676fd0f9df3cbb37443a394a3d"}}
{"design_id": "8e0f030b43c5", "module_name": "NV_BLKBOX_SRC0_X", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/NV_BLKBOX_SRC0_X.v", "sha256": "4ffd42b467eb78226528a384b6af69f48dca9a98cbb02c58b1ddf9216fa18355"}}
{"design_id": "8e166cfd97fb", "module_name": "sirv_uart", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_uart.v", "sha256": "48091e2c80b5be0c559af6419f7836295ccfadbc36f0819da9adb362b9a1fc23"}}
{"design_id": "8e51031c04a4", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emmu/dv/dut_emmu.v", "sha256": "019933b0272665a548bd3e529ee166416760d9a78302e6920d6bfd3bf4a6931b"}}
{"design_id": "8e737f84f6ae", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga_axi/rtl/fpga_core.v", "sha256": "e210704f4227d0c3ee57cddb686473b59e883c2b9d39e4f5b2b1d9d777c76a9a"}}
{"design_id": "8e89a7472d2c", "module_name": "NV_NVDLA_sdp", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_sdp.v", "sha256": "28a0084f92eb7e1fabed2dd8838bbb273a65fcbd6af277f8a499f3c772780213"}}
{"design_id": "8e923d54660f", "module_name": "test_arp_eth_rx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_arp_eth_rx_64.v", "sha256": "de02bd0b980d3c6c7fcd39e9b03fb656258fb2871d958ba73de187ccabfd236a"}}
{"design_id": "8e92edd82591", "module_name": "axi_dmac_resize_dest", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/axi_dmac_resize_dest.v", "sha256": "becd54ba543f94f237241a9bf5f657a32fb2d86f7b36c0df3e88a17f2017bfd4"}}
{"design_id": "8ea2e315d385", "module_name": "oh_stimulus", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_stimulus.v", "sha256": "5d5f52c1b34f14df900c83c3b0ca54a8a35e365bb20b3ee7d5936ca004ff788b"}}
{"design_id": "8eeaa4e797a5", "module_name": "oh_nand4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_nand4.v", "sha256": "a30bd04f0c904260b4ed0aa1525e8ce110cc1a9e6600e12232ac4ab67e30f552"}}
{"design_id": "8eed3d88814d", "module_name": "axi_cdma_desc_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_cdma_desc_mux.v", "sha256": "9ea015e93946c6415f9ce87b4119e56dbb30db2ecb189dc8b8849dcb3fa3c5f7"}}
{"design_id": "8f176b1c5377", "module_name": "spi_master_controller", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_spi_master/spi_master_controller.v", "sha256": "09f113d747e103f3067366529a3116e480f13cb656547a6726eb4465688759a3"}}
{"design_id": "8f332adcf3b5", "module_name": "axi_ad9361_lvds_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v", "sha256": "444b9cef303d45462ae4f17d9f82b33a8a337af12cb8901bde4655bf965ca45a"}}
{"design_id": "8f36c9dfc8da", "module_name": "mqnic_app_block", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/app/template/rtl/mqnic_app_block.v", "sha256": "fde6ad5f2d9cbfac6d9e3e11943dfa168da80393976ef85b18a1e2c2762fc40b"}}
{"design_id": "8f4fa1e88ca9", "module_name": "eth_mac_dual_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DE10_Agilex/fpga_100g/rtl/eth_mac_dual_wrapper.v", "sha256": "d4b9d772cf254c0721701b8a9fc19850575f148fe4840c5a405bae136938057c"}}
{"design_id": "8f6e7f0ade89", "module_name": "ct_fadd_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fadd_top.v", "sha256": "873af8c989a3ada6a3ee4d9a504982b6d6b9042b4cf870872dca02e29b222327"}}
{"design_id": "8f7589d230ed", "module_name": "ad_ip_jesd204_tpl_adc_regmap", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v", "sha256": "e9f94dad3e5e897201a6406b5baeefadd11a20bb7f7aa00a62767afd695afa5b"}}
{"design_id": "8f84e289a469", "module_name": "util_mfifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_mfifo/util_mfifo.v", "sha256": "67ae747e4121967fc08645aade682efe1bd3f94f2aefd9982467af9373a9825c"}}
{"design_id": "8fa776cb4ded", "module_name": "axilfetch", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/axilfetch.v", "sha256": "737a8873cbe0204212d5a5f603a4303be1bade15b8826305996ec6bb6610569a"}}
{"design_id": "8faa48fc9313", "module_name": "axi_gpreg", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_gpreg/axi_gpreg.v", "sha256": "de996307637619a28d70d4daba3ca396bb815d1cb4e4c52d02953f71e4c117b8"}}
{"design_id": "8fac1cb5c5f1", "module_name": "led_sreg_driver", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/fb2CG/fpga/rtl/led_sreg_driver.v", "sha256": "91ef35971991fd2b536d1ccb263e892441e9fa0d631e8a14d3db896238f3cb34"}}
{"design_id": "8fc44901f72a", "module_name": "dv_top", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/testbench/dv_top.v", "sha256": "79d8d702f3a587123dfd7b5bedd257aa66fda5a53324a7e4f937e4c7c4262109"}}
{"design_id": "8fd9516d3a2c", "module_name": "oneHotClk_async_read_clock", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/oneHotClk_async_read_clock.v", "sha256": "2c901affebaf0e9cc6ae02700a6947e5f2c4e093367891c3b7b3068d6443f24b"}}
{"design_id": "8fda136fb505", "module_name": "nv_ram_rwsthp_80x72", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsthp_80x72.v", "sha256": "c766bf937cf004e7a59acdd3dccfb533d9839427a01450ade6bab81a69c75cd0"}}
{"design_id": "8ff30217d16f", "module_name": "ct_spsram_2048x59", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_2048x59.v", "sha256": "a198f8c05f8f3bc6a524f9f3bdda3ca08abca7d89104c930d403d0a8d49dcf16"}}
{"design_id": "90160f79c872", "module_name": "sha_padding_b_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/sha/sha_padding_b_tb.v", "sha256": "05467f7c1f0b8651a0da70c61b458a8cf1d4a8554051934463ab68df35f12b53"}}
{"design_id": "9021e308f619", "module_name": "plic_granu2_arb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_granu2_arb.v", "sha256": "2177ca71c987171e10823c0deab2ff39ec826544034a662a082ca6a57a6c4e24"}}
{"design_id": "903a2962fa8c", "module_name": "asic_ao31", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao31.v", "sha256": "6a5fe42ec96e875c08fbe34bc5c45dabb11e2aaadea4a8a16ee04935cc46e1bc"}}
{"design_id": "905b736b9d2a", "module_name": "ct_lsu_snoop_resp", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_snoop_resp.v", "sha256": "6cb04d9983b8c0e88c13912349061a271bbff5e0775713aa2b1da76b471cdf47"}}
{"design_id": "906b3b773d82", "module_name": "burst_read_master", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "avalon_mm_master_templates/burst_read_master.v", "sha256": "a80bdb4894ef432658f2e3be1cac2f80a728373b493bed68f360f37ab30fc83c"}}
{"design_id": "9073fe9db6ea", "module_name": "eth_axis_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_axis_rx.v", "sha256": "4fb3ab7e0ccafdc85a46f37e533b7fb6e74a7101cfc18757126175ed01354d59"}}
{"design_id": "90a0dd049a7b", "module_name": "clock_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/clock_rom.v", "sha256": "5f36ce6da2c5650c7a5be2c7fce8088121599e1e6d9bd1acf2f88737b1ca9b13"}}
{"design_id": "90a705507bb2", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga/rtl/fpga_core.v", "sha256": "bf982090247fae4d90d3eeb787666bc90d30e594d127bb0e12ffff4fc5651ac4"}}
{"design_id": "90b80ff5efdc", "module_name": "axis2avst", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/axis2avst.v", "sha256": "3822c5400411975ac818f40c72e985e7eaae4d5fe4a089b9874a19ef3143bfd0"}}
{"design_id": "90ebe823b1b7", "module_name": "fec_rot_10", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_10.v", "sha256": "21f43b222232ddbdfc9452225021be5a7e979af15dd5690ffe8fb47102b14f7d"}}
{"design_id": "90f12a786f6f", "module_name": "NV_NVDLA_apb2csb", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/apb2csb/NV_NVDLA_apb2csb.v", "sha256": "7b82c8b364ce06b451d2893f9271f67006513daae46ef7fcc1fd473a1abf0e3d"}}
{"design_id": "910e58140041", "module_name": "axis_async_fifo_adapter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v", "sha256": "9dc661b88d459a318e40722df277720fe64ef4309230462e8538b1a44da1d57c"}}
{"design_id": "911385612caa", "module_name": "gearbox_33_32", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_33_32.v", "sha256": "3a06459d45a6651acb88aca91e6a7328e9c2c58ef1e7ddd9e9672de10f70519c"}}
{"design_id": "912008f7f970", "module_name": "ad_pps_receiver", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_pps_receiver.v", "sha256": "16dc9d3702dfc4c95e3868c3e164ba58c4ce998849b822e86b123ad25e0742c7"}}
{"design_id": "91404990a0c4", "module_name": "i2c_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG640/fpga/rtl/i2c_master.v", "sha256": "ff46775d79e00853c9008f668ae9dfb71ad2cb93d6fec783aa08e527f207efb4"}}
{"design_id": "914fbb985b50", "module_name": "pcie_axi_master", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_axi_master.v", "sha256": "7003ff8fe3dc795f90bf9f7517a093d38ac3fa5cd8a8843fb2104bae410c3897"}}
{"design_id": "9175b8d5e4c2", "module_name": "eth_gth_phy_quad", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/HTG640/fpga_cxpt16/rtl/eth_gth_phy_quad.v", "sha256": "a9c86e87b929bcc3fc4048415a3a05d8c504b15b8224bfed62f2bb95a72b9261"}}
{"design_id": "919f8d0254c2", "module_name": "dv_driver", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/testbench/dv_driver.v", "sha256": "cd0542dc398bf9791f61bbad745e7d5d99a0b1ef7d183664af876be42607536c"}}
{"design_id": "919fe54cc775", "module_name": "NV_NVDLA_CVIF_csb", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_CVIF_csb.v", "sha256": "646fc0ebaf5234675b9a264e29d25cea8624be3f7bb966712d76c80f47f6ad5c"}}
{"design_id": "91d39f4584d2", "module_name": "asic_clknand2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clknand2.v", "sha256": "e5a6d6e9c51ec469d7ed6e86269b623287618cacbd48b943f68e8e57f6694d0c"}}
{"design_id": "92431e081d61", "module_name": "fifo", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/fifo.v", "sha256": "911ee3e6d89b79905953905806c9651909ac7e3b41dcb9fe2fefc3b7664aa358"}}
{"design_id": "924411a2ffc2", "module_name": "axis_rate_limit", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_rate_limit.v", "sha256": "bdfb4e29768c5224c543098765b8d648f3fe774eb42643c289d85b446414d155"}}
{"design_id": "925fefb82002", "module_name": "servant", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant.v", "sha256": "4e36259237896970acb838ef8792ace30e7817b300ad652cb9e2aad716113c6c"}}
{"design_id": "926d73dc9133", "module_name": "ct_had_common_regs", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_common_regs.v", "sha256": "f9ea8822b32e135df903226c630800d3768817b0654c1016564a356db367abd0"}}
{"design_id": "928d3cc1e03b", "module_name": "ad_serdes_in", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/common/ad_serdes_in.v", "sha256": "1aee243f828b5994c333473cee06a556a2c375cc2012eef5d43c7ae99de513f7"}}
{"design_id": "92dfd8888172", "module_name": "NV_NVDLA_CSC_single_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/csc/NV_NVDLA_CSC_single_reg.v", "sha256": "06876d139f422ed8022469c9667020851d9204d47b180ea3cbbaecfd7751d86f"}}
{"design_id": "93195bfb7e49", "module_name": "ct_vfalu_dp_pipe7", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_vfalu_dp_pipe7.v", "sha256": "385dc331e29bc0131f8fd17f31407ffe3201f45fd705ff6a75b49aba74ce6c52"}}
{"design_id": "9319fca4be3d", "module_name": "ct_spsram_128x144", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_128x144.v", "sha256": "f6e12aea810347315bf3cc477e803c6f3d467008e488ac09d3716760898e05b8"}}
{"design_id": "933100cf6051", "module_name": "ad_csc_RGB2CrYCb", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_csc_RGB2CrYCb.v", "sha256": "03073dcc1f6611d723301641f42311811d9bc100a7d03753ecec35b0920519ee"}}
{"design_id": "936e54c7f7a2", "module_name": "apb1_sub_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/apb1_sub_top.v", "sha256": "74c7d9cd56e216a06dc62964b6ebf33bf6b33f46579ef3ddd04eeff2328f6645"}}
{"design_id": "938b4f44d256", "module_name": "pcie_us_axi_master_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_axi_master_wr.v", "sha256": "4b7c25ae0fee8c62a6278701dae11b6b6c2500d6ca55d0bbe9976f2401d1090f"}}
{"design_id": "93fac93dd143", "module_name": "axi_ad9783_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9783/axi_ad9783_channel.v", "sha256": "cc90627a6e7079e01549e81a87b6097cee56cd44b38bd2ca7672aee1168c9ad0"}}
{"design_id": "9421d0abedf8", "module_name": "mii_phy_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/mii_phy_if.v", "sha256": "6e752ba3e981758f1a4d01b54e3b6855111ca5bad5ceab77f972fba935095c00"}}
{"design_id": "9440ea506475", "module_name": "ct_idu_is_biq_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_is_biq_entry.v", "sha256": "6eeed6b50296ae3c0252fcd4bf22d06843129c66158aeaf33180bd1f6aa8c307"}}
{"design_id": "94426178d643", "module_name": "ct_fcnvt_stoh_sh", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fcnvt_stoh_sh.v", "sha256": "908b8e1b1a0498b0195a429d0692491626cd431a541c91589b3532c9f7a44d23"}}
{"design_id": "9458a180716f", "module_name": "NV_NVDLA_CMAC_CORE_rt_out", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v", "sha256": "f262f2fd6705a73e437a405b02c6a08563bd50c27d8a08f21beaac9787ce3b1c"}}
{"design_id": "946d93d4aefc", "module_name": "uart_baud_gen", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/uart/uart_baud_gen.v", "sha256": "d003fefe9619cc31dc2a6aa77f688421f6331911226d224429c14175dfe81e13"}}
{"design_id": "947191ddea22", "module_name": "td1", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/pinswap_hier.v", "sha256": "acfd6fbef9191373e3400e5bf02069dcd63f3fb6e19c8747d2f4e080ac383ecf"}}
{"design_id": "9473b621d575", "module_name": "axis_xgmii_rx_32", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_xgmii_rx_32.v", "sha256": "b1537e8511db33898a5e6357d7c4c88ba672455bb051ab57e3ea77d2dd64e584"}}
{"design_id": "947a5e107d34", "module_name": "zipdma", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/zipdma/zipdma.v", "sha256": "2bd872e4352e8c33cd787d31d02ced3e16ce78202fb82715eb8164fbffbc88d2"}}
{"design_id": "94a03e239566", "module_name": "ct_hpcp_cntinten_reg", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_cntinten_reg.v", "sha256": "d58cf856950b463f0513340da7a6f5ce84b5e8752ec87c84f252ff68409cc5df"}}
{"design_id": "94a13b1cf0ae", "module_name": "quad_stream_grabber", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/quad_stream_grabber.v", "sha256": "736064fe921f7202adf43e57ec4864aab3649d238816203ce087abc44af65ec7"}}
{"design_id": "94ac607a74be", "module_name": "dcache_mux", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_cache_axi/src_v/dcache_mux.v", "sha256": "c6489050cf64368e2da4cb6e820591fd2064e2091faad508f87048ede44cdf4c"}}
{"design_id": "94ae8aa54ec6", "module_name": "axi_ad777x_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad777x/axi_ad777x_if.v", "sha256": "0a80132566a6d95e815a6f6298b293ea88b7d6f5830f5793fbee729440d423f2"}}
{"design_id": "94da0087f7f3", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9081_fmca_ebz/zc706/system_top.v", "sha256": "c5440bd6d95b131aaa793fb76ba1e2e107329ef70c2bd89372ec8f8a50b44bb7"}}
{"design_id": "94eb61df01a9", "module_name": "ternary_add", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/ternary_add.v", "sha256": "d42821bca6c5ad99341f8fffce26b1890b2aa0e29e7124f2bde27da37c3cd007"}}
{"design_id": "951ef1dcdb3f", "module_name": "sirv_AsyncResetRegVec", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_AsyncResetRegVec.v", "sha256": "c356203f72b2610e2db6cf2d9d7e700a5def2d56ed94281e3e8085f40a188f33"}}
{"design_id": "951feac59153", "module_name": "wdt_biu", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/wdt.v", "sha256": "476cbe0d85f68a784ecd2de82360ee7385a15d550f6dcc07f90bb1693d69a09b"}}
{"design_id": "952952b9668b", "module_name": "gth_i2c_init", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/gth_i2c_init.v", "sha256": "62b87caa1275f7c2867bba1e42dfeba4a0071d3c8e8acc7882c996c04b228c8f"}}
{"design_id": "9549d4b4dbf2", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/S10DX_DK/fpga/rtl/sync_reset.v", "sha256": "a6701ef1a7412be2615592c2db70a7cebc07baa208ffba79e34ecaedf0289a91"}}
{"design_id": "9551f147bf6b", "module_name": "test_pcie_us_axi_master_rd_256", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axi_master_rd_256.v", "sha256": "9d95b9eddff4cdbfd1c8231445b3dbeeff38c25e9c438b4859fcc7bfb8e09771"}}
{"design_id": "95619027fc34", "module_name": "axis_async_fifo_adapter", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_async_fifo_adapter.v", "sha256": "9dc661b88d459a318e40722df277720fe64ef4309230462e8538b1a44da1d57c"}}
{"design_id": "9573559c0bda", "module_name": "axi_laser_driver_regmap", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_laser_driver/axi_laser_driver_regmap.v", "sha256": "efe1c926c6556e6d678574d23b8c75c5834e1671613a48c9d448e92e3770c60d"}}
{"design_id": "959291fe3d48", "module_name": "fmcomms11_spi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/fmcomms11/common/fmcomms11_spi.v", "sha256": "b4091ca8845c169b888d0fc34b7cbcd7ca9aa1f21f608dc2a1f6b088f23268e2"}}
{"design_id": "959dcd04e665", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9213_evb/vcu118/system_top.v", "sha256": "3f06d26b8e3eeecfd1f640ea5a68cfaa9360087eb1282f8c641aa4b2395065a6"}}
{"design_id": "95be23d3e5af", "module_name": "prio_encode", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arbitration/prio_encode.v", "sha256": "887d759c1c9116c72336f710bef879168d3b1c3d24a0f7521bf7bec0e1b613fa"}}
{"design_id": "95bfe2d07328", "module_name": "serving_ram", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "serving/serving_ram.v", "sha256": "506c71b24e8e7364a9b2acea400a1ba6edacb48c6ccf34816f673694bd9bb6ac"}}
{"design_id": "95d26e145ec5", "module_name": "pcie_us_cfg", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_cfg.v", "sha256": "74b252e326c2ea4942c9e1379419cc7127a81e00860db57a502e5556bac73e73"}}
{"design_id": "95dd2886d977", "module_name": "axi_ad7606x_16b_pif", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad7606x/axi_ad7606x_16b_pif.v", "sha256": "8b8d5176d7184c0d0b40751ab5af6a197f6f172bd5b725eb67fb0c82c9ffa4c8"}}
{"design_id": "96183586d5f4", "module_name": "test_axis_ram_switch_4x1_64_256", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_ram_switch_4x1_64_256.v", "sha256": "8d23f22eb01ada5c7e243d4ba9e195fa3611fe0c3a6a9343d15e81e78fe69910"}}
{"design_id": "964c75ba547b", "module_name": "axi_crossbar_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_crossbar_rd.v", "sha256": "d42e9e3b8d94ba9e135cd3e5841ee570dce2cd15d50e7ca87621c8eca246fe98"}}
{"design_id": "9656ad69701b", "module_name": "ecfg_if", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/ecfg_if.v", "sha256": "f29850ef464e9aae15c8730ed08893974876c9e47c2a2c74080682693d31ba90"}}
{"design_id": "965704182bd8", "module_name": "asic_ao221", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao221.v", "sha256": "b3db8399f494b115889e1b41d4c8598a6bd826a8e22f716cb80d2b4f1f5ec050"}}
{"design_id": "967d3acc9116", "module_name": "oh_sdffq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_sdffq.v", "sha256": "96bdc021a260337a2253b181c7c68e8e3444dbe5c7bfc696b92a5876189bd539"}}
{"design_id": "9689fcfde0ba", "module_name": "eth_phy_10g_tx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_phy_10g_tx.v", "sha256": "3ccc7a6dd0c23bd94ca9ab8f603408e823cc000f4429013deeb9b9714c0f7769"}}
{"design_id": "96908adc85ee", "module_name": "ad_csc_CrYCb2RGB", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_csc_CrYCb2RGB.v", "sha256": "88d3ddec9f1f2ecec66d03f9c68afafa29433ac0b72cad70ae6b9d1eebaef242"}}
{"design_id": "96a464a94ab6", "module_name": "edma", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "edma/hdl/edma.v", "sha256": "3c9372eb2759a78bc5fb26cf630bbe572bfb33d19d4f401a771e101d36841edc"}}
{"design_id": "96cc483b518b", "module_name": "eightbyeight_sad", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/video/eightbyeight_sad.v", "sha256": "52e980b2141f0503ec0730246c0a64b75349da842245e272fb1fd0a3582d88b7"}}
{"design_id": "96eb8973c896", "module_name": "gearbox_20_66", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_20_66.v", "sha256": "fafea71298af6d559d0a2f9ffc975a771967aa81a9ea81548fe9e396e1049705"}}
{"design_id": "970e2be65d6d", "module_name": "IBUFDS_IBUFDISABLE_INT", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IBUFDS_IBUFDISABLE_INT.v", "sha256": "be897ed18d0fd351ec522eaa3f385150504a19888b86c318612f0604fd031584"}}
{"design_id": "972d9d0d61fb", "module_name": "int_sum_block", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/int_sum_block.v", "sha256": "54bd3eb57fb362180b9e2ba00ad8878c9818d660b718131b4b2cf05dc0cc2199"}}
{"design_id": "97657a0f93eb", "module_name": "pfcache", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/pfcache.v", "sha256": "bb9bf05651bc4e27e9e97261b1c16ffe2967e4209041c0207a36096dd42d5918"}}
{"design_id": "976b9840c897", "module_name": "axi_pulse_gen_regmap", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_pulse_gen/axi_pulse_gen_regmap.v", "sha256": "458f302e328177dc502415d2df365d0828049c220380c1e9d7f8cb9192214d2f"}}
{"design_id": "97829966de71", "module_name": "oh_buffer", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_buffer.v", "sha256": "4a342b1856ba2e5fcd92474baf6cb894e390b5d695fa7eb96e6d3f98e46c3f26"}}
{"design_id": "97a5cc6dcaa6", "module_name": "pll", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/rtl/pll.v", "sha256": "2daadf5f5216b9f95071a19ca14806073f42174768661e15a93e853c146859a6"}}
{"design_id": "97b950206083", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/DE5-Net/fpga/rtl/fpga_core.v", "sha256": "3a949a4ec103f57d9a5b9ae2cf2144212008747ae8090cef538da9c588f7687c"}}
{"design_id": "97c77df8cc93", "module_name": "axis_adapter", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_adapter.v", "sha256": "4b9b6649f12e374c24d36f2d42680ecf1f38cca8ae4fda7fd68dbf722b6c8140"}}
{"design_id": "97e86647fcf0", "module_name": "ct_piu_top_dummy_device", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_piu_top_dummy_device.v", "sha256": "0752529ec4ac2efac0c2e41c37e5c355abb397e1bc870d332403053ca8704d9f"}}
{"design_id": "981a0ca2bce2", "module_name": "NV_NVDLA_CDMA_single_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdma/NV_NVDLA_CDMA_single_reg.v", "sha256": "c059e274422d40522e3aef391bd12898f24ea796c48e0b860acc4546f3009a96"}}
{"design_id": "9822bd45819e", "module_name": "pcie_us_axi_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_axi_master.v", "sha256": "7f5dff665f88b4b66da5d9de6a96594b06b10468fdded3a4d56492e79f9cdf65"}}
{"design_id": "984063cac9a2", "module_name": "axis_xgmii_rx_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_xgmii_rx_64.v", "sha256": "99d2b9578a440f03232030ae3da72eeb26b1cc8321d8eb24aa34b98fc46b8ccb"}}
{"design_id": "98a7cab8ec6b", "module_name": "ct_fspu_dp", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fspu_dp.v", "sha256": "fd56774e1411b8bf8a77f66b5ce33dfe84462348a0f76b3b51b0e23d4187ec19"}}
{"design_id": "98e8b2852c4b", "module_name": "serv_top", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_top.v", "sha256": "c35b88bed5732309069203b2d04421622eaae108d5bf5daef3de273daf43388e"}}
{"design_id": "992960aade6b", "module_name": "servile", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servile/servile.v", "sha256": "3ae38ac0da93e45980dc01ba41c40ac3ebf84f4ad505889971cb9ae00b0fef02"}}
{"design_id": "99497c324a1b", "module_name": "dcache_axi_axi", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_cache_axi/src_v/dcache_axi_axi.v", "sha256": "ff193fd3a4db1b1d6b0df8eee80356b95972e40047162985e7dbea3a0f061151"}}
{"design_id": "99a0ef4e2e79", "module_name": "ip_demux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip_demux.v", "sha256": "cbebf69d304360e1619ab14609c26fc3e4af718ccc35a3395e14f4e4d0f7887b"}}
{"design_id": "99a16d0f8e76", "module_name": "IBUFE3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IBUFE3.v", "sha256": "67f79334cfb7b2f17a2f9ac8d5b644f0a7352d734ff59bafeec7b2d31726ad9b"}}
{"design_id": "99c773eaa802", "module_name": "cpl_queue_manager", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/cpl_queue_manager.v", "sha256": "1fd90351f92575064c732afbc1c39833dd7b8ce0f102797c32448ce0175e9db4"}}
{"design_id": "99f714c4b095", "module_name": "icontrol", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/peripherals/icontrol.v", "sha256": "d27a66ebf70fd3675892d6581cdeaa797c210d0558e15cb0a5a3c217d2fc4e40"}}
{"design_id": "9a59db819d5f", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v", "sha256": "3acbafc43b45c863c1a6d00ca8d5e8810e7fed0fd0785bcaedbc4bd0450e0828"}}
{"design_id": "9a679fe44578", "module_name": "axi_ad9684", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9684/axi_ad9684.v", "sha256": "63ca1c31637b82a82fe76e0ad3ed2f6e9c7baf75da62ef86c398415d3226051c"}}
{"design_id": "9a69033a5ecc", "module_name": "ssio_ddr_in_diff", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ssio_ddr_in_diff.v", "sha256": "21b2150f2027498fc56d9505b7e3ca454e45a35966561ec4e0bfc3303c230e94"}}
{"design_id": "9a8257f41af8", "module_name": "axis_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/AU250/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "9a98b4cf81b8", "module_name": "oh_bin2onehot", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_bin2onehot.v", "sha256": "3860a4b7227b25034fb463d4943b1c7c8c19b8a06e4498775d7b04c4c082a058"}}
{"design_id": "9acb30b13d6e", "module_name": "axis_cobs_encode", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_cobs_encode.v", "sha256": "2aa1b67891e6bf61941678ebbccd0f24ffa1fa0ef899206f06f1f435830ac9b9"}}
{"design_id": "9ad86037ad79", "module_name": "dma_if_desc_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_if_desc_mux.v", "sha256": "338312e054d42f66e36f28946e05b94646ed1d63a41e4e740f4d55cbe278e64b"}}
{"design_id": "9af4030f9eeb", "module_name": "crc32c_dat64_only", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/crc32c_dat64_only.v", "sha256": "412c0cf853311575ffb52dc860e6d0916c0e7686f21e967289ea39042f0322f1"}}
{"design_id": "9b476fa41092", "module_name": "ct_idu_rf_pipe1_decd", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_rf_pipe1_decd.v", "sha256": "646f25d57817258816a7aa31bbb45cf14508d996f4bba95f912e38a41bfc744a"}}
{"design_id": "9b5f871cd013", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga_axi/rtl/sync_reset.v", "sha256": "67ea2e751ee7cdf5c7528902eab32a63f11bd090e1380934fd7334b361c7d874"}}
{"design_id": "9bb156bc33b1", "module_name": "nv_ram_rwsp_160x16", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsp_160x16.v", "sha256": "d38ae5530f632a878317c487b985107765e8a17cdbd7c397670979db15a0166e"}}
{"design_id": "9bcb28f26df0", "module_name": "axis_gmii_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_gmii_rx.v", "sha256": "70d8e8c8ebfd22b8b1ffed7c077864c1944217a3e844f79cd3807cc41cf449d7"}}
{"design_id": "9be6d3eacef4", "module_name": "test_axis_ram_switch_1x4_256_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_ram_switch_1x4_256_64.v", "sha256": "50c24e7b393641529facbb26a0362084715e9abe10134c683b9bfa79acb35a5e"}}
{"design_id": "9c0fb2d609e5", "module_name": "pcie_us_axis_cq_demux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_axis_cq_demux.v", "sha256": "77a17587a5e1202fd02713cb4170526db4f748f0e7e86807627783c9c7ff277c"}}
{"design_id": "9c2637671aac", "module_name": "twelve_four_comp", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/twelve_four_comp.v", "sha256": "8fa91fa720c1a739746bb374a1d71048cb5bee3877a34a5072a830c28c666186"}}
{"design_id": "9c2ffaef3c8d", "module_name": "util_rfifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_rfifo/util_rfifo.v", "sha256": "822bf91e7fabbb4984514cf0cc1ed48107eb1ca36d5472b2386174382e950d7e"}}
{"design_id": "9c4df79a33d8", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga/rtl/sync_reset.v", "sha256": "67ea2e751ee7cdf5c7528902eab32a63f11bd090e1380934fd7334b361c7d874"}}
{"design_id": "9c64a998d71b", "module_name": "pcie_axi_master_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_axi_master_wr.v", "sha256": "fa7debc2b126487a53fb76e8830be316ce179a510c150368b33d4255d4c6b934"}}
{"design_id": "9c7e509ddf47", "module_name": "ip", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ip.v", "sha256": "ec609c681edf22a1bcf803255dceeffe4b668b541bce00105e7c0cdaec710c42"}}
{"design_id": "9c87d1dddcfb", "module_name": "adrv9001_tx_link", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/adrv9001_tx_link.v", "sha256": "8a04b09ead3ef915cbedd2cf808c93e23f5c72f5a9461b223ef992997e9a87c2"}}
{"design_id": "9cb1966149b9", "module_name": "util_delay", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/util_delay.v", "sha256": "23aef750063af48fe613471a9a80a84e3c292a82fc50e4e9739feef3a4c8cdc7"}}
{"design_id": "9cd70286622a", "module_name": "axis_xgmii_tx_32", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_xgmii_tx_32.v", "sha256": "a90912e4c71597be643c120af26412018e1a0b18185afa615f295819c83da4ce"}}
{"design_id": "9cf25dcfa24c", "module_name": "NV_NVDLA_SDP_WDMA_gate", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_gate.v", "sha256": "60ba40bdc254146da4b6f471888021de411e02d3087f3ebc2dae1f68775b24c6"}}
{"design_id": "9cfe537be77d", "module_name": "spm", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/gpl/test/region01-spm.nl.v", "sha256": "6bb51d515f756e9d5873ea6f66cd93e372c4ccd547081e977ba22c39ae1f080a"}}
{"design_id": "9cff5c736bcb", "module_name": "tim5_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/tim5.v", "sha256": "f2c0d5485a3639150f082888c337805926f095f11303bd0e376e7ad3c7b84dbe"}}
{"design_id": "9d6347ef4656", "module_name": "axil_register", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_register.v", "sha256": "b58a923af874e3600727f214897cee868591487d8c00317603e5f232d9f2fa07"}}
{"design_id": "9dae3b35b717", "module_name": "axis_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU118/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "9db5a15aad31", "module_name": "axi_adxcvr_mdrp", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v", "sha256": "e90ca364f296bc049340cf206a1e85ef75f72a42a6f41622389e03ffc68f63f6"}}
{"design_id": "9dc01c6bd44e", "module_name": "over_under", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/compare/over_under.v", "sha256": "3ff4439e7662aa03f70c3880f57bb2c6ce387dd0a1dac8ea6e01e763f36ee5b8"}}
{"design_id": "9dfa81e16d1f", "module_name": "dma_if_mux_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_if_mux_rd.v", "sha256": "9a8baf220a009c8fa1105026835a3d7a4419a32a40a9ff5b16185c14ce1572a7"}}
{"design_id": "9e232b7d9a04", "module_name": "sbox_ram", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/rc4/rc4.v", "sha256": "70987a8b7370212ddbb7c5bf7e51a831b78c5d2ee81c3bf63342ef208db1d755"}}
{"design_id": "9e2fab7e73bb", "module_name": "ct_spsram_512x59", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_512x59.v", "sha256": "327babd0b63a0691fc7a12d4efc5f7ba99559966becf539544504b3d482ce99b"}}
{"design_id": "9e3d71e88934", "module_name": "xor6", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ecc/xor6.v", "sha256": "7c21ab31f3ace8799d147b9b228fd8d41a2a92c40ba73b0e5460dc00f0fcf5b4"}}
{"design_id": "9e410c3a8a04", "module_name": "vga_driver", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/video/vga_driver.v", "sha256": "9213542e221d270743edafc0c067b29c48035000e182d9281796337fe7a36cef"}}
{"design_id": "9e50313359ea", "module_name": "ct_ifu_icache_if", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_icache_if.v", "sha256": "0683ba185db513af5ca81d4c92a7116a09e1234f1d62e81c59668c8fa2474b59"}}
{"design_id": "9e9d4f34fd5f", "module_name": "oh_shift", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_shift.v", "sha256": "a6088988dc60f67a90c40286074cc728c32e5aa8752369bae127e53a56e8984c"}}
{"design_id": "9eb44b147830", "module_name": "testbench", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/testbench/testbench.v", "sha256": "c13ae6789c0d9b7f2d9bb0a9fae4e17e34e8ac7625a9823ee690c07eab83d12f"}}
{"design_id": "9ecaad5a7278", "module_name": "ip_eth_tx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip_eth_tx_64.v", "sha256": "ec717dc691fc9ede23ec9e593aad84683c68efd245fe088c1ecab18eb74b1e8e"}}
{"design_id": "9eda204fab54", "module_name": "axi_ad35xxr_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad35xxr/axi_ad35xxr_if.v", "sha256": "720060d3413ea3f679db929a5749c280a70f7ceb0a231a487ec00d26f0b527e3"}}
{"design_id": "9ee58486626b", "module_name": "reg5", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/reg5.v", "sha256": "d1242a304f16cd8af93287904a4442a1057bef2443d068dc05965b6b5b49c619"}}
{"design_id": "9f03801dff13", "module_name": "sirv_qspi_media", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_qspi_media.v", "sha256": "df26de82874f0dbd20f971f58c38c9e19912da0dbcd7c87af2562388572e6093"}}
{"design_id": "9f27a68b987d", "module_name": "axis_eth_fcs", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_eth_fcs.v", "sha256": "9aba0ff55de115dcab4a2f3ed46bf967bf5fb1eb8011bffcbd5842bf2e37a731"}}
{"design_id": "9f5109790371", "module_name": "decode_8b10b", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "encdec_8b10b.v", "sha256": "9c02451501e9f31f59d8a6cae46726a368ccd3a2bd083df99e6c49dc215c0a50"}}
{"design_id": "9f6b5d7c47f4", "module_name": "test_eth_mac_10g_fifo_ptp_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_eth_mac_10g_fifo_ptp_64.v", "sha256": "27e8f8ff526755cdc8d7d7aa6dfb0671cdf0b630323b2d988f44de191ef757db"}}
{"design_id": "9f7adc926a87", "module_name": "test_arp", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_arp.v", "sha256": "1188e6fa6d22745f6849eb5c3d58be7aaee78d09b595d1dd5c6fd2ab92d38df0"}}
{"design_id": "9f92eb6f46bb", "module_name": "NV_NVDLA_CACC_CALC_int16", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_int16.v", "sha256": "9df1be2c11cf59d7fc03ee71f457d9c28796042304d8f3231a7d54c1799e9ac3"}}
{"design_id": "9fe08eac3e5f", "module_name": "sirv_AsyncResetRegVec_36", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_AsyncResetRegVec_36.v", "sha256": "400136576d3ab215d54baeeedf0baed7f75551feaabe9f430ed99da3c128cb15"}}
{"design_id": "9ff400b32531", "module_name": "sys_pll_0002", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll/sys_pll_0002.v", "sha256": "169ddce38784f9c55dccad652f184bf057b3cde38a1fe5e2d68c6af331185ce4"}}
{"design_id": "a01c2f345aca", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/VCU108/fpga_10g/rtl/fpga_core.v", "sha256": "de591ed4d5b20f9350515b9e5f12672017aeebf3c1e66a39045a773a4fbb5818"}}
{"design_id": "a04df587f249", "module_name": "two_to_one", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/two_to_one.v", "sha256": "89fa892a2ead982248580b7de7b0803f91202453a8d2c95bcdfbd89975a3ae37"}}
{"design_id": "a0720456c762", "module_name": "nv_ram_rwsthp_80x15", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsthp_80x15.v", "sha256": "bbd3f23c105b4b96239d70a5b5e2c2e5084f87b2474b1a6cd29a2544a641df03"}}
{"design_id": "a07309079e05", "module_name": "asic_oai311", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oai311.v", "sha256": "0c9c56b44d1de8d5935ee162136e368deed93a715ec9b326a1ccefecf0590c04"}}
{"design_id": "a086c5c4f5ba", "module_name": "ad_upack_tb", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/tb/ad_upack_tb.v", "sha256": "6b31bbaa98632a2c5f98e423f42b8fea451367d08403d46bc0b42aaa63068d3d"}}
{"design_id": "a0a559ddc99f", "module_name": "five_to_twenty", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/muxing/five_to_twenty.v", "sha256": "3cd90858a8440812c746dbe4766eba2510a69dc2f53cb3c8e2f97c2804d578e7"}}
{"design_id": "a0a69a03f1cc", "module_name": "smu_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/smu_top.v", "sha256": "07161c1411e526c7f26278f6a891a28031c3f2d7b8120ea2bbbd973d6e5709fd"}}
{"design_id": "a0ae702a6074", "module_name": "axi_interconnect", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_interconnect.v", "sha256": "2a06ac654ea73fc960b24922466cb50990584a8318959bea3912cefb0bbf6e65"}}
{"design_id": "a0b512fa0a9c", "module_name": "adv_timer_apb_if", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_adv_timer/adv_timer_apb_if.v", "sha256": "4d371d76d13a66a2d899101703cdb04bf2f09ce8280ec287c4bcc096536ccbe8"}}
{"design_id": "a10a99b5d08f", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9361z7035/ccbob_lvds/system_top.v", "sha256": "32c43955dbb89c3722dd35639401da7ceb5af239776239b827c6df29ba52cff9"}}
{"design_id": "a158a543789d", "module_name": "oh_mux3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mux3.v", "sha256": "69052129664262d8cc5a27ee1fced2cfd58d3c7b20db26284077eaa2174fe44f"}}
{"design_id": "a180380966d1", "module_name": "e902_had_test", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "case/had_soc/e902_had_test.v", "sha256": "ae9c6f09b61677a4f32216265f7cfccdcb1b22c32ed2f3f5f35c9ae484a2061e"}}
{"design_id": "a1c0c8c58eba", "module_name": "eth_mac_1g", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_1g.v", "sha256": "caacd61ad484d96ff14991100009aa67f16aa66a85d9bd245ed2869926da652c"}}
{"design_id": "a1c363c542ae", "module_name": "udp", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp.v", "sha256": "750d3cf657463e28cab742eaf2309022840f3d00b45e3b668153b7fd63254cd7"}}
{"design_id": "a1c61375df75", "module_name": "axi_adapter", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_adapter.v", "sha256": "38f7a2ca6396fc95bcc74050b0298c8682dbd4b0a7b0b095b90d980ca73f7e9e"}}
{"design_id": "a1d69b32c106", "module_name": "up_pmod", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_pmod.v", "sha256": "350bcc35dc0a276143cc568c1578fd6c189a670bb512c2201b96efcc0376f4ca"}}
{"design_id": "a204432600d3", "module_name": "oh_oai311", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oai311.v", "sha256": "26177bc4524343733f602cddacdb17184d397e66e1a9be75c796fe883796adcc"}}
{"design_id": "a21633135e4d", "module_name": "spi_master_io", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "spi/hdl/spi_master_io.v", "sha256": "bb77a229db66bb099d3db209fa0de9b3e515b611eac706090029ed9d4ab6113e"}}
{"design_id": "a21835098d42", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/rtl/fpga.v", "sha256": "2c52ee609910b0309ea6ddfabba2bf404b1e75a189520a6c2c872dd164449dcd"}}
{"design_id": "a21fc314d307", "module_name": "ct_vfdsu_double", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_double.v", "sha256": "ef7f95275e4d59d343e16233d21c266a6b690d1a372ebe2b630bf8f858840888"}}
{"design_id": "a2217c393792", "module_name": "timer_cntrl", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_adv_timer/timer_cntrl.v", "sha256": "dc2aa8d94308cd7b196a0e0f2568bc3215809149dfa0f895f87ded666c3de656"}}
{"design_id": "a23f1aecf34c", "module_name": "nv_ram_rws_32x16", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rws_32x16.v", "sha256": "7937430cdf48d84a19ef0bf304ce3f324bc7e4cdcb6e41274024a416f402db44"}}
{"design_id": "a2438878a360", "module_name": "pll_hdmi_0002", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/pll_hdmi/pll_hdmi_0002.v", "sha256": "45ec17829bf7a119136c8a5a9df98b59a87178a6e9ae71658a0e00bca91058b6"}}
{"design_id": "a25034f2723b", "module_name": "axi_ad9361_lvds_if_c5", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v", "sha256": "7ce5e916f0017b478b241ad8f4fd15b3213e4fe14661c998fd81928a439d4fa2"}}
{"design_id": "a265f5b8ba3c", "module_name": "axi_ram_wr_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_ram_wr_if.v", "sha256": "cec0682f902f11d61c852812426ffa61417d281b82df10625cbfafd621209743"}}
{"design_id": "a2737d6c19f0", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/power1.v", "sha256": "291f806f4331dd3e6c3f9a47f2a495118238b9ad9313086554839b1357816103"}}
{"design_id": "a27d6358f05a", "module_name": "test_axis_ram_switch_1x4_256_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_ram_switch_1x4_256_64.v", "sha256": "50c24e7b393641529facbb26a0362084715e9abe10134c683b9bfa79acb35a5e"}}
{"design_id": "a29f3a468b1d", "module_name": "axi_axil_adapter_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_axil_adapter_wr.v", "sha256": "9f0ee91dd9b70e642e992262e8ff3151bb4ae52fc616f01d6964f28789cae0e2"}}
{"design_id": "a2b04b1e325c", "module_name": "adrv9001_rx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/intel/adrv9001_rx.v", "sha256": "da72e9d7656a0cac5926c4ad0814e26cc31d9acf459afae92ee7d58c6a7f7636"}}
{"design_id": "a2b3609d22da", "module_name": "altera_pll_reconfig_top", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/pll_cfg/altera_pll_reconfig_top.v", "sha256": "bbdceeda812e1580c5b7da23893c030110612bdc3c114a92a993e265742996ec"}}
{"design_id": "a2f183046469", "module_name": "IOBUFDS_DIFF_OUT_INTERMDISABLE", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IOBUFDS_DIFF_OUT_INTERMDISABLE.v", "sha256": "68bdad7adcff148c07f078842d6577e0aca0b194a5a37a63c096db8595d85f1a"}}
{"design_id": "a308c88ea5fd", "module_name": "axi_axil_adapter_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_axil_adapter_wr.v", "sha256": "9f0ee91dd9b70e642e992262e8ff3151bb4ae52fc616f01d6964f28789cae0e2"}}
{"design_id": "a32007f59645", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/ML605/fpga_sgmii/rtl/fpga_core.v", "sha256": "6d8ed82cffee1d16a9b33bfc7c54ae89b1ce1e5287ec61f2620b657ab3c5c332"}}
{"design_id": "a322077fb991", "module_name": "fpga_byte_spram", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/sim_lib/fpga_byte_spram.v", "sha256": "1839d0974380f490b9320f6915f36f41f43b560de5ea64e58f4fab74a848f489"}}
{"design_id": "a3355aab41f2", "module_name": "RAMDP_256X8_GL_M2_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_256X8_GL_M2_E2.v", "sha256": "d5d6d7dd086eaf51b56d2918ae2080de01095aa3eca8422a9852a1558f30019d"}}
{"design_id": "a348dde5cd85", "module_name": "ip_eth_tx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ip_eth_tx.v", "sha256": "53a1378a6cd5cfa50ece8169f3f83bf4fadd6a66abe04809fe6a995ea224b3ce"}}
{"design_id": "a359581a10ef", "module_name": "fec_rot_31", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_31.v", "sha256": "1e75f6c76c37574c8d37b267521f2e4dbece9368d2f34435f317fd2c51e4bf89"}}
{"design_id": "a35acd5d3547", "module_name": "ct_f_spsram_128x104", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_128x104.v", "sha256": "2c2fdcb9207afc3ceaf6929c356a881ae1e466968edcebe914d4612101d27431"}}
{"design_id": "a370d7c62ad4", "module_name": "axi_ad9467", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9467/axi_ad9467.v", "sha256": "dfaa1bc8037222491699b41dcba04d19d55bdcbee1b6504ed009384a95e3736f"}}
{"design_id": "a37a66968642", "module_name": "fec_rot_26", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_26.v", "sha256": "a730183684af1d0e2a2d3eb5a0c02c9d9f8ea1cbc907341c6d046c966fe93979"}}
{"design_id": "a3a22e46ff75", "module_name": "pcie_s10_if", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_s10_if.v", "sha256": "b082f99b6b9eb42bf65a8108e6728faf204c95fb6806ad761f46a1f2b0cb6223"}}
{"design_id": "a3aae05c0be9", "module_name": "ad_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_pnmon.v", "sha256": "828c6c1d9581a54b85b11b180629e35bb2e28af2846cf4d660c1bac9c786fece"}}
{"design_id": "a3f3d1a64768", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad469x_evb/de10nano/system_top.v", "sha256": "7d86849cdda4789759a2e711890a4ef9c515b6b3420462e828849afc69f0d1d8"}}
{"design_id": "a436ee1e699d", "module_name": "up_dac_common", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_dac_common.v", "sha256": "9186112d2652c4868f6e3efd7b9341cbefc8eec7a16d813d8725a9ce57322cda"}}
{"design_id": "a445d3234df7", "module_name": "p_SSYNC3DO_S_PPP", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/p_SSYNC3DO_S_PPP.v", "sha256": "0dbd83682036e00bb97aa92d713a8da5baba38d7f1824c93568d2da8ba82dbce"}}
{"design_id": "a4a4b8e6e07e", "module_name": "int_test2_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/int_test2_rom.v", "sha256": "daf5506115753446260e355f2f7483be1bb50b302d4d30fa71cebdea8f4e973f"}}
{"design_id": "a4ad35860be8", "module_name": "mrx_io", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "mio/hdl/mrx_io.v", "sha256": "cace15e8d25f201f72cb9c36d9706e9542d335d3d5df359dfd8e2a45b1166dd3"}}
{"design_id": "a4c08d5be07e", "module_name": "servclone10_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servclone10_clock_gen.v", "sha256": "6118d1483b86992a6f4006f1a2ac9addbade1fe5111049b7d3a0c4052d35eb8f"}}
{"design_id": "a4caa596d559", "module_name": "aes_128_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/aes/aes_128_tb.v", "sha256": "cdf4339a3d9aa119dfa749be1250c14e666aa8a9eb65e98c5295325d2cf5c8e2"}}
{"design_id": "a4d0bd4d4f50", "module_name": "servix_ebaz4205_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servix_ebaz4205_clock_gen.v", "sha256": "1dfa25144a2b50c2bc3883e7577773d6d6b1e8123395738e9d1b57c113aa97aa"}}
{"design_id": "a4f95616267a", "module_name": "axis_fifo_adapter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v", "sha256": "7662fbf53def5dfb353a590a3ae7309b4f9519847288c90a42ed63df57c95d00"}}
{"design_id": "a4fbd8209445", "module_name": "auto_pwm_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/auto_pwm_rom.v", "sha256": "da85ed2a58d489c3157b0335b3add6d82e266c3c734f656d060f2e689b592c12"}}
{"design_id": "a51378b6973b", "module_name": "hex_display", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/DE2-115/fpga/rtl/hex_display.v", "sha256": "ea22655727a677b17d5fa73929ef535aca235915a18d69e9091dd31b98efec1c"}}
{"design_id": "a51dd0513a10", "module_name": "axi_ad9963_tx_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9963/axi_ad9963_tx_channel.v", "sha256": "d69f3a4f5302e898fbe828ae73ae3372444a21338a1246a171fb67cdad31b9aa"}}
{"design_id": "a52edda9a780", "module_name": "axi_ad9963_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9963/axi_ad9963_if.v", "sha256": "62cd364815dad5d74bcbb80db97ae5a0a2c61cbc89c4cd6a5065e5bdf590dd40"}}
{"design_id": "a533c5a4ec75", "module_name": "gmii_phy_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/gmii_phy_if.v", "sha256": "9da180f3c5e7036c8cdc81a157315789c409cbf7c63f672ad3fec37ac966afc3"}}
{"design_id": "a53ea2294c94", "module_name": "up_down_counter", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_adv_timer/up_down_counter.v", "sha256": "a987f14cd590e2a04696066c835bbb0f7f4602281f8bb9c61f2be14ccf44c6a5"}}
{"design_id": "a54adae5e5d7", "module_name": "pcileech_tlps128_bar_controller", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "ScreamerM2/src/pcileech_tlps128_bar_controller.sv", "sha256": "83436421ca0a388518106ecd9a2202b95e424bf3f0de972109bb953f59b65eb7"}}
{"design_id": "a55445760aef", "module_name": "asic_or2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_or2.v", "sha256": "1bc50f033ed43d715ebefdbe4d0696a4a64994d10cce497efb0eca89b0858cac"}}
{"design_id": "a566b7d5255b", "module_name": "test_axis_xgmii_tx_32", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_axis_xgmii_tx_32.v", "sha256": "d188578eb9c8b7ed5ec9ba055fec034f5c75a18a5108b65bf0bf057a2c9accd0"}}
{"design_id": "a56e37b99644", "module_name": "axi_ad9361_rx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/axi_ad9361_rx.v", "sha256": "a46b35b4a68105f532b1ae7c0a471ba5a211d52c00ca3af56eded37deb7e60d7"}}
{"design_id": "a57f0dc10d05", "module_name": "RAMDP_32X16_GL_M1_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_32X16_GL_M1_E2.v", "sha256": "4379b402cd19ff2e5b97e8248bd54adb13dba6fa85625e05289e8fb63ae3150b"}}
{"design_id": "a595cd23c0b9", "module_name": "NV_NVDLA_ssync3d", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/car/NV_NVDLA_ssync3d.v", "sha256": "d6aec3128068314c492c2f476ee4ce41a60cbe43865d9b18e510dcf8d2c0eef9"}}
{"design_id": "a5a447b7fb3c", "module_name": "test_axis_rate_limit", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_rate_limit.v", "sha256": "3f8918ce45ac37ed047f4d94b334e378b61f5f697c7d2579ef99162b8bda5aa2"}}
{"design_id": "a5ec955a1b0e", "module_name": "axi_crossbar_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_crossbar_wr.v", "sha256": "0892781788371df9d3449608d342542269eb05efd0b6827fdea575d538368816"}}
{"design_id": "a5f12ec0b80f", "module_name": "axi_ad9625_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9625/axi_ad9625_pnmon.v", "sha256": "1ee989bb110a01e525af0dcf49996b908b210dc91cc68b0da0f6a8e964fa4881"}}
{"design_id": "a60973472129", "module_name": "clkdivider", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "fpga/artydevkit/src/clkdivider.v", "sha256": "bb8cf1603b147d801604ff9c5e49c3a43f6e5712e3ea6f3026cc9813d860073f"}}
{"design_id": "a61b454ec8c7", "module_name": "ice40_pll", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/ice40_pll.v", "sha256": "5381cd11c3786125fbd4e05806b16caa1f4baed2b425bd596826b83e4dd2fe40"}}
{"design_id": "a64ebccf5f54", "module_name": "gearbox_32_66", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_32_66.v", "sha256": "a67ce7d59eddee45036f36097a64e6f0d81649c7b7037a954921bc27a86afd5c"}}
{"design_id": "a698e05f703a", "module_name": "axis_ll_bridge", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_ll_bridge.v", "sha256": "0642f97b993ce2f73104deb502aaa58e62c4581937beb1db1acfc114ba0efd65"}}
{"design_id": "a6d0114eedf8", "module_name": "axiops", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/axiops.v", "sha256": "30de8f5db700fb7dd8f708c4fb2c6712e5f89a0e30313e5b829786ed449e77e4"}}
{"design_id": "a6d639166200", "module_name": "NV_NVDLA_MCIF_CSB_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_MCIF_CSB_reg.v", "sha256": "76db1d340a8a9f989c6de49f08dd5afa45cc2f7dc0f9b78d718f33fe618ec500"}}
{"design_id": "a6e7c38a37f8", "module_name": "spi_master_clkgen", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_spi_master/spi_master_clkgen.v", "sha256": "7af6f73803cab880ec8926ac95f7b20b74ff748d884db5fb55e4ef98467d7343"}}
{"design_id": "a6f94717f277", "module_name": "pcie_msix", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_msix.v", "sha256": "85da9abfe32cc3ca92934ac9ae2c1228da606496e8762a9015766791410d9570"}}
{"design_id": "a6ff54487b15", "module_name": "cic_int", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_cic/cic_int.v", "sha256": "3803fe7515ab23eb04f5b61e389dfb36d39374588fdf2d3ae737a076517c971e"}}
{"design_id": "a705b91aa9e6", "module_name": "up_tpl_common", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v", "sha256": "a28190619952d4c99f40a29a998045a9893c279f370e54ba681ca4134da3416a"}}
{"design_id": "a712e07a79f1", "module_name": "gcd", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "test/gcd_sky130hs.v", "sha256": "352a127b1d610ce99863cf32014fbf8cce9b68f0d98d350a532a70be086830f7"}}
{"design_id": "a71947a6a023", "module_name": "asic_clkicgand", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clkicgand.v", "sha256": "8f528b06ca5fa1ff4b35376a15c07ba0cc5c4bbc1fc16fdbcb6c9a8e4e1fd153"}}
{"design_id": "a732eb254baa", "module_name": "frequency_monitor", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/frequency_monitor.v", "sha256": "8b3f275b0814d207755d43ea4b3ce0537d5ca2a2df81b2aa312a850adadca557"}}
{"design_id": "a7540a2ebebd", "module_name": "ct_idu_rf_fwd_preg", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_rf_fwd_preg.v", "sha256": "ced59b49665f83f535296fa0a591c7152015fd2df9c9df44307310c1c07919a2"}}
{"design_id": "a77cfe67e5a0", "module_name": "axi_logic_analyzer_reg", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_logic_analyzer/axi_logic_analyzer_reg.v", "sha256": "7541320f909b415efdec4efa92f015ca36fb4501a1d3d50361af4c9142e3ef04"}}
{"design_id": "a79fb7f0d378", "module_name": "util_dec256sinc24b", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/util_dec256sinc24b.v", "sha256": "0a722c9c9dc0305a084cda581b59b7bed4e216f77a64854096f49842c82c0add"}}
{"design_id": "a7b960cece7a", "module_name": "pcie_axil_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_axil_master.v", "sha256": "4b66bd5dc9c5ed0c2616773a310e0deb6b3e0ecd7958f176a33b850feeaf7767"}}
{"design_id": "a7c2e472211c", "module_name": "gearbox_32_33", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_32_33.v", "sha256": "4f2e4b4827963789b9acb9ad915b38e4e77a288d5f161bfd549d0f2c0e69674d"}}
{"design_id": "a7df993e55ad", "module_name": "serv_rf_ram", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_rf_ram.v", "sha256": "779ad3243dfa648f276240d260ff4ac1a1e83cc1364afb93d40c586905ce4338"}}
{"design_id": "a7e5b04acc5a", "module_name": "oh_clockor", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_clockor.v", "sha256": "2c8a2099ee0b2d6ae23e9dabc4d710ac1651b376497b4ef5fbe8e4dec7fe5fc8"}}
{"design_id": "a800f5e776ea", "module_name": "sirv_ResetCatchAndSync_2", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_ResetCatchAndSync_2.v", "sha256": "21fa8eea49c0ae91f1251da49e579989cc916af7663ab785cc71326f07dc980e"}}
{"design_id": "a80bb71b9d00", "module_name": "crc32_dat64", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat64.v", "sha256": "6bc7e90553acee952fb15bdc036b309ad30ba2740cc8348b8c8ccfc854bda962"}}
{"design_id": "a823cdd4d6ed", "module_name": "pcie_us_axi_master_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_axi_master_wr.v", "sha256": "4b7c25ae0fee8c62a6278701dae11b6b6c2500d6ca55d0bbe9976f2401d1090f"}}
{"design_id": "a83521ee2480", "module_name": "ad_dds_cordic_pipe", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_dds_cordic_pipe.v", "sha256": "2c7b92ba6edd695c3604248fbd354b8324186309c97f980dd0589b5dd701333b"}}
{"design_id": "a863cc0be373", "module_name": "crc32c_dat64_only", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32c_dat64_only.v", "sha256": "666688a5a21649842b70c1db9e999c96d39b1496176894df16a19e338065bda3"}}
{"design_id": "a87e7724fe5f", "module_name": "oh_oai33", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oai33.v", "sha256": "d68ac908932fc2e7fa031732e33e3ebff1ebadd9c7980fab1dfd3755d93bd4b3"}}
{"design_id": "a89e2da0051d", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/common/coraz7s/system_top.v", "sha256": "53cbb04f1a38b818ee2e59aba4af887bfdedf14e6c32ac72dad0ddecd0896704"}}
{"design_id": "a8a80b2aab07", "module_name": "axil_crossbar", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_crossbar.v", "sha256": "f48acdb965988038196bc0742f2f18174a1ecd35386a061f634bc64ccf6adb27"}}
{"design_id": "a8d14a666092", "module_name": "oh_sdffrqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_sdffrqn.v", "sha256": "e62aa195a27553f4b4327d86d70f988cedbf9246c398b48e82625c83e492473b"}}
{"design_id": "a8dbd062ca1c", "module_name": "ct_iu_mult", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_mult.v", "sha256": "4c7dd62c5cb049c1bf0caa02287d8ae6dc5fafdaa48879c420212f67b87931a2"}}
{"design_id": "a8f18ba633d4", "module_name": "oh_fifo_sync", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_fifo_sync.v", "sha256": "d5aa3f916aeaf4f9f90a2a816d6498429f33dab4ffe2e6032f19d7cf640706bd"}}
{"design_id": "a90bcdc187fc", "module_name": "NV_NVDLA_CACC_CALC_fp_48b", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v", "sha256": "ef3dbfb8b56f4359f6554af9e3c07e3b47b87423b255c17aaedeeb0dc94b7028"}}
{"design_id": "a94417596a3c", "module_name": "test_axis_register_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_register_64.v", "sha256": "8c39a310bbd63aac8c189d15c559c6e2df3e2fa371ca7001f10316ce3c4d3824"}}
{"design_id": "a9667f15a44e", "module_name": "axis_srl_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_srl_fifo.v", "sha256": "b657b6592e9a31a5f88289cfd34b1504b2114443a1c4df0ba89d10b4235a3104"}}
{"design_id": "a979e9260814", "module_name": "temp_sense", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/debug/temp_sense.v", "sha256": "ee15717f2de4c63ea9e1bb58f68c00661c397b6059dc9c4414af1c599998c320"}}
{"design_id": "a9990a088671", "module_name": "gearbox_66_20", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_66_20.v", "sha256": "2d8fa256e5b48b820deedf355a9decf1bfa743b64708490bd76908e28445bc44"}}
{"design_id": "a99da3640f09", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/fpga_core.v", "sha256": "546b4a8d4eaddc844c2d863a048590ab0eb564ad5c5ff147db0bce02eeb8d352"}}
{"design_id": "a9ad8db671de", "module_name": "ad_ip_jesd204_tpl_adc_deframer", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v", "sha256": "0236834a20131d052e61673073b0030e7196823e2b4e27c9888be3375f4e684a"}}
{"design_id": "a9bd122faad5", "module_name": "axi_ad9361_tdd_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/axi_ad9361_tdd_if.v", "sha256": "55934ddf40f09f0de96fccd0e7149fa705ccb6e1c7615dddaf16d0e358c19934"}}
{"design_id": "a9d639334909", "module_name": "eth_phy_10g_rx_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_phy_10g_rx_if.v", "sha256": "30ff48b0b1ad4dd08d0c3038eeb57a371758535e0a3f2883709cdc01a2289a70"}}
{"design_id": "a9f721e66bdd", "module_name": "crc_ethernet", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc_ethernet.v", "sha256": "c57c67834a51314439ddb7017b274cc653b3e185ff0beb0db49e6c762fdd65ef"}}
{"design_id": "aa0322cbe597", "module_name": "tim3_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/tim3.v", "sha256": "b911b0d929bd76aed940372f9ffe7765aeab8eed7aacbdabd54f0b185344a50c"}}
{"design_id": "aa1dbd139706", "module_name": "IDELAYCTRL", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IDELAYCTRL.v", "sha256": "c297ff572890e45b8051ae95988563ff911aa2b110eb3903fb6684c441bd2d66"}}
{"design_id": "aa375abc63a6", "module_name": "ct_spsram_256x84", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_spsram_256x84.v", "sha256": "080956bd91953214477e4e7794422a8a65e3fd3ac2e7ca064bb6b98872f82d71"}}
{"design_id": "aa51fb7081fd", "module_name": "axi_etrace", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "etrace/hdl/axi_etrace.v", "sha256": "b7a4eaf15be7ce34aa918f5a828cfcace0b298cf3115fd5fe15210af1c0a4a61"}}
{"design_id": "aa6231e9f6da", "module_name": "NV_BLKBOX_BUFFER", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/NV_BLKBOX_BUFFER.v", "sha256": "03f78348a1f6b07362c392876e56e19b47effd09e3c240c7a27ee77c51e027fd"}}
{"design_id": "aa68ba60c2c9", "module_name": "ecc_encode_2bit", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ecc/ecc_2bit.v", "sha256": "8135bb4da4b45c1c0d90e1d5d5e4eec171c1059ad4291af8776868f39e241985"}}
{"design_id": "aa6923ee2ac5", "module_name": "test_udp_arb_mux_4", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_udp_arb_mux_4.v", "sha256": "33d8a8e53c74c391f195dbb7363ba29696fb2ab9cce2396b6007a3dba964423f"}}
{"design_id": "aa6c8c0bea9f", "module_name": "macro_only", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/mpl/test/testcases/macro_only.v", "sha256": "4aeeeab9e4e2101169863faac5272fc739023375a1b22b3352467ca2b3c807dd"}}
{"design_id": "aa8be4ce74f2", "module_name": "avst2axis", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/avst2axis.v", "sha256": "714dd73a9c6642011e062368dec3a819cf82d3950ffd365fd96e4664ca843500"}}
{"design_id": "aa8d7967a57d", "module_name": "adrv9001_pack", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/adrv9001_pack.v", "sha256": "d677670a6154d9f956b020ad32b7aad3dd43fae1004fe2300191705488aad498"}}
{"design_id": "aa8eaf7fb5e9", "module_name": "NV_NVDLA_SDP_NRDMA_gate", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_gate.v", "sha256": "b83ec625dc915c5e6fae37bee81a77d5144d9bc3e4ec89d4a1b2751a95669291"}}
{"design_id": "aa91a5b221fd", "module_name": "erx_core", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/erx_core.v", "sha256": "10bc667a51c95c3020f3c62971bbf560886fd6f9d2c07cbdbe6cf6999f97103b"}}
{"design_id": "aad3a5e37410", "module_name": "plic_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_top.v", "sha256": "4fd6189023d93401c2898bf9335f5a21f620e177fc448039867d6c86cb8b17b1"}}
{"design_id": "aaec59f7deb5", "module_name": "axi_ad9625", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9625/axi_ad9625.v", "sha256": "74b5cd35ae334a822658b1aeda8413464ada80fe7f2ae8b6b2acef7ee3aa4743"}}
{"design_id": "aaff7c8725f1", "module_name": "axi_ad485x_crc", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad485x/axi_ad485x_crc.v", "sha256": "d661d6e35b99f2b697d6a472d33a477dd5204f272d0f573bad18ed278ff17dad"}}
{"design_id": "ab66de6deeb8", "module_name": "ct_vfmau_ff1_10bit", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfmau/rtl/ct_vfmau_ff1_10bit.v", "sha256": "50e67d371e0aed7fd72d6ba0a386ba45cb75b3047f8789122401490f030da171"}}
{"design_id": "ab6b60e88d71", "module_name": "mdio_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU118/fpga_25g/rtl/mdio_master.v", "sha256": "63308070f3c1f13bb298f0e971ee5ff9fd161fe4070b5eddd85278f6dd043da3"}}
{"design_id": "ab77301a2546", "module_name": "si570_i2c_init", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/DE5-Net/fpga/rtl/si570_i2c_init.v", "sha256": "6d79cff038a7ee8f74021dfcd57e5c050476a545b0d9ba4f669098c90650f791"}}
{"design_id": "ab8a746f307a", "module_name": "pulse_merge", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pulse_merge.v", "sha256": "be969a374712e76002434cdf6c1ba55f31a250a8b7e088aa1d301b031b39ba6f"}}
{"design_id": "ab8b2dc7354b", "module_name": "ct_f_spsram_2048x59", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_2048x59.v", "sha256": "7faa1b6be37e4eb1c563cc4fb1b5ec62662fad6948d8e35e3943d9adc238e092"}}
{"design_id": "abc1fc6f0dbe", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9434_fmc/zed/system_top.v", "sha256": "0253f685794f08106ce822b897215a2a46bd333f4b8186ca926b63ad6895d65e"}}
{"design_id": "abd06f33c328", "module_name": "asic_latq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_latq.v", "sha256": "1209fd37b5858969424f66116fce79d01e87a361389cc470885795a07900bfdc"}}
{"design_id": "abd41d5c6347", "module_name": "axi_axil_adapter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_axil_adapter.v", "sha256": "b3aec5057016d4cc8a7114b02d88b8d7cce8021c178741d310af3d93b0f9659e"}}
{"design_id": "ac036811d54a", "module_name": "fec_rot_3", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_3.v", "sha256": "b7492293144c9b087cae3eb7724536a3e193733a70a1edc0ef2ef900ed8bf667"}}
{"design_id": "ac18eff9ec6b", "module_name": "example_core", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/common/rtl/example_core.v", "sha256": "a6ed90cef9bb1a335d501e2e05d753b89b9fe0548c32e8c79d5c766b05287902"}}
{"design_id": "ac2035d76caf", "module_name": "oh_verify", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_verify.v", "sha256": "714fa63515abfcdf71397f3429e73912deb25ebe44a6239dcd176d860926e552"}}
{"design_id": "ac220354c9b6", "module_name": "ct_ifu_precode", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_precode.v", "sha256": "5c977be60fca173a20e8ec2521e095dbe8dbbb48f4c545bb79d172d1b4032803"}}
{"design_id": "ac4958c1468e", "module_name": "sirv_spigpioport", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_spigpioport.v", "sha256": "7f4905cc4131b0a1ea24970c4c4f04c22f9471c97b89ef8c9ac61b0acf3b6a0c"}}
{"design_id": "ac600f801640", "module_name": "etx_clocks", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/etx_clocks.v", "sha256": "535e5a6cc02fb8187d8f36610faff1fbfefd39bf8d76ef13fc89c5a6fcad29a9"}}
{"design_id": "ac6fcf576b6d", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/testbench/dut_fifo_generic.v", "sha256": "43371bc14b9d5557e1cfb77effa53e0f1f4e2822f0106db960d91071b4a9025f"}}
{"design_id": "ac738bd4397f", "module_name": "axis2avst", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/S10DX_DK/fpga_10g/rtl/axis2avst.v", "sha256": "3822c5400411975ac818f40c72e985e7eaae4d5fe4a089b9874a19ef3143bfd0"}}
{"design_id": "ac8c58c1138b", "module_name": "RAMPDP_60X168_GL_M1_D2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMPDP_60X168_GL_M1_D2.v", "sha256": "9ac4f7b1208ccf30e91af42f9fc505580be72820ed068f68b46c9fb6d3e40132"}}
{"design_id": "acf4c0265ee8", "module_name": "single_port_ram", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "dual_port_single_port_ram_templates/Verilog/single_port_ram.v", "sha256": "066562fa290ea9c7019b76725af12eadffd9c9a315d4c6a62b1ab0de442cd436"}}
{"design_id": "acfb6504f845", "module_name": "ptp_ts_extract", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ptp_ts_extract.v", "sha256": "6373a8982dae454eb6b3275a007901ac6d658c10c1976848f751348008c8abaa"}}
{"design_id": "ad040f79f8c9", "module_name": "arbiter", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/arbiter.v", "sha256": "a001507c82843e36e133dea75491fc044f56660fac0aff0127cf3afec7f927e0"}}
{"design_id": "ad193c7c1579", "module_name": "test_axis_async_frame_fifo_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_async_frame_fifo_64.v", "sha256": "6bc5b2435e6aeed39ce66eed589153e3bdba23b27d12d0b72326ba06304c96a3"}}
{"design_id": "ad218ab3cf00", "module_name": "ct_ifu_pcgen", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_pcgen.v", "sha256": "99641bf464fa063c6f32f88f154905f5d4f0212b5b97a5a603ef9f208782801e"}}
{"design_id": "ad34d8a9e973", "module_name": "axi_hdmi_tx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hdmi_tx/axi_hdmi_tx.v", "sha256": "6dfba977c0e1b71cbaddcc022c584219b60a81e61170e1807fc1a177acfc7631"}}
{"design_id": "ad81b7a26725", "module_name": "ct_lsu_pfu_gpfb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_gpfb.v", "sha256": "f5d5f9e8a6c55d194c2db7dde5cd47ef7581063281ba8872dd29193a257c15de"}}
{"design_id": "adccd439f01b", "module_name": "tx_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tx_fifo.v", "sha256": "55c59ff85289afa911f1e10ed4eda2b736627221dc0622982585ad0bbd84acd6"}}
{"design_id": "add764c170ab", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/bus1.v", "sha256": "524b2f71ea3cdde1e06a1a7c2ef6743b3564e773607d4bfd535082e2325a4bd7"}}
{"design_id": "adf16ee9f3b5", "module_name": "pulse_merge", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pulse_merge.v", "sha256": "be969a374712e76002434cdf6c1ba55f31a250a8b7e088aa1d301b031b39ba6f"}}
{"design_id": "adf744e8b38c", "module_name": "axi_ad9963", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9963/axi_ad9963.v", "sha256": "290602fc4b613524b5e1f0f592665bb8783edecdf0362c4428f7b6f410e07f37"}}
{"design_id": "adf884626ca2", "module_name": "fec_rot_11", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_11.v", "sha256": "fc57e1d44475e403f111a21c32db8da97c1549beb96cb5be721e0ad5174963ca"}}
{"design_id": "ae0c213f9d13", "module_name": "util_gmii_to_rgmii", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_gmii_to_rgmii/util_gmii_to_rgmii.v", "sha256": "0867afe211851216095d87422917b06b7188750e919e569a64ed4d1039e287d8"}}
{"design_id": "ae87bcf82291", "module_name": "bilbo_lfsr_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/random/bilbo_lfsr_tb.v", "sha256": "caa928e3a7f49787124ec7ae308d3544cc8a4983c197e3775e7ab46b447ddab0"}}
{"design_id": "aea5c81a4762", "module_name": "ct_spsram_1024x92", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_1024x92.v", "sha256": "2a8bb30d1b0d2050a525a92267c7fb438960fcc6f3732acda04723843cdc8f72"}}
{"design_id": "aea6a296332e", "module_name": "NV_NVDLA_glb", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/glb/NV_NVDLA_glb.v", "sha256": "b352af691985f5f024a820ae8cb932f96b0386ff0ff83ae3911c87baa52cfac4"}}
{"design_id": "aec3d2def00c", "module_name": "pll_hdmi", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/de10nano_cyclonev_mister/sys/pll_hdmi.v", "sha256": "327d94e5e5d6568bcc4489ee279f752969f18aa62af088649ad27f34fa476617"}}
{"design_id": "aed63ed2dda5", "module_name": "int_test", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/pacoblaze/int_test.v", "sha256": "9b47efdd19057b42d68b747a173420026a2344ca84f39b10190a1b22a956aa6b"}}
{"design_id": "aeeb2e199fb5", "module_name": "mio", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "mio/hdl/mio.v", "sha256": "e7d9829c3c98f6e60a09db056ca1557bfd498e5ce32fced685ba5bd463eda2d6"}}
{"design_id": "af62b8d95bc1", "module_name": "servive_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servive_clock_gen.v", "sha256": "0ef30c7eb0133cb8ab02c4e91fad421d40b3f278e390dc8b381de9e59503b5fe"}}
{"design_id": "af74b75159e5", "module_name": "ptp_perout", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ptp_perout.v", "sha256": "e8562fb34d5fe4e2da2af31c398e379b35eb605b319a6902146b33a0da2a6c66"}}
{"design_id": "afcd8192adfc", "module_name": "pipefetch", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/pipefetch.v", "sha256": "958eadc27b73c753284426ac6a1c5a98d25b6d1a5a28c90b411dc9c5addff4c3"}}
{"design_id": "afeb6ab9a658", "module_name": "cmac_gty_ch_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/cmac_gty_ch_wrapper.v", "sha256": "1d025c207fd85ad529a3d85c687b204215194dcb8b44608e2544493a41203bf2"}}
{"design_id": "aff634c5b3ef", "module_name": "ecc_8bit_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ecc/ecc_8bit_tb.v", "sha256": "f60ad39479f59ce201eb3d3a609bd945200c92b6e284f7dffb71105b7fdac927"}}
{"design_id": "b00e823b169f", "module_name": "test_eth_mac_10g_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_eth_mac_10g_64.v", "sha256": "b5d86fe7bca013f79ad4615e79d9b6c6dd47ad6bc9ddfe1d4e576a9f4feeab1b"}}
{"design_id": "b00f131ff268", "module_name": "sirv_uartrx", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_uartrx.v", "sha256": "65aca4e94bb5828e3729a0387b8df52b08cfeef29ed7ad99709de3a66917c7f6"}}
{"design_id": "b0137f126964", "module_name": "up_xfer_status", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_xfer_status.v", "sha256": "a103d5d646bdf4512739638bd44fe6db2d2c068c7665356e97a6e535d05b5136"}}
{"design_id": "b0277e149020", "module_name": "NV_NVDLA_ssync3d_c", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/car/NV_NVDLA_ssync3d_c.v", "sha256": "196d75488e54336653dfb2441142c66349bc1e0e97785eecfa83c29ebf4519f8"}}
{"design_id": "b02b28ff30eb", "module_name": "pcie_axi_master_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_axi_master_wr.v", "sha256": "fa7debc2b126487a53fb76e8830be316ce179a510c150368b33d4255d4c6b934"}}
{"design_id": "b04118626a62", "module_name": "AN2D4PO4", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/AN2D4PO4.v", "sha256": "904e5edc7fd8c10e318dd7bcae1e30b126851912c77f2ecd33cd427a59f58c7f"}}
{"design_id": "b0587470c2fc", "module_name": "des_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/des/des_tb.v", "sha256": "b6a37f153346dff408688feb92402356d302b7ac4fcc55e78d5243e19b157dcf"}}
{"design_id": "b0766127e0ed", "module_name": "axil_adapter_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_adapter_wr.v", "sha256": "1945be51e41c4c8b6c1e48af9d85f13cf761af5d1dfc42dad66cda40afc60f07"}}
{"design_id": "b089a8b568ff", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/fmcomms2/kcu105/system_top.v", "sha256": "3a30a910a6d3105e83dece0f9860d59d763731695e572e1fbf85b5792283f073"}}
{"design_id": "b090acf7afc9", "module_name": "e203_ifu", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/core/e203_ifu.v", "sha256": "99ef0b1bce26fb50c287737fd82575c2deec94175847f52d443d88b81dc7a281"}}
{"design_id": "b09a42b2e940", "module_name": "ternary_add", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/ternary_add.v", "sha256": "e287c6de9a38c3a43151a81b69cd8361d25381aea9a8c61fa9a94ceafe98f2a8"}}
{"design_id": "b0a3cda79130", "module_name": "axis_pipeline_register", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_pipeline_register.v", "sha256": "89bcac460e3822dbbed3f2dbd4d9902faac1262d9dcad867b39c97a6f4402fcc"}}
{"design_id": "b0a666edf055", "module_name": "axi_addr", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/axi_addr.v", "sha256": "d7c976a26eb42398b326d0b651642444dac3ba0bde96b10fe6fbc758922ee703"}}
{"design_id": "b0addb5644bf", "module_name": "fifo_counter", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/common/fifo_counter.v", "sha256": "422c7f0cb3ae5402072301ccf5dcf14bb070edb2563b3c5034ca2aea04350dbf"}}
{"design_id": "b0e677d22ba6", "module_name": "NV_NVDLA_SDP_RDMA_REG_dual", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v", "sha256": "de4e44c2490d6f78dcd21afb879538d872c8d13b8abcb8a767536c33205d470c"}}
{"design_id": "b0f6bb8fa34c", "module_name": "axil_reg_if_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_reg_if_wr.v", "sha256": "ec2f3d3d97b694dd4ff046d791fc7a0f95856c41049a107eac1aa3b3daab7412"}}
{"design_id": "b0f723bc03bb", "module_name": "reg_based_cam", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/reg_based_cam.v", "sha256": "35f0f5b6b0758553945b4277570df8ac69102ad788066e10413fe64f37cc02b3"}}
{"design_id": "b10383e810ec", "module_name": "altera_reset_controller", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/altera_reset_controller.v", "sha256": "f98ccfbc671bbc30ee82c4e9ff7b916e3aad8ccb7120a4748c65de0ec32f57ea"}}
{"design_id": "b155c46dd72e", "module_name": "asic_aoi21", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_aoi21.v", "sha256": "98c270c6d97e9aa90fc7d64b216b9d6dbe5427267480078bc67a150539267ecd"}}
{"design_id": "b15df261e7fb", "module_name": "oh_dffnq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_dffnq.v", "sha256": "2712def4d25b9ed20ef4672c224e351858ab4c6a58cce32d0ead64eb95fe14c4"}}
{"design_id": "b15fca6227b7", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/cpp/TestBufferRemoval3_6.v", "sha256": "76d4d05d4de81af95ae0274398e8c6f9e57d1db1be0493df3095c8a4eaefd457"}}
{"design_id": "b173d59fab64", "module_name": "ct_idu_id_fence", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_id_fence.v", "sha256": "b03e2b3c41529d678df20a3fb52fc303ffe9d00d360cbf8f200a2b62ab271657"}}
{"design_id": "b17497502b2c", "module_name": "tim0_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/tim.v", "sha256": "b6d13cd1af41ccdbb757df7672a3298359f7849c9de5d61dbf71cdfe718ba9f0"}}
{"design_id": "b19b70f61311", "module_name": "ct_f_spsram_2048x32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_2048x32.v", "sha256": "9cbd8988f3800b924015094421d652a0851f18a67e78367fd548de10fa2b27a8"}}
{"design_id": "b1c3511bbfcc", "module_name": "fpga", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/Alveo/fpga/rtl/fpga_au280.v", "sha256": "9a269c7d8c3ca5f0de5376284fc292cf950a456a9c1d0f815fd84f2b44362c5c"}}
{"design_id": "b1d1d57bdc96", "module_name": "axi_ad777x", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad777x/axi_ad777x.v", "sha256": "363c9db06b96de480dcb262525121987f38115df14800d0e6e047c54e0c548ee"}}
{"design_id": "b1d9d191a5e1", "module_name": "axi_ad9122_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9122/axi_ad9122_channel.v", "sha256": "86f3f7f4585404d6bff3f9292c21308c1bd49637fe49c2eabfafbd855e0be4e4"}}
{"design_id": "b1db00e6742d", "module_name": "jesd204_f_tile_adapter_tx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx.v", "sha256": "c7d5dff311757efecccbbd6c4daf0c18b965147edcf7c941e07e63f54864a8a2"}}
{"design_id": "b1e49d4b968f", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/constant1.v", "sha256": "6e9d8457c25e33e09341af101ca2ba8f44aab8e7dfab2daae13a70bf98549bac"}}
{"design_id": "b20ff6ee8dd6", "module_name": "phy_reconfig", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/DE5-Net/fpga/cores/phy_reconfig.v", "sha256": "25b50c3b0b5785d05042242b6e989b25c8a5e17c4191303189ae32085c3ab5d9"}}
{"design_id": "b253a3b7e749", "module_name": "udp_demux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_demux.v", "sha256": "c734f329ed67f289d98832855eb5182f7d863653a8aac13b56a76eee59e5e0d8"}}
{"design_id": "b25c453cf6ac", "module_name": "NV_NVDLA_sync3d_s", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/car/NV_NVDLA_sync3d_s.v", "sha256": "ee57a4f97054674262fb85dbe473016c9a4ab68fb275722ab6404641b22ffb7a"}}
{"design_id": "b26edc963304", "module_name": "plic_hart_arb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_hart_arb.v", "sha256": "2b5021fdc83ef734b92f15f65a4cfed929389775e438268d629c2860d79418c8"}}
{"design_id": "b272889c7f70", "module_name": "tx_scheduler_rr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tx_scheduler_rr.v", "sha256": "fdfe75f525e99f6c46290db58638fe0de17e248df9e9cb87c092d1a648e78765"}}
{"design_id": "b27c7ca0d057", "module_name": "NV_NVDLA_CACC_slcg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cacc/NV_NVDLA_CACC_slcg.v", "sha256": "0d2f3eb8bd8a6785ae4835258b655b72d65c5c8836a2958302dd9044965fc6b7"}}
{"design_id": "b2938509dea7", "module_name": "NV_NVDLA_MCIF_READ_ig", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_ig.v", "sha256": "5552cb4d2a9e33ecb3f29f35f47bd15681c34935b836c0665bc58d6d7fbfbaf0"}}
{"design_id": "b2a53c8944bf", "module_name": "asic_sdffsqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_sdffsqn.v", "sha256": "4e60b25eff0dce61ac597a379499dcee060805123fdd6abbeb69432cc1d0e871"}}
{"design_id": "b2c1019b86e2", "module_name": "test_pcie_us_axi_master_rd_256", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/tb/test_pcie_us_axi_master_rd_256.v", "sha256": "9d95b9eddff4cdbfd1c8231445b3dbeeff38c25e9c438b4859fcc7bfb8e09771"}}
{"design_id": "b2ce3d8de066", "module_name": "asic_ao211", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao211.v", "sha256": "8ca5957451242ba771a1589ebfa0ad9d2310a4557ae8efcaea1286c7b0068138"}}
{"design_id": "b2f525eaef61", "module_name": "fmcomms8_spi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/fmcomms8/common/fmcomms8_spi.v", "sha256": "335e085df316dc9c105604ee77cf3d7bd697ab7693c2b3d628ef614f82ff5d25"}}
{"design_id": "b321e734ea27", "module_name": "IOBUFDS", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IOBUFDS.v", "sha256": "fc32e4eb217432644dc078a48c9358a83a85ea69779826ab83b9069e6724bf20"}}
{"design_id": "b3288316c9c9", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/S10DX_DK/fpga_10g/rtl/fpga.v", "sha256": "a7d004c3dab410c5ae729c97c2dd88c7a2096cda8ed3c1fba5e2b579a0f63526"}}
{"design_id": "b33b0703690c", "module_name": "ad_adl5904_rst", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_adl5904_rst.v", "sha256": "388601bcd5109d6c1815a30f7ceba5cf25f37dda9e3e165760c583799e862208"}}
{"design_id": "b3408527d1d9", "module_name": "nv_ram_rwsthp_60x168", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsthp_60x168.v", "sha256": "9697ce7ac462e48a07501ef5587fe8c2f73fc2148481609280ba5035230a8e1b"}}
{"design_id": "b372be0a8c5c", "module_name": "util_dacfifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_dacfifo/util_dacfifo.v", "sha256": "98b166d7d30b052be70c711c1fed27081800a67445f78f1ac084b8420eb1a8cb"}}
{"design_id": "b3c3a75e0916", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9208_dual_ebz/vcu118/system_top.v", "sha256": "b3053a6113b1a7bb39e496db61e13e4ca95821bc7aa020c008b660683bd2f774"}}
{"design_id": "b3ce96a73446", "module_name": "asic_dmux4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dmux4.v", "sha256": "ee8dd0a7ebd4d37e6880189b7afc4c6e4ac7fd975bbc66f5169aa6fe1863971f"}}
{"design_id": "b3de060d95d2", "module_name": "ct_ifu_ibctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_ibctrl.v", "sha256": "a1eead25e57e8a50aca01ff99b87ae73fefa17c3304ca322cfefa6a3275d18f2"}}
{"design_id": "b3e496b906a2", "module_name": "simpleuart", "split": "train", "source": {"repository": "https://github.com/YosysHQ/picorv32", "commit": "ef203c2b0a3fb793280f5114941416c425c5b461", "path": "picosoc/simpleuart.v", "sha256": "6b970be4255ef5f951f80a3b0cb27f73844df94349f4e4460bc4dbc4bb49ca1b"}}
{"design_id": "b3fa9c9968a0", "module_name": "pcie_s10_if_rx", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_s10_if_rx.v", "sha256": "3b725f7492a6cde765335296290ffd0fda7400edb9507b401bc86a432fc46969"}}
{"design_id": "b40b9863b74b", "module_name": "oneHotClk_async_write_clock", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/oneHotClk_async_write_clock.v", "sha256": "eef7c727c38cabf354e2dc268433b47857e89d4564503a756e2a74ed4dbd1bfb"}}
{"design_id": "b425d025bdd1", "module_name": "parallella_base", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "parallella/hdl/parallella_base.v", "sha256": "95a7de27af1cdf4b472e64ce869a8984517a463f993d76288140583849961336"}}
{"design_id": "b434c6ae2f8e", "module_name": "oh_par2ser", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_par2ser.v", "sha256": "667b9f95f2f943624d7bf4e2977fd7a97e86cde2e5c7c1833c12d6c20e941e89"}}
{"design_id": "b43de332d789", "module_name": "sirv_aon_wrapper", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_aon_wrapper.v", "sha256": "da4ba087072df5e1e1c290e9dca8f9f01726666d9e7f7ed7d6613d6218c99e3d"}}
{"design_id": "b452cfd210ae", "module_name": "RAMDP_32X32_GL_M1_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_32X32_GL_M1_E2.v", "sha256": "acb4693e93eaa58e89436430a85980eace7d8c866f0582b19a12a0ae0bc8b775"}}
{"design_id": "b47dd22bbf09", "module_name": "sirv_AsyncResetRegVec", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_AsyncResetRegVec.v", "sha256": "2675dd51b18345103da79ebb806afb23810a735f8bcc664e0b40d763d1eed1b9"}}
{"design_id": "b4a6baa3564a", "module_name": "axi_crossbar_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_crossbar_rd.v", "sha256": "d42e9e3b8d94ba9e135cd3e5841ee570dce2cd15d50e7ca87621c8eca246fe98"}}
{"design_id": "b4c89745f063", "module_name": "control_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/control_rom.v", "sha256": "37356bef8728b3a7e5017d8f0f5d1f196b923eefd8cc74a1210857af9aba5ff3"}}
{"design_id": "b4e3eb2ed38e", "module_name": "system_top_lvds", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/dc2677a/c5soc/system_top_lvds.v", "sha256": "279be0d7c86a48d8a06e657bb84d65d41c3c37873ccfb575ed95e081d5b0a0d4"}}
{"design_id": "b4f4a5c447fa", "module_name": "service_go_board", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/service_go_board.v", "sha256": "99a38b5a4485c4184060b9b4a40bccf39f968434e56910559ccf0cb83667a5bb"}}
{"design_id": "b5113f4e89e9", "module_name": "counter", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/odb/test/data/floorplan_initialize2.v", "sha256": "a9258a3f6bc9ca5a563edf9134d08d105cd04df6c7f20151a832d36b54ac078f"}}
{"design_id": "b51f3e97b218", "module_name": "sirv_qspi_physical", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_qspi_physical.v", "sha256": "5bb8ccd6c69e63a1ab876c0d243cb71d7e5a2f92e7796f61bccbb46976842092"}}
{"design_id": "b54673116fb6", "module_name": "rgmii_phy_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/rgmii_phy_if.v", "sha256": "e8a04a072d1763f76180671237baa0871b4e48749d046eeac013170b7342e50d"}}
{"design_id": "b550b13c10bd", "module_name": "crc_register", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc_register.v", "sha256": "4a62707ff8b87f5a2af56f176e7088fc918026716bbc06b1e12fa0003262af29"}}
{"design_id": "b556e830a26c", "module_name": "hi_fanout", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/clone_hier.v", "sha256": "064583e56294c0a4058e46b5d6dccd6a0eac683ffdf75436ff9b8c7a7b73dba1"}}
{"design_id": "b56bdeb2e1ab", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9026/vcu118/system_top.v", "sha256": "18d761e09e4b744616684396f208a74fb4a9ba369da0fc7d469dbf9fc82ac150"}}
{"design_id": "b57ff3f91e07", "module_name": "pi2c", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "parallella/hdl/pi2c.v", "sha256": "0bfe369bd1104515cea38016f588526320a795fcfa24f66977c33fd8d307f7b7"}}
{"design_id": "b5897ad6d197", "module_name": "ssio_ddr_out", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ssio_ddr_out.v", "sha256": "7697bcee212054c1a276a579c3fd641cc7ecac1106fd1f8339110cd479f22aea"}}
{"design_id": "b59151758370", "module_name": "mdio_master", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/mdio_master.v", "sha256": "63308070f3c1f13bb298f0e971ee5ff9fd161fe4070b5eddd85278f6dd043da3"}}
{"design_id": "b5a16617aacd", "module_name": "pcie_us_axis_rc_demux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_axis_rc_demux.v", "sha256": "fbb616656003efb1602ce7948d67cd8a688fdc7bc7d20ec1c19198231188d10a"}}
{"design_id": "b5ab62df86f3", "module_name": "phy_reconfig", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/DE5-Net/fpga/cores/phy_reconfig.v", "sha256": "25b50c3b0b5785d05042242b6e989b25c8a5e17c4191303189ae32085c3ab5d9"}}
{"design_id": "b5c0f3ad2407", "module_name": "asic_dmux6", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dmux6.v", "sha256": "83370f761fef0c31612081d8d55c3539934ca2ecd9d9cd1844d916bd30636169"}}
{"design_id": "b6075d903d16", "module_name": "ct_had_event", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_event.v", "sha256": "d314d416eacd49e004c0eacefdec20bcf0a463c7129471bbd040a304d06d2f84"}}
{"design_id": "b60c1c977b41", "module_name": "test_pcie_us_axi_master_64", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axi_master_64.v", "sha256": "231271a7a6959c38a8fe18c0efe4832b9920b18d92b7325fa0955159130de40e"}}
{"design_id": "b613df610f1f", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v", "sha256": "ff8c44d0f54bbdeebfea2d4487db12d9ed0b12ac373b629c145a526f442c2e9a"}}
{"design_id": "b63a8954cdd7", "module_name": "busdelay", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/ex/busdelay.v", "sha256": "c717ba5fcfd7efb80c72b87d013561fffa76bf5755479e1e0ab7219002cfa470"}}
{"design_id": "b66a8085e91c", "module_name": "axi_adxcvr_up", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/axi_adxcvr/axi_adxcvr_up.v", "sha256": "c4f5611eb1d26f0d054e4e71adf7a06ce8f006f1bf938595fc7bbcd091da8fcf"}}
{"design_id": "b66f7b00cbe7", "module_name": "NV_NVDLA_cmac", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cmac/NV_NVDLA_cmac.v", "sha256": "c94853511bb514809f1023201b6323af6dcf1b14f6d523638107d2ae40cd80c7"}}
{"design_id": "b6730eb1ac40", "module_name": "zipjiffies", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/peripherals/zipjiffies.v", "sha256": "91cd95fd108bbff2da3fe30ffa230a3bd7b356fc8f161cce9ba93d474b8d08ae"}}
{"design_id": "b67774e2fbbe", "module_name": "pcie_s10_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_s10_if.v", "sha256": "b082f99b6b9eb42bf65a8108e6728faf204c95fb6806ad761f46a1f2b0cb6223"}}
{"design_id": "b67cbc4839d9", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga_axi/rtl/sync_reset.v", "sha256": "67ea2e751ee7cdf5c7528902eab32a63f11bd090e1380934fd7334b361c7d874"}}
{"design_id": "b68c3fffdda1", "module_name": "asic_muxi2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_muxi2.v", "sha256": "70a26282a06354ece6e165ebc818f73ec501e487677e681a2121a15a66b138b2"}}
{"design_id": "b6a1a3b33a2b", "module_name": "fec_parity", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_parity.v", "sha256": "2cb165b3e968dccc98d5a1eaf461cfbe20c3a70794c9245de28ed9619f15253c"}}
{"design_id": "b6ada1e33431", "module_name": "rx_checksum", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/rx_checksum.v", "sha256": "be027f25d0560152706f64981e2c925a888a580d6f51986864c8f4f8accbb0ab"}}
{"design_id": "b6aeeca1a89c", "module_name": "spi", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "spi/hdl/spi.v", "sha256": "560ca1a9c5314f6d7bc17a0f598ccb51534dd53d1a674d2f97e0e376583b7ce2"}}
{"design_id": "b6b3aef3c168", "module_name": "test_axis_frame_length_adjust_8", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_frame_length_adjust_8.v", "sha256": "1b7fd40b83ef52a3e0f0fa8c3ec620f34c2b970aae90973eb3222e5382a1dc57"}}
{"design_id": "b6f20ea8c80b", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/report_floating_nets1.v", "sha256": "806c3abde93db9da724748b51bace3825af6934bac0072ca4d5ccc356e82d3b9"}}
{"design_id": "b70f116bbb18", "module_name": "asic_and3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_and3.v", "sha256": "393a6914fb36069beed4d51870e8c3dd4273782f5f2ac34dcf8eccabf9d952b9"}}
{"design_id": "b730b3227f73", "module_name": "asic_oai221", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oai221.v", "sha256": "4cb7c6884e7729f4d327aa5230c1da927ef3e5d61a19ead803941feaed24c844"}}
{"design_id": "b75f75a62741", "module_name": "fec_rot_18", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_18.v", "sha256": "447864eb8ae95145cc00f57fdcc9f7ef925c8d8e181dfb5759d8c64a6c97a3f7"}}
{"design_id": "b7a5e1287cd8", "module_name": "ct_lsu_dcache_ld_tag_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_dcache_ld_tag_array.v", "sha256": "0c2c24f578f6772a09c259a25a0644a3370e246be9b26c9a84810c881477b53b"}}
{"design_id": "b7e2d429dea6", "module_name": "NV_NVDLA_RUBIK_slcg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/rubik/NV_NVDLA_RUBIK_slcg.v", "sha256": "91098c0db75ef6861ce37aa52088a45b5af05d017541bd4423dd2de787810d54"}}
{"design_id": "b80e6bcc545a", "module_name": "src_axi_stream", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/src_axi_stream.v", "sha256": "abf6887e145e8e4498290419e53ae8f6ffe853b57f592cce16d5205386c246f5"}}
{"design_id": "b8151ffbc822", "module_name": "pll", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "boards/max1000_max10/pll.v", "sha256": "1f428769ea3b8317921589a372305096cea30249faacbbcf87bf29dec00610cb"}}
{"design_id": "b81c050c0a63", "module_name": "nv_ram_rwsthp_19x80", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsthp_19x80.v", "sha256": "df7d6c007335e366c167ba7875db68e12b969a9ec0b1118cd690d95158a2b689"}}
{"design_id": "b8306974ff6c", "module_name": "util_fir_int", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_fir_int/util_fir_int.v", "sha256": "05fb7f89ce4454f3a2a566124a08e34675e6d48fbb6db47885d048ec4a3c54ad"}}
{"design_id": "b83c090b2b1f", "module_name": "axi_ltc2387_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ltc2387/axi_ltc2387_if.v", "sha256": "b3a76fcc4129c517e2836396c93516275c15aa3bcba9031d3943d0c243085586"}}
{"design_id": "b8a624b6cffc", "module_name": "memdev", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/memdev.v", "sha256": "c701202009de4dd443358debedd86a91494890969ffc84931b83d2331ae53e33"}}
{"design_id": "b8aade771458", "module_name": "ct_ifu_ind_btb_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_ind_btb_array.v", "sha256": "2453b2d05a13dc79463d3b6acd826c19c6693c3d55569ab9364679ede6c8d891"}}
{"design_id": "b8ae7034a4c1", "module_name": "ct_had_bkpt", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_bkpt.v", "sha256": "3b0911df9dfb84a3a20cc6bd7edde9cafe0b2fd2bed8fbfd07841a297e58e1bd"}}
{"design_id": "b8bace424644", "module_name": "debug_stim", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/tests/cases/debug/debug_stim.v", "sha256": "7ff8f17f4d71e1ab5fafd1f7f6709774eb52a42209e2518d7f85456878c21e42"}}
{"design_id": "b8c446d41cbd", "module_name": "oh_debouncer", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_debouncer.v", "sha256": "39b7a38f89f40aa1f5f0f3c498642747ed34972ddb1e14d5b76a008ef4ac74e1"}}
{"design_id": "b8cae5d756e2", "module_name": "eth_phy_10g_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_phy_10g_rx.v", "sha256": "6852e9f65cceb80626281bba46fa529822498238f27d7deee2905187586e5784"}}
{"design_id": "b8ce8e9cecd6", "module_name": "mqnic_rb_clk_info", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_rb_clk_info.v", "sha256": "bc2e66433ea43be5d125d4aebdc765b9eec46145936fbf95a6304a83e60d3b26"}}
{"design_id": "b8d5ff37e692", "module_name": "sub_modules", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dft/test/sub_modules_sky130.v", "sha256": "cfaead62590d787675927806bde24a95ce71b0b92e56a33a16d2458bbf56be68"}}
{"design_id": "b8d778e0a7f7", "module_name": "axi_ad9122_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9122/axi_ad9122_if.v", "sha256": "03b64228bfa9aa45027eb3a3da85175f5c9a06bb293a12635760b9aff99cd945"}}
{"design_id": "b8f4fc145786", "module_name": "mdio_master", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/VCU118/fpga_1g/rtl/mdio_master.v", "sha256": "63308070f3c1f13bb298f0e971ee5ff9fd161fe4070b5eddd85278f6dd043da3"}}
{"design_id": "b9133a82cb78", "module_name": "nv_ram_rwsp_128x6", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsp_128x6.v", "sha256": "e40fa84823c3738665e2c5c6bfe17082b1fea12f3e57a029fbf7b61b8763a580"}}
{"design_id": "b91d763cd5f3", "module_name": "axi_hdmi_tx_vdma", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hdmi_tx/axi_hdmi_tx_vdma.v", "sha256": "077a43b8352f30eea5635c3261a3ba9fc6635c66e016391233ad4290a1790b4c"}}
{"design_id": "b91e3e15e91c", "module_name": "synchronizer", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/synchronization/synchronizer.v", "sha256": "1ffe910d000ccdf8599e8e98ebd772ff6b44901c65bebb09748905daa3be20d2"}}
{"design_id": "b93dc355e20f", "module_name": "ScanShareSel_JTAG_reg_ext_cg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/ScanShareSel_JTAG_reg_ext_cg.v", "sha256": "f15ab8e2af0ba5546f241747e2db6cfad7421a6a7dacf5eec2289f2d0d4bbc2a"}}
{"design_id": "b947a0f7c88d", "module_name": "oh_aoi32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_aoi32.v", "sha256": "1ef66d077a60a48d0b576e0d095b7971b8ca39edcc981c62b3acbaaeb97bf2a7"}}
{"design_id": "b97734e0e728", "module_name": "servant_ecp5", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_ecp5.v", "sha256": "d548a6a888cf03048b8ca048fe84aabefb95bfac0bf52cf229b5050cf7be1845"}}
{"design_id": "b993b1fec297", "module_name": "ct_mmu_dutlb_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_dutlb_entry.v", "sha256": "c8b69ba6b5308f7962a7bd8ddf568a5a483f94fe0e0652aa2def753bfb5fb771"}}
{"design_id": "b99b822bc2ca", "module_name": "asic_sdffqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_sdffqn.v", "sha256": "90866c971d5b7abdcb0fce31f2d28915292c0b4435efc9eb2ec673451d23f410"}}
{"design_id": "b9bf36c98e21", "module_name": "tdma_ber", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tdma_ber.v", "sha256": "78d9d5e9d3f5ab1b74bc58d9b61ed9f11e53f8a4cbfd2d3f86b9ae75701e7c75"}}
{"design_id": "b9ce64d2ce3b", "module_name": "oh_datagate", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_datagate.v", "sha256": "f2fe02da87a691bb4c3137c8ade17428d2e961486f5d1ac2510b5ebdfd4c6638"}}
{"design_id": "b9e21d1df1d4", "module_name": "busmnt", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "tb/busmnt.v", "sha256": "43fdb24f210d0db070bb8d2980848089d69f1310dba05df1e459b06f311caeeb"}}
{"design_id": "b9e46c4f593f", "module_name": "in_range", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/compare/in_range.v", "sha256": "ce73bfb2fa6107411224c3507391494f25b6a8b79b1842643a064777664715fb"}}
{"design_id": "ba16b2af4733", "module_name": "ct_f_spsram_1024x32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_1024x32.v", "sha256": "a0fb3fb73f39c345c46abb9add5adcac87da6cc3fa89246203e4645f2c63c2a9"}}
{"design_id": "ba187f1c9ce1", "module_name": "oh_iddr", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_iddr.v", "sha256": "a3363398be851efbb711cb62309fe66fea75e8b2f094500c72731faee2d40011"}}
{"design_id": "ba4a3301ccb6", "module_name": "axis_cobs_decode", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_cobs_decode.v", "sha256": "5964e1b3a0820c2ab348e0f87793b4a18c08b55586a5c65d6a1c86d9602babf6"}}
{"design_id": "ba4e54701d25", "module_name": "axi_ad7606x", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad7606x/axi_ad7606x.v", "sha256": "9a731a84e43c6527f0485f13fa87e131eb257755073c7c2fa18b9e7b5df57b09"}}
{"design_id": "ba5a38453cbf", "module_name": "uart_tx", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "uart_tx.v", "sha256": "e54adaa77b2f6c2200ac693a858bf435048f8492b03f18d0fe4bcfdf001b215d"}}
{"design_id": "ba8f0d9c386c", "module_name": "crc16_dat24", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc16_dat24.v", "sha256": "0297139587bfdc0992ff2bcb0463585df9542b7d05802b56707a5336be12e922"}}
{"design_id": "bab2087fa8d3", "module_name": "ct_idu_is_aiq_lch_rdy_2", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_is_aiq_lch_rdy_2.v", "sha256": "91d8a7aad3672a426b713c4d51b4117a79aa70463322bd63c8f89fb56f327d6e"}}
{"design_id": "bac6a8ddb3f6", "module_name": "sirv_pmu_core", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_pmu_core.v", "sha256": "d53b2a3a9b14805f057387585800d01d73e4c7919b5ef46e775dc875fb58ce90"}}
{"design_id": "bacb1df267ad", "module_name": "util_dacfifo_bypass", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/avl_dacfifo/util_dacfifo_bypass.v", "sha256": "100d020f54145ada0d9cc4f46fba8972e6af87dcf11edf29ad93a692bbdf22d5"}}
{"design_id": "badc9ce9a8dd", "module_name": "axilite2axi", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/axilite2axi.v", "sha256": "f500694c4aa3a735123b8258e2ceef71715b2d344d62abe967156360baeb6011"}}
{"design_id": "bb158c3ed41d", "module_name": "pcie_s10_msi", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_s10_msi.v", "sha256": "ebe335e19b1fffcedad2f108284ab0c943da91e7563ba6444e8d2a54a4ffb195"}}
{"design_id": "bb18d0ace7c4", "module_name": "ct_lsu_pfu_gsdb", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_pfu_gsdb.v", "sha256": "bf09952c103c8a724c225ffae03a13c58435f5142e08b0f38d8a2f5b5a3a65aa"}}
{"design_id": "bb1c1f134883", "module_name": "uart6_atlys", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "KCPSM6_Release9_30Sept14/UART_and_PicoTerm/ATLYS_design/uart6_atlys.v", "sha256": "c7226388e1e97bd58e7a91dc8f9946409e29cba5a029a62b5e26e27cb485fa65"}}
{"design_id": "bb24362ff345", "module_name": "ct_lsu_lfb_data_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_lfb_data_entry.v", "sha256": "75d92db6b5e69094607a3b42c8f5a67997e5c03d5c7db0e588a2bde7abadd6fc"}}
{"design_id": "bb252fe98aba", "module_name": "eth_mac_10g", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_10g.v", "sha256": "a3e3e6102c747ad7d29a7e87252b2fbb9484f480dad768bcf19fda82b10f7e8d"}}
{"design_id": "bb2d3c00e77a", "module_name": "axi_dacfifo_wr", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_dacfifo/axi_dacfifo_wr.v", "sha256": "8c513000c0180599ee0438e8551921908ca7b222aaf604a5c9108476b9e8124f"}}
{"design_id": "bb5b3eaf1591", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/cpp/TestBufferRemoval3_3.v", "sha256": "d2585332d0fa25cd0f22915584b4972828e0f2dc63bdc039d5b7a925c3aeccbd"}}
{"design_id": "bbb726e9dc2b", "module_name": "axil_adapter", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_adapter.v", "sha256": "7bc9936dc5c19d42397b638397064aa3ba51906c2cfbf1200d80a8f28ddaea26"}}
{"design_id": "bbd36ec6dda4", "module_name": "sync_reset", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/sync_reset.v", "sha256": "c1f90f36f63da7deb27225349283c0e3524900d3ba3fb61e2189529784c91b02"}}
{"design_id": "bbd3759c3e9d", "module_name": "pcie_ptile_cfg", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_ptile_cfg.v", "sha256": "56017776de17ea7a42e739a9a663d5b596874b539931dc26e2d6bbede8c3a909"}}
{"design_id": "bbf27cff3057", "module_name": "input_stage", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_adv_timer/input_stage.v", "sha256": "e93b2f66e44ebb3d0d96ecbd5620d28589c818b16411b84bd631d574cf111f34"}}
{"design_id": "bbf87bfe341d", "module_name": "oh_mult", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mult.v", "sha256": "e32eb72ab84bd23bf4626321ed0beda8d1374ef684d10c244405102eb05c67cf"}}
{"design_id": "bc126e407365", "module_name": "ct_biu_other_io_sync", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_other_io_sync.v", "sha256": "11cb45c8ed7dd871f68a88e4fcfb05c33ba5adce83caaa7b6533f667c7e60884"}}
{"design_id": "bc679a4d55c9", "module_name": "ct_spsram_32768x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_32768x128.v", "sha256": "80f1bff3be1b38141ae7fee9a507f5d932902cb70820de3fb14b32f49ad98d6d"}}
{"design_id": "bc7802371755", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/DE10_Agilex/fpga/rtl/fpga.v", "sha256": "ca848534f8e00953da051f6a82264c34b6c2fc5bbd553249857a1b43c35714b1"}}
{"design_id": "bc788e91bec4", "module_name": "example_core_pcie_us", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/common/rtl/example_core_pcie_us.v", "sha256": "1285c85c84f06f3d75e55b324feac0c0feea5cd4f2be8afb81572a3d805f0aeb"}}
{"design_id": "bcacf28e636a", "module_name": "axi_ada4355_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ada4355/axi_ada4355_if.v", "sha256": "603310c91ac4e459a63b2b365320a0d3dbb662a2708e7fac53ae232f128476a6"}}
{"design_id": "bcae2ccc725b", "module_name": "led_ctrl_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/led_ctrl_rom.v", "sha256": "7b4b3739f841c5647da9616174ba6cdfa8ef2b299097e6d5f6c686108110e0b6"}}
{"design_id": "bcd417bbd6b0", "module_name": "test_16_sinks", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/cts/test/simple_test_hier.v", "sha256": "734329f850843c0bbe79a956365a566a88b532d6c43561ffd5da15c01d238695"}}
{"design_id": "bce8ef74cfc1", "module_name": "eth_mac_dual_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DE10_Agilex/fpga_100g/rtl/eth_mac_dual_quad_wrapper.v", "sha256": "0e01bac0c93ede7259aa7f095fdbd6512f8ac8bb67909e55abf0cfc2e17c6c4a"}}
{"design_id": "bcec8b4dfc34", "module_name": "axis_eth_fcs_check_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_eth_fcs_check_64.v", "sha256": "5d5d06c813a8b108173db5636266f4511de5fa6cf5478fb48472e72e6a752ad9"}}
{"design_id": "bcf8e2e0ca3b", "module_name": "axi_crossbar", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_crossbar.v", "sha256": "f2e5177a8c8bbe4ed844554eece7abd207365a8a7a20796e0654e08362b51b3d"}}
{"design_id": "bd0dfa8a76a0", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/common/c5soc/system_top.v", "sha256": "6a50d7ab2df039bf575ed28564fe448b17e0d822f68054705d9385419015168a"}}
{"design_id": "bd12cfd34ba5", "module_name": "ip_eth_rx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ip_eth_rx.v", "sha256": "f8f4bfb0352872b3e7a52616242e51fd5c6261c93a2569fbf9e0777620e1f8ae"}}
{"design_id": "bd173ec0e9ca", "module_name": "pcie_ptile_if_tx", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_ptile_if_tx.v", "sha256": "49c4f3424ab1bd4c429e38e42eead52c9232d8375731aa816cfae84c79d3c360"}}
{"design_id": "bd2c36a47761", "module_name": "ct_f_spsram_128x144", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_128x144.v", "sha256": "62713d14f948fbc4c26975042b276303178adc8ebf044fd56a31d7c52d39ff00"}}
{"design_id": "bd91163366d3", "module_name": "axis_baser_tx_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_baser_tx_64.v", "sha256": "93cfcc649ae207f34f97fc91c93320d4243e2f262736d9b9fcef181f14407cdf"}}
{"design_id": "bd96a8d4ae5b", "module_name": "servclone10", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servclone10.v", "sha256": "92676794510cc3770a8533c51036e1dbc4c0e34db261a86c4089b4ce1a0a0f45"}}
{"design_id": "bdb285db3646", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v", "sha256": "a4c9c65250507cf5fda79689130865404998ec4373958a6091d83516931a6ebf"}}
{"design_id": "bddc6528e0d1", "module_name": "ip_complete_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip_complete_64.v", "sha256": "df3502b52dcce13eb75ccb1dd66a2d7526bf5381be71aeb700963a224508da0a"}}
{"design_id": "bde34d3a0af9", "module_name": "ct_fcnvt_htos_sh", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fcnvt_htos_sh.v", "sha256": "d62c243794f3e0be753d27f36e8fb41d14effca3805cad123a490927fb2b0e2e"}}
{"design_id": "bdeddeec2eb3", "module_name": "uclock_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/uclock_rom.v", "sha256": "0da04b760b502c63dbcdd37e20116bceff2d45952563b2ccb3dfbbd19f42f7c4"}}
{"design_id": "be0f8918436c", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/520N_MX/fpga/rtl/fpga.v", "sha256": "55cdfe26ce340d8dd6a080a0e0b7764bb48719099a52619a362f6800a5ea8640"}}
{"design_id": "be3bc642a71c", "module_name": "gated_clk_cell", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v", "sha256": "6cfad397c18daabdff77e3a520ccbf964e4178197cc9a0f8dd825bbf928a91c8"}}
{"design_id": "be4146e300a9", "module_name": "sync_level2pulse", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/common/rtl/sync_level2pulse.v", "sha256": "774051f9aad6aed2c6aad8536d3c9e60eb17740abfe84838ac659f5cffb44588"}}
{"design_id": "be4d8028c233", "module_name": "axi_ad7405", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad7405/axi_ad7405.v", "sha256": "6c2c97e5ca076c1f74ed8828f769aec4db56b8d7658b1822d11d04ae613d7653"}}
{"design_id": "be9110a96c06", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v", "sha256": "33014523748633b9139714f5b08dd3f3547a95968d734af9fed5b47dd1778f15"}}
{"design_id": "beb0e01f7483", "module_name": "asic_clkicgor", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clkicgor.v", "sha256": "ae47dff46a0422c461645c7d77b908914648ee1485430ebf6edaaddbff2c87f4"}}
{"design_id": "bec2b615ba6a", "module_name": "axil_crossbar_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_crossbar_rd.v", "sha256": "b43f1a86164949e78e01e29864c9a2cad5bd442be8356231d2993beaeb3d4e99"}}
{"design_id": "bedab6208fb8", "module_name": "adrv9001_rx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/adrv9001_rx.v", "sha256": "19c1d6f53026fc22824691f231b4c28ffbb6d86716830cd104a660abaff4dfdf"}}
{"design_id": "bf04328f80c3", "module_name": "sirv_qspi_media", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_qspi_media.v", "sha256": "f025be99fed8f13907b1778881619a4ebc7f55342c8d734ab6d6dea629d78d5d"}}
{"design_id": "bf9704e223e3", "module_name": "syn_csb_master", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "verif/synth_tb/csb_master.v", "sha256": "fd329eaabe3abe373f17a256cd045a2655566f0d23f18bb8a60e1b37a4012fbf"}}
{"design_id": "bfa1373d59cd", "module_name": "ct_idu_rf_fwd_vreg", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_rf_fwd_vreg.v", "sha256": "c25740b6b1e33e08e3638350fac6b9494001949f130066987be58859fc94ca0f"}}
{"design_id": "bfd6e27d4037", "module_name": "asic_dsync", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dsync.v", "sha256": "4d803fa7e330b40c9699fc053de7a989898cd4dc0a3a15a65738675f81132b6d"}}
{"design_id": "bfe00d48012a", "module_name": "test_axis_cobs_decode", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_cobs_decode.v", "sha256": "d881dd11679bc5d73b6dd1001450372800a32c3690c53901595e392a98dea534"}}
{"design_id": "bff636f501c3", "module_name": "nv_ram_rwsp_128x11", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsp_128x11.v", "sha256": "319752c081033cc9b51e824abc72c666173f6b0be4a499ae3416c3a57696e75e"}}
{"design_id": "c022ebed08be", "module_name": "ct_ciu_bmbif", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_bmbif.v", "sha256": "c1711578f6cf3070268faf3079cb2367e97d5e323909bc30509b371e9c12158f"}}
{"design_id": "c028d68cee33", "module_name": "eth_gth_phy_quad", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG640/fpga_cxpt16/rtl/eth_gth_phy_quad.v", "sha256": "a9c86e87b929bcc3fc4048415a3a05d8c504b15b8224bfed62f2bb95a72b9261"}}
{"design_id": "c033ec62cfd7", "module_name": "axi_ad9434_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9434/axi_ad9434_pnmon.v", "sha256": "3106034213484383aaba31e2240007f338b61bc58bcd7613fb7f23092afdfbd8"}}
{"design_id": "c035dda61bf6", "module_name": "sirv_AsyncResetRegVec_36", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_AsyncResetRegVec_36.v", "sha256": "741613f950eb24a1266bbbe2722ac98ecae9abd647350243c6d9545c73cabb7d"}}
{"design_id": "c03a0311c6d7", "module_name": "dma_psdpram_async", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_psdpram_async.v", "sha256": "67e06c3d2de78e50d559302266c15001e44c4ed3143d55660fff971f1fb37f51"}}
{"design_id": "c055ae73dc65", "module_name": "crc32_dat32_any_byte", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat32_any_byte.v", "sha256": "65ea747f3c801942034b9d28a99b013bcf354d0afdc5e3caac75dc4d85d4f5d2"}}
{"design_id": "c08798152e7d", "module_name": "sirv_AsyncResetRegVec_67", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_AsyncResetRegVec_67.v", "sha256": "65d42b646f8c1dfd6b9530656e8d3801afc013277005965e8ea71ad4d8f529f5"}}
{"design_id": "c0b453b44285", "module_name": "axis_adapter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_adapter.v", "sha256": "4b9b6649f12e374c24d36f2d42680ecf1f38cca8ae4fda7fd68dbf722b6c8140"}}
{"design_id": "c0c4e925b1fd", "module_name": "sirv_qspi_arbiter", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_qspi_arbiter.v", "sha256": "cd7ef97bfd10f11a146d276334c25f17c92a0ebc28783c200c85619d0f26d9bc"}}
{"design_id": "c0c9ba698019", "module_name": "ad_dds_sine", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_dds_sine.v", "sha256": "78aa69456db4dfe8f9d6a0b8d7af91c12344e03cf1dbee03abd246d2a4b75a5b"}}
{"design_id": "c0ee5ba8313a", "module_name": "axi_ad9467_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9467/axi_ad9467_pnmon.v", "sha256": "fc36af4a59fe144dd6389eafe1bbce88d5d67bd2c18905c3c0c0f45d1781c972"}}
{"design_id": "c1512867c334", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/AU250/fpga_axi/rtl/fpga_core.v", "sha256": "e210704f4227d0c3ee57cddb686473b59e883c2b9d39e4f5b2b1d9d777c76a9a"}}
{"design_id": "c1921da15adb", "module_name": "axi_register_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_register_wr.v", "sha256": "02dd26f56ee04ad834a28e02ef2726852ab527fb23c3a88b377f3ce55a719c4b"}}
{"design_id": "c1b76d933a35", "module_name": "eth_mac_mii", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_mii.v", "sha256": "0de7c247c1d13b0069d969f4b0bbbf6377c5db380feff9eb87c99a0bd715daf7"}}
{"design_id": "c1bf15a34e50", "module_name": "ptp_td_phc", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ptp_td_phc.v", "sha256": "3595915a28856442648fb5372c791dae9e68a092da23c5bd3a7d578c3d0cb980"}}
{"design_id": "c1d4b1db1de7", "module_name": "axi_ram_wr_rd_if", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_ram_wr_rd_if.v", "sha256": "36997f5e6de6accab4211704b25c97a5a53319004d2046fe93b1b7d44edb68a2"}}
{"design_id": "c20935a6a253", "module_name": "oh_or3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_or3.v", "sha256": "cae34752ce852ad1a9475cd8148e5b03ae457669ae50b57dd67954f9978df51a"}}
{"design_id": "c21a81e09020", "module_name": "ct_had_ir", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_ir.v", "sha256": "b9d65bdf0547612bd53822c603a389ddbea6a70cf02cfed8e381d9e11e1a4a35"}}
{"design_id": "c21b51036df5", "module_name": "gpio0", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/gpio0.v", "sha256": "b7fb2d40adfe8153867c96ce37e002796d4aa7985e7b996349ea25cadef190f2"}}
{"design_id": "c21f41518019", "module_name": "test_udp_demux_4", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_udp_demux_4.v", "sha256": "f37ee9f3a1af5c38253f228a27788c967ac3ecf3371c0b79b10a37bca5b38055"}}
{"design_id": "c25d55a2cc45", "module_name": "ct_lsu_amr", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_amr.v", "sha256": "532fb08207473e9944b93bbb5813ec99bddc7ce3da93e6051b426152cfce434b"}}
{"design_id": "c278498adcb6", "module_name": "asic_nor2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_nor2.v", "sha256": "83ba032d24964fc2e9caaed7f73716d8b50c5c4449ede7f64cf671eb02b211ad"}}
{"design_id": "c285451d72f3", "module_name": "wbdown", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/wbdown.v", "sha256": "d1ad3d2829037533ee67fd080dfd7acf21ceef71ce4946484bdcd0c8f17c3f55"}}
{"design_id": "c2892a12bc21", "module_name": "pcileech_mux", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "sp605_ft601/pcileech_mux.v", "sha256": "9b8d56eece879f721d37553dd32622aec71ef0945c1c51f0b722752fea792f65"}}
{"design_id": "c2a2614d0d06", "module_name": "tx_req_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tx_req_mux.v", "sha256": "86072c0e5175f13ee59a7ca57dcccdf85f7c0fcc5b023be991275c2c8c06e9ac"}}
{"design_id": "c2bef58c9f29", "module_name": "pcileech_mux", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "ScreamerM2/src/pcileech_mux.sv", "sha256": "0c264ebf3ab163fbe122bc90ad03cb874809ac9f3e73048b563a768abbd5e63c"}}
{"design_id": "c2d2ba878b52", "module_name": "pipe_equal", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/compare/pipe_equal.v", "sha256": "bc5fe6cfa7afcf5bc3fc0b3f0f9ba119fb11ddfeb6303c45346a71c8aeb714ad"}}
{"design_id": "c2d5951564ef", "module_name": "servant_pf", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_pf.v", "sha256": "23b19fd34372969d4fea7105ec46536e437d0bba560476fa4c75c77ae7ef5fcf"}}
{"design_id": "c2fd355c8789", "module_name": "three_two_comp", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/three_two_comp.v", "sha256": "70d15bce736bab3db5b518679ec630c4c93c20673d37b401d6b49e2de881f188"}}
{"design_id": "c31789c92fed", "module_name": "axi_adxcvr_es", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_adxcvr/axi_adxcvr_es.v", "sha256": "76ec46ebdfa5292e25a8bfd3ace49d8d44ab45a7392bd33cb1364c22ef129ec6"}}
{"design_id": "c32e0d6f599b", "module_name": "seconds_counter", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/counter/seconds_counter.v", "sha256": "1964fd4b8d65433c1d697e9594cad14917abed43218e36b81d0ad409ab720537"}}
{"design_id": "c33584acecd9", "module_name": "and2", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/check_axioms.v", "sha256": "177e4a0668eba9596a1e3b6e42aaadec6018960ce9f1899fca34c54a219c44f7"}}
{"design_id": "c34b9f776b9e", "module_name": "ct_sysio_kid", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/cpu/rtl/ct_sysio_kid.v", "sha256": "526d3bdecb827fa6b06add572216daec02c57b81fda1909bd50f3a3a227567bb"}}
{"design_id": "c38b3b4dc470", "module_name": "servant_md_kolibri", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_md_kolibri.v", "sha256": "e651ea90cb0ac3e078b6f2083aee725c458d11659e0c63bcc9f72d3e9149635a"}}
{"design_id": "c3c01aacb669", "module_name": "NV_NVDLA_CSC_SG_wt_fifo", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/csc/NV_NVDLA_CSC_SG_wt_fifo.v", "sha256": "1a62bb98d205bc129c941ba29f6be2b52a61c8d6871593cf300b714f3053eaa4"}}
{"design_id": "c3c88e3cfab9", "module_name": "ct_had_etm", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_etm.v", "sha256": "512f6c4ab1c0818bc367e0a67213e6f4adf4f6a37a4d8e18b6f7469f9aed8016"}}
{"design_id": "c3e7611730ef", "module_name": "ct_f_spsram_8192x32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_8192x32.v", "sha256": "87e9cc3426b46b406b47ae3eae3e8f2c7837308b739ddd6725c6bf54ea7c1d73"}}
{"design_id": "c3f0f3f95311", "module_name": "test_arp_cache", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_arp_cache.v", "sha256": "7dec006d2de7dedfd83727dea842e71b859f577fbaa7e958227dd07c2a9ec724"}}
{"design_id": "c4063c278ee3", "module_name": "asic_oa22", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oa22.v", "sha256": "3af3e581cb0424e3822f84cf46590b891e9358bd7250ba3a37cebf56997ed95a"}}
{"design_id": "c41967f35aa6", "module_name": "irq_rate_limit", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/irq_rate_limit.v", "sha256": "fd9a6bc5366f61e8739a7844a6628a1a7cc08e0aa72871d12babd924ce08a65d"}}
{"design_id": "c44c8483a2e7", "module_name": "ct_spsram_4096x144", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_4096x144.v", "sha256": "e449f737b82235ef7ca11fd04bf4f65bbdf06e05d6427daff9ed715138c6faeb"}}
{"design_id": "c451cc522835", "module_name": "oh_mux6", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mux6.v", "sha256": "c22021101284f4111ff718f8198287a968d050540ac0a4cafc3d0792d43c2de6"}}
{"design_id": "c480c391eb65", "module_name": "axiicache", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/axiicache.v", "sha256": "57169a69107445eb0e1165ebcc36ec8e464c082c74a71130909287d8b4349211"}}
{"design_id": "c52089673db3", "module_name": "ip_complete", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip_complete.v", "sha256": "4c0aac8dc73adac3f867f0f15e6bb1abda45f4d7417878e149fea79500791f63"}}
{"design_id": "c523153460c6", "module_name": "dcache_pmem_mux", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_cache_axi/src_v/dcache_pmem_mux.v", "sha256": "545f0b9929802a3fefa836931fc48f3a43887d8ad519edb4fc7eb19fcf98720e"}}
{"design_id": "c5269a80a427", "module_name": "zipdma_mm2s", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/zipdma/zipdma_mm2s.v", "sha256": "2d301683c43f87ced2c3c108a0704d20631c07c97291adca20e6857f84ae7b9c"}}
{"design_id": "c5403ab30428", "module_name": "udp_checksum_gen", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_checksum_gen.v", "sha256": "95ad19792cb143b4250d8e65ad8dea9ac1be8a8d1fa61ca631c80b24d16719fa"}}
{"design_id": "c563c61999a1", "module_name": "sirv_pmu", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_pmu.v", "sha256": "e886ccc79fc82153e153580c8b23e3ac07183c66145e50e3cc2189fa05195654"}}
{"design_id": "c565789c5964", "module_name": "adrv9001_rx_link", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/adrv9001_rx_link.v", "sha256": "ee53e7d27c0edae9cf306f3f2c57a767b64077dd5322ce55a113c73da64d5f2e"}}
{"design_id": "c59d50be16e6", "module_name": "oh_ram", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_ram.v", "sha256": "4768fdaf7327dfedefb41c5d09d485d52437d6698aafe1def721a644ee46c276"}}
{"design_id": "c5b6f86f233c", "module_name": "test_dma_if_pcie_us_wr_64", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_dma_if_pcie_us_wr_64.v", "sha256": "b69f710ee0b1ba26a4c5c0ac9ae6e256a3f852cd82ad513cb6e845aaac0164d1"}}
{"design_id": "c5ce9da80c74", "module_name": "ct_mmu_dplru", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_dplru.v", "sha256": "d5593bc8fdeaf63faefe87ec75555a11cfcdd66ce4d8d0021e25b52b6723adf7"}}
{"design_id": "c5d44b700aa3", "module_name": "sirv_AsyncResetRegVec_1", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_AsyncResetRegVec_1.v", "sha256": "2834d3ba92948d01eebe5900a2633febdbe785dfb696ad809a309ac4162e73b4"}}
{"design_id": "c5f419c17e72", "module_name": "oh_rsync", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_rsync.v", "sha256": "756a22ce9859b132119c21189bf25dddf18fdbd65bfbe1c0e870f4c7f9d07598"}}
{"design_id": "c61c13649994", "module_name": "clock_mux", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/synchronization/clock_mux.v", "sha256": "8e12e1cc1860ac32a49970ae084ac3d0d199a0ca0ae8c4760f2943f43d6a36d5"}}
{"design_id": "c645478021b9", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "c64f3135a384", "module_name": "crc32_dat16", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat16.v", "sha256": "adb4065e2c97b336e2fa0180f51ed732671dbbff29ff3481c83874ee3a95b531"}}
{"design_id": "c66c16e55df7", "module_name": "i2c_master", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG9200/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v", "sha256": "ec735fe59297c73dc165ca127cfd487ca19fe051f3dbecebd98e13589f77cd86"}}
{"design_id": "c66d171fe750", "module_name": "pcie_us_if", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_if.v", "sha256": "18ec3da717070040dd197afba830f736885ee4702029fb7000758ebe312beb44"}}
{"design_id": "c6751053f0af", "module_name": "ct_spsram_256x54", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_256x54.v", "sha256": "f226bfd2138fb208ffc1a3598365d08700a364ddc79b57872b828085df586eb4"}}
{"design_id": "c697504035a4", "module_name": "bin_to_gray", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/translation/bin_to_gray.v", "sha256": "e916322964ed8dcbb318f11c1ab819b1a8e9196150b8e6040c3a6e68e93bafd4"}}
{"design_id": "c6b1df368df6", "module_name": "ice40up5k_spram", "split": "train", "source": {"repository": "https://github.com/YosysHQ/picorv32", "commit": "ef203c2b0a3fb793280f5114941416c425c5b461", "path": "picosoc/ice40up5k_spram.v", "sha256": "980fe3f8f66c8ad644d018320216b420dc237d3b955749b3f01f461016e26e7b"}}
{"design_id": "c6c17a919b77", "module_name": "NV_NVDLA_GLB_csb", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/glb/NV_NVDLA_GLB_csb.v", "sha256": "e4097ebce8a6655687586df1e995c18b97ff799cf3a3b6666c58d7c640d1847d"}}
{"design_id": "c6dff7da5e3a", "module_name": "NV_NVDLA_SDP_MRDMA_gate", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_gate.v", "sha256": "c42d9a76e0b3d041bcc748a1b0a4a71bdb7f18a7d63e3be3ae7ea5facf66fa02"}}
{"design_id": "c6e35d1e16b0", "module_name": "axis_fifo_adapter", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_fifo_adapter.v", "sha256": "7662fbf53def5dfb353a590a3ae7309b4f9519847288c90a42ed63df57c95d00"}}
{"design_id": "c6f6dee30495", "module_name": "servant_ax309", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_ax309.v", "sha256": "d6f7d214c83cd45cfecffb757ae3e9b20a43f1b642dcea792ddf65aa6e365fbe"}}
{"design_id": "c709700fa571", "module_name": "uart_rx", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_uart/uart_rx.v", "sha256": "3eaff563777043772c66d1bf504ff5ddcd5723689b53a50444bb90aec618c39a"}}
{"design_id": "c70a0d239efb", "module_name": "axi_crossbar_addr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_crossbar_addr.v", "sha256": "5d0e1a5b885c6b271b864b64a834057496428147ce3c3ae633459251239048fb"}}
{"design_id": "c74103a637dc", "module_name": "jtag_io_out0", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/jtag_io_out0.v", "sha256": "a42d9dcaa18925c77e2cd644d4d992314a80822c1a90e4a6651619e4884c0188"}}
{"design_id": "c744a68bdeda", "module_name": "ct_vfdsu_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_top.v", "sha256": "63ba716c6b09d3ff23d7a95b55c451b099af4414655d69dd191638496c46370e"}}
{"design_id": "c75695847049", "module_name": "countdown", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/cgt/test/countdown_asap7.v", "sha256": "e438cc09619d59b7acf9c0eff792da7ff6dc610cc7207e34a21b5c1739a108ec"}}
{"design_id": "c764c7842c0c", "module_name": "demofull", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/demofull.v", "sha256": "8e6a878397ad913aa6bb7d0cd0c45b41335bcf2222878cf6205fec4599883248"}}
{"design_id": "c766d819cf14", "module_name": "eth_phy_10g_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_phy_10g_rx.v", "sha256": "6852e9f65cceb80626281bba46fa529822498238f27d7deee2905187586e5784"}}
{"design_id": "c773c75b7efc", "module_name": "axi_pulse_gen", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_pulse_gen/axi_pulse_gen.v", "sha256": "e0d3b89f3c5671a78a7b5570b149335f3c5751cf0af728d1ff1b849cd6a77169"}}
{"design_id": "c77dec7bf298", "module_name": "pcie_us_if_rq", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_if_rq.v", "sha256": "2435f567585bad3583e5e985b42e49d3613921ea6e921bd45fb216ca9310a4b1"}}
{"design_id": "c7a2091904c3", "module_name": "test_axis_demux_4_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_demux_4_64.v", "sha256": "e2141ea69c9afaad002f25f0fb4a20c149d923d5ec97d38f13285dd5c067ae33"}}
{"design_id": "c7a442677785", "module_name": "approx_fp_sqrt", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/approx_fp_sqrt.v", "sha256": "85e2f92aeb61b224a80ced2b7bea3362134b3931e9e758a205802efb62c9afe8"}}
{"design_id": "c804ad9954e9", "module_name": "gearbox_66_32", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/gearbox_66_32.v", "sha256": "e3554a8b15efe839185f2cb9235c5bc2d7d0b60758d9b1fe459ad18b60860afc"}}
{"design_id": "c83cd8444a29", "module_name": "ad_mem_dual", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_mem_dual.v", "sha256": "375676b2e7cf3676503eae3ab6426fbb876611a80f611bd96cf82b091d5cdaf0"}}
{"design_id": "c845bf179b65", "module_name": "test_pattern", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/test_pattern.v", "sha256": "133fd73f2d4d5621a56856a08ded07628b29be53df6907fc042c6e03d9bcf5d5"}}
{"design_id": "c8494c23e68c", "module_name": "OBUFDS", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/OBUFDS.v", "sha256": "d59b647aa9cfec6049ee0ae2a9a36ff202730d5196fa15e667a28aa4fa19e7a5"}}
{"design_id": "c891c075f68f", "module_name": "oh_csa62", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_csa62.v", "sha256": "9d7f4b972c2cd50cc0114d648f4a12d8749b850cb916ecfcf20d8a695037d80c"}}
{"design_id": "c8c4e6032022", "module_name": "ethernet_xcvu11p", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/corundum/ethernet/xcvu11p/ethernet_xcvu11p.v", "sha256": "f3457b2cbfa03d5cca241c4e0c367c6faacd200ba1d55b193cc43b0c649d401d"}}
{"design_id": "c8f0823eede7", "module_name": "fec_rot_14", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_14.v", "sha256": "05399b72c280515d42cd14d3dbb2f24bd5504eca6a107e6b2e4fc5f896f773e3"}}
{"design_id": "c9219a39a30d", "module_name": "fec_rot_27", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_27.v", "sha256": "c4d92a954899301abf15a1d2e19ee615d198e56cf1245d2f87641192bfb5d3ab"}}
{"design_id": "c9259114f428", "module_name": "sirv_hclkgen_regs", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_hclkgen_regs.v", "sha256": "4da8c7eab7218ca7c401e76b3fab5f4ff69c5d74527fa57fc92d61b0b32c0f94"}}
{"design_id": "c9448d18f114", "module_name": "mqnic_egress", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_egress.v", "sha256": "a2cfad7c7558ddcfc139868228c9bd3595ecd9b2bede07271c6a801771da4e6c"}}
{"design_id": "c94ba0543e5c", "module_name": "asic_oai32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oai32.v", "sha256": "b42e9a758d499b56170bb8d15ce88fb50cbf4e5563cc4bec341409bc8f6c30d5"}}
{"design_id": "c954651323e5", "module_name": "aes_round_256", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/aes/aes_round_256.v", "sha256": "b45fa4527daf8b96096c1798a4eb6959a039b2bfe12a78bd52ae4f098559629d"}}
{"design_id": "c97b2ba975d4", "module_name": "dma_ram_demux_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_ram_demux_rd.v", "sha256": "41ffae6d95c4781848cb9f392ce419770de78446ac506b6fcaf1ce7fc1627fc7"}}
{"design_id": "c992151aade0", "module_name": "ct_f_spsram_512x44", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_512x44.v", "sha256": "ec8a67e55ac70a5a195206f13b1888808dc2815a6159c72f3b673d5492346eae"}}
{"design_id": "c9b40acfcf64", "module_name": "fpga_ram", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/fpga_ram.v", "sha256": "9907d3f5929d1dd425fc3c7d91a854ab177a4e6f410e10c45bdec060e0797fab"}}
{"design_id": "c9b748ebac8b", "module_name": "axi_fifo_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_fifo_wr.v", "sha256": "e0f06c5c6e3deae0b764e85319e16395c7b2e428b7419853c264129350df67ca"}}
{"design_id": "ca720a4fed80", "module_name": "icache_data_ram", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_cache_axi/src_v/icache_data_ram.v", "sha256": "de6ba2a00f3d8b78fee11da52ab45156bab22a3cea008364d724cdf48574d280"}}
{"design_id": "caa99c4a5fb9", "module_name": "blockram", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/blockram.v", "sha256": "f1d2819cbc441387455cd08f8660dac722c6c438db49cc3de2f8eface4d6cc39"}}
{"design_id": "cab561b64370", "module_name": "oh_aoi31", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_aoi31.v", "sha256": "0dadad5c9ea2919b37a873c5bda5f6283c720e9b494c77e426e6aa96fd4b1353"}}
{"design_id": "cac95bf72d52", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga_axi/rtl/fpga_core.v", "sha256": "8bddf6c0219b64cb3aa91c496c445543557c19477a8e2f76b019c6cbe7f92869"}}
{"design_id": "cae91cb84e4a", "module_name": "testint_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/testint_rom.v", "sha256": "e88cc11c4dc604a5468cd1488ba307f6375c2839217dba86cd551deb79caf8cc"}}
{"design_id": "cafb738fb6c8", "module_name": "RAMDP_128X6_GL_M2_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_128X6_GL_M2_E2.v", "sha256": "be356ef2c1b9c593351215203eabedd5902f235d5995193ed7fba8bbf7f813ac"}}
{"design_id": "cb0c71cfdcfb", "module_name": "px_had_sync", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/pmu/px_had_sync.v", "sha256": "9391e4379a1ee7d0de82a85e33e232b3b05476a521533a495821a1bb1482f851"}}
{"design_id": "cb1f0cd3c3a5", "module_name": "mem_icg_check_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/impl/mem_icg_test/mem_icg_check_top.v", "sha256": "df1610cec845ffb666d55bf1b00c9434cd77b9a62595daac1b3ca449c4ef2d64"}}
{"design_id": "cb258decb2e3", "module_name": "fpga", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/fb2CG/fpga_axi/rtl/fpga.v", "sha256": "f5722fb5fe13d892ed50056114d3a1e27bb8ec685f0cc49925d195ee2b4a7d77"}}
{"design_id": "cb6acd110c15", "module_name": "test_eth_mac_10g_fifo_32", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_eth_mac_10g_fifo_32.v", "sha256": "de40293f10623ecfbd4ca52792d5db48cb9fecb11cff2a9e8a24d1b47e3ca3db"}}
{"design_id": "cb868f1ab740", "module_name": "tcm_mem_ram", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_tcm_axi/src_v/tcm_mem_ram.v", "sha256": "17df5fcb4b68d20cad6987779a72b884161235e66791d1e46d0fee893e021a62"}}
{"design_id": "cb8c12396e2b", "module_name": "data_offload_regmap", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/data_offload/data_offload_regmap.v", "sha256": "a9bd18c444a333059652c1b6b87057731afb245b4a1f58c0d75db59595f14146"}}
{"design_id": "cb9212e9193e", "module_name": "arp", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/arp.v", "sha256": "41e2301695fdfc1cc93252041107574a0ed040ba92c99d57dce73317804f4698"}}
{"design_id": "cbb961451466", "module_name": "pmu", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/pmu/pmu.v", "sha256": "1b2cfaf5a2da9041709f30e1ec184715f353188aea0272651039d2b25fd735ef"}}
{"design_id": "cbdc5d689798", "module_name": "pcie_s10_if_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_s10_if_rx.v", "sha256": "3b725f7492a6cde765335296290ffd0fda7400edb9507b401bc86a432fc46969"}}
{"design_id": "cc0263530cc1", "module_name": "zipdma_rxgears", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/zipdma/zipdma_rxgears.v", "sha256": "bf0a4c4f3bd8c10412f796df53c9f20418dbde89074c582f51dc733534155c63"}}
{"design_id": "cc0ee9236ef1", "module_name": "tx_checksum", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tx_checksum.v", "sha256": "2d5d1b885daf9a77e0121b39b9b21dbef17d8b2716571a47c659e0f14b241386"}}
{"design_id": "cc11212ea30d", "module_name": "oh_clockmux", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_clockmux.v", "sha256": "921a594c497031a3f0a755d93dfe80642d81ddb89a3f838414afb2fe04158ea5"}}
{"design_id": "cc13a40604a1", "module_name": "riscv_decoder", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "core/riscv/riscv_decoder.v", "sha256": "aadb8a158a4b5cb52c86a84571542e5ea087450ebbc88e274f29095eadbdb443"}}
{"design_id": "cc4355a98d52", "module_name": "eth_gth_phy_quad", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG640/fpga/rtl/eth_gth_phy_quad.v", "sha256": "a9c86e87b929bcc3fc4048415a3a05d8c504b15b8224bfed62f2bb95a72b9261"}}
{"design_id": "cc5b233057f9", "module_name": "test_axil_adapter_16_32", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/tb/test_axil_adapter_16_32.v", "sha256": "c67a49e7a9e1525daf88eebe0fe2f9fa0c57bb50a89ab6888fd6f61306eb8340"}}
{"design_id": "cc71a36dde65", "module_name": "dma_psdpram_async", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_psdpram_async.v", "sha256": "67e06c3d2de78e50d559302266c15001e44c4ed3143d55660fff971f1fb37f51"}}
{"design_id": "cc762d3e658c", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/AU250/fpga_axi/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "cc8e2fa959bc", "module_name": "compare_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/compare/compare_tb.v", "sha256": "271459f6259eedb297f6848f30da4fcc219d4267bc65b3bbaa9fa5bedb13c92d"}}
{"design_id": "cc9e245d31e4", "module_name": "compare3m_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/compare3m_tb.v", "sha256": "4df61cab5f0347953b204bc584aa7bddd9849036d5c35f12157173ef6ee4bdad"}}
{"design_id": "ccc7a10cf19e", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ZCU106/fpga_axi/rtl/fpga.v", "sha256": "227add849c0b97397f2e1c1864c6dbca844d9ceba327c2e17a7018b92305075d"}}
{"design_id": "ccc84f3ac2f9", "module_name": "servile_arbiter", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servile/servile_arbiter.v", "sha256": "69d57d934956fdfa83cb02a24642ecd8b7a28bfa7786c3f515d68d4d07dd5507"}}
{"design_id": "cd2d7970ab20", "module_name": "hsci_mfrm_det", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hsci/hsci_mfrm_det.v", "sha256": "9b041f5adbc2f41c16b17c70ab7f41f1c2064a50edcd560a63561d7c99b1189d"}}
{"design_id": "cd38c68ed09f", "module_name": "axi_ad9684_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9684/axi_ad9684_if.v", "sha256": "d31b5c24bc35398a84bed7a3e0ccf9895ca58ddeebcd6c36dee82d53d1fc8fc5"}}
{"design_id": "cd8e76ccda08", "module_name": "oh_mx3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mx3.v", "sha256": "0f5642b357b95cb877fc22423c5e2f52f53a98d0548745a9bcfd571a13dfc8e2"}}
{"design_id": "cdce3454266d", "module_name": "NV_NVDLA_PDP_rdma", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/NV_NVDLA_PDP_rdma.v", "sha256": "3e4c905107e620640763bbaa135c7026d85c8cbced12f7fbda57ec20321c3244"}}
{"design_id": "ce1cec9cab21", "module_name": "axi_xcvrlb", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_xcvrlb/axi_xcvrlb.v", "sha256": "8af84a83499666362b74a5e6d8deb8d548097c7fb5bb8b728050e34db8b6cbbe"}}
{"design_id": "ce5e97ca14a3", "module_name": "spi_master", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "rtl/lib/spi/spi_master.v", "sha256": "b7973c9a3e0bf7178cdcc143d44ef525b825947164487cfdbff4b3acdae121c8"}}
{"design_id": "ce774f2a0f07", "module_name": "test_pcie_us_axi_master_wr_128", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axi_master_wr_128.v", "sha256": "4e91aed1c93f98f4fe1fc537cf631df4051ed6863d176254480be8d7a9a6c866"}}
{"design_id": "ce8b6c75ed55", "module_name": "ptp_clock", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ptp_clock.v", "sha256": "7d62e2a1715384e8c47f7cbb474662f9c183ea325942dbe1e456610f6110da81"}}
{"design_id": "cea5da608e21", "module_name": "NV_NVDLA_PDP_REG_single", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/NV_NVDLA_PDP_REG_single.v", "sha256": "850f750cf3f2cc75f393b60fb15d3320f5d66c668d24de723cfd00f082f9ea7a"}}
{"design_id": "ceb2f0eaa23e", "module_name": "dma_ram_demux_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_ram_demux_wr.v", "sha256": "77dbe7e0f710744b34e11d8a83a41bac3c63c83b858e2c0bce3aa9a160083cc2"}}
{"design_id": "cf1951d2ccc7", "module_name": "mpyop", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/mpyop.v", "sha256": "2b831b42a8b14671925c2284ce2e838378f3d738b1293eca74ede4c861aed5a4"}}
{"design_id": "cf217aa36f4a", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/S10DX_DK/fpga_10g/rtl/fpga.v", "sha256": "a7d004c3dab410c5ae729c97c2dd88c7a2096cda8ed3c1fba5e2b579a0f63526"}}
{"design_id": "cf228caca9a6", "module_name": "avl_adxcfg", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/avl_adxcfg/avl_adxcfg.v", "sha256": "1502347a094ece77e1dfbdd2d7a53b5def728870c14ab2ad5c90b8f420d0d34b"}}
{"design_id": "cf2ebd22989d", "module_name": "mac_ts_insert", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mac_ts_insert.v", "sha256": "266ebdcfe877c38b11096da4a3023d8351adea6598e0585fe9f17b31c40fae10"}}
{"design_id": "cf34e8b10adb", "module_name": "pffifo", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/pffifo.v", "sha256": "d1301833eb21e0ee9f9fbbecf92e2a3e8c7b6353b8bb048ca4a6142261236223"}}
{"design_id": "cf4057da4218", "module_name": "dma_client_axis_sink", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_client_axis_sink.v", "sha256": "a1e03efa7a8810a967b1e4a6b68fc75b0cbfc6f6a2ac137b9aa7321001029dd5"}}
{"design_id": "cf58aa4f776c", "module_name": "axi_ad9265_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9265/axi_ad9265_pnmon.v", "sha256": "d6775de23d43c5242cf98bf661352585268615b1c8a04ad57ba8a27c80d34b35"}}
{"design_id": "cf69a6a14510", "module_name": "asic_dmux8", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dmux8.v", "sha256": "fd144f5778ffe668bbc149015aa6c106d43e8be5fc722eb6e1c6ed8b6bbef9e8"}}
{"design_id": "cf6f667b4a7f", "module_name": "multi_sink", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/cts/test/hier_insertion_delay.v", "sha256": "df9fef3d992d9dcd42a2527d0aa05ead68f677e8c3a1b3b7819dc1e96e4f00b6"}}
{"design_id": "cf7bab93a9cf", "module_name": "ram", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/mem/ram.v", "sha256": "64ff25c24a3b9ebbbfe90a9fd0c15f282755a1476b1136da65541e9d031b5328"}}
{"design_id": "cfca3cf55878", "module_name": "axi_ad9265_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9265/axi_ad9265_channel.v", "sha256": "95be0b4858a230f9b4e871e3220903fdf3328d99de5f702f8bdf4e80e9434501"}}
{"design_id": "cfccb9ed17bc", "module_name": "ct_lsu_dcache_tag_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_dcache_tag_array.v", "sha256": "98be34da988c5619b38ad73588312303c8acbdc15c5fe7fef47a35b45a5d60e8"}}
{"design_id": "cfcdc5aef151", "module_name": "dut", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emailbox/dv/dut_emailbox.v", "sha256": "135dd42d1bddf25bfe091b4b0b13e7c2c9e83cbcf079a790192598160273552d"}}
{"design_id": "cfe660dc8bc4", "module_name": "oh_ao22", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_ao22.v", "sha256": "6d7814435bd0032083045793335b1514573beabcfe2fa16249b9feec35f42168"}}
{"design_id": "cfedd24e4570", "module_name": "ct_spsram_2048x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_2048x128.v", "sha256": "6607ec913cebf99bbfd1ad0d46b2ac34e82ec9290d5c9d6065bf6ad82d418ad7"}}
{"design_id": "cff06d09c71a", "module_name": "oh_or2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_or2.v", "sha256": "9c1d9207c549107456856dc25d9870ffca8c0b65ae492899695cd08eca6cea53"}}
{"design_id": "cff8ce0ab968", "module_name": "axil_dp_ram", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_dp_ram.v", "sha256": "5751657db197c9505aa2d57d64d32417e3a142c9fa725a013655f163d43fa33c"}}
{"design_id": "d0037a561cb7", "module_name": "eth_mac_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/S10DX_DK/fpga_10g/rtl/eth_mac_quad_wrapper.v", "sha256": "8f791e0327b0b071b54096258ad651b3cf9a0e56f0d2e6041511068c9a31ba5e"}}
{"design_id": "d024e3a8e1e0", "module_name": "tim6_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/tim6.v", "sha256": "e16b04afe9d66d5c22cbd885da786257fe4decf7336d661aa39be34b437d2098"}}
{"design_id": "d05480adad77", "module_name": "oh_oa21", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oa21.v", "sha256": "7ab2022b030dbdff6ff34a37c4aee7faad8a6ab98a6f9de877817a932d2c53da"}}
{"design_id": "d0b432caecd4", "module_name": "twenty_to_five", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/muxing/twenty_to_five.v", "sha256": "9319bd89057a2243e370312af74a8ee9701b274ffaf8673ef6aade96d2705e35"}}
{"design_id": "d10327fedcf8", "module_name": "ct_vfmau_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfmau/rtl/ct_vfmau_ctrl.v", "sha256": "36aa261c7a6d6c13c01bec8e291c7244eb1aae1902fb6fd8a68a6e77d432b206"}}
{"design_id": "d10fbbccd00e", "module_name": "pulse_sync", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hsci/pulse_sync.v", "sha256": "8ba1b931dcbc6b72b6546600ae175a238ac41f264822df200db1606484aec01c"}}
{"design_id": "d11ddf6b0502", "module_name": "ct_pmp_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/pmp/rtl/ct_pmp_top.v", "sha256": "a2295c70e221c9dbf95e0f712fc75a18cd22e0a6e05024c15ad6e20894da06e9"}}
{"design_id": "d12657c1aae6", "module_name": "tx_buffer_fifo_8word", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/tx_buffer_fifo_8word.v", "sha256": "164e69359b2daf78ae9eb16f12810e5ad913c83b7c3afc3043eefa2839ff0da5"}}
{"design_id": "d12d787fc99c", "module_name": "oh_latnq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_latnq.v", "sha256": "a8d278bac3c24c78978ad9106c6e2552370044bf4a5228e1f9d2400bc92c3478"}}
{"design_id": "d143bd57c549", "module_name": "fec_rot_6", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_6.v", "sha256": "0b19471cacf7be410b28aeb5c372444532065fe973c3c876cb9b598e7926ee4b"}}
{"design_id": "d14f66158869", "module_name": "response_generator", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/response_generator.v", "sha256": "b50b2e909ff440d65d68eb11680af833de0d6d91bdc6f3419fa26fb9508e883b"}}
{"design_id": "d14f78afdb25", "module_name": "test_eth_axis_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_eth_axis_rx.v", "sha256": "d61e9216cc048f35d672afcdc1f752f80846f5c5e29deee8ee2040e13d6f0705"}}
{"design_id": "d15319c7d0e7", "module_name": "SDFSNQD1", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/SDFSNQD1.v", "sha256": "5e1829db211c5a52d248a1029e5d3a532c5ea5a073c53ddce761ca83ecfd3a68"}}
{"design_id": "d1562e18496b", "module_name": "debounce_v2", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "debounce_v2.v", "sha256": "91ec1409b6ed6a4b5bff47af83e597cbd70e35d1661fc19375b19cae27f51566"}}
{"design_id": "d156ad229ec4", "module_name": "test_arp_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "tb/test_arp_64.v", "sha256": "0127dea29626fd453ba0192644057a90828de8f5935bbb16058acb71150ddb80"}}
{"design_id": "d163a0c403b5", "module_name": "mult_3tick", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/mult_3tick.v", "sha256": "3d2d8ee9c6fa56a4bb7f901ced07e6d7e8cef9d1393d45b6a0facf43b9e2f730"}}
{"design_id": "d1907cf0216c", "module_name": "util_pipeline_stage", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/util_pipeline_stage.v", "sha256": "c2c3b9303533319052e6432ff94222ce3ed4f31f5c086fb045a47a2c8bac8998"}}
{"design_id": "d1a018f10603", "module_name": "NV_NVDLA_CMAC_CORE_slcg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_slcg.v", "sha256": "c86a859862554e1fd84af71c7ebfc0c178b9782ac234d73931dd7cae46957b2d"}}
{"design_id": "d1d84f93e62f", "module_name": "fir_interp", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dac_interpolate/fir_interp.v", "sha256": "9ffc874cffe924043c12b621f2845fc046d526c050cca4176e255ffa77d9fa70"}}
{"design_id": "d1dbf92d744f", "module_name": "servant_te0802_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_te0802_clock_gen.v", "sha256": "39df2dc623155d01850c48914646dd7f643f6ee19504b7d6607dcee00630c229"}}
{"design_id": "d1e0bd306edf", "module_name": "ptp_clock_cdc", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ptp_clock_cdc.v", "sha256": "0c8c81cff4871a4b27998a12403902bbff9c6fc22e66d70eea3150b4e79b9dc6"}}
{"design_id": "d1e6ba08eacc", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/fmcomms5/zcu102/system_top.v", "sha256": "739b81d18076be3b1b1e84e4253bfe3194f61a02c625c9c1049a61d7e6d2152f"}}
{"design_id": "d207fc01ad64", "module_name": "sirv_plic_man", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_plic_man.v", "sha256": "cd10cb359df076f508837b7985979c5290d6c67ef756a2fa34a1e77073f8e949"}}
{"design_id": "d20c2128b353", "module_name": "udp_checksum_gen_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_checksum_gen_64.v", "sha256": "c28f8aeebfe34c74ef753f45478d64dfbaf615d0d854d61f75d0d112ca8995f0"}}
{"design_id": "d21178aa556e", "module_name": "sirv_gnrl_pipe_stage", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/general/sirv_gnrl_bufs.v", "sha256": "4b6251852b5ade18697aa24adc775f27b6af85808f86eedc569ecb4f87f3492d"}}
{"design_id": "d2409a3356d3", "module_name": "sirv_sim_ram", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/general/sirv_sim_ram.v", "sha256": "7894a1e5e030db5a72ca0c271ba018afa42bab4ea72a26f368f1a19a61ae3312"}}
{"design_id": "d25ae076431f", "module_name": "etx", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/etx.v", "sha256": "ae13dfd9fe6a2c40151e2394b58432204ddd9d9608f48a298c608a2f85688183"}}
{"design_id": "d302fef0cceb", "module_name": "ct_ifu_lbuf_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_lbuf_entry.v", "sha256": "aaec934d958fe5fcbc0f1470aec01dc347e54bc91b0bf1fb1a37fa0dc0eb0eaa"}}
{"design_id": "d307dc465712", "module_name": "example_core_pcie_ptile", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/common/rtl/example_core_pcie_ptile.v", "sha256": "58f2bda8cde2da1323d2606665298e74826b69b4ead5d107933e1bfe907391a7"}}
{"design_id": "d30b6833504c", "module_name": "IBUFDS", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/IBUFDS.v", "sha256": "45e1c538d87ed783231d2c16da60d00a1307f0ad4757a09b8d8c18a4a3300d4b"}}
{"design_id": "d31dc21affab", "module_name": "axilempty", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/axilempty.v", "sha256": "d43192045ab25fb11c946ce2ca2ea8da7197292d296f158cfa9ad9b9933aa11e"}}
{"design_id": "d354247819c3", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU108/fpga_axi/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "d355c10b2440", "module_name": "ethernet_vcu118", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/corundum/ethernet/vcu118/ethernet_vcu118.v", "sha256": "19e03454a6937907c08a5a4b8ba5a22d29a8c1b04a5cf8e3a9d71546116f4b9a"}}
{"design_id": "d356cce9e296", "module_name": "dynamic_delay", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "benchmark_projects/ise_benchmark/dynamic_delay.v", "sha256": "bb26adf4840925811e4b0ea56e62580e435874979156ff325cd1373a70cfb35f"}}
{"design_id": "d3604392b5b3", "module_name": "dummy", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/upf/test/data/isolation/mpd_top.v", "sha256": "1bb7b6b0f15ff1ebbd83a87b10a6f466907b91eded8116813dc98d922a0fcd95"}}
{"design_id": "d3771eb33c71", "module_name": "oh_clockmux4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_clockmux4.v", "sha256": "4289a089bc826457c2def0444f83afb6e26d5d62aad21dcb87509d39f97dd660"}}
{"design_id": "d377509c0471", "module_name": "sirv_qspi_physical_1", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_qspi_physical_1.v", "sha256": "c8fb4adac67371514ce563cf360e98f579202835f04fcbddaaa14762dfcc3fd5"}}
{"design_id": "d3f1188719b0", "module_name": "NV_NVDLA_PDP_RDMA_REG_dual", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v", "sha256": "d919809148755558c31c77a9c956eafb42c016a527b4787b66b5e86a93cde773"}}
{"design_id": "d3fd647a83c8", "module_name": "dcache_if_pmem", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_cache_axi/src_v/dcache_if_pmem.v", "sha256": "d5d51714b56c3a32afd79c09ad640c6e6ae6d56a7c6fe1602b106d5f16008398"}}
{"design_id": "d44484529370", "module_name": "dma_if_pcie_us", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_if_pcie_us.v", "sha256": "e0e4e2001f95062a61bcbb9ad25c0195a453334b6507b2c385e95ee9bd6fd902"}}
{"design_id": "d464d8643805", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU118/fpga_axi/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "d474ac3a1631", "module_name": "axi_dac_interpolate", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dac_interpolate/axi_dac_interpolate.v", "sha256": "36f3c9492def45dcb13d1411b8ae4791841f962503ffbea6ca848602173ad5c7"}}
{"design_id": "d4929ba0d0dc", "module_name": "stats_collect", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/stats_collect.v", "sha256": "f6194c56986445e887c647b29cd721d84d82a2ea53fa41801cbc1c91cf6371a1"}}
{"design_id": "d49fa2136571", "module_name": "axi_ad35xxr", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad35xxr/axi_ad35xxr.v", "sha256": "382fb2b1be9dc2218f8c53d7a8cd0eb556a61b25dc86cfd25f4dbecd3851fccc"}}
{"design_id": "d4a54f6556b9", "module_name": "emesh_wralign", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emesh/hdl/emesh_wralign.v", "sha256": "e31d09213fc0f77084f8a6194ff8757c7158798fcda341c47572c083e3a340fa"}}
{"design_id": "d4a62b03a2de", "module_name": "axil_crossbar_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_crossbar_wr.v", "sha256": "6b415d4d265a6694810913b67f62f93bd01128c59afe962d2784d45b9f310663"}}
{"design_id": "d4f19dfc3f40", "module_name": "sirv_aon_porrst", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_aon_porrst.v", "sha256": "1bc839e9b50a8169a65e5819c62bcf88b75755f0b60c46b30307fb190eaa285d"}}
{"design_id": "d4f94040c1e5", "module_name": "test_axis_arb_mux_4", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_arb_mux_4.v", "sha256": "86d6bfe7161c2acaade1834965153fed029fae4f9f8e0233809c96b16e6c1522"}}
{"design_id": "d507a83abd00", "module_name": "axi_pwm_gen_1", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_pwm_gen/axi_pwm_gen_1.v", "sha256": "f59833562e418c4de6b0c0bebaa280d514d3b5188d8c91c31687af359ede5177"}}
{"design_id": "d50a17adc4fb", "module_name": "axilcon", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/axilcon.v", "sha256": "e53522732c3a9160708d26a9e5e1f20e9a8451f82433418458d0ea8cd3633527"}}
{"design_id": "d51fbc8efc46", "module_name": "servant_ecp5_evn_clock_gen", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_ecp5_evn_clock_gen.v", "sha256": "1f2ff047f903703c400087fb1fda749d2a243dbff534bdc2d13aa6d9e51cb7ea"}}
{"design_id": "d53ce5228ad5", "module_name": "soft_ecc_ram_32bit_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ecc/soft_ecc_ram_32bit_tb.v", "sha256": "b0d9751784de9c6c30f1e62e41ab6100bfc94ac3fbc57614830ce5d52b7bc1ae"}}
{"design_id": "d5410a7b8ef2", "module_name": "ziptimer", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/peripherals/ziptimer.v", "sha256": "52c184e1267e93cf247971b2fed92209cfa18da4f7839f08f5b4aa0f67ef5df5"}}
{"design_id": "d553579584ce", "module_name": "oh_xor3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_xor3.v", "sha256": "ea1f2b9d9eeea1dd8d38fda7143f1dd8d4e01789746150bcf66643a3449820a9"}}
{"design_id": "d56c2ea95ba1", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X25/fpga/rtl/sync_reset.v", "sha256": "67ea2e751ee7cdf5c7528902eab32a63f11bd090e1380934fd7334b361c7d874"}}
{"design_id": "d5e56d96ffb6", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/Arty/fpga/rtl/fpga.v", "sha256": "ef12dfbf862df839bfef28e8133404a62c78cae24ec0f014c2c56b79300eaae2"}}
{"design_id": "d60d3554657c", "module_name": "sirv_LevelGateway", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_LevelGateway.v", "sha256": "a72ad6d2ae8b199742da8bf228f114b4c718ccf3286597abb39971193cedf25e"}}
{"design_id": "d613a91af207", "module_name": "fifo_hw_test", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/fifo_hw_test.v", "sha256": "3f4e7538b1bae6c52471cf6fb5e0c7a39163e195b8113a8a2c8f1ff6583421ec"}}
{"design_id": "d6383e044910", "module_name": "RAMDP_20X288_GL_M1_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_20X288_GL_M1_E2.v", "sha256": "5869125191c3cf11800a10eff69cef40b31ec94e74fa357ab012a4d2a635f904"}}
{"design_id": "d656807af0e2", "module_name": "pcie_tlp_demux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_tlp_demux.v", "sha256": "6b3c76538e54e7b71ece96ea5ad17bbc720b8b98d1fe18033a58aaea4b142511"}}
{"design_id": "d6b9a7d72f14", "module_name": "ct_vfalu_dp_pipe6", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_vfalu_dp_pipe6.v", "sha256": "83ddffde7852fd7dc3b5a804df51f09ee074467c7143ca7143dfabe3319b7f5c"}}
{"design_id": "d6bca092cb3b", "module_name": "des", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/des/des.v", "sha256": "34cf94e07ddd404e920a158b342a2a19f90056ddb56db94a1e68268079064b57"}}
{"design_id": "d6e41b087c5b", "module_name": "sirv_queue", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_queue.v", "sha256": "fc1b9ee9fe87a9a8ff1a8c50de9d74164d0b5080716557ab814e82a67b1ae133"}}
{"design_id": "d6fbd9235e16", "module_name": "ct_lsu_sd_ex1", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_sd_ex1.v", "sha256": "0a099bbae601b331b4b38b5906df15fb15b77d98ca865255da4a8a41d9a9f3a9"}}
{"design_id": "d74dd1ede811", "module_name": "gcd", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/gcd_asap7_cts.v", "sha256": "df40b82e99d111059369c5850d4fe0ec75fbd06994c5ad40236179026c0718ee"}}
{"design_id": "d75b1f0ba13e", "module_name": "pcie_tlp_fc_count", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_tlp_fc_count.v", "sha256": "05c471cf6dbb21948be867340aed09507e369dff69aeb4cd7c13f7845ff191be"}}
{"design_id": "d760f50c007f", "module_name": "asic_clknor2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_clknor2.v", "sha256": "36f87f68f49801158e4113422fe6fa8ed3082bd67e8cf1a5b99220da3e9e3349"}}
{"design_id": "d77d40da4813", "module_name": "up_hdmi_rx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_hdmi_rx.v", "sha256": "3ec17fda2d15abca5013bd02aaa8e647effbf1a554e3b016dbf2546cb7dc9e23"}}
{"design_id": "d7e04db7b797", "module_name": "axi_ad9963_rx_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9963/axi_ad9963_rx_channel.v", "sha256": "8e044ca5bbe8dbccd3e033527324a0a813e901876a7b10aa6cd77388ac60b5d7"}}
{"design_id": "d7eb04e10e9d", "module_name": "ptp_td_rel2tod", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ptp_td_rel2tod.v", "sha256": "2eefda2745a10c94f63971719ebb798910cd489f85deca0f83d4c46b2a0251ae"}}
{"design_id": "d7f9c9c1d7cc", "module_name": "udp_arb_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_arb_mux.v", "sha256": "a867eb6abe05986f71cae6ded5bdbf3746d54f358d8fdec83382fe38b8e6fc9d"}}
{"design_id": "d857db4ae363", "module_name": "i2c_master_byte_ctrl", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_i2c/i2c_master_byte_ctrl.v", "sha256": "84c975a59642918dc5d31c471413559e8beef3cfe7b589542791742bf212a8e9"}}
{"design_id": "d85d3a6fc6bb", "module_name": "axi_pulsar_lvds_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_pulsar_lvds/axi_pulsar_lvds_if.v", "sha256": "397ab1d55c177bffd1213d929fc9df05fb3456f6412da2fa1070d5c470096c9d"}}
{"design_id": "d88d7cd40497", "module_name": "fec_rot_16", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_16.v", "sha256": "f694c327f5bd5bd24b5cf01a3378d01d3dd80d24c51216f6cebacb3c3cda332c"}}
{"design_id": "d8978ef9ee27", "module_name": "bitscan_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arbitration/bitscan_tb.v", "sha256": "b2379a248b1e9980b5a051b818030639ec18da6f1db64268af0abcb6de85e3f4"}}
{"design_id": "d8bcb2a55d36", "module_name": "BUFGCE", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/common/rtl/BUFGCE.v", "sha256": "23b223f76f42d776fadfae0ae3b2f297791e5d95a985245e47f1642698a9e4f5"}}
{"design_id": "d936a79f7b37", "module_name": "testbench", "split": "train", "source": {"repository": "https://github.com/YosysHQ/picorv32", "commit": "ef203c2b0a3fb793280f5114941416c425c5b461", "path": "scripts/smtbmc/tracecmp.v", "sha256": "7f6e358b57f6c2bc2d048921f0e0a268f72719e649ad486a1922d048aa300104"}}
{"design_id": "d96c8f7c09f5", "module_name": "sys_pll", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/gowin_fmax_test_prj_template_v1/ip/sys_pll/sys_pll.v", "sha256": "083585100d7ff1048184d337f43979f4aaa85cb5f0dea476b0d49ab377a90204"}}
{"design_id": "d97265defaee", "module_name": "sirv_tlwidthwidget_qspi", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_tlwidthwidget_qspi.v", "sha256": "61d4c3b29f4a581c6798d27971d7b8a6d6f172117b554ceee565349d3b943220"}}
{"design_id": "d9836f9b4e87", "module_name": "serv_rf_top", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_rf_top.v", "sha256": "89faedf7530c34305bfbffd261732d95016bf5627f10b7bbafaa8e1fd6cd49c9"}}
{"design_id": "d99eea21bb0f", "module_name": "test_axi_dma_32_32", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "tb/test_axi_dma_32_32.v", "sha256": "729b55a61203fc31be5747f8c75b90394a2da9009d53ba4042ed69df8945cacb"}}
{"design_id": "d9d7ff8c2973", "module_name": "oh_regfile", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_regfile.v", "sha256": "68dcc4953303cc3d95899d1a4afd9d862f4ebfd961ca38cba21906df3edb0967"}}
{"design_id": "d9ee3dd75ea8", "module_name": "asic_dmux5", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dmux5.v", "sha256": "39af62a930819548b7ebd164dcf29e5bad4c23908aed2ed93db8a29131521d24"}}
{"design_id": "da0ee4b2e445", "module_name": "axi_adapter_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_adapter_wr.v", "sha256": "915b13883a1f13fd7b2c279186e5857778812802c52aea1580aacd804b82abe1"}}
{"design_id": "da37d7ee72f2", "module_name": "timer_module", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_adv_timer/timer_module.v", "sha256": "59435233271979437d50ae81ce9300221b657a7a7c2ec919f977230d52c452ff"}}
{"design_id": "da4a97259230", "module_name": "cntr", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/counter/cntr.v", "sha256": "996efc62dbe73f00d1cf2febea51bcb0b9f45f8a4ee506fba7f8fbc91361223b"}}
{"design_id": "da6a77cbdf19", "module_name": "servant_ac701", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_ac701.v", "sha256": "d1d0e2d0c44b9b78da7273f011bab154ad7d492136309501e0c73a1ff710b53f"}}
{"design_id": "da8302448f54", "module_name": "test_axis_frame_join_4", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_frame_join_4.v", "sha256": "593d16ceff9579c84c7f2dff1a002e45eb47ed7162959a90f2eeebe1ba061d1c"}}
{"design_id": "dace26edf59f", "module_name": "axi_register_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_register_rd.v", "sha256": "63f1bd6f9d72ae28643fd7af3a5d5bcb05d45cbfb290c59c120c327ba49aa575"}}
{"design_id": "dae0298636e4", "module_name": "NV_NVDLA_SDP_REG_single", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v", "sha256": "7582c59a7440b1094f287131a0fa8d59c4eb94c278dc3c628af230d73be9c0bb"}}
{"design_id": "daff7779a2cc", "module_name": "ct_mmu_iutlb_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_iutlb_entry.v", "sha256": "3b33d5eb2117a50b8e8fbea12317f02f7c5d900997fff4edae16b89364fb3d9c"}}
{"design_id": "db06d04bb42c", "module_name": "hi_fanout", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/repair_fanout1_hier.v", "sha256": "e09c4065f7d4ec95074043f4a588d028dfbf8d9a9ab3820228dd6c778bfa579e"}}
{"design_id": "db1ea2c2b37d", "module_name": "ct_vfdsu_prepare", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_prepare.v", "sha256": "bbab0f92f4698015ec000955e150cd2bdc12e58877341e0df98bf031e623a464"}}
{"design_id": "db3a1a68724c", "module_name": "ct_ciu_snb_dp_sel_8", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_snb_dp_sel_8.v", "sha256": "ea6ed539c6cd5c66a26b9b9faa5e0721de710d5a0ebd5bbf6f045f82a3a0695b"}}
{"design_id": "db7bd3393ba8", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v", "sha256": "07f64426d63f1b99b0722ca7ed8a47f01704ef52e09a2151444a84fb2e6f16f3"}}
{"design_id": "db9197b50062", "module_name": "udp_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_64.v", "sha256": "910e0dfdc12652d520cb49237e35d2dffcb006ac0029e7f46c0c1e66e34ca2a6"}}
{"design_id": "db95c6d3af5b", "module_name": "oh_and3", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_and3.v", "sha256": "e6ea200d2c0b6bed770bb5e44574220fb5e57233a12006d8979f384e9e2526d3"}}
{"design_id": "dbb8d9509f3b", "module_name": "axi_register_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_register_wr.v", "sha256": "02dd26f56ee04ad834a28e02ef2726852ab527fb23c3a88b377f3ce55a719c4b"}}
{"design_id": "dbb91ed10912", "module_name": "mqnic_l2_ingress", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/mqnic_l2_ingress.v", "sha256": "477726bace1bd0d09152a8fbbbd0e4d563640ead2338a50fb80beff52b8ac4a8"}}
{"design_id": "dbcc3941825c", "module_name": "apb0_sub_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/apb0_sub_top.v", "sha256": "015978b4a0073baa38343b2d9d04b20a3bade1964a1054d8c17d18e2cbdb4a31"}}
{"design_id": "dbfcb120ab50", "module_name": "burst_write_master", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "avalon_mm_master_templates/burst_write_master.v", "sha256": "cd3fe61639ac0295ce1f465db9406bd2d317a1aa5231cd6c6edc0fb3b9cf65f1"}}
{"design_id": "dc2ca22f0261", "module_name": "ct_f_spsram_64x108", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_64x108.v", "sha256": "9f0dd47bfa223ecc634f3ffff55e270d69b4d2c6c661965a8f04cc90eb012b94"}}
{"design_id": "dc46b1ca1885", "module_name": "approx_fp_div_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/float/approx_fp_div_tb.v", "sha256": "19bc7f80a8159b4e195f2828263a788586e35ca603cf169a356a3805ea2a7857"}}
{"design_id": "dc4a3fb6f144", "module_name": "test_fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v", "sha256": "81c2fa1b89bdd48a1c53c82eccc192f5f02746d7d5f6cfdc2cfd1a2f8802ad83"}}
{"design_id": "dc9ba97c49d7", "module_name": "ad_ss_422to444", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_ss_422to444.v", "sha256": "3c31e7b9a8f4ded52fb3a9ab4b75e9b67ed293425661ee17605e15ce2640fb0c"}}
{"design_id": "dcca1d4b699d", "module_name": "ct_vfmau_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfmau/rtl/ct_vfmau_top.v", "sha256": "c1f4357dd1521b6585e164ef130880d714341d17a00a4968f0cf4cf85624c1ad"}}
{"design_id": "dcd632e5d83e", "module_name": "NV_NVDLA_CSC_slcg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/csc/NV_NVDLA_CSC_slcg.v", "sha256": "bb6d9d2f872056689db94bc8bccbee6decdee45e0ae84d9e3fc8c62173a2b52f"}}
{"design_id": "dceedc38639d", "module_name": "wbxbar", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "sim/rtl/wbxbar.v", "sha256": "c37441c98cb3714635be3187c99a355d5e4001848dfc760f805a3ea7378e6ac5"}}
{"design_id": "dd0f5195c2b4", "module_name": "eth_mac_1g_gmii", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_mac_1g_gmii.v", "sha256": "44e755d50945c37a2cbd6cd39c7401451b02a005c154af88642b4050360a0b69"}}
{"design_id": "dd23c5afd087", "module_name": "eth_demux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_demux.v", "sha256": "5ec09074734c9fcb0d1cd91f7ad752d4f20fe5279dcf44ceb2cdacedb7939aa6"}}
{"design_id": "dd4662e2771e", "module_name": "insert_parity", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/insert_parity.v", "sha256": "f11f2ab219127b962cfc3cdd32758ab5c997ee177ec1f4248fb3df52814719c4"}}
{"design_id": "dd65880a4412", "module_name": "test_udp_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_udp_64.v", "sha256": "fe87b2ef466980da46f262c78e31efd3b1ef21ecd56d4efd0414e5da0228fe96"}}
{"design_id": "dd6fd1748287", "module_name": "axi_err128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/axi/axi_err128.v", "sha256": "eadaae2be974de40aed0bf6a0dd26cd611bb86bc183738ee176ce620216d1ae3"}}
{"design_id": "dd7e9576d521", "module_name": "axi_pulsar_lvds_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v", "sha256": "63e73745fce660fa5d82699cb4e534a634e2ea27cdc16711e94cb7b979aefdcc"}}
{"design_id": "dd841a2c669c", "module_name": "eth_axis_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_axis_tx.v", "sha256": "5f17bd77f979ca97218bd161d421e4230190c7f0f47d1556c4e3e0ad7166aa3e"}}
{"design_id": "dda48a56e94f", "module_name": "asic_sdffrq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_sdffrq.v", "sha256": "80b608962d2c336b93bc33318d41a73ddc24fb65419c4d532bfe932bf0f7f44f"}}
{"design_id": "ddac962a30a3", "module_name": "system_timer", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/counter/system_timer.v", "sha256": "6dfbe72f9a5079f45bd25bf98ac3b24b5dc9b931fc330a9963db2f424adbdfa3"}}
{"design_id": "ddd79afc04f0", "module_name": "wbwatchdog", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/peripherals/wbwatchdog.v", "sha256": "22216cee727ffd8e71ee01ce0aa2510900ba30a0fdbcb7ecc8d2fdb407fd564c"}}
{"design_id": "ddd977bc67cd", "module_name": "ad_ip_jesd204_tpl_adc_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v", "sha256": "a401b83e7b011710183e2ed955088b1dda1416757da0bc8adf1015e4dfc9ab10"}}
{"design_id": "de20b19debf5", "module_name": "test_fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v", "sha256": "09182e67703e523c69c894ed59136a6f421fa64c53467b9d6e785f38a433ce03"}}
{"design_id": "de319688aa05", "module_name": "axis_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/axis_fifo.v", "sha256": "b49606665dcef7805fd2cc42ee8514402898a0dee1af2df61dd0a2d332d19a28"}}
{"design_id": "de3cfc702541", "module_name": "sirv_clint", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_clint.v", "sha256": "a2009569b93a9d549d2b4b1f791b43e05b5a96645501126b37b8f1a1711b1444"}}
{"design_id": "de410e7e5f0b", "module_name": "axi_ad9671_pnmon", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9671/axi_ad9671_pnmon.v", "sha256": "8df163ba2c15f408534db34bbccae3e4b7f8adba22bb93067c22589c5fb10346"}}
{"design_id": "de4b132c458a", "module_name": "axi_vfifo_raw", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_vfifo_raw.v", "sha256": "3ee0d011b2d769f58254be0e53ad0406222f2813f063e346c62a2b6b4fc74806"}}
{"design_id": "de751ec1e43a", "module_name": "test_pcie_us_axi_master_128", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/tb/test_pcie_us_axi_master_128.v", "sha256": "36d8c2869bcd3b0651945d4834adf1965319c001219acaf923f52303057d4b96"}}
{"design_id": "de9c4174e7e5", "module_name": "addsub1", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/pacoblaze/addsub.v", "sha256": "c8f529ddbcf3c4406bbea18d2fe490d0a96a61ebf46a108ac6f63f2d85b48826"}}
{"design_id": "dee4f39f08e7", "module_name": "test_axi_axil_adapter_16_32", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "tb/test_axi_axil_adapter_16_32.v", "sha256": "384a433b88286ec611ca75bf65abec29471eca72c7042732e1d7d7d620c92660"}}
{"design_id": "dee6c85c9351", "module_name": "oh_oai222", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oai222.v", "sha256": "0d4c3db4db9ea5e9823a2bc8f48332e4152c3cc91a344b9da4c5437f822d57aa"}}
{"design_id": "deed03715f2e", "module_name": "eth_phy_10g_rx_frame_sync", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_phy_10g_rx_frame_sync.v", "sha256": "6bdf55011c55cd96c10aa462e8dbb6c77a1aa8ddef602cb8bc551e2f2b9491e5"}}
{"design_id": "df2c96726ef9", "module_name": "emesh_if", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emesh/hdl/emesh_if.v", "sha256": "8b2ce67806903990365a101eb4f07cb82e61a18cb017d3dd899c4c8e936df0d1"}}
{"design_id": "df3cd588dc7b", "module_name": "xgmii_interleave", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/xgmii_interleave.v", "sha256": "1bba6881732c709041ce7a6be15c32cedfa89c3c7091e682f8495a96719b8635"}}
{"design_id": "df45cc5c86fe", "module_name": "pcie_tlp_fifo_raw", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_tlp_fifo_raw.v", "sha256": "d914cf4a293903794f497f8cdf6155d4e166ab26a475593c793903d89f35ea27"}}
{"design_id": "df7e851bb448", "module_name": "xgmii_baser_enc_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/xgmii_baser_enc_64.v", "sha256": "588a0871d72fe7350636e404fb3345c8659d94ee79b97abbd9feb81e447b7696"}}
{"design_id": "df7ea7d4a859", "module_name": "xcvr_ctrl", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/xcvr_ctrl.v", "sha256": "c119978a2fb8e94b3547b893b045ed2e0eff835de41e0e41c0faa4bb1800472c"}}
{"design_id": "df8e2fa88dec", "module_name": "axi_adaq8092_rand_decode", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adaq8092/axi_adaq8092_rand_decode.v", "sha256": "3da4904638d30694cd10281672d8165f6879bd4445f42b3ba3cfd1d0c5e17b75"}}
{"design_id": "dfbd457c88e1", "module_name": "oh_dffrq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_dffrq.v", "sha256": "1f0102c85797ac2045e709d81274bd80e814b6ab71badce75207c8528aa35f22"}}
{"design_id": "dfd64b0573ae", "module_name": "ct_lsu_dcache_info_update", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_dcache_info_update.v", "sha256": "c08629e932bf495311d31d048378cd09cb9a756a591c1416dd2798d39d6de738"}}
{"design_id": "dfdeec8a05f4", "module_name": "test_axis_frame_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/tb/test_axis_frame_fifo.v", "sha256": "3f8808cb8976c4d3a02695b7e4112b0a18c978b90c9e038215be06594d0d006e"}}
{"design_id": "e014512c4191", "module_name": "stats_dma_latency", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/stats_dma_latency.v", "sha256": "e5b70e982267dd4b02ccbc419d6992c135c2574054bf29f15bb9860f21134839"}}
{"design_id": "e01451e08b9c", "module_name": "axis_baser_rx_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_baser_rx_64.v", "sha256": "50ab52a1be6dfa62bfeae6decc443a065871d1117f4f69d21bb14f176f8e6873"}}
{"design_id": "e025cbe1a145", "module_name": "oh_gray2bin", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_gray2bin.v", "sha256": "f284a5ece05a8845877947f3edfde4f63dd4ce7f42cfa3bf0bdfff5b022ec7c1"}}
{"design_id": "e0286eeb4e12", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9081_fmca_ebz/vcu118/system_top.v", "sha256": "7c0bddf9038f5c186f62b0f37a31c086708c6cf6516831bc20c0a64683a44eab"}}
{"design_id": "e03807be296f", "module_name": "udp_mux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_mux.v", "sha256": "fdbb8ffd42405d3db2201894eab36b2e618056f611c3301c15f862e37a1d0de8"}}
{"design_id": "e042d18d134d", "module_name": "sirv_pwm8_core", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_pwm8_core.v", "sha256": "18796c275e559a8a7235562080dc568a4672456161e04e69ce6a864da638b311"}}
{"design_id": "e04fbea127d7", "module_name": "NV_NVDLA_BDMA_gate", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/bdma/NV_NVDLA_BDMA_gate.v", "sha256": "d3b6580f9af02e50d4be48c76573156048eed7143b40e93b2e71b41580c9be70"}}
{"design_id": "e069fb4edb5c", "module_name": "asic_oa21", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oa21.v", "sha256": "1e7935d104585022d430f76d0b5562c8ca7c2c913a65be630db51f7d9b6d8b51"}}
{"design_id": "e0b648a046ed", "module_name": "axis_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_fifo.v", "sha256": "7d1ea178349654c92f2ac4823620004abe067b37f9fbd09fcff97fe00db6e19c"}}
{"design_id": "e0bb97b57e56", "module_name": "ct_fadd_close_s1_h", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fadd_close_s1_h.v", "sha256": "cfd33ad0759acfde97e3d8b85e0b2e6ce4238545f603a36072e7a3c903068bfa"}}
{"design_id": "e0c132ef8133", "module_name": "test_pcie_us_axi_master_wr_64", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "tb/test_pcie_us_axi_master_wr_64.v", "sha256": "7d2fe8aad5a3ac0bd77309d56cc88a4f6fdb2d60e11424b5169425bb350fabc4"}}
{"design_id": "e0c13a0b07a0", "module_name": "eth_axis_tx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_axis_tx.v", "sha256": "5f17bd77f979ca97218bd161d421e4230190c7f0f47d1556c4e3e0ad7166aa3e"}}
{"design_id": "e0cf49f6c4d7", "module_name": "NV_NVDLA_CDP_RDMA_REG_dual", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v", "sha256": "544c84aa7bc3e385e2b26df9537cc367512204ca16dbd20d6eecf85958cf2788"}}
{"design_id": "e0d2141f3a3d", "module_name": "axi_ad9783_core", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9783/axi_ad9783_core.v", "sha256": "64cf600b5c5df95f07cd2a18bbe5688c7bcb4a051830ec5b4260f62a28b8c0ce"}}
{"design_id": "e0d3469d3144", "module_name": "test_fpga_core", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v", "sha256": "017cf0ced9956892b88bdb4f773a067e1234cb0a99aa888b1149a13ca9d50f3a"}}
{"design_id": "e0e1d2a940d8", "module_name": "xor_6", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/crc_speed.v", "sha256": "e59470c1f081cdefa512c432fe52d13545f2631638a86189db4c08308db31e47"}}
{"design_id": "e0edd5af2173", "module_name": "NV_NVDLA_GLB_CSB_reg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/glb/NV_NVDLA_GLB_CSB_reg.v", "sha256": "d4de7206e90ff58f7cb47960e11cede84c3d634edad65209682ed9d1e3bcf626"}}
{"design_id": "e11aa5dcc864", "module_name": "dummy", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/ifp/test/upf/mpd_top.v", "sha256": "1bb7b6b0f15ff1ebbd83a87b10a6f466907b91eded8116813dc98d922a0fcd95"}}
{"design_id": "e154a2a7521e", "module_name": "ct_rtu_compare_iid", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_compare_iid.v", "sha256": "d697c75c481b73b3220592ea887fb0bdd2219131d7136b9079f7c7263d387a8f"}}
{"design_id": "e1645fb39f49", "module_name": "axi_read_slave", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/tb/axi_read_slave.v", "sha256": "f0b916bf8f8b41ac87c766b801d1e82d1f20a9317b5684c885625bff168286f2"}}
{"design_id": "e178936e7c2a", "module_name": "NV_NVDLA_sync3d", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/car/NV_NVDLA_sync3d.v", "sha256": "5dd38448b07ac711dd00b11311b20dfc1070303c0b82df46fa1750527bac1b5c"}}
{"design_id": "e17a35a70227", "module_name": "ct_mp_rst_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rst/rtl/ct_mp_rst_top.v", "sha256": "3703cc3a2aa66f99ca0179a3f8a8852eb4ed21bfd07a0975932d2284094b1686"}}
{"design_id": "e17b619bdbc8", "module_name": "asic_dffrq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dffrq.v", "sha256": "9249f6228c694b79ca727324c89d5cb2f380d77ed13d41e26fec86c90b385ba4"}}
{"design_id": "e1c30d879788", "module_name": "axi_ad9361_alt_lvds_tx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v", "sha256": "e342a4b6293fd34ac2b5e39a81d12f0735641fe99eb9a15dbfabb6c7cb4225f0"}}
{"design_id": "e1deae3a5d45", "module_name": "asic_latnq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_latnq.v", "sha256": "dc4afd16976c1b0c3d0c280ade1c36f4b4e7808c12c78743e4f3e3e4aa351870"}}
{"design_id": "e21c1a331128", "module_name": "dma_if_mux", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_if_mux.v", "sha256": "b98f11ef6c7e0acf4433d1bf9e5383b3792c8fde3ef4c8c3e4938e225f19ae52"}}
{"design_id": "e247f5c802c7", "module_name": "sha1prog_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/sha1prog_rom.v", "sha256": "78f7e033ba69e68310afac0731d848b3bbbfb8d368ec6bcdc363d31cb608baf8"}}
{"design_id": "e253ebbc0211", "module_name": "PAD_OSC_IO", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/sim_lib/PAD_OSC_IO.v", "sha256": "e935d5024d1f09abca982945e274d6e960f4031750bc93b61cb970f6fc978834"}}
{"design_id": "e2628c437899", "module_name": "test_axil_cdc", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/tb/test_axil_cdc.v", "sha256": "11382b967e225cb506c764ebb000a6a4bdd5eb00ab1594580f67c50d424f268e"}}
{"design_id": "e2a3bb9cce0a", "module_name": "i2c_master_bit_ctrl", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/i2c_master_bit_ctrl.v", "sha256": "2ab60ae6cd865f82d440bc83bfc11c8775cc39f6ca21254c7b240416ee4e56bc"}}
{"design_id": "e2c119d9b172", "module_name": "ct_mmu_ptw", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_ptw.v", "sha256": "d88281354b11c55fbb186f9e425fae228097fed640ef40eb368756127c797bed"}}
{"design_id": "e2d7517124e9", "module_name": "ad9265_spi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9265_fmc/common/ad9265_spi.v", "sha256": "65dfd354daff10382db80473cfef6d2c73b154d855b4ab0e9046e563cdc546f7"}}
{"design_id": "e3309d6233fc", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dbSta/test/clock_pin.v", "sha256": "1b90cfd6644bcddea42cd2482e96aa291973568b7237fd12ab0c4f8f84f5bc68"}}
{"design_id": "e3af5e4c3933", "module_name": "fec_rot_12", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_12.v", "sha256": "c4b21a2b5b1797322beae61bc7bdd534bc22e34043882c6de1455ba89648e674"}}
{"design_id": "e3db7606cf07", "module_name": "pcie_tlp_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_tlp_fifo.v", "sha256": "7f08e45fac4ad71449164c1dffefba7cc4bb64d9cac67752970a076489e5256e"}}
{"design_id": "e3dcc52890ca", "module_name": "NV_NVDLA_RT_cacc2glb", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/retiming/NV_NVDLA_RT_cacc2glb.v", "sha256": "cdad83d8b052994bddd7f2651a9d178b87be6e56ac3bb259f0f3d26b47bc6422"}}
{"design_id": "e40209fae149", "module_name": "axil_crossbar_rd", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_crossbar_rd.v", "sha256": "b43f1a86164949e78e01e29864c9a2cad5bd442be8356231d2993beaeb3d4e99"}}
{"design_id": "e409ebcb7e23", "module_name": "oh_nor4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_nor4.v", "sha256": "38eab73e711bdc25e68ba60e7264059bbde9ac0a79f4eebc2250533c31381d2e"}}
{"design_id": "e43a2af50be4", "module_name": "event_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/event_mux.v", "sha256": "d0c09f5d1b9252299fb10aeb050aeb48d5307c5f7c3385a30999b23a07ae4b4a"}}
{"design_id": "e453a175adce", "module_name": "asic_ao32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao32.v", "sha256": "5f61e63ab49ea57666f113585521f2f06defefc2c9c8d4278a655a1d04f1be06"}}
{"design_id": "e45fa8e0c581", "module_name": "axil_dp_ram", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_dp_ram.v", "sha256": "5751657db197c9505aa2d57d64d32417e3a142c9fa725a013655f163d43fa33c"}}
{"design_id": "e4761e331c66", "module_name": "up_hdmi_tx", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_hdmi_tx.v", "sha256": "ffd377f89fc6b34de58df72689121ba0caa825eec6fbc3edba391392c8634ec7"}}
{"design_id": "e4a1bd908cde", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "12f9316c4c4e2563251588e10f6c64b2f4a2690951837caebeb46b602f496901"}}
{"design_id": "e4a89c1ebea1", "module_name": "axis_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/axis_fifo.v", "sha256": "b49606665dcef7805fd2cc42ee8514402898a0dee1af2df61dd0a2d332d19a28"}}
{"design_id": "e4c426c8bddc", "module_name": "fpga_core", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v", "sha256": "80ea9c49c39e27f8c178d73ca438483782f395bb780b73e85b4d1f02b776fa55"}}
{"design_id": "e54aadd7dba4", "module_name": "axis_stat_counter", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_stat_counter.v", "sha256": "2a431655333c6d4b8daad55a80eb2b22b9796e92b15a2c295a6b5d2f5e0e2ce1"}}
{"design_id": "e56fc9634d7c", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9009/a10soc/system_top.v", "sha256": "d49c9a02800386087fe5f5df7655bbf930498562d8817b83b9f1dd84a24711b6"}}
{"design_id": "e593c3a07b03", "module_name": "zipdma_fsm", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/zipdma/zipdma_fsm.v", "sha256": "089fae396990ef9d824263b63dd4aee381ea5e2000ad629ac34e14fd61f25c29"}}
{"design_id": "e5969d8dba8c", "module_name": "axi_adrv9001_tx_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/axi_adrv9001_tx_channel.v", "sha256": "2be33e482fb22893350ce4ecaec1e2ade00d66724d1e9f58e3fcef70e94eae0c"}}
{"design_id": "e5a16a08e64c", "module_name": "ssio_sdr_in", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/ssio_sdr_in.v", "sha256": "b71edd7c90d19ebe30850f20ef8e781d74e1233ab4b01bc613d652d853d88d2b"}}
{"design_id": "e5c3975d15c8", "module_name": "eth_arb_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/eth_arb_mux.v", "sha256": "5207295c7093e70f16a31497a67abb285f18acdac370d726735e94e89e4cc759"}}
{"design_id": "e6014df6f5c0", "module_name": "oh_pwr_buf", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_pwr_buf.v", "sha256": "253bf2b62de8de64b452cc0b532247d417096b0ca0b42f0c8269ed37d7491db6"}}
{"design_id": "e614c8142a41", "module_name": "sysid_rom", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/sysid_rom/sysid_rom.v", "sha256": "99ac5922da0352e549e3829a308f4262a75e4dcdcee807885018eb79fdb01870"}}
{"design_id": "e61fce7af794", "module_name": "axi_fifo_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_fifo_wr.v", "sha256": "e0f06c5c6e3deae0b764e85319e16395c7b2e428b7419853c264129350df67ca"}}
{"design_id": "e62e2940566d", "module_name": "ct_f_spsram_8192x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_8192x128.v", "sha256": "c7b34080aa77e9b415ab9f2f553745b9c335b8ad178b1800daaf5725b9bc4051"}}
{"design_id": "e62ff03f6049", "module_name": "tim1_sec_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/wujian100_open", "commit": "83e297583bb3454b688f9f27d6bc20ff3276ad32", "path": "soc/tim1.v", "sha256": "476c17ec62b5a345da0d4b39395c47b4e72180e894c17baac5a4978a60736e49"}}
{"design_id": "e646cf8fc59f", "module_name": "axi_adcfifo_wr", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_adcfifo/axi_adcfifo_wr.v", "sha256": "bc4b3a43721c7056caec190023dd94b739315c77f9402525033fbe10f330f042"}}
{"design_id": "e671a0ae3289", "module_name": "servant_cmod_a7", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "servant/servant_cmod_a7.v", "sha256": "684337bbaabdc9c13b2abda9605a18d05dc97a5745c730c4345349502b588857"}}
{"design_id": "e697eaa7586f", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/520N_MX/fpga_10g/rtl/eth_xcvr_phy_wrapper.v", "sha256": "f5869f43282941cee4fda242ccb18410dfffa9588158ee4d4b73e6ea8eaeaa8b"}}
{"design_id": "e6ac975bc8c1", "module_name": "oh_pulse", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_pulse.v", "sha256": "2d6cb0f59370560da0b2cf92e1ac8d45c0f72d65e9ecf22bdc4cc3ac9c369092"}}
{"design_id": "e6c87f72276d", "module_name": "darkspi", "split": "test", "source": {"repository": "https://github.com/darklife/darkriscv", "commit": "955511961f139c54d3385063cd9bf40f4dddadd8", "path": "rtl/darkspi.v", "sha256": "56239510247384888f7c99599267f9db34b00df846028012c06e42023e4ca8a1"}}
{"design_id": "e6cb977a2f69", "module_name": "spiflash", "split": "train", "source": {"repository": "https://github.com/YosysHQ/picorv32", "commit": "ef203c2b0a3fb793280f5114941416c425c5b461", "path": "picosoc/spiflash.v", "sha256": "5e30ee6eaadd532e2547ee0a3cb41e5bd4a1ee3c72fd484275ce680dff49ba57"}}
{"design_id": "e6ee8ce6d2e3", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/fb2CG/fpga_axi/rtl/fpga.v", "sha256": "f5722fb5fe13d892ed50056114d3a1e27bb8ec685f0cc49925d195ee2b4a7d77"}}
{"design_id": "e6fd5fd668e7", "module_name": "ct_lsu_dcache_data_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_dcache_data_array.v", "sha256": "157a478433eca11996a7a67b564a0ecf47c6f062ba645be4e2a276a656a2fa55"}}
{"design_id": "e700eaf2994d", "module_name": "oh_xnor4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_xnor4.v", "sha256": "20ce113ab3375db864c08143a4c9f0c6f27631d17de320059f62c990263975c9"}}
{"design_id": "e704629abe32", "module_name": "reg1", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/rsz/test/split_load_hier.v", "sha256": "e372f656c6be932ac7be0142d13f0e0074f4171aaf07347c8c10e6aef4d9e637"}}
{"design_id": "e705b34cc003", "module_name": "oh_oai32", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oai32.v", "sha256": "31da6cf747ac2d865517de5ade8b98a7ffb69f515ed995f0045465c6bd425057"}}
{"design_id": "e70d6c2a74e5", "module_name": "asic_tbuf", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_tbuf.v", "sha256": "c811c9d21e07afcf036580f95475d5f532b1a5c7374a3a3130e3981c237219dc"}}
{"design_id": "e713e1e42751", "module_name": "ct_pmp_comp_hit", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/pmp/rtl/ct_pmp_comp_hit.v", "sha256": "624bdeb9496abb864f58bd9fea9df41dc2b13f760fb0203e6f83a801c47e85c9"}}
{"design_id": "e733db5555a8", "module_name": "pcie_us_if_cq", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_us_if_cq.v", "sha256": "b5e50b2b8f3df3c237b4ddf5ab383482fc3458aa8f2c80e237a4b80dbf37bd50"}}
{"design_id": "e7349bcc5997", "module_name": "dma_if_axi", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_if_axi.v", "sha256": "3c59447dd7ff7b55fc42c53720e5c904edfc380ef2552b0b82975b1eb8348dfa"}}
{"design_id": "e75eb20031db", "module_name": "oh_oa31", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oa31.v", "sha256": "526e02d782550a2ca59a98558b504b9e397a30229dfa797e9d59ac1a2ec8f3a5"}}
{"design_id": "e75fe1b42c41", "module_name": "top_small", "split": "train", "source": {"repository": "https://github.com/YosysHQ/picorv32", "commit": "ef203c2b0a3fb793280f5114941416c425c5b461", "path": "scripts/quartus/synth_area_top.v", "sha256": "761af16546237f9efd11fdfd9babce0e40e02a0fe9ba455c1f5128350f831102"}}
{"design_id": "e777471305d4", "module_name": "chain_delay_adjust", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/random/chain_delay_adjust.v", "sha256": "baf922566d16d97fdbae1a47fec80f789d4eef6cf56b561d3da7f36aee3cb885"}}
{"design_id": "e7890e1d73f0", "module_name": "ad9467_spi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad9467_fmc/common/ad9467_spi.v", "sha256": "7bd4cbdf0181711dfffe8a784e95bdfafe7d74bb68d4016353901cbdf545d129"}}
{"design_id": "e794b13c5e40", "module_name": "progctrl_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/progctrl_rom.v", "sha256": "9180a6e802a8f54e4d98137a9a2832f4c358aaebcf418684c23e64ec3466bd13"}}
{"design_id": "e79c2ac5b181", "module_name": "ct_rtu_expand_96", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_expand_96.v", "sha256": "04bf6a1cf653991ca05a82732fed2a4a2e9bc160121b807792ecbbfa8ec104ec"}}
{"design_id": "e7b420fa0488", "module_name": "ct_piu_other_io_dummy", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_piu_other_io_dummy.v", "sha256": "46d777d800debb20dbf072dbe57eb9783e3cde42b0e6bd20b4dbcce0f1a7cf41"}}
{"design_id": "e7e1cfe36cb1", "module_name": "axi_gpio", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "gpio/hdl/axi_gpio.v", "sha256": "1fd62504156e95916017419d8ad42bf10b98775926b1a14bf8c14764e4130c52"}}
{"design_id": "e7e3700bbbde", "module_name": "asic_oai31", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_oai31.v", "sha256": "f0cf1c7f11037fb9446195977ec7e3b781b1ed8aabb66698053c50259cf5fde5"}}
{"design_id": "e7f3cb69c26b", "module_name": "gth_i2c_init", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/HTG640/fpga/rtl/gth_i2c_init.v", "sha256": "62b87caa1275f7c2867bba1e42dfeba4a0071d3c8e8acc7882c996c04b228c8f"}}
{"design_id": "e7faf6749539", "module_name": "oh_mx4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mx4.v", "sha256": "75db1ecd8d12d42836536bbd125113f9d05fe210864e9c39baa4842062a811eb"}}
{"design_id": "e800f8df819b", "module_name": "oh_aoi21", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_aoi21.v", "sha256": "866a0bb487b22c9e0b3c31183cbe49e8bb7033607261e4bfa552c06a4c529c1e"}}
{"design_id": "e88675435720", "module_name": "arp_eth_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/arp_eth_rx.v", "sha256": "4113e03df063b91d64be4da8e455ba45d8251cecc8e66ec75cec93c518443bee"}}
{"design_id": "e88d75b4b9d1", "module_name": "gpio_slave", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/common/fm87/gpio_slave.v", "sha256": "b7aa9fe47a399e93d746286abb9a1c3cb61a7557713207feb2b240a4765a136d"}}
{"design_id": "e894671065dc", "module_name": "phy_mac_link", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_mii_to_rmii/phy_mac_link.v", "sha256": "0f08bc434a76f7d06c0a5873f58823cadd1c6f8262e61472b9acadb17d598758"}}
{"design_id": "e8b3f6ba350e", "module_name": "pcie_ptile_if_rx", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_ptile_if_rx.v", "sha256": "f303f9cd079acf0dc9e8039b704d41e0d7648c2bfd928f3af3f4bcffc16647dd"}}
{"design_id": "e8ca1f28b824", "module_name": "dram_test_ch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/app/dma_bench/rtl/dram_test_ch.v", "sha256": "fbe764ba2e6016072ea00140dd2a9238bd38cb1d69816ae48e3401b4f54173d5"}}
{"design_id": "e911b964c5ec", "module_name": "axi_register_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_register_rd.v", "sha256": "63f1bd6f9d72ae28643fd7af3a5d5bcb05d45cbfb290c59c120c327ba49aa575"}}
{"design_id": "e93f4c92a296", "module_name": "i3c_controller_pack", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/i3c_controller/i3c_controller_host_interface/i3c_controller_pack.v", "sha256": "22a854435dff46bc88b8807f0e0a49b0a179fe8d70dabf7fba7457739473110f"}}
{"design_id": "e96b4b37e8d9", "module_name": "sync3d_c_ppp", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/sync3d_c_ppp.v", "sha256": "e600fdeda30bf55aa6170a7eaf2d1794b8c660587ff15235a0b0bcbed40ac013"}}
{"design_id": "e9742977a96b", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/VCU108/fpga_1g/rtl/fpga.v", "sha256": "93ff138d2ddd821bccb616c7c31bf0e5a3744bb985223782d0c6e82cd243336d"}}
{"design_id": "e97632eb97fc", "module_name": "write_master", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "avalon_mm_master_templates/write_master.v", "sha256": "9b595735035c515daaa8d98e899f456d7be3dda22381ad6e53025f7f813c6f63"}}
{"design_id": "e99b99f22533", "module_name": "max_chain_count", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/dft/test/max_chain_count_sky130.v", "sha256": "ce5a8b9e08786984fb92895dbb624f6add2e23b769970eebdf1e4da6199af483"}}
{"design_id": "e9b2c6e26f39", "module_name": "tx_4channel_arbiter", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arbitration/tx_4channel_arbiter.v", "sha256": "973ce5b5f8e7bb5fa61889eaaa885253844d96f2bae24a0144ae37db186aeb74"}}
{"design_id": "e9de2835df78", "module_name": "ct_f_spsram_1024x64", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_1024x64.v", "sha256": "095153adaf6fed9c2d62faa32f953e8b3d3ae38075646f71a276230942484e5c"}}
{"design_id": "ea0d7c03b2c6", "module_name": "sum_of_3bit_pair", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/sum_of_3bit_pair.v", "sha256": "9d28fcdab0b1129528b470014ca780446489d8408f572195106998f2d0db1acf"}}
{"design_id": "ea8492aed244", "module_name": "axi_logic_analyzer_trigger", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_logic_analyzer/axi_logic_analyzer_trigger.v", "sha256": "8d27e73dd93ed60bd40a0f78d25b4e39b3cd2bc61cf373341b63cb32d548dc79"}}
{"design_id": "ea866c38f1ea", "module_name": "NV_NVDLA_CDP_REG_single", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_REG_single.v", "sha256": "7a75f932142088382424b237d37fd90d319478b2e4033abe1d6bc19936c199c4"}}
{"design_id": "ea96b154ada2", "module_name": "prescaler", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/apb_adv_timer/prescaler.v", "sha256": "ef988285ad3788b859a9ab212be364abb819aa7a41b5ca7eb5306dd88ec7a6d5"}}
{"design_id": "eaf6cbc4e731", "module_name": "NV_NVDLA_CDMA_slcg", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdma/NV_NVDLA_CDMA_slcg.v", "sha256": "f6989c521aa4f0a676262773538fe52a26fadfd4572b785184a96e8b17a80f6f"}}
{"design_id": "eb03a0b748f0", "module_name": "addsub_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/pacoblaze/addsub_tb.v", "sha256": "d7738589094c523976e4029b7d4764d898034c0272854ac0d881684405b66483"}}
{"design_id": "eb698d1d2b01", "module_name": "tdma_scheduler", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/tdma_scheduler.v", "sha256": "474bbdfdc8c3c1ad147898a898cc0fcafc92672e9704d9b8470c1687a79228a2"}}
{"design_id": "eb7f3dc4976d", "module_name": "test_axi_axil_adapter_16_32", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/tb/test_axi_axil_adapter_16_32.v", "sha256": "384a433b88286ec611ca75bf65abec29471eca72c7042732e1d7d7d620c92660"}}
{"design_id": "eb8126e0be0f", "module_name": "ct_mmu_jtlb_tag_array", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_jtlb_tag_array.v", "sha256": "64ae93178071b48faea40ef08713e3d193c85431a63df5d5c1e57cf732afc6c1"}}
{"design_id": "eb85b47c4756", "module_name": "axi_dacfifo", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/axi_dacfifo/axi_dacfifo.v", "sha256": "4ead86b12fec7dc34904f345a9ee44ec6ddb1536095ef4311c1cead4cfc99587"}}
{"design_id": "eb9f62ca32f1", "module_name": "udp_ip_rx_64", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_ip_rx_64.v", "sha256": "d91fae456b9687f4b9a5ee5720091b315b2bc9922eb7c7b1a682e37a6a92c51f"}}
{"design_id": "ebaf40b51001", "module_name": "wbpriarbiter", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/ex/wbpriarbiter.v", "sha256": "69957920d425237cdffbdbdc45bfd914010f5fa06f2ee396ac5cd2b9d5f4c6da"}}
{"design_id": "ebb7b25a3f73", "module_name": "ct_ebiu_ncwt_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ebiu_ncwt_entry.v", "sha256": "fce9b8eb5b79cc89b8d58dabedbe2140937f3925f668a649168816369ace779c"}}
{"design_id": "ebd296b77384", "module_name": "pcie_tlp_fifo_raw", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_tlp_fifo_raw.v", "sha256": "d914cf4a293903794f497f8cdf6155d4e166ab26a475593c793903d89f35ea27"}}
{"design_id": "ebe29323f694", "module_name": "sirv_pmu", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_pmu.v", "sha256": "3f369dc1ce2de62e8f4de341850fb6567bad18f4bad28dbb4033c607d0c8c0b4"}}
{"design_id": "ebef0117e6ac", "module_name": "dma_if_mux_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/dma_if_mux_wr.v", "sha256": "fdb5ea18a19f17ac76e22e215ab01eea572c5145096259eb62af735afc4cef21"}}
{"design_id": "ebf92c95bfea", "module_name": "dummy", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "test/upf/mpd_top.v", "sha256": "1bb7b6b0f15ff1ebbd83a87b10a6f466907b91eded8116813dc98d922a0fcd95"}}
{"design_id": "ec13ee6e2fa9", "module_name": "udp_complete_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_complete_64.v", "sha256": "57e4f5cd7af926276b0790b9c371e648d5badfd4f9d83beead93fc1320da1d50"}}
{"design_id": "ec25d3b305ea", "module_name": "ct_f_spsram_65536x128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_65536x128.v", "sha256": "acf534f537151648bb904daf8dab706bbbbdcefdf9ab7e3121166094efbd2fa1"}}
{"design_id": "ec2deffb0957", "module_name": "pcileech_mux", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "pciescreamer/src/pcileech_mux.sv", "sha256": "7407a99286b66088e932957d624bb5d62c991c555f9c96679c5ce15eb462553f"}}
{"design_id": "ec4d261600a1", "module_name": "oh_pulse2pulse", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_pulse2pulse.v", "sha256": "5f38aa408b143c425782944f69e97d79f45f3b01f86c6ce8c1007ef4df1938fd"}}
{"design_id": "ec6e3e1f927a", "module_name": "asic_sdffrqn", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_sdffrqn.v", "sha256": "02f1fbec2fefd4cab6b741ecc3c496289edbe02a9aaf62fd7c3a9dd8ef099045"}}
{"design_id": "eca5190081bf", "module_name": "match_or_inv", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/compare/match_or_inv.v", "sha256": "b627e5463b688516b6c6e157ec340aabdd761831695245d70c1010c663d8f85e"}}
{"design_id": "ecd7ec520951", "module_name": "ct_spsram_128x16", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_128x16.v", "sha256": "5c48433c6e673ec02d3a15d2f25107ec1aba0828ce21710d95a18ad641a6f570"}}
{"design_id": "ed242c49089c", "module_name": "axi_clock_monitor", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_clock_monitor/axi_clock_monitor.v", "sha256": "bf22cbfc03f12de1493f2161ab56ebe684ef8d03d67cbac6c711e0dbac784c25"}}
{"design_id": "ed2890825128", "module_name": "axi_adaq8092_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adaq8092/axi_adaq8092_channel.v", "sha256": "3b4bf3f538fdaee6ec063ed8c23dc837a52b5fc565e29438a0975a26c3f7a5ad"}}
{"design_id": "ed35efb38229", "module_name": "RAMDP_20X80_GL_M1_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_20X80_GL_M1_E2.v", "sha256": "8bc631c5c390db1ab86695d3312efa61e033573cfb890e714f5b2d796dec60f3"}}
{"design_id": "ed5539454a32", "module_name": "erx_protocol", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "elink/hdl/erx_protocol.v", "sha256": "9c34ea2a9ebaf0c421f8b6d9599d17c0899af0c23b4ed800a2eb90d3d34dc43a"}}
{"design_id": "ed8594c332dc", "module_name": "axi_register_slice", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/axi_register_slice.v", "sha256": "d468c258a61dc50171d2e253414a29090f5623052a1c7d0725f3393bdfb2a233"}}
{"design_id": "ed89146a6cfc", "module_name": "nv_ram_rwsp_80x256", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsp_80x256.v", "sha256": "9e9f0a01df231e82f680fe434027fddc7bd5f1125cb1953cce5b246eec9513a9"}}
{"design_id": "edb2a89c39b0", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/VCU1525/fpga/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "eddd2a1bde74", "module_name": "ct_mmu_iutlb_fst_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/mmu/rtl/ct_mmu_iutlb_fst_entry.v", "sha256": "a0346777685c93016f16992b939b49ec3323f9a84716c0f53eee816e9f00f587"}}
{"design_id": "edde12d3682d", "module_name": "test_axi_dma_wr_32_32", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/tb/test_axi_dma_wr_32_32.v", "sha256": "aa07e11e9fca179a45591b50169fb4527e3277095e3f9163f51d691f6e9a6d64"}}
{"design_id": "ee1c50703eb9", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "ee2dc10e241c", "module_name": "oh_sdffrq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_sdffrq.v", "sha256": "e47461ca27302c0ca7990b6ef5f66ed9afa1a4ebbb05433f28c8cfabd04c9d2b"}}
{"design_id": "ee3845168e44", "module_name": "ct_lsu_wmb_ce", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_wmb_ce.v", "sha256": "4274634521395e570638dcc46e8d25b9ee33bf25014e07d427b5d197a3276ebb"}}
{"design_id": "ee494b3d4ba2", "module_name": "axi_interconnect", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_interconnect.v", "sha256": "2a06ac654ea73fc960b24922466cb50990584a8318959bea3912cefb0bbf6e65"}}
{"design_id": "ee499848ab6f", "module_name": "tcm_mem_pmem", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_tcm_axi/src_v/tcm_mem_pmem.v", "sha256": "171b6a903df5b76b98893acdbfd6c75e029a21ffce6f916789129bac08de51aa"}}
{"design_id": "ee51c3a987b5", "module_name": "rx_hash", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/rx_hash.v", "sha256": "38cf3e5058ddf3a900717e89f80c654f361389cc16c02a52089b2a2c1f27e8d5"}}
{"design_id": "ee5b67305757", "module_name": "axis_async_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v", "sha256": "faeeaeadcba90268689f9fd227b1c8088d856ec8290ef6ab10b6d25e018858d4"}}
{"design_id": "ee6599a31976", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/ML605/fpga_gmii/rtl/fpga.v", "sha256": "686c6f5d5db222ac8953de8dd960bca7ab339a0c6b1a5ef69afd8c6212a6541f"}}
{"design_id": "eeaff45b6dfb", "module_name": "asic_ao222", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao222.v", "sha256": "6016051d1097f7a7875dd4d85857272e3b8b621cfd73900a64378628624918f2"}}
{"design_id": "eeb602e8227b", "module_name": "ct_spsram_256x23", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_spsram_256x23.v", "sha256": "81149bd957fc204a3b31609704a312bfe18b0ce176a24bb4ae3a8f3b937947aa"}}
{"design_id": "eedda887f11e", "module_name": "oh_oa222", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_oa222.v", "sha256": "18c8d0bd2fc8c220b27dca244783f9454251029f791331b675d31e714d75dafd"}}
{"design_id": "eef8a9c3c4ae", "module_name": "top", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "src/cut/test/side_outputs_extract_logic_depth.v", "sha256": "cdd1dc17fd9d9156affe65d0122679d07cd126d48492292b47ef6ff41dacf2e7"}}
{"design_id": "ef0238c44f4f", "module_name": "oh_edgealign", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_edgealign.v", "sha256": "727a6cb6856bc537ccf3030db2e954aa7ba8978edc7662f6dce89c07149e09c7"}}
{"design_id": "ef028ca80c2d", "module_name": "up_dac_channel", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/up_dac_channel.v", "sha256": "b3f6a2eb7e5b5fa254db4503484df1e0b3a1313e5545191209746d33e518f0d5"}}
{"design_id": "ef0315e4e055", "module_name": "ip_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip_mux.v", "sha256": "1d5232ab50868b1a2c386e88af330f7027774d90485cf7ec2f75ec2296de890a"}}
{"design_id": "ef0a0a2f3c01", "module_name": "sync3d_s_ppp", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/sync3d_s_ppp.v", "sha256": "ca172f0b4eb1cee435842d775af71dc1eb35d60033b351e8f1f209773042c10c"}}
{"design_id": "ef2c25b52108", "module_name": "priority_mux_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/muxing/priority_mux_tb.v", "sha256": "849e6b5dfef30f4279a9bd9186464d805d9e5de5f4ebabeb099ff7cf112edabe"}}
{"design_id": "ef4716939775", "module_name": "clock_mux_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/synchronization/clock_mux_tb.v", "sha256": "6358c11ef0ef749871f844677e9ae56ef03af08335e9ebd661aa5571e9c760c8"}}
{"design_id": "ef66a24004c5", "module_name": "axi_interconnect128", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/axi/axi_interconnect128.v", "sha256": "e36f5de3869716982af37bb9b69d5163d7fc0cf6a3417514cc8a44d228223c37"}}
{"design_id": "ef9e6dad34bb", "module_name": "reset_filter", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/synchronization/reset_filter.v", "sha256": "050ce68955dd54d5f024f474813dc5790ecdedc5edf8d5362e076678791d7708"}}
{"design_id": "efdc75025e8d", "module_name": "sirv_pwmgpioport", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_pwmgpioport.v", "sha256": "99ad69caff2f5a3cf1991af7c5b84415109c88bf71cc30ce1e578c75d04f200d"}}
{"design_id": "f023061d6900", "module_name": "axi_register", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_register.v", "sha256": "76eea19cf4967cfeb40cb4c0f10de3e20b70e841a79271134de685df7e91e3a2"}}
{"design_id": "f0392cf975c0", "module_name": "axi_ram_wr_if", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_ram_wr_if.v", "sha256": "cec0682f902f11d61c852812426ffa61417d281b82df10625cbfafd621209743"}}
{"design_id": "f05b4b5794c4", "module_name": "adrv9001_aligner8", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adrv9001/adrv9001_aligner8.v", "sha256": "65ac1a481a4b4ade54becd3aa6aa2bf5e46f63196ce9639893057ba1b81410ec"}}
{"design_id": "f0ac3b03c0ff", "module_name": "jtag_io_master_0", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/jtag_io_master_0.v", "sha256": "3b5dacc3e9b15ef71e7f0979f59c88b4a4f7f10a09c378c3aaa035fb2baf34ad"}}
{"design_id": "f0b2a9c36cc5", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/520N_MX/fpga/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "f0c1c623fc36", "module_name": "ascii_to_bin", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/des/ucrypt.v", "sha256": "945a7b51df3ed8365cce5f7d3e106e5514d63109112361bfee960f2f2e224db7"}}
{"design_id": "f11090427c69", "module_name": "avl_adxphy", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/intel/avl_adxphy/avl_adxphy.v", "sha256": "df7362626ec03ed112edf00ca6577e43dc17279e7629c85b0ed73b1a5dc851b7"}}
{"design_id": "f11941066222", "module_name": "serv_compdec", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_compdec.v", "sha256": "b1799ad9c5f10756fc336788d4bf871c5a6d4181c2f62568fad1b3bbe86504ae"}}
{"design_id": "f1551fd3c167", "module_name": "pcileech_tlps128_cfgspace_shadow", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "GBOX/src/pcileech_tlps128_cfgspace_shadow.sv", "sha256": "d0caedb2459a9ed8a42dfbbd06839417c83f2ddb864b73443dc99dbcaab24269"}}
{"design_id": "f1860bd2ce94", "module_name": "NV_NVDLA_SDP_erdma", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_erdma.v", "sha256": "3152108a5982125b0798c2551ed8d0a3132c31bd50f549cfde6943c5faae3d96"}}
{"design_id": "f1a801827761", "module_name": "ct_ebiu_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ebiu_top.v", "sha256": "bee6a6a2c2fd2c859f28eba43a6e910e9de24d064cfd57cd5a605a8cb296e5e7"}}
{"design_id": "f1c07662ef46", "module_name": "gcd", "split": "val", "source": {"repository": "https://github.com/The-OpenROAD-Project/OpenROAD", "commit": "3e3e483a4e3f98e2b5470b272040699de6dedbee", "path": "test/gcd_sky130hd.v", "sha256": "2d9509a0fd79565607e67b904cd2ae444fe7c033315d81e06ab11bebfe6e2efa"}}
{"design_id": "f1c4d6311c4b", "module_name": "axis_eth_fcs", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_eth_fcs.v", "sha256": "9aba0ff55de115dcab4a2f3ed46bf967bf5fb1eb8011bffcbd5842bf2e37a731"}}
{"design_id": "f1c8e1176e34", "module_name": "axi_ad9265_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9265/axi_ad9265_if.v", "sha256": "fcfb13d8e271f0b74142e520ebdc3ff600ab3e63a7c13723e0509e6e174b057b"}}
{"design_id": "f1d6ffcdd6bc", "module_name": "int_test_rom", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/test/int_test_rom.v", "sha256": "53e3acd78daa65a69f926973679b13d9dbd3423f81f214c2fb3541b57712b1b3"}}
{"design_id": "f1ee00d18caf", "module_name": "cpuops", "split": "test", "source": {"repository": "https://github.com/ZipCPU/zipcpu", "commit": "42606d2d6ef55df313772232977621b2d72f0159", "path": "rtl/core/cpuops.v", "sha256": "54707430127001eb7e716eb14ff3b733ecfeac437a4a1cec6906bb7befa48a7e"}}
{"design_id": "f1f384c9320b", "module_name": "ct_iu_div_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_div_entry.v", "sha256": "cc70fc5f572f4b229dc19d7e43937f3cd85e4cdab9192ade725e58a13a4cf569"}}
{"design_id": "f247c186d585", "module_name": "crc32_dat80", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat80.v", "sha256": "0d558bb39b85f1ff16bba36f5f6bd858f995d2da0d26d16dd43bf37071cf9345"}}
{"design_id": "f250e6007377", "module_name": "uart_receive", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/uart/uart_receive.v", "sha256": "25596a1660273a0bc9f7126eb50ef067b4c8c46e582c1705e7efb1ca1fe0d702"}}
{"design_id": "f271953e7eec", "module_name": "sirv_plic_man", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_plic_man.v", "sha256": "b7b8022f306eb7a93f20fda6d131feaa725aa04315bae87d3154572ab052c028"}}
{"design_id": "f2aa2da4467b", "module_name": "axi_generic_adc", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_generic_adc/axi_generic_adc.v", "sha256": "12556c064589bff6dc46223ae0ec0ca216b1fa2da0a7a9e91721ca79fa8b71a9"}}
{"design_id": "f2ad417ef85a", "module_name": "daq3_spi", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/daq3/common/daq3_spi.v", "sha256": "801dab8289e7ae2d8fbe85917b2a3d2bdecc6d229578f157cc8067f615d78fb9"}}
{"design_id": "f2b8988221b3", "module_name": "asic_nand4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_nand4.v", "sha256": "9e7e3f60bf71cc64bc7c1e198bf0f9dafb1286507425fa569de19446ace16cd3"}}
{"design_id": "f2b9602dda92", "module_name": "pcie_axi_master_rd", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_axi_master_rd.v", "sha256": "7089eeefbec3a75236ef7a74f779cb514fc48026d83d9b4100a8ff60d507b0e3"}}
{"design_id": "f2c4414f467f", "module_name": "ct_ifu_debug", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_debug.v", "sha256": "d9cadc403820c5333001aff1a35cc08a17018115b4de73765a0fe5332596667d"}}
{"design_id": "f2ea43224078", "module_name": "sync_signal", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ML605/fpga_sgmii/rtl/sync_signal.v", "sha256": "a89c005b14019c94f72fee6308e370044333742bec9494df1fbdd3096988f919"}}
{"design_id": "f2f36e114bb9", "module_name": "sync_reset", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/rtl/sync_reset.v", "sha256": "67ea2e751ee7cdf5c7528902eab32a63f11bd090e1380934fd7334b361c7d874"}}
{"design_id": "f302c05c9406", "module_name": "sirv_hclkgen_regs", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_hclkgen_regs.v", "sha256": "8755434bcca698e0e7daf2c11c7d508a290d4b21cbf2b61a58b48d095ac23168"}}
{"design_id": "f309ea16907f", "module_name": "ct_idu_rf_prf_vregfile", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_rf_prf_vregfile.v", "sha256": "8c6982e997651b2286bf8168eedaa209551ee843ba167eb312e16931445c37c4"}}
{"design_id": "f3373a6826f3", "module_name": "emesh_readback", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "emesh/hdl/emesh_readback.v", "sha256": "e82210b65c47b5126ac66087058ac925addb4e37e87ee7dd1bb0bc438ea5e8cb"}}
{"design_id": "f34b29d01893", "module_name": "util_pulse_gen", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/util_pulse_gen.v", "sha256": "b0cf36bf59980370db24d17d810975b20896c9466a55cd8b7d84aaac159fa494"}}
{"design_id": "f3a47e93d135", "module_name": "serv_bufreg2", "split": "val", "source": {"repository": "https://github.com/olofk/serv", "commit": "f200eb2ed7b69ac1c6b8eddd47654522aeee5ce8", "path": "rtl/serv_bufreg2.v", "sha256": "6586c95a64a064ff6f4d001996d33f15e0f6d452e01ebb4da6120db06ddd0a51"}}
{"design_id": "f3c15a3108d0", "module_name": "pcie_s10_if_tx", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/pcie_s10_if_tx.v", "sha256": "617347b6e8d5f5941f69dce07d005804db88369be5ea73858f8285390d69e9e5"}}
{"design_id": "f3e7f6ae36bc", "module_name": "addsub_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/pacoblaze/addsub_tb.v", "sha256": "d7738589094c523976e4029b7d4764d898034c0272854ac0d881684405b66483"}}
{"design_id": "f3eb4acef41f", "module_name": "priority_encoder", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/priority_encoder.v", "sha256": "df28220d95b47df349a72803a9751aad331eb8e1435416e8686d00572a974dd5"}}
{"design_id": "f400d6628f9a", "module_name": "pcileech_fifo", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "sp605_ft601/pcileech_fifo.v", "sha256": "2a7831229012ca3ea90e97f3316a37335e4f834ddf189c449a74c37effa0d12d"}}
{"design_id": "f40b554ff883", "module_name": "udp_mux", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/udp_mux.v", "sha256": "fdbb8ffd42405d3db2201894eab36b2e618056f611c3301c15f862e37a1d0de8"}}
{"design_id": "f4244f9a6ebc", "module_name": "nv_ram_rwsp_32x32", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rwsp_32x32.v", "sha256": "40dd66dd3aa4a59f057f21b538f5ba4109d15118377978533fe478958033e1df"}}
{"design_id": "f4388e54c7ea", "module_name": "nv_ram_rws_256x7", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/synth/nv_ram_rws_256x7.v", "sha256": "dbae6e38b2c2d0519253ccdfe0395067718b451dd2b96198d5618c5b0a1345e2"}}
{"design_id": "f4521ea8c636", "module_name": "xcvr_ctrl", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v", "sha256": "c119978a2fb8e94b3547b893b045ed2e0eff835de41e0e41c0faa4bb1800472c"}}
{"design_id": "f4532fb6a24e", "module_name": "oh_ao31", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_ao31.v", "sha256": "6ffdb70832c7207df375cb19ef3a326ddb1dd5302d95bd9a5dccaf96223fd7f5"}}
{"design_id": "f45fcfbac768", "module_name": "axis_arb_mux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_arb_mux.v", "sha256": "bee8d11f32f7fb1c5afdd6cdad872cd7de9dc94bcb4787f9aa119f2ebbc489a6"}}
{"design_id": "f468dc6e84c2", "module_name": "asic_isolo", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_isolo.v", "sha256": "9f25ac03893b267ff531ef200c5c8eeedd282621a4f9606e80479183d09e6207"}}
{"design_id": "f46b27ac5c6a", "module_name": "axil_crossbar_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_crossbar_wr.v", "sha256": "6b415d4d265a6694810913b67f62f93bd01128c59afe962d2784d45b9f310663"}}
{"design_id": "f4820efdcb60", "module_name": "axis_frame_length_adjust", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_frame_length_adjust.v", "sha256": "4b11a92dbdcd0b7b4999d94a62f57b0fc9e0476c543cffcfc817b0b7405f148b"}}
{"design_id": "f4a2ff328241", "module_name": "ad_mem", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_mem.v", "sha256": "c9d50e1d5395f0154e595931076e71e62dd2926fb0485f810c48203c8567eaf0"}}
{"design_id": "f4ab34c38ff9", "module_name": "ct_ciu_l2cif", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_l2cif.v", "sha256": "8d54e79122328ab15b00698dc45c572afc70e905f59cb7c4d93568e3e75d6751"}}
{"design_id": "f4b334dd2336", "module_name": "oh_ao222", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_ao222.v", "sha256": "288c6d9e1dbc555b1b540f3eee1225083948b03b92e84e2c7699f095287ac1da"}}
{"design_id": "f50ba6eec114", "module_name": "example_core_pcie_ptile", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/common/rtl/example_core_pcie_ptile.v", "sha256": "58f2bda8cde2da1323d2606665298e74826b69b4ead5d107933e1bfe907391a7"}}
{"design_id": "f50c23258d02", "module_name": "ct_iu_bju_pcfifo_read_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/iu/rtl/ct_iu_bju_pcfifo_read_entry.v", "sha256": "292c7f1f31d8ad91677038a38220e33746b65954c4328a3e9c6b37ee213a476c"}}
{"design_id": "f521a38ee276", "module_name": "ct_biu_req_arbiter", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/biu/rtl/ct_biu_req_arbiter.v", "sha256": "90a0b05ea7ba36ce39a23d029089f146ee58be871d13a92a82c81a64055ba2ed"}}
{"design_id": "f5266b46e789", "module_name": "mac_ctrl_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/mac_ctrl_rx.v", "sha256": "b5c0eda334c078518adb5fb7db324ae966ebddba0031bc91cedd32b831137fb1"}}
{"design_id": "f529b78c209b", "module_name": "rx_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/common/rtl/rx_fifo.v", "sha256": "e9d4a43ed2ec595ef4cc9ea2dedd3f8d769ef635cb36f079743bec75474392cc"}}
{"design_id": "f53b20621364", "module_name": "axi_ram", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/AU250/fpga_axi/rtl/axi_ram.v", "sha256": "1126d3b8116bd489252e8835c47d3a34d917f4600b002c0b91a838c457f0847b"}}
{"design_id": "f555daa29c7d", "module_name": "example_core_pcie", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/common/rtl/example_core_pcie.v", "sha256": "34e62561df75230ed56e05a3ce40b1c70f48f7d666967062cdf7f923c646c77b"}}
{"design_id": "f5625c50d049", "module_name": "sirv_ResetCatchAndSync_2", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/perips/sirv_ResetCatchAndSync_2.v", "sha256": "1276066c3cb7b5b758c151682c049e6fe4629ef807d69331ca841003f9d669d7"}}
{"design_id": "f585e5d99b60", "module_name": "PGAOPV_DFCNQD2PO4", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/PGAOPV_DFCNQD2PO4.v", "sha256": "1c2490e2e45b8d32bc1d4b829540adb3466fda049c0ff2095521c3410b729357"}}
{"design_id": "f5cfc2f3bceb", "module_name": "ad_dds_sine_cordic", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_dds_sine_cordic.v", "sha256": "6306d918be81624a5f7c7450370012b6cdb02e747d81d260de41d957e32b7d8a"}}
{"design_id": "f5d84da9eea8", "module_name": "mix_one_column", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crypto/aes/mix_columns.v", "sha256": "1b6266a6f80be5c3fcdbc5717c9fdaae70b136bb4a1d1db4ef50c6bd0396c13d"}}
{"design_id": "f5da8d514832", "module_name": "axi_dma_wr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_dma_wr.v", "sha256": "91b24115e3a5940a6057d06554fb5c61594a22fc71391e871e5c14f1e21ea0b2"}}
{"design_id": "f62dfa373396", "module_name": "ct_clint_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/clint/rtl/ct_clint_top.v", "sha256": "eca7b0ed7af6f7925ed9e582be139f78f25d9126fa9a5089bf32a06d1b02d802"}}
{"design_id": "f63f31aac05f", "module_name": "six_three_comp", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/arithmetic/six_three_comp.v", "sha256": "15ef8101209651c3f5df817f8b37a0eaa4f2e83e74c090b3b674f51e73bb0a75"}}
{"design_id": "f64c2e208186", "module_name": "ct_piu_other_io", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_piu_other_io.v", "sha256": "49b9af42daa9851a1c7608498023df18d940bf646d2f4a20eb4e64161ff80011"}}
{"design_id": "f64e0c66fd2b", "module_name": "ct_fadd_close_s0_d", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfalu/rtl/ct_fadd_close_s0_d.v", "sha256": "894ac650be41e28af495f3251e6e090dbb6058f489b1b13be68d01f39d540e95"}}
{"design_id": "f65918464f1e", "module_name": "ct_mp_clk_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_mp_clk_top.v", "sha256": "9a1a3bb1beec4528751ad92a1f6f0ca50fb35a8a755aec65eb66d48c93fb651b"}}
{"design_id": "f6807a950c91", "module_name": "arp_eth_tx", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/arp_eth_tx.v", "sha256": "88be298ea8f236900416ebd3295aa2fa86a8785acc2b8edca87278afc2338f86"}}
{"design_id": "f69474875a28", "module_name": "axi_slave", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/tb/axi_slave.v", "sha256": "50deac620dcbeefb22c15efda3eedf0c555c126c185a6f8a68766f76e354bbc8"}}
{"design_id": "f6d094e5d892", "module_name": "uart_tb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/communication/uart_tb.v", "sha256": "b999a5c7b6a9648161bf6cdb415fae915d8617313af0a1864bb24dd2b00ddd12"}}
{"design_id": "f6ed351bcd9b", "module_name": "axi_vfifo_dec", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axi_vfifo_dec.v", "sha256": "c8f86151e2721bd9c4e96e9845c8efccbbeceffb5ec0df0949ab0a6febc7ed56"}}
{"design_id": "f70c4cdc3612", "module_name": "dport_axi", "split": "val", "source": {"repository": "https://github.com/ultraembedded/riscv", "commit": "7ae6f803e30f78c6ea3121e73c3adf50ff912730", "path": "top_tcm_axi/src_v/dport_axi.v", "sha256": "491b38cf4f7ed58b0f7ae8ec3a483b64dba9aebab1b35566073fdaae0f2c6961"}}
{"design_id": "f723ea7edd93", "module_name": "latency_aware_read_master", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "avalon_mm_master_templates/latency_aware_read_master.v", "sha256": "5c8b92cd663ec2285f5a938fe87a7043fa8f47d4d55035e8c8b73f983f8ed83c"}}
{"design_id": "f736a2a24f47", "module_name": "arbiter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/arbiter.v", "sha256": "d54d337db4812f927b2e9b5788dfa39f9bd578ad01b7846c5fa7f2610b0923fa"}}
{"design_id": "f7518a19f2a5", "module_name": "util_axis_resize", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/util_axis_resize/util_axis_resize.v", "sha256": "a475d68efba2fd89a4477d1cf640c748078d0e05ca8c76fba8eb0fccfa36ea28"}}
{"design_id": "f78739c838bd", "module_name": "axi_fifo_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/axi/axi_fifo_entry.v", "sha256": "944a3f0d677f2b599278b71e9d0e6171d4bce548a13801d01cbe11c132a66520"}}
{"design_id": "f791bb311f14", "module_name": "NV_NVDLA_cacc", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cacc/NV_NVDLA_cacc.v", "sha256": "790d3af0fa0acf9fa1b01a42ca6113576f0b44224e61d50993d8c9f29b90793f"}}
{"design_id": "f79914b288a4", "module_name": "xor6", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/xor6.v", "sha256": "7c21ab31f3ace8799d147b9b228fd8d41a2a92c40ba73b0e5460dc00f0fcf5b4"}}
{"design_id": "f7c612527828", "module_name": "axis_gmii_tx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_gmii_tx.v", "sha256": "41c3b79feadd774aae0b00f8837d48e6bc066947b01db8f1645cfef98e0e0397"}}
{"design_id": "f7d80f7c7ac0", "module_name": "axis_xgmii_tx_32", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/axis_xgmii_tx_32.v", "sha256": "5aa9cb71980c795702c54ac7f49815ff04655eb8bdc4b3c50843c61c795077db"}}
{"design_id": "f7e9268b506f", "module_name": "reg_cam_cell", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/reg_cam_cell.v", "sha256": "a619c33432bff667009133f1a9b1ed39550d79fa201e3b58088fa83d7ddac6c1"}}
{"design_id": "f8168fe4bec1", "module_name": "xgmii_interleave", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/xgmii_interleave.v", "sha256": "1bba6881732c709041ce7a6be15c32cedfa89c3c7091e682f8495a96719b8635"}}
{"design_id": "f8969a1c8ab1", "module_name": "asic_dmux2", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dmux2.v", "sha256": "ef91c6cb0ddeffab50437b7f88781131d065736213c5e7ac6c334ca094b0791c"}}
{"design_id": "f8aa4544fea3", "module_name": "ct_idu_rf_prf_gated_ereg", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_rf_prf_gated_ereg.v", "sha256": "6d5e5365bdf552bc46fb09f1eb33c8382cb59e93c86c633d47edecfb7d5c28d2"}}
{"design_id": "f8b30886e498", "module_name": "p_SDFCNQD1PO4", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/p_SDFCNQD1PO4.v", "sha256": "b145c0d63e2c5772e8d620a252ccd699787f25d3a662f6f1f130f156b7daeead"}}
{"design_id": "f8c4331f76fe", "module_name": "sirv_pwm16_core", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_pwm16_core.v", "sha256": "cc09c11112c8dd7394995c7e9546e6707ce741e367612f5e1b594576b8fe40e4"}}
{"design_id": "f8db21036287", "module_name": "eth_xcvr_phy_quad_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/VCU108/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v", "sha256": "0d6dce07b6a8fe51a55c4e9cb9100bbc0e307c0f56f77475a3e9d7a7e4c93b22"}}
{"design_id": "f8e7ad715517", "module_name": "eth_mac_1g_gmii", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/eth_mac_1g_gmii.v", "sha256": "44e755d50945c37a2cbd6cd39c7401451b02a005c154af88642b4050360a0b69"}}
{"design_id": "f8f3df45f20c", "module_name": "fec_rot_4", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_4.v", "sha256": "220c5384bc20f9cf39d84105e44a6d6b87c86a98cbadb984edce3228e37df9e6"}}
{"design_id": "f91b5dd00c25", "module_name": "apb_bridge", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/apb/apb_bridge.v", "sha256": "5ad82b4bc4561ad9a657975427bbd9b27fa65062fe1611af6c6f12b47efe7d86"}}
{"design_id": "f91fbb0063e3", "module_name": "NV_NVDLA_RT_csb2cacc", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/retiming/NV_NVDLA_RT_csb2cacc.v", "sha256": "c09c5089858be7c7655aff3006ac705b07972f08d9e0f0fd9e5fbb76605ab558"}}
{"design_id": "f9335f65297b", "module_name": "ct_ifu_l0_btb_entry", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_l0_btb_entry.v", "sha256": "f1746ad67a11e5d58a5c0a40170d715856af7a96ade16f299cb3a2ed696a9232"}}
{"design_id": "f94a1cda7670", "module_name": "word_align_control", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/word_align_control.v", "sha256": "24614d244eefad9ad750c967f535b153bcccadbec1dad082f4bafe4bd3b53438"}}
{"design_id": "f9612aeb1de7", "module_name": "single_port_ram_with_init", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "dual_port_single_port_ram_templates/Verilog/single_port_ram_with_init.v", "sha256": "b08973686ef332d383d52af148d22bed667fd07925809987a125c9bde57037b0"}}
{"design_id": "f973127a3abe", "module_name": "test_eth_arb_mux_64_4", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_eth_arb_mux_64_4.v", "sha256": "d27acdfea7942a99b6d20cf94744a439d4e812b12deab3f163d2b4417c30a8ee"}}
{"design_id": "f976902364e0", "module_name": "axis_stat_counter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_stat_counter.v", "sha256": "2a431655333c6d4b8daad55a80eb2b22b9796e92b15a2c295a6b5d2f5e0e2ce1"}}
{"design_id": "f98a92274227", "module_name": "axi_ad9671_if", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad9671/axi_ad9671_if.v", "sha256": "d285a94fdbb502a74ae6f46b79c658df70d8c94f2eafcbc1319a828b0c7f73ae"}}
{"design_id": "f9ca6d8d1f9b", "module_name": "debounce_switch", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/ML605/fpga_rgmii/rtl/debounce_switch.v", "sha256": "02d6ba80136cb9be942347e33c43881f465acbfc4f41b6af3a32d41c86b4ef5a"}}
{"design_id": "f9e9bc4e6ec7", "module_name": "MUX2HDD2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/vlibs/MUX2HDD2.v", "sha256": "24e632a1f3093c2830cdbdf90578bcd4777b996719562db1ab4e224576c94586"}}
{"design_id": "f9fd10ad2a3d", "module_name": "crc32_dat8", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/crc/crc32_dat8.v", "sha256": "2e85fc3dc278303d026b7d4165903bfae8a3c34b456f58d2e1bd40cd8de0da12"}}
{"design_id": "fa17f8884a8c", "module_name": "asic_inv", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_inv.v", "sha256": "75875ee84412215116cecab43ae2193d394a7e60169eea48032ceb528bda3817"}}
{"design_id": "fa1ca7ad10bb", "module_name": "pcie_us_if", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/pcie_us_if.v", "sha256": "18ec3da717070040dd197afba830f736885ee4702029fb7000758ebe312beb44"}}
{"design_id": "fa3bca7becd4", "module_name": "sync_level2level", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/common/rtl/sync_level2level.v", "sha256": "7530a4e8a17cd2ed2fcc9710634e10e9ae5754f1262e5a0f84619e9cbcfeeef1"}}
{"design_id": "fa48035f59e5", "module_name": "oh_mux7", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_mux7.v", "sha256": "a68ad2529b78f757a6ebd95dab322594f2b5986a7ffac65ccf4841b834db5ca1"}}
{"design_id": "fa6a3879c8fc", "module_name": "fir_decim", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adc_decimate/fir_decim.v", "sha256": "77a14e382861a9e3773781f0f6ec8d556f5b1f97317d54cc5e570c81e4bd51d7"}}
{"design_id": "fa79cf7c5b12", "module_name": "ad_pngen", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/common/ad_pngen.v", "sha256": "d23fb20e8bef104ce7c7947945595a81203ba9169e2ca24e8090a59a776c2ecc"}}
{"design_id": "fa80ce98ed85", "module_name": "ct_spsram_1024x32", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_spsram_1024x32.v", "sha256": "e5c6b9f1997dcd69de0ee9d01e674cae41d05575848fa7bd647aa9d31cd2a182"}}
{"design_id": "fa82378e0dc6", "module_name": "dma_psdpram", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "rtl/dma_psdpram.v", "sha256": "5d06400fe8c45ff27a0eaabb33206b684b2f2c5adf59353fcabe891e9ac29513"}}
{"design_id": "fab12c713235", "module_name": "axis_register", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-pcie", "commit": "25156a9a162c41c60f11f41590c7d006d015ae5a", "path": "example/ADM_PCIE_9V3/fpga_axi/rtl/axis_register.v", "sha256": "ebb03f4f7184b4c45f47ee4448e627f8c40348d08f98e727eb9e7f86f4402fea"}}
{"design_id": "fab6f2df9421", "module_name": "ready_skid", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/storage/ready_skid.v", "sha256": "1eef24da58fabb405c9b44e65f88e67037ad8f775886590b329f61916817202c"}}
{"design_id": "fab799e6c34b", "module_name": "test_axis_demux_4_64", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/tb/test_axis_demux_4_64.v", "sha256": "e2141ea69c9afaad002f25f0fb4a20c149d923d5ec97d38f13285dd5c067ae33"}}
{"design_id": "fb2779111906", "module_name": "CLKDIV", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "xilibs/dv/CLKDIV.v", "sha256": "4ec27a1c242a80f95ed5262eb1bd26cb7be993d72c596bfb572c858964e7759a"}}
{"design_id": "fb60564b48ca", "module_name": "test_udp", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/tb/test_udp.v", "sha256": "2c27964827bfbb68be0aac466dd9ddc7b122c01394a26453661747fc48c1c618"}}
{"design_id": "fb607b3736f6", "module_name": "oh_latq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_latq.v", "sha256": "6c2409d2363478cd28b8a84e4923c4c34f632a62ea8308bf2603e972e85429be"}}
{"design_id": "fb78eb6f95f2", "module_name": "ct_had_nirv_bkpt", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_nirv_bkpt.v", "sha256": "50a06b0c88947385e053bf2ec35c981e9b5b2889456ea570ece5a3f4d3634f82"}}
{"design_id": "fbb09e5c8b7d", "module_name": "axi_hdmi_rx_core", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_hdmi_rx/axi_hdmi_rx_core.v", "sha256": "4d7e8c14e84d61c8c58f719ea455a6d12276c5c72a2e1a34fde6bef6b4eeed41"}}
{"design_id": "fbe564aa4d49", "module_name": "axi_ram", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi/rtl/axi_ram.v", "sha256": "1126d3b8116bd489252e8835c47d3a34d917f4600b002c0b91a838c457f0847b"}}
{"design_id": "fbed0de86b04", "module_name": "NV_NVDLA_CDP_DP_nan", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v", "sha256": "d405af6d56f69121d51663a148f64ee16e338855373e8f3cb754fb6a4a764595"}}
{"design_id": "fbee8f186294", "module_name": "ct_spsram_1024x144", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/l2c/rtl/ct_spsram_1024x144.v", "sha256": "9cea61e7cc75411f95f457d1c0255303156539368de65bdd19dc2fdb01d19f77"}}
{"design_id": "fc1114eb269d", "module_name": "uart_apb_reg", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/uart/uart_apb_reg.v", "sha256": "d375d57bc365e2393aee2cbd2b076509bdf36f92cdd2b0ea2e2c6ecf9230b453"}}
{"design_id": "fc1184de64e3", "module_name": "ct_vfdsu_ctrl", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ctrl.v", "sha256": "bff3f286c5cb1a23a4f71ccb4b16bc74dcb931659564b1734489d07b208f6e29"}}
{"design_id": "fc153ff7b6d4", "module_name": "six_three_comp", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/interlaken_lane/six_three_comp.v", "sha256": "a69863e526f5cff58a0f7a00ec413d6fde53a0bb19140fcd513cc16fe8e8aa70"}}
{"design_id": "fc3e3be92dac", "module_name": "oh_xor4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_xor4.v", "sha256": "4f3147df0749895d48c4cd67eb249e2d834c6c7e7f49fbeede358692176c06a9"}}
{"design_id": "fc528c2838ce", "module_name": "asic_and4", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_and4.v", "sha256": "f82a2a1f6c289039f7839492bb4cb9af6ec76469a854b64fa0a07f3bb3932567"}}
{"design_id": "fc6477556e87", "module_name": "ct_f_spsram_128x16", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_128x16.v", "sha256": "4d033316c3ae3b3b1128327b03765c1ecfe1da8ef7a2da424716a98d585a74db"}}
{"design_id": "fc81fdd1e1c5", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_top_xmicrowave.v", "sha256": "c0d6f0f1f551831c205fe7f17d922d10783271430d6e6066f61c52bc020cc8ca"}}
{"design_id": "fca3047d52a1", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad7124_asdz/de10nano/system_top.v", "sha256": "4779f9ebb40102af37c8e251128f52c1e0a313f8256fb888ba9d6603c8303b96"}}
{"design_id": "fcb548e5ef92", "module_name": "custom_master", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "avalon_mm_master_templates/custom_master.v", "sha256": "a987c573c9b2f9e3326a18bcf3ccb1cb7b1c86722c5800959726bb39345ba3d7"}}
{"design_id": "fcc35a05042d", "module_name": "ip_eth_rx", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/ip_eth_rx.v", "sha256": "f8f4bfb0352872b3e7a52616242e51fd5c6261c93a2569fbf9e0777620e1f8ae"}}
{"design_id": "fcd27e298f84", "module_name": "LUT1", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/LUT1.v", "sha256": "00f1e4f89b27678e4901a49858da74745583b125986decb31a650639952652f0"}}
{"design_id": "fcff5f337487", "module_name": "axil_adapter_wr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_adapter_wr.v", "sha256": "1945be51e41c4c8b6c1e48af9d85f13cf761af5d1dfc42dad66cda40afc60f07"}}
{"design_id": "fd1c59bfd7d4", "module_name": "util_clkdiv", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/xilinx/util_clkdiv/util_clkdiv.v", "sha256": "2a8888635f063cdbcb237f2882b565352f02a3a1838d361bfbdda56a14e13e0a"}}
{"design_id": "fd1ef650e623", "module_name": "fec_rot_21", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/ethernet_fec/fec_rot_21.v", "sha256": "70cbae7e660809188ef647ba28b794ea3b58468229ac7ddd993b783394cba4a5"}}
{"design_id": "fd2d60c75d66", "module_name": "ct_lsu_dcache_top", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_dcache_top.v", "sha256": "717e4985470cf85310bb578787ccef8146f3ed85e2781b14507bc193cf9d63b6"}}
{"design_id": "fd31450894da", "module_name": "axis_ram_switch", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_ram_switch.v", "sha256": "87de8b2f0f408bda4d7046c1cf5999edf885f6a613dfb75cf992bba8455f27c8"}}
{"design_id": "fd53676c4861", "module_name": "pcileech_fifo", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "NeTV2/src/pcileech_fifo.sv", "sha256": "1173c8174b50b746333449d89598a4a3abbb9857754172f7fb599706eec6b57b"}}
{"design_id": "fd86780b434d", "module_name": "axi_spi", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "spi/hdl/axi_spi.v", "sha256": "81a91b4e4aede17a36afa68cbeb1155be8d0a2987e9b393c264c814bf25dbf5e"}}
{"design_id": "fd88e7dbafbd", "module_name": "RAMDP_256X7_GL_M2_E2", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/rams/model/RAMDP_256X7_GL_M2_E2.v", "sha256": "8bfdb08a5c3b3088b2221bac751ba974524f0d7bf95e32e8b13cb7113265553c"}}
{"design_id": "fd9aae3e975d", "module_name": "dma_read_shutdown_tb", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_dmac/tb/dma_read_shutdown_tb.v", "sha256": "6267afd2b48ab653cdf98c78933e3b247250ef41c315abbf48927eaabbe4a2f1"}}
{"design_id": "fdac2b29f51f", "module_name": "NV_NVDLA_SDP_CORE_gate", "split": "val", "source": {"repository": "https://github.com/nvdla/hw", "commit": "8e06b1b9d85aab65b40d43d08eec5ea4681ff715", "path": "vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_gate.v", "sha256": "8cdc339649b17b9d3335b2eb5ea4833cbb2c3d9c31384818b01f1355c0d37a1c"}}
{"design_id": "fdb7520663a1", "module_name": "ct_f_spsram_256x23", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_256x23.v", "sha256": "a4189cc7240beef6d803e8871ab65a7425b84ca5bcef0c22bb44afbff8822f03"}}
{"design_id": "fdc162fcf20d", "module_name": "soc", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "smart_run/logical/common/soc.v", "sha256": "4708e2faf6fa616398ef4909c9b3c24c2824d882346a10b5890b278d6dc586c6"}}
{"design_id": "fdecc2ec6818", "module_name": "sirv_jtaggpioport", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/sirv_jtaggpioport.v", "sha256": "07fdf04dcdb6ac90f26e37283f323566c7d222cc2a8ad61448c3f16d4964c04d"}}
{"design_id": "fdf7830cf9a7", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/DCS7132LB/fpga_25g/rtl/fpga.v", "sha256": "9b827794ae3e857a10d21aab6331e7d64c0418139ee721ec4454ad1d220dc098"}}
{"design_id": "fe012548db30", "module_name": "iddr", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/iddr.v", "sha256": "1c7d429c684ae16b7326d242a3a681879a0243e07d1c3a00143a364d79aa47a9"}}
{"design_id": "fe1f5e1f150c", "module_name": "priority_encoder", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/rtl/priority_encoder.v", "sha256": "df28220d95b47df349a72803a9751aad331eb8e1435416e8686d00572a974dd5"}}
{"design_id": "fe228414d645", "module_name": "up_ad5766_sequencer", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_ad5766/up_ad5766_sequencer.v", "sha256": "2ab4aba9223f8c46a35eff0748c36e799aaf69f104b0f7cb6b0c9ed19725ef62"}}
{"design_id": "fe2b075d0bc4", "module_name": "axil_crossbar_addr", "split": "test", "source": {"repository": "https://github.com/alexforencich/verilog-axi", "commit": "516bd5dadc3365b7f9e225d2af8fe0b8d804fe53", "path": "rtl/axil_crossbar_addr.v", "sha256": "a687cef2780b571b1a1b85746e4e093d0d7131d77bf9d6c610f333b0e27480c0"}}
{"design_id": "fe33c764ca5c", "module_name": "ct_had_trace", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_trace.v", "sha256": "e8736de183fd7d16e63fa7d47b85102fb3a92fcc5fe46822aae7fc8d1b2a2489"}}
{"design_id": "fe78fae72a98", "module_name": "system_top", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "projects/ad57xx_ardz/de10nano/system_top.v", "sha256": "c5b574a0cae932ded2195c7596711b422e3cfa6739a9eb14e976271c3319b849"}}
{"design_id": "fe7b472a818d", "module_name": "axis_pipeline_fifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/lib/axis/rtl/axis_pipeline_fifo.v", "sha256": "a7cdccbf905c3f95d4a626fe77d84879a09c3f472dffc5ea2eb7acc9ba113c02"}}
{"design_id": "fea56c31fb44", "module_name": "udp_arb_mux", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "rtl/udp_arb_mux.v", "sha256": "a867eb6abe05986f71cae6ded5bdbf3746d54f358d8fdec83382fe38b8e6fc9d"}}
{"design_id": "fed1d0fc04f4", "module_name": "sirv_gnrl_ram", "split": "val", "source": {"repository": "https://github.com/riscv-mcu/e203_hbirdv2", "commit": "9f3e34f337f5d0a1236a285871ffa2032491617a", "path": "rtl/e203/general/sirv_gnrl_ram.v", "sha256": "07ade2feda6635e67aa79821f256b21cd0db9308537906c55612ee1e74034260"}}
{"design_id": "fee249489ea8", "module_name": "asic_ao311", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_ao311.v", "sha256": "0f062131fdba225214f0bfa60a300a214a548ef5749db1f3c9651cb30c463e0b"}}
{"design_id": "fee751f18f9a", "module_name": "axi_adaq8092", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adaq8092/axi_adaq8092.v", "sha256": "f03a73166c20f9921b343b24df73573632ddedd5789af6cb685a239765934b06"}}
{"design_id": "feedc375176e", "module_name": "oh_header", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "stdlib/rtl/oh_header.v", "sha256": "b3c30a04d409bca20f4d3bb517872a6239542850f95302d7e7f62c067b8d01c3"}}
{"design_id": "fef1ddde907d", "module_name": "axi_adc_trigger_reg", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_adc_trigger/axi_adc_trigger_reg.v", "sha256": "c7d8c0f26f09975b65f5e7c56d8f96270ce3ce28acf31598d70e29396047f1f7"}}
{"design_id": "fef6fa070931", "module_name": "axi_ram", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/rtl/axi_ram.v", "sha256": "1126d3b8116bd489252e8835c47d3a34d917f4600b002c0b91a838c457f0847b"}}
{"design_id": "ff1a4a68d5e0", "module_name": "ct_f_spsram_512x59", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/fpga/rtl/ct_f_spsram_512x59.v", "sha256": "f490aee5dfea1dcaa384f5f42548710b0c8dbfafc57df64bd25de543c6860ae1"}}
{"design_id": "ff30b82d7d71", "module_name": "pcileech_ft601", "split": "train", "source": {"repository": "https://github.com/ufrisk/pcileech-fpga", "commit": "c538c4170678c13f723dc921905fb81ff3c71d8e", "path": "CaptainDMA/35t325_x4/src/pcileech_ft601.sv", "sha256": "e7eac681cc144e40c29ff9f5984bf221c6cc6b4f280f5ff095a2ad0da26e4059"}}
{"design_id": "ff3108ee3c5c", "module_name": "fpga", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "example/RV901T/fpga/rtl/fpga.v", "sha256": "fc71a44c191c0dca25fdec1547ef0598e30ec54f458b71c51d218259a4f4b258"}}
{"design_id": "ff78318dfec9", "module_name": "axi_pulsar_lvds", "split": "train", "source": {"repository": "https://github.com/analogdevicesinc/hdl", "commit": "c9a501d87a420d2e28aa9d931557bdb4122f3c4f", "path": "library/axi_pulsar_lvds/axi_pulsar_lvds.v", "sha256": "097222cb68e1f003208ff0dc9fd6e5d7c4f9b9c059945a44eee4571332163a64"}}
{"design_id": "ff99529f6b9e", "module_name": "asic_dffnq", "split": "train", "source": {"repository": "https://github.com/aolofsson/oh", "commit": "7edfcb5f0506fb854449fbe09598a7ec88bb2067", "path": "asiclib/hdl/asic_dffnq.v", "sha256": "f6dce190ea3c6dde94772c4f748b62b005fb16e2554b138ebe66cd5539f837e9"}}
{"design_id": "ffb2932fc19a", "module_name": "axi_vfifo", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axi_vfifo.v", "sha256": "1fed2250a36b21275d22bd05eeb3ce6185c38bdfbb367c5fa862e374698bbee6"}}
{"design_id": "ffb33b299469", "module_name": "top_small", "split": "train", "source": {"repository": "https://github.com/YosysHQ/picorv32", "commit": "ef203c2b0a3fb793280f5114941416c425c5b461", "path": "scripts/vivado/synth_area_top.v", "sha256": "761af16546237f9efd11fdfd9babce0e40e02a0fe9ba455c1f5128350f831102"}}
{"design_id": "ffb4f90531b0", "module_name": "axis_eth_fcs_insert", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/rtl/axis_eth_fcs_insert.v", "sha256": "864c9d4d5cc3607b38ba5ca3f6c75c930d2dee690663b504f1952bb9e717d981"}}
{"design_id": "ffbe681c584f", "module_name": "INV", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "pacoblaze-2.2/xilinx/unisims/INV.v", "sha256": "853556ad0c36d01dd3839f0cbf1953c28290d30d38d709fae05cd311c8443e04"}}
{"design_id": "ffceafbeab47", "module_name": "i2c_master_top", "split": "test", "source": {"repository": "https://github.com/SI-RISCV/e200_opensource", "commit": "7fd27944f84cdc1a7162950cde173a43ee05ba19", "path": "rtl/e203/perips/i2c_master_top.v", "sha256": "53b59acb9ca23e901075508374d8b3dd4c2191baa4f5af5bd6d538efdb83904d"}}
{"design_id": "ffd284325035", "module_name": "ycbcr_to_rgb", "split": "train", "source": {"repository": "https://github.com/pConst/basic_verilog", "commit": "2654273b2c4e556a98e806f3a19b52c9b3c74614", "path": "Advanced Synthesis Cookbook/video/ycbcr_to_rgb.v", "sha256": "32e05873feb3673c73f8e67d07af63b250720f679c3e30a2c9abfbf0c3f179bd"}}
{"design_id": "ffd4d049f864", "module_name": "eth_xcvr_phy_wrapper", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/eth/example/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v", "sha256": "f5869f43282941cee4fda242ccb18410dfffa9588158ee4d4b73e6ea8eaeaa8b"}}
{"design_id": "ffd7abe378c1", "module_name": "axis_srl_fifo", "split": "train", "source": {"repository": "https://github.com/alexforencich/verilog-ethernet", "commit": "77320a9471d19c7dd383914bc049e02d9f4f1ffb", "path": "lib/axis/rtl/axis_srl_fifo.v", "sha256": "b657b6592e9a31a5f88289cfd34b1504b2114443a1c4df0ba89d10b4235a3104"}}
{"design_id": "ffd9c51a0d9a", "module_name": "multiplier_65x65_3_stage", "split": "train", "source": {"repository": "https://github.com/XUANTIE-RV/openc910", "commit": "b91c90914c19f114d35c8f6b73408eb241ed847c", "path": "C910_RTL_FACTORY/gen_rtl/iu/rtl/multiplier_65x65_3_stage.v", "sha256": "f772f0b5895020ff4e4c59cd2210dccf9198bf62015599b1ac586d886a4bdd86"}}
{"design_id": "ffee3dd0b91e", "module_name": "axil_adapter", "split": "train", "source": {"repository": "https://github.com/corundum/corundum", "commit": "1ca0151b97af85aa5dd306d74b6bcec65904d2ce", "path": "fpga/lib/axi/rtl/axil_adapter.v", "sha256": "7bc9936dc5c19d42397b638397064aa3ba51906c2cfbf1200d80a8f28ddaea26"}}